Chip temperature detection method and device, equipment and storage medium

Abstract

The chip temperature detection method, device and equipment and the storage medium provided by the embodiment of the invention comprise the steps that a test machine outputs a target control signal to a sorting machine in response to a received target selection operation triggered by a target object, so that the sorting machine controls the temperature of a sorting machine cavity to rise to a preset temperature after receiving the target control signal; the testing machine obtains voltage information of the to-be-tested chip in the sorting machine and determines the actual temperature of the to-be-tested chip in the sorting machine according to the voltage information; the testing machine determines a target adjusting signal according to the relation between the actual temperature of the to-be-tested chip in the sorting machine and the preset temperature of the cavity of the sorting machine; and the testing machine outputs the target adjusting signal to the sorting machine, so that after the sorting machine receives the target adjusting signal, the temperature of a cavity of the sorting machine is controlled to be adjusted on the basis of the preset temperature. The precision of the chip parameters collected by the chip under the three-temperature test is ensured, and the chip test precision is further ensured.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of chip testing technology and related technical fields, and in particular, to a chip temperature detection method, apparatus, device, and storage medium. Background Art

[0002] Power Management Integrated Circuits (PMIC) are chips that are responsible for the conversion, distribution, detection and other power management of electronic equipment systems. They are mainly responsible for identifying the CPU power supply amplitude, generating corresponding short-term waves, and promoting power output of subsequent circuits.

[0003] In the prior art, after the power management chip is manufactured, it needs to undergo three-temperature testing: low-temperature, room-temperature, and high-temperature testing. The existing three-temperature testing method for power management chips achieves the chip's test temperatures at low, room-temperature, and high temperatures by changing the ambient temperature within the measurement sorting chamber. However, in actual use scenarios, when the ambient temperature within the measurement sorting chamber reaches the temperature required for the three-temperature test of the power management chip, the power management chip may not be completely consistent with the temperature within the measurement sorting chamber, resulting in inaccurate test temperatures for the power management chip. Summary of the Invention

[0004] The embodiments described herein provide a chip temperature detection method, apparatus, device, and storage medium to solve the problems existing in the prior art.

[0005] In a first aspect, according to the present disclosure, a chip temperature detection method is provided, which is applied to a tester of a chip temperature detection system. The chip temperature detection system also includes a sorter, the sorter and the tester are communicatively connected, and a temperature test is performed on a chip to be tested in the sorter. The tester is communicatively connected to the chip to be tested via a test board, comprising:

[0006] The tester outputs a target control signal to the sorter in response to receiving a target selection operation triggered by a target object, so that the sorter controls the temperature of the sorter cavity to rise to a preset temperature after receiving the target control signal, wherein the target selection operation is used to select a test mode for the chip to be tested, and the test modes for the chip to be tested include low temperature test, normal temperature test, and high temperature test;

[0007] The tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter according to the voltage information;

[0008] The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity;

[0009] The testing machine outputs a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on a preset temperature after receiving the target adjustment signal.

[0010] In some embodiments of the present disclosure, the tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter based on the voltage information, including:

[0011] The tester collects a sample voltage of the chip to be tested inside the sorter at a sampling moment;

[0012] The tester determines the actual temperature of the chip to be tested in the sorter at the sampling moment according to the sampled voltage, the reference temperature and the reference voltage.

[0013] In some embodiments of the present disclosure, the tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, including:

[0014] When the actual temperature of the chip to be tested in the sorter is lower than the preset temperature of the sorter cavity, determining a first target adjustment signal according to information of a difference between the preset temperature of the sorter cavity and the actual temperature of the chip to be tested in the sorter;

[0015] When the actual temperature of the chip to be tested in the sorter is greater than the preset temperature of the sorter cavity, a second target adjustment signal is determined according to the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity.

[0016] In some embodiments of the present disclosure, before determining the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, the tester further includes:

[0017] The tester obtains temperature adjustment values ​​of the sorter cavity under different temperature differences, wherein the temperature difference is the absolute value of the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity;

[0018] The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity, including:

[0019] The tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, as well as the temperature adjustment value of the sorter cavity under different temperature differences.

[0020] In some embodiments of the present disclosure, further comprising:

[0021] When the actual temperature of the chip to be tested is the same as the preset temperature of the sorting machine cavity, the tester outputs a test signal to the sorter to enable the sorter to test the chip to be tested and sends the obtained test parameters of the chip to be tested to the tester.

[0022] In a second aspect, according to the present disclosure, another chip temperature detection method is provided, which is applied to a sorter of a chip temperature detection system, wherein the chip temperature detection system also includes a tester, wherein the sorter and the tester are communicatively connected, and a chip to be tested is placed in a cavity of the sorter for temperature testing, wherein the tester is communicatively connected to the chip to be tested, and includes:

[0023] The sorting machine receives the target control signal output by the testing machine, and controls the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal, wherein different target control signals correspond to different preset temperatures;

[0024] The sorting machine receives the target adjustment signal output by the testing machine, and adjusts the temperature of the sorting machine cavity according to the target adjustment signal.

[0025] In a third aspect, according to the present disclosure, a chip temperature detection device is provided, which is applied to a tester of a chip temperature detection system. The chip temperature detection system also includes a sorter, the sorter and the tester are communicatively connected, and the temperature test of the chip to be tested is performed in the sorter. The tester is communicatively connected to the chip to be tested via a test board, including:

[0026] a target control signal output module, configured to output a target control signal to a sorting machine in response to receiving a target selection operation triggered by a target object, so that the sorting machine controls the temperature of the sorting machine cavity to rise to a preset temperature after receiving the target control signal, wherein the target selection operation is used to select a test mode for the chip to be tested, and the test modes for the chip to be tested include low-temperature test, normal-temperature test, and high-temperature test;

[0027] an actual temperature determination module, configured to obtain voltage information of the chip to be tested in the sorting machine, and determine the actual temperature of the chip to be tested in the sorting machine based on the voltage information;

[0028] a target adjustment signal determination module, configured to determine a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorting machine and a preset temperature of the sorting machine cavity;

[0029] The adjustment signal output module is used to output a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on a preset temperature after receiving the target adjustment signal.

[0030] In a fourth aspect, according to the present disclosure, another chip temperature detection device is provided, which is applied to a sorter of a chip temperature detection system, wherein the chip temperature detection system further includes a tester, wherein the sorter and the tester are communicatively connected, and a chip to be tested is placed in a cavity of the sorter for temperature testing, wherein the tester is communicatively connected to the chip to be tested, and comprises:

[0031] a control module, configured to receive a target control signal output by the test machine, and control the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal, wherein different target control signals correspond to different preset temperatures;

[0032] The regulating module is used to receive the target regulating signal output by the testing machine and regulate the temperature of the sorting machine cavity according to the target regulating signal.

[0033] In a fifth aspect, according to the contents of the present disclosure, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the method in any of the above embodiments are implemented.

[0034] In a sixth aspect, according to the contents of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in any of the above embodiments are implemented.

[0035] The chip temperature detection method, device, equipment and storage medium provided by the embodiment of the present disclosure are as follows: first, the tester responds to the target selection operation triggered by the target object and outputs a target control signal to the sorter, so that the sorter controls the temperature of the sorter cavity to rise to a preset temperature after receiving the target control signal; then the tester obtains the voltage information of the chip to be tested in the sorter and determines the actual temperature of the chip to be tested in the sorter based on the voltage information; then the tester determines the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity; finally, the tester outputs the target adjustment signal to the sorter, so that the sorter controls the temperature of the sorter cavity to be adjusted based on the preset temperature after receiving the target adjustment signal. By collecting the relationship between the actual temperature of the chip to be tested during the test process and the preset temperature of the sorter cavity, the temperature of the sorter cavity is adjusted, thereby ensuring that the temperature of the chip to be tested reaches the temperature in the test mode selected by the target object, and ensuring the accuracy of the chip parameters collected under the three-temperature test.

[0036] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0038] Figure 1 This is a flow chart of a chip temperature detection method provided by an embodiment of the present disclosure;

[0039] Figure 2 is an interactive schematic diagram of a chip temperature detection method provided by an embodiment of the present disclosure;

[0040] Figure 3 is a flow chart of another chip temperature detection method provided by an embodiment of the present disclosure;

[0041] Figure 4 1 is a schematic structural diagram of a chip temperature detection device provided by an embodiment of the present disclosure;

[0042] Figure 5 is a structural diagram of another chip temperature detection device provided by an embodiment of the present disclosure;

[0043] Figure 6It is a structural diagram of a computer device provided by an embodiment of the present disclosure.

[0044] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0047] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it necessarily refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] The term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists, A and B exist, and B exists. Additionally, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0049] Furthermore, in all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0050] In the description of this application, unless otherwise specified, "plurality" means more than two (including two), and similarly, "multiple groups" means more than two (including two).

[0051] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0052] The chip three-temperature testing method provided by the embodiment of the present disclosure is applied to a chip three-temperature testing device, which may be a terminal device.

[0053] In view of the problems existing in the prior art, an embodiment of the present disclosure provides a chip temperature detection method, which is applied to a test machine of a chip temperature detection system. Figure 1 is a flow chart of a chip temperature detection method provided by an embodiment of the present disclosure. Figure 2 This is a schematic diagram of the interaction between a sorting machine and a testing machine provided by the embodiment of the present disclosure, combined with Figure 1 and Figure 2 ,The specific process of the chip temperature detection method includes:

[0054] S110 , the testing machine outputs a target control signal to the sorting machine in response to receiving a target selection operation triggered by a target object, so that the sorting machine controls the temperature of the sorting machine cavity to rise to a preset temperature after receiving the target control signal.

[0055] The target selection operation is used to select a test mode for the chip to be tested. The test modes for the chip to be tested include low temperature test, normal temperature test, and high temperature test.

[0056] Among them, the target selection operation is used to select the test mode of the chip to be tested. The test modes of the chip to be tested include low-temperature testing, normal temperature testing and high-temperature testing. For example, the test environment temperature of the chip to be tested is -40 degrees Celsius during low-temperature testing, the test environment temperature of the chip to be tested is 25 degrees Celsius during normal temperature testing, and the test environment temperature of the chip to be tested is 125 degrees Celsius during high-temperature testing.

[0057] Specifically, the chip temperature detection system includes a testing machine and a sorting machine. The sorting machine includes a high and low temperature hot and cold hedge meter, a temperature sensor, a sorting machine cavity, a carrier and a test board. The carrier carries the test board. The sorting machine cavity and the carrier form a closed space. The chip to be tested is communicatively connected with the test board. The test board and the chip to be tested are arranged in the closed space. The temperature sensor collects the temperature of the sorting machine cavity.

[0058] The target objects may be chip design engineers of a chip design company, and the selection operations include a low-temperature test selection operation, a normal-temperature test selection operation, and a high-temperature test selection operation.

[0059] In a specific embodiment, in response to a target selection operation triggered by a received target object, a target control signal is output to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to rise to a preset temperature after receiving the target control signal.

[0060] Specifically, when the testing machine receives the target selection operation triggered by the target object, it outputs a target control signal to the sorting machine to control the high and low temperature hot and cold hedger of the sorting machine, so as to raise the temperature in the sorting machine cavity to the target test temperature corresponding to the test mode based on the high and low temperature hot and cold hedger. For example, if the test mode selected by the target object is low temperature test, the high and low temperature hot and cold hedger of the sorting machine will control the temperature in the sorting machine cavity to -40 degrees Celsius; if the test mode selected by the target object is normal temperature test, the high and low temperature hot and cold hedger of the sorting machine will control the temperature in the sorting machine cavity to 25 degrees Celsius; if the test mode selected by the target object is high temperature test, the high and low temperature hot and cold hedger of the sorting machine will control the temperature in the sorting machine cavity to 125 degrees Celsius.

[0061] In some usage scenarios that require high chip precision, it is necessary to ensure the accuracy of the chip parameters collected by the chip in the corresponding low-temperature test, normal temperature test, and high-temperature test scenarios. In order to ensure the accuracy of the chip parameters collected by the chip in the corresponding test mode, it is necessary to ensure that the temperature of the chip reaches the set temperature under the low-temperature test, normal temperature test, and high temperature test. However, in the existing technology, during the chip testing process, only the temperature of the sorting machine cavity where the chip is located reaches the temperature of the low-temperature test, normal temperature test, and high temperature test, and it cannot be guaranteed that the temperature of the chip reaches the temperature of the low-temperature test, normal temperature test, and high temperature test. Therefore, in the existing chip testing process, the accuracy of the chip parameters collected by the chip under the three-temperature test cannot be guaranteed.

[0062] Based on the problems existing in the prior art, in the chip temperature detection method provided in the embodiment of the present disclosure, the preferred test machine outputs a target control signal to the sorting machine based on the target selection operation triggered by the target object, so that the sorting machine controls the sorting machine cavity to rise to a preset temperature after receiving the target control signal.

[0063] S120: The tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter based on the voltage information.

[0064] In addition, the tester is not only connected to the sorter for communication, but also connected to the chip to be tested through the test board on which the chip to be tested is placed.

[0065] In a specific embodiment, the tester obtains the voltage information of the chip to be tested in the sorting machine, and determines the actual temperature of the chip to be tested in the sorting machine based on the voltage information, including: the tester collects the sampling voltage of the chip to be tested inside the sorting machine at a sampling moment; the tester determines the actual temperature of the chip to be tested in the sorting machine at the sampling moment based on the sampling voltage, the reference temperature and the reference voltage.

[0066] The tester obtains the sampling voltage of the chip to be tested in the sorter at different sampling times by placing the test board on which the chip to be tested is placed, and then determines the actual temperature of the chip to be tested in the sorter at the sampling time based on the sampling voltage, reference temperature and reference voltage.

[0067] Specifically, the actual temperature of the chips to be tested in the sorter satisfies:

[0068] T=TReference+(V-VReference)*α

[0069] Wherein, T is the actual temperature of the chip to be tested in the sorter, V is the sampling voltage of the chip to be tested in the sorter, TReference is the reference temperature, VReference is the reference voltage, and α is the temperature voltage coefficient.

[0070] The temperature voltage coefficient is a preset value. The reference voltage under low temperature test is based on the low temperature test scenario (for example, -40 degrees Celsius, that is, the reference temperature under low temperature test is -40 degrees Celsius), given a fixed current, and the voltages of N test chips under the fixed current are collected separately, and the average is obtained; the reference voltage under normal temperature test is based on the normal temperature test scenario (for example, 25 degrees Celsius, that is, the reference temperature under normal temperature test is 25 degrees Celsius), given a fixed current, and the voltages of N test chips under the fixed current are collected separately, and the average is obtained; the reference voltage under high temperature test is based on the high temperature test scenario (for example, 125 degrees Celsius, that is, the reference temperature under high temperature test is 125 degrees Celsius), given a fixed current, and the voltages of N test chips under the fixed current are collected separately, and the average is obtained.

[0071] S130 , the tester determines a target adjustment signal according to a relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity.

[0072] In a specific embodiment, the tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, including:

[0073] When the actual temperature of the chip to be tested in the sorting machine is lower than the preset temperature of the sorting machine cavity, the first target adjustment signal is determined according to the difference information between the preset temperature of the sorting machine cavity and the actual temperature of the chip to be tested in the sorting machine; when the actual temperature of the chip to be tested in the sorting machine is higher than the preset temperature of the sorting machine cavity, the second target adjustment signal is determined according to the difference information between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity.

[0074] In a specific implementation method, when the actual temperature of the chip to be tested in the sorting machine is lower than the preset temperature of the sorting machine cavity, a first target adjustment signal is output; when the actual temperature of the chip to be tested in the sorting machine is higher than the preset temperature of the sorting machine cavity, a second target adjustment signal is output. The specific sizes of the output first target adjustment signal and the second target adjustment signal that need to be adjusted are based on the relationship between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity.

[0075] Therefore, before executing step S130, it also includes: the tester obtains the temperature adjustment value of the sorting machine cavity under different temperature differences, wherein the temperature difference is the absolute value of the difference between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity.

[0076] First, the temperature adjustment value of the sorting machine cavity is obtained under different temperature differences, and then the target adjustment signal is output according to the relationship between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity. When the actual temperature of the chip to be tested in the sorting machine is lower than the preset temperature of the sorting machine cavity, the temperature adjustment value corresponding to the temperature difference is found according to the temperature difference between the preset temperature of the sorting machine cavity and the actual temperature of the chip to be tested in the sorting machine, and then the first target adjustment signal is output to the sorting machine to make the sorting machine increase the temperature of the sorting machine cavity by the temperature adjustment value. When the actual temperature of the chip to be tested in the sorting machine is higher than the preset temperature of the sorting machine cavity, the temperature adjustment value corresponding to the temperature difference is found according to the temperature difference between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity, and then the second target adjustment signal is output to the sorting machine to make the sorting machine lower the temperature of the sorting machine cavity by the temperature adjustment value.

[0077] S140, the testing machine outputs a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on the preset temperature after receiving the target adjustment signal.

[0078] After determining the target adjustment signal, the tester outputs the target adjustment signal to the sorter. The sorter receives the target adjustment signal output by the tester and adjusts the temperature of the sorter cavity so that under the three-temperature test, the actual temperature of the chip to be tested in the sorter cavity meets the three-temperature test requirements, thereby improving the test accuracy of the chip to be tested.

[0079] Based on the above embodiment, the method provided in the embodiment of the present disclosure further includes:

[0080] When the actual temperature of the chip to be tested is the same as the preset temperature of the sorting machine cavity, the tester outputs a test signal to the sorting machine to enable the sorting machine to test the chip to be tested and sends the obtained test parameters of the chip to be tested to the tester.

[0081] In the above embodiment, after the test machine outputs the target adjustment signal to the sorting machine, the sorting machine will adjust the temperature of the sorting machine cavity. After the temperature of the sorting machine cavity is adjusted, the sampling voltage of the chip to be tested will change, and the test machine will obtain the sampling voltage of the chip to be tested in the sorting machine cavity again, and then determine the actual temperature of the chip to be tested in the sorting machine according to the sampling voltage, reference temperature and reference voltage of the chip to be tested. When the actual temperature of the chip to be tested is the same as the preset temperature of the sorting machine cavity, the test machine outputs a test signal to the sorting machine to make the sorting machine test the chip to be tested, and receives the sample voltage. The test machine collects the test parameters of the chip to be tested collected by the sorting machine. After receiving the test parameters of the chip to be tested collected by the sorting machine, the test machine determines whether the chip to be tested meets the design requirements by comparing the test parameters of the chip to be tested with the preset parameters. When the chip to be tested meets the design requirements, the test machine outputs an indication signal to instruct the sorting machine to flow the chip to be tested into the normal workpiece area. When the chip to be tested does not meet the design requirements, the test machine outputs an indication signal to instruct the sorting machine to flow the chip to be tested into the abnormal workpiece area, thereby realizing accurate wafer testing of each chip to be tested under different test modes.

[0082] The chip temperature detection method provided by the embodiment of the present disclosure is as follows: first, the tester responds to the target selection operation triggered by the target object and outputs a target control signal to the sorter, so that the sorter controls the temperature of the sorter cavity to rise to a preset temperature after receiving the target control signal; then the tester obtains the voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter based on the voltage information; then the tester determines the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity; finally, the tester outputs the target adjustment signal to the sorter, so that the sorter controls the temperature of the sorter cavity to be adjusted based on the preset temperature after receiving the target adjustment signal. By collecting the relationship between the actual temperature of the chip to be tested during the test process and the preset temperature of the sorter cavity, the temperature of the sorter cavity is adjusted, thereby ensuring that the temperature of the chip to be tested reaches the temperature in the test mode selected by the target object, and ensuring the accuracy of the chip parameters collected under the three-temperature test.

[0083] Based on the above embodiments, Figure 3This is a flow chart of another chip temperature detection method provided by an embodiment of the present disclosure. The chip temperature detection method is applied to a sorting machine of a chip temperature detection system, combined with Figure 2 、 Figure 3 ,The specific process of the chip temperature detection method includes:

[0084] S210 , the sorting machine receives the target control signal output by the testing machine, and controls the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal.

[0085] Among them, different target control signals correspond to different preset temperatures.

[0086] Specifically, after the sorting machine receives the target control signal output by the testing machine, the sorting machine controls the high and low temperature hot and cold hedge instrument based on the target control signal output by the testing machine, so as to raise the temperature in the sorting machine cavity to the target test temperature corresponding to the test mode based on the high and low temperature hot and cold hedge instrument. For example, if the test mode selected by the target object is low temperature test, the high and low temperature hot and cold hedge instrument of the sorting machine controls the temperature in the sorting machine cavity to -40 degrees Celsius; if the test mode selected by the target object is normal temperature test, the high and low temperature hot and cold hedge instrument of the sorting machine controls the temperature in the sorting machine cavity to 25 degrees Celsius; if the test mode selected by the target object is high temperature test, the high and low temperature hot and cold hedge instrument of the sorting machine controls the temperature in the sorting machine cavity to 125 degrees Celsius.

[0087] S220: The sorting machine receives the target adjustment signal output by the testing machine, and adjusts the temperature of the sorting machine cavity according to the target adjustment signal.

[0088] When the sorter receives the target adjustment signal output by the tester, it adjusts the temperature of the sorter cavity so that under the three-temperature test, the actual temperature of the chip to be tested in the sorter cavity meets the three-temperature test requirements, thereby improving the test accuracy of the chip to be tested.

[0089] It should be noted that the chip temperature detection method provided in the above embodiment is applied to the chip mass production test process. Before the chip mass production test is carried out, a fixed current is given, and the voltages of N test chips under the fixed current are collected separately in a low-temperature test environment (the temperature of the sorting machine cavity is -40 degrees Celsius), and the average is obtained to obtain the reference voltage under the low-temperature test; a fixed current is given, and the voltages of N test chips under the fixed current are collected separately in a normal temperature test environment (the temperature of the sorting machine cavity is 25 degrees Celsius), and the average is obtained to obtain the reference voltage under the normal temperature test; a fixed current is given, and the voltages of N test chips under the fixed current are collected separately in a high-temperature test environment (the temperature of the sorting machine cavity is 125 degrees Celsius), and the average is obtained to obtain the reference voltage under the high-temperature test.

[0090] On the basis of the above embodiments, the present disclosure also provides a chip temperature detection device, such as Figure 4 As shown, the chip temperature detection device includes:

[0091] The target control signal output module 410 is configured to output a target control signal to the sorting machine in response to receiving a target selection operation triggered by a target object, so that the sorting machine controls the temperature of the sorting machine cavity to rise to a preset temperature after receiving the target control signal, wherein the target selection operation is used to select a test mode for the chip to be tested, and the test modes for the chip to be tested include low temperature test, normal temperature test, and high temperature test;

[0092] The actual temperature determination module 420 is used to obtain voltage information of the chip to be tested in the sorting machine and determine the actual temperature of the chip to be tested in the sorting machine based on the voltage information;

[0093] A target adjustment signal determination module 430 is configured to determine a target adjustment signal based on a relationship between an actual temperature of the chips to be tested in the sorting machine and a preset temperature of the sorting machine cavity;

[0094] The adjustment signal output module 440 is used to output a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on a preset temperature after receiving the target adjustment signal.

[0095] The chip temperature detection device provided by the embodiment of the present disclosure first outputs a target control signal to the sorter in response to receiving a target selection operation triggered by a target object, so that the sorter controls the temperature of the sorter cavity to rise to a preset temperature after receiving the target control signal; then the tester obtains the voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter based on the voltage information; then the tester determines the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity; finally, the tester outputs the target adjustment signal to the sorter, so that the sorter controls the temperature of the sorter cavity to be adjusted based on the preset temperature after receiving the target adjustment signal. By collecting the relationship between the actual temperature of the chip to be tested during the test process and the preset temperature of the sorter cavity, the temperature of the sorter cavity is adjusted, thereby ensuring that the temperature of the chip to be tested reaches the temperature in the test mode selected by the target object, and ensuring the accuracy of the chip parameters collected under the three-temperature test.

[0096] In a specific embodiment, the tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter according to the voltage information, including:

[0097] The tester collects a sample voltage of the chip to be tested inside the sorter at a sampling moment;

[0098] The tester determines the actual temperature of the chip to be tested in the sorter at the sampling moment according to the sampled voltage, the reference temperature and the reference voltage.

[0099] In a specific embodiment, the tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, including:

[0100] When the actual temperature of the chip to be tested in the sorter is lower than the preset temperature of the sorter cavity, determining a first target adjustment signal according to information of a difference between the preset temperature of the sorter cavity and the actual temperature of the chip to be tested in the sorter;

[0101] When the actual temperature of the chip to be tested in the sorter is greater than the preset temperature of the sorter cavity, a second target adjustment signal is determined according to the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity.

[0102] In a specific embodiment, the tester further includes, before determining the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity:

[0103] The tester obtains temperature adjustment values ​​of the sorter cavity under different temperature differences, wherein the temperature difference is the absolute value of the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity;

[0104] The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity, including:

[0105] The tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, as well as the temperature adjustment value of the sorter cavity under different temperature differences.

[0106] In a specific embodiment, it also includes:

[0107] When the actual temperature of the chip to be tested is the same as the preset temperature of the sorting machine cavity, the tester outputs a test signal to the sorting machine to enable the sorting machine to test the chip to be tested and sends the obtained test parameters of the chip to be tested to the tester.

[0108] Based on the above embodiments, the present disclosure also provides another chip temperature detection device, such as Figure 5As shown, the chip temperature detection device includes:

[0109] The control module 401 is configured to receive a target control signal output by the tester and control the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal, wherein different target control signals correspond to different preset temperatures;

[0110] The adjustment module 402 is configured to receive a target adjustment signal output by the tester and adjust the temperature of the sorting machine cavity according to the target adjustment signal.

[0111] The present application also provides a computer device. Figure 6 , Figure 6 This is a basic structural block diagram of the computer device in this embodiment.

[0112] The computer device includes a memory 510 and a processor 520 that are interconnected and communicate with each other via a system bus. It should be noted that the figure only shows a computer device having components 510-520, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0113] Computer devices can be desktop computers, laptops, PDAs, cloud servers, etc. Computer devices can interact with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0114] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (such as SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, or a Flash Card equipped on the computer device. Of course, the memory 510 may also include both the internal storage unit of the computer device and its external storage device. In this embodiment, the memory 510 is generally used to store the operating system and various application software installed on the computer device, such as the program code of the above-mentioned method. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or are about to be output.

[0115] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program code or instructions, which include computer operating instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or process data, such as the program code for running the above method.

[0116] In this article, a bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. This bus system can be divided into address buses, data buses, and control buses. For ease of illustration, the figure uses only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0117] Another embodiment of the present application further provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads the computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method, and to generate a device that implements the functional actions specified in each block or combination of blocks in the block diagram.

[0118] Computer-readable media include but are not limited to electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any appropriate combination of the foregoing, the memory is used to store program codes or instructions, the program codes include computer operating instructions, and the processor is used to execute the program codes or instructions of the above-mentioned methods stored in the memory.

[0119] The definitions of memory and processor can be found in the description of the aforementioned computer device embodiment and will not be repeated here.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0121] Each functional unit or module in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0122] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0123] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0124] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0125] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A chip temperature detection method, applied to a tester of a chip temperature detection system, wherein the chip temperature detection system further comprises a sorter, wherein the sorter is communicatively connected to the tester, and a temperature test is performed on a chip to be tested in the sorter, wherein the tester is communicatively connected to the chip to be tested via a test board, wherein: include: The tester outputs a target control signal to the sorter in response to receiving a target selection operation triggered by a target object, so that the sorter controls the temperature of the sorter cavity to rise to a preset temperature after receiving the target control signal, wherein the target selection operation is used to select a test mode for the chip to be tested, and the test modes for the chip to be tested include low temperature test, normal temperature test, and high temperature test; The tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter according to the voltage information; The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity; The testing machine outputs a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on a preset temperature after receiving the target adjustment signal.

2. The method according to claim 1, characterized in that The tester obtains voltage information of the chip to be tested in the sorter, and determines the actual temperature of the chip to be tested in the sorter according to the voltage information, including: The tester collects a sample voltage of the chip to be tested inside the sorter at a sampling moment; The tester determines the actual temperature of the chip to be tested in the sorter at the sampling moment according to the sampled voltage, the reference temperature and the reference voltage.

3. The method according to claim 1, characterized in that The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity, including: When the actual temperature of the chip to be tested in the sorter is lower than the preset temperature of the sorter cavity, determining a first target adjustment signal according to information of a difference between the preset temperature of the sorter cavity and the actual temperature of the chip to be tested in the sorter; When the actual temperature of the chip to be tested in the sorter is greater than the preset temperature of the sorter cavity, a second target adjustment signal is determined according to the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity.

4. The method according to claim 3, characterized in that Before determining the target adjustment signal based on the relationship between the actual temperature of the chip to be tested in the sorting machine and the preset temperature of the sorting machine cavity, the test machine further includes: The tester obtains temperature adjustment values ​​of the sorter cavity under different temperature differences, wherein the temperature difference is the absolute value of the difference between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity; The tester determines a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorter and a preset temperature of the sorter cavity, including: The tester determines the target adjustment signal according to the relationship between the actual temperature of the chip to be tested in the sorter and the preset temperature of the sorter cavity, as well as the temperature adjustment value of the sorter cavity under different temperature differences.

5. The method according to claim 1, wherein Also includes: When the actual temperature of the chip to be tested is the same as the preset temperature of the sorting machine cavity, the tester outputs a test signal to the sorter to enable the sorter to test the chip to be tested and sends the obtained test parameters of the chip to be tested to the tester.

6. A chip temperature detection method, applied to a sorter of a chip temperature detection system, wherein the chip temperature detection system further comprises a tester, wherein the sorter and the tester are communicatively connected, and a chip to be tested is placed in a cavity of the sorter for temperature testing, wherein the tester is communicatively connected to the chip to be tested, wherein: include: The sorting machine receives the target control signal output by the testing machine, and controls the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal, wherein different target control signals correspond to different preset temperatures; The sorting machine receives the target adjustment signal output by the testing machine, and adjusts the temperature of the sorting machine cavity according to the target adjustment signal.

7. A chip temperature detection device, applied to a tester of a chip temperature detection system, wherein the chip temperature detection system further comprises a sorter, wherein the sorter is communicatively connected to the tester, and the temperature of the chip to be tested is tested in the sorter, wherein the tester is communicatively connected to the chip to be tested via a test board, wherein the device is characterized in that: include: a target control signal output module, configured to output a target control signal to a sorting machine in response to receiving a target selection operation triggered by a target object, so that the sorting machine controls the temperature of the sorting machine cavity to rise to a preset temperature after receiving the target control signal, wherein the target selection operation is used to select a test mode for the chip to be tested, and the test modes for the chip to be tested include low-temperature test, normal-temperature test, and high-temperature test; an actual temperature determination module, configured to obtain voltage information of the chip to be tested in the sorting machine, and determine the actual temperature of the chip to be tested in the sorting machine based on the voltage information; a target adjustment signal determination module, configured to determine a target adjustment signal according to a relationship between an actual temperature of the chip to be tested in the sorting machine and a preset temperature of the sorting machine cavity; The adjustment signal output module is used to output a target adjustment signal to the sorting machine, so that the sorting machine controls the temperature of the sorting machine cavity to be adjusted based on a preset temperature after receiving the target adjustment signal.

8. A chip temperature detection device, applied to a sorter of a chip temperature detection system, wherein the chip temperature detection system further comprises a tester, wherein the sorter and the tester are communicatively connected, and a chip to be tested is placed in a cavity of the sorter for temperature testing, wherein the tester is communicatively connected to the chip to be tested, wherein: include: a control module, configured to receive a target control signal output by the test machine, and control the temperature of the sorting machine cavity to rise to a preset temperature according to the target control signal, wherein different target control signals correspond to different preset temperatures; The regulating module is used to receive the target regulating signal output by the testing machine and regulate the temperature of the sorting machine cavity according to the target regulating signal.

9. A computer device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 5 or the method according to claim 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 5 or the method according to claim 6 is implemented.

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