Display panel

Abstract

The invention provides a display panel which comprises an array substrate, the array substrate comprises a plurality of pixel units, and each pixel unit comprises a first display area and a second display area. The array substrate further comprises a substrate; the first electrode layer is arranged on the substrate and comprises a first electrode located in the first display area and a second electrode located in the second display area; at least one passivation layer disposed over the first electrode layer; and the second electrode layer is arranged above the passivation layer and comprises a third electrode which is positioned in the first display area and is electrically connected with the first electrode, and a fourth electrode which is positioned in the second display area and is electrically connected with the second electrode. The first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the first capacitor and the second capacitor are different in capacitance. Capacitors with different capacitance sizes are arranged in different display areas, driving voltages of the different display areas are controlled, then the liquid crystal deflection angles of the different display areas are controlled, adjustment of pictures with different visual angles is achieved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the development of liquid crystal display technology, people have increasingly higher requirements for LCD display quality. Liquid crystal displays (LCDs) include various display modes, such as vertical alignment (VA) and fringe field switching (FFS). However, existing LCDs, regardless of the display mode, suffer from poor viewing angles. Summary of the Invention

[0003] The present application aims to provide a display panel, which aims to adjust the images of the existing display panel at different viewing angles and improve the display effect.

[0004] An embodiment of the present application provides a display panel, which includes an array substrate, the array substrate including a plurality of pixel units, each of the pixel units including a first display area and a second display area, the array substrate further including: a substrate; a first electrode layer, the first electrode layer being arranged on the substrate, the first electrode layer including a first electrode and a second electrode, the first electrode being located in the first display area, and the second electrode being located in the second display area; at least one passivation layer, the passivation layer being arranged above the first electrode layer; and a second electrode layer, the second electrode layer being arranged above the passivation layer, the second electrode layer including a third electrode and a fourth electrode, the third electrode being located in the first display area and electrically connected to the first electrode, the fourth electrode being located in the second display area and electrically connected to the second electrode; wherein the first electrode and the third electrode constitute a first capacitor, the second electrode and the fourth electrode constitute a second capacitor, and the capacitances of the first capacitor and the second capacitor are different.

[0005] In the above display panel, a thickness of the passivation layer in the first display area is different from a thickness of the passivation layer in the second display area.

[0006] In the above-mentioned display panel, the passivation layer includes: a first passivation layer, which is arranged above the first electrode layer; and a second passivation layer, which is arranged above the first passivation layer; wherein the thickness of at least one of the first passivation layer and the second passivation layer in the first display area is different from the thickness in the second display area.

[0007] In the above display panel, the passivation layer further includes a third passivation layer, the third passivation layer is disposed above the second passivation layer, and the third passivation layer is only disposed in the second display area.

[0008] In the above display panel, the third electrode is electrically connected to the first electrode through a first via hole, and the fourth electrode is electrically connected to the second electrode through a second via hole.

[0009] In the above-mentioned display panel, the passivation layer includes: a first passivation layer, the first passivation layer is arranged above the first electrode layer, and a third via and a fourth via are arranged on the first passivation layer, the third via is located above the first electrode in the first display area, and the fourth via is located above the second electrode in the second display area; wherein, the third via is a via formed by the first via on the first passivation layer, and the fourth via is a via formed by the second via on the first passivation layer.

[0010] In the above-mentioned display panel, the passivation layer also includes: a second passivation layer, the second passivation layer is arranged above the first passivation layer, and a fifth via hole and a sixth via hole are arranged on the second passivation layer, the fifth via hole is located above the third via hole in the first display area, and the sixth via hole is located above the fourth via hole in the second display area; wherein, the fifth via hole is a via hole formed by the first via hole on the second passivation layer, and the sixth via hole is a via hole formed by the second via hole on the second passivation layer.

[0011] In the above display panel, the third electrode is located inside the third via hole and the fifth via hole and in a partial area above the second passivation layer close to the fifth via hole.

[0012] In the above-mentioned display panel, the passivation layer also includes: a third passivation layer, the third passivation layer is arranged above the second passivation layer, and the third passivation layer is provided with a seventh via hole at a position above the sixth via hole in the second display area; wherein the seventh via hole is a via hole formed by the second via hole on the third passivation layer.

[0013] In the above display panel, the fourth electrode is disposed inside the fourth via hole, the sixth via hole, the seventh via hole, and a partial area above the third passivation layer close to the seventh via hole.

[0014] The display panel provided herein utilizes an array substrate with multiple pixel units, each including a first display area and a second display area, and capacitors of varying capacitance are provided in the different display areas. This allows for adjustment of images at different viewing angles, thereby improving display quality. Specifically, the display panel of the present invention includes a substrate, a first electrode layer, at least one passivation layer, and a second electrode layer. The first electrode layer is provided on the substrate and includes a first electrode located in the first display area and a second electrode located in the second display area. The second electrode layer is provided above the passivation layer and includes a third electrode located in the first display area and electrically connected to the first electrode, and a fourth electrode located in the second display area and electrically connected to the second electrode. The first and third electrodes form a first capacitor, while the second and fourth electrodes form a second capacitor, and the first and second capacitors have different capacitances. Due to the different capacitances of the first and second capacitors, when the same voltage is applied, the charge on the two capacitors differs, resulting in different voltages across the two capacitors. This voltage difference causes the liquid crystal molecules in the first and second display areas to have different deflection angles, resulting in different display effects at different viewing angles. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic structural diagram of an embodiment of an array substrate provided in an embodiment of the present application;

[0017] Figure 2 A schematic structural diagram of another embodiment of the array substrate provided in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of the structure of the third electrode prepared according to an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the structure of preparing the third passivation layer provided in an embodiment of the present application;

[0020] Figure 5 This is a schematic diagram of the structure for preparing the fourth electrode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0022] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0023] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0024] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which are described in detail below.

[0025] like Figure 1 The figure shows a schematic structural diagram of an embodiment of an array substrate provided in an embodiment of the present application. Figure 1 In the embodiment shown, the array substrate includes a plurality of pixel units, each pixel unit includes a first display area and a second display area, and the array substrate includes:

[0026] substrate 10;

[0027] The first electrode layer 20 does not completely cover the substrate 10 . The first electrode layer 20 includes a first electrode 201 and a second electrode 202 . The first electrode 201 is located in the first display area, and the second electrode 202 is located in the second display area.

[0028] The second electrode layer 30 is located above the first electrode layer 20. The second electrode layer 30 includes a third electrode 301 and a fourth electrode 302. The third electrode 301 is located in the first display area and connected to the first electrode 201 through a first via hole. The fourth electrode 302 is located in the second display area and connected to the second electrode 202 through a second via hole.

[0029] The first electrode 201 and the third electrode 301 form a first capacitor, and the second electrode 202 and the fourth electrode 302 form a second capacitor. The capacitances of the first capacitor and the second capacitor are different.

[0030] The array substrate provided in an embodiment of the present application includes a first display area and a second display area, and further includes: a substrate; a first electrode layer, the first electrode layer does not completely cover the substrate, the first electrode layer includes a first electrode and a second electrode, the first electrode is located in the first display area, and the second electrode is located in the second display area; a second electrode layer, the second electrode layer is located above the first electrode layer, the second electrode layer includes a third electrode and a fourth electrode, the third electrode is located in the first display area and electrically connected to the first electrode through a first via hole, and the fourth electrode is located in the second display area and electrically connected to the second electrode through a second via hole; wherein the first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the capacitance of the first capacitor and the second capacitor are different. By setting capacitors of different capacitance values ​​in different display areas of the array substrate, the present application can control the driving voltage of different display areas, thereby controlling the liquid crystal deflection angle of different display areas, thereby achieving adjustment of images with different viewing angles.

[0031] like Figure 2 FIG. 1 is a structural diagram of another embodiment of the array substrate provided in the embodiment of the present application. Figure 2 In the embodiment shown, the array substrate also includes a first passivation layer 40, which is arranged above the first electrode layer 20, and the first passivation layer 40 completely covers the substrate 10 and the first electrode layer 20; that is, the first passivation layer completely covers the first electrode layer 20, and other areas on the substrate 10 except the first electrode layer 20.

[0032] A third via hole and a fourth via hole are also provided on the first passivation layer 40. The third via hole is located above the first electrode 201 in the first display area, and the fourth via hole is located above the second electrode 202 in the second display area. In other words, the third via hole is located corresponding to the first electrode 201, and the fourth via hole is located corresponding to the second electrode 202.

[0033] The third via hole is the via hole formed on the first passivation layer 40 of the aforementioned first via hole, and the fourth via hole is the via hole formed on the first passivation layer 40 of the second via hole.

[0034] Please refer to Figure 2 ,exist Figure 2 In the embodiment, the array substrate further includes a second passivation layer 50, which is disposed above the first passivation layer 40 and completely covers the first passivation layer 40. A fifth via hole and a sixth via hole are also disposed on the second passivation layer 50. The fifth via hole is located above the third via hole in the first display area, and the sixth via hole is located above the fourth via hole in the second display area. In other words, the third via hole and the fifth via hole are disposed in correspondence with each other, and the fourth via hole and the sixth via hole are disposed in correspondence with each other.

[0035] The fifth via hole is a via hole formed on the second passivation layer 50 by the first via hole, and the sixth via hole is a via hole formed on the second passivation layer 50 by the second via hole.

[0036] It should be noted that the third electrode is located inside the third and fifth vias, as well as in a portion of the area above the second passivation layer 50 near the fifth via; the third electrode completely fills the interiors of the third and fifth vias. The third electrode 301 is connected to the first electrode 201 through the third and fifth vias (i.e., the first via), and the third electrode 301 and the first electrode 201 form a first capacitor in the first display area.

[0037] Please refer to Figure 2 ,exist Figure 2 The middle array substrate further includes a third passivation layer 60, which completely covers the second passivation layer 50 and the third electrode 301. However, a seventh via hole is provided in the third passivation layer 60 above the sixth via hole in the second display area. The seventh via hole is formed on the third passivation layer 60 from the second via hole. In some embodiments, the third passivation layer 60 may be provided only in the second display area.

[0038] At this time, the fourth via hole, the sixth via hole and the seventh via hole constitute a second via hole, and the fourth electrode 302 is arranged inside the fourth via hole, the sixth via hole and the seventh via hole, and a portion of the area above the third passivation layer 60 near the seventh via hole. Figure 2As shown, at this time, the fourth electrode 302 is connected to the second electrode 202 through the fourth via hole, the sixth via hole and the seventh via hole (ie, the second via hole), and the fourth electrode 302 and the second electrode 202 constitute a second capacitor in the second display area.

[0039] At this time, the first display area includes a first capacitor, and the second display area includes a second capacitor; and the capacitance value of the capacitor is inversely proportional to the distance between the two electrodes of the capacitor, so the distance between the two electrodes of the capacitor can be adjusted to adjust the size of the capacitor. For the embodiment of the present application, the size of the capacitance value can be adjusted by adjusting the thickness of the passivation layer; specifically, the thickness of the passivation layer in the first display area is different from the thickness of the passivation layer in the second display area. Among them, the thickness of at least one of the first passivation layer and the second passivation layer in the first display area is different from the thickness in the second display area. Specifically, adjusting the size of the first capacitor can be achieved by adjusting the thickness of the first passivation layer 40 and the second passivation layer 50; and adjusting the size of the second capacitor can be achieved by adjusting the thickness of the first passivation layer 40, the second passivation layer 50 and the third passivation layer 60.

[0040] By adjusting the thickness of the passivation layer, the first and second capacitors are adjusted, and the voltage across the first and second capacitors is adjusted to adjust the liquid crystal deflection angle. The liquid crystal deflection angle affects the image ultimately displayed on the display panel. Therefore, in the embodiment of the present application, two capacitors are provided, and the image on the display panel is adjusted by adjusting the distance between the electrodes of the two capacitors.

[0041] The embodiment of the present application further provides a display panel, which includes the array substrate as described in any one of the above items. Figure 1 The figure shows a schematic structural diagram of an embodiment of an array substrate provided in an embodiment of the present application. Figure 1 In the embodiment shown, the array substrate includes a first display area and a second display area, and the array substrate includes:

[0042] substrate 10;

[0043] The first electrode layer 20 does not completely cover the substrate 10 . The first electrode layer 20 includes a first electrode 201 and a second electrode 202 . The first electrode 201 is located in the first display area, and the second electrode 202 is located in the second display area.

[0044] The second electrode layer 30 is located above the first electrode layer 20. The second electrode layer 30 includes a third electrode 301 and a fourth electrode 302. The third electrode 301 is located in the first display area and connected to the first electrode 201 through a first via hole. The fourth electrode 302 is located in the second display area and connected to the second electrode 202 through a second via hole.

[0045] The first electrode 201 and the third electrode 301 form a first capacitor, and the second electrode 202 and the fourth electrode 302 form a second capacitor. The capacitances of the first capacitor and the second capacitor are different.

[0046] The display panel provided in an embodiment of the present application includes the array substrate as described above, the array substrate including a first display area and a second display area, and further including: a substrate; a first electrode layer, the first electrode layer not completely covering the substrate, the first electrode layer including a first electrode and a second electrode, the first electrode being located in the first display area, and the second electrode being located in the second display area; a second electrode layer, the second electrode layer being located above the first electrode layer, the second electrode layer including a third electrode and a fourth electrode, the third electrode being located in the first display area and electrically connected to the first electrode through a first via hole, and the fourth electrode being located in the second display area and electrically connected to the second electrode through a second via hole; wherein the first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the first capacitor and the second capacitor have different capacitances. By setting capacitors of different capacitances in different display areas of the array substrate, the present application can control the driving voltages of different display areas, thereby controlling the liquid crystal deflection angles of different display areas, thereby achieving adjustment of images with different viewing angles.

[0047] like Figure 2 FIG. 1 is a structural diagram of another embodiment of the array substrate provided in the embodiment of the present application. Figure 2 In the embodiment shown, the array substrate also includes a first passivation layer 40, which is arranged above the first electrode layer 20, and the first passivation layer 40 completely covers the substrate 10 and the first electrode layer 20; that is, the first passivation layer completely covers the first electrode layer 20, and other areas on the substrate 10 except the first electrode layer 20.

[0048] A third via hole and a fourth via hole are also provided on the first passivation layer 40. The third via hole is located above the first electrode 201 in the first display area, and the fourth via hole is located above the second electrode 202 in the second display area. In other words, the third via hole is located corresponding to the first electrode 201, and the fourth via hole is located corresponding to the second electrode 202.

[0049] The third via hole is the via hole formed on the first passivation layer 40 of the aforementioned first via hole, and the fourth via hole is the via hole formed on the first passivation layer 40 of the second via hole.

[0050] Please refer to Figure 2 ,exist Figure 2In the embodiment, the array substrate further includes a second passivation layer 50, which is disposed above the first passivation layer 40 and completely covers the first passivation layer 40. A fifth via hole and a sixth via hole are also disposed on the second passivation layer 50. The fifth via hole is located above the third via hole in the first display area, and the sixth via hole is located above the fourth via hole in the second display area. In other words, the third via hole and the fifth via hole are disposed in correspondence with each other, and the fourth via hole and the sixth via hole are disposed in correspondence with each other.

[0051] The fifth via hole is a via hole formed on the second passivation layer 50 by the first via hole, and the sixth via hole is a via hole formed on the second passivation layer 50 by the second via hole.

[0052] It should be noted that the third electrode is located inside the third and fifth vias, as well as in a portion of the area above the second passivation layer 50 near the fifth via; the third electrode completely fills the interiors of the third and fifth vias. The third electrode 301 is connected to the first electrode 201 through the third and fifth vias (i.e., the first via), and the third electrode 301 and the first electrode 201 form a first capacitor in the first display area.

[0053] Please refer to Figure 2 ,exist Figure 2 The middle array substrate further includes a third passivation layer 60, which completely covers the second passivation layer 50 and the third electrode 301. However, a seventh via hole is provided in the third passivation layer 60 above the sixth via hole in the second display area. The seventh via hole is formed on the third passivation layer 60 by the second via hole.

[0054] At this time, the fourth via hole, the sixth via hole and the seventh via hole constitute a second via hole, and the fourth electrode 302 is arranged inside the fourth via hole, the sixth via hole and the seventh via hole, and a portion of the area above the third passivation layer 60 near the seventh via hole. Figure 2 As shown, at this time, the fourth electrode 302 is connected to the second electrode 202 through the fourth via hole, the sixth via hole and the seventh via hole (ie, the second via hole), and the fourth electrode 302 and the second electrode 202 constitute a second capacitor in the second display area.

[0055] In this case, the first display area includes the first capacitor, and the second display area includes the second capacitor. The capacitance of a capacitor is inversely proportional to the distance between its two electrodes, so the distance between the two electrodes can be adjusted to adjust the capacitance. In this embodiment of the present application, the first capacitor can be adjusted by adjusting the thickness of the first passivation layer 40 and the second passivation layer 50. The second capacitor can be adjusted by adjusting the thickness of the first passivation layer 40, the second passivation layer 50, and the third passivation layer 60.

[0056] By adjusting the thickness of the passivation layer, the first and second capacitors are adjusted, and the voltage across the first and second capacitors is adjusted to adjust the liquid crystal deflection angle. The liquid crystal deflection angle affects the image ultimately displayed on the display panel. Therefore, in the embodiment of the present application, two capacitors are provided, and the image on the display panel is adjusted by adjusting the distance between the electrodes of the two capacitors.

[0057] like Figure 3 The figure shows a schematic diagram of the structure of the third electrode prepared in the embodiment of the present application. Figure 3 In the embodiment, a third via hole is provided at a position corresponding to the first electrode 201 on the first passivation layer 40, and a fifth via hole is provided at a position corresponding to the second via hole on the second passivation layer 50. At this time, the material of the third electrode 301 is deposited on the second passivation layer 50 and inside the third and fifth via holes using a method such as chemical vapor deposition (CVD), so that the material of the third electrode 301 completely covers the second passivation layer 50 and inside the third and fifth via holes.

[0058] At this time, the third electrode material completely covering the second passivation layer 50 needs to be etched to remove part of the third electrode material located in the second display area, leaving only part of the third electrode material located in the first display area and close to the fifth via hole to obtain the third electrode 301.

[0059] like Figure 4 The figure shows a schematic diagram of the structure of preparing the third passivation layer provided in the embodiment of the present application. Figure 4 In the embodiment, it is necessary to coat the third passivation layer 60 material on the second passivation layer 50 and the third electrode using a method such as CVD, so that the third passivation layer material completely covers the second passivation layer 50 and the third electrode.

[0060] After coating the third passivation layer, the fourth electrode needs to be prepared. Figure 5 The figure shows a schematic diagram of the structure for preparing the fourth electrode according to an embodiment of the present application. Specifically, the fourth, sixth, and seventh vias are first prepared in the second display area. Specifically, the seventh via is prepared on the third passivation layer, the sixth via is prepared on the second passivation layer, and the fourth via is prepared on the first passivation layer. The fourth, sixth, and seventh vias are positioned correspondingly, ultimately forming a second via that penetrates the first, second, and third passivation layers.

[0061] After the second via hole is prepared, a fourth electrode material is coated on the third passivation layer and inside the second via hole using a CVD method, so that the fourth electrode material completely covers the third passivation layer and the inside of the second via hole. Figure 5 As shown, the uppermost layer is the coated fourth electrode material.

[0062] To obtain the final fourth electrode, the coated fourth electrode material needs to be etched to remove a portion of the fourth electrode material, leaving only a portion of the fourth electrode material near the second via hole (i.e., the seventh via hole) in the second display area. The fourth electrode and the second electrode constitute the second capacitor in the second display area.

[0063] Please refer to Figure 2 , Figure 2 The complete structural diagram of the array substrate provided in the embodiment of the present application. Figure 2 In the embodiment, the third passivation layer completely covers the third electrode, and the fourth electrode is partially disposed above the third passivation layer.

[0064] It should be noted that in the embodiments of the present application, the capacitance of the first capacitor and the second capacitor is adjusted mainly by adjusting the thickness of the passivation layer; however, in other embodiments, this can also be achieved by adjusting the electrode area in the capacitor, specifically by adjusting the area of ​​the first electrode 201, the second electrode 202, the third electrode 301 and the fourth electrode 302. However, if the capacitance is adjusted by adjusting the electrode area, it is necessary to prepare masks of different areas so that the prepared electrode areas are different, but this is not easy to adjust the electrode area in real time. Compared with preparing a new mask, it is easier to change the thickness of the passivation layer during the preparation of the passivation layer; therefore, the embodiment of the present application changes the capacitance by changing the thickness of the passivation layer.

[0065] The present application further provides a method for preparing an array substrate, the array substrate including the array substrate as described in any one of the above items, the array substrate including a first display area and a second display area; the method for preparing the array substrate may include:

[0066] providing a substrate;

[0067] preparing a first electrode layer above the substrate, the first electrode layer not completely covering the substrate, the first electrode layer including a first electrode and a second electrode, the first electrode being located in the first display area, and the second electrode being located in the second display area;

[0068] A second electrode layer is prepared above the first electrode layer, the second electrode layer is located above the first electrode layer, the second electrode layer includes a third electrode and a fourth electrode, the third electrode is located in the first display area and is electrically connected to the first electrode through the first via hole, and the fourth electrode is located in the second display area and is electrically connected to the second electrode through the second via hole;

[0069] The first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the capacitances of the first capacitor and the second capacitor are different.

[0070] The array substrate prepared by the method for preparing an array substrate provided in an embodiment of the present application includes a first display area and a second display area, and further includes: a substrate; a first electrode layer, wherein the first electrode layer does not completely cover the substrate, the first electrode layer includes a first electrode and a second electrode, the first electrode being located in the first display area and the second electrode being located in the second display area; a second electrode layer, wherein the second electrode layer is located above the first electrode layer, the second electrode layer includes a third electrode and a fourth electrode, the third electrode being located in the first display area and electrically connected to the first electrode through a first via hole, and the fourth electrode being located in the second display area and electrically connected to the second electrode through a second via hole; wherein the first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the first capacitor and the second capacitor have different capacitances. By setting capacitors of different capacitances in different display areas of the array substrate, the present application can control the driving voltage of different display areas, thereby controlling the liquid crystal deflection angles of different display areas, thereby achieving adjustment of images with different viewing angles.

[0071] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0072] In specific implementation, the above units or structures can be implemented as independent entities, or can be arbitrarily combined to implement as the same or several entities. The specific implementation of the above units or structures can refer to the previous method embodiments and will not be repeated here.

[0073] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0074] The above is a detailed introduction to an array substrate, a display panel and a method for preparing an array substrate provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes an array substrate, the array substrate includes a plurality of pixel units, each of the pixel units includes a first display area and a second display area, and the array substrate further includes: substrate; a first electrode layer, the first electrode layer being disposed on the substrate, the first electrode layer comprising a first electrode and a second electrode, the first electrode being located in the first display area, and the second electrode being located in the second display area; at least one passivation layer, the passivation layer being disposed above the first electrode layer; and a second electrode layer, the second electrode layer being disposed above the passivation layer, the second electrode layer comprising a third electrode and a fourth electrode, the third electrode being located in the first display area and electrically connected to the first electrode, the fourth electrode being located in the second display area and electrically connected to the second electrode; The first electrode and the third electrode form a first capacitor, the second electrode and the fourth electrode form a second capacitor, and the capacitances of the first capacitor and the second capacitor are different.

2. The display panel according to claim 1, wherein: The thickness of the passivation layer in the first display area is different from the thickness of the passivation layer in the second display area.

3. The display panel according to claim 1, wherein: The passivation layer comprises: a first passivation layer, the first passivation layer being disposed above the first electrode layer; a second passivation layer, the second passivation layer being disposed above the first passivation layer; Wherein, at least one of the first passivation layer and the second passivation layer has a thickness different in the first display area from that in the second display area.

4. The display panel according to claim 3, wherein: The passivation layer further includes a third passivation layer, the third passivation layer is disposed above the second passivation layer, and the third passivation layer is only disposed in the second display area.

5. The display panel according to claim 1, wherein: The third electrode is electrically connected to the first electrode through a first via hole, and the fourth electrode is electrically connected to the second electrode through a second via hole.

6. The display panel according to claim 5, wherein: The passivation layer comprises: a first passivation layer, the first passivation layer being disposed above the first electrode layer, and having a third via hole and a fourth via hole disposed on the first passivation layer, the third via hole being located above the first electrode in the first display area, and the fourth via hole being located above the second electrode in the second display area; The third via hole is a via hole formed by the first via hole on the first passivation layer, and the fourth via hole is a via hole formed by the second via hole on the first passivation layer.

7. The display panel according to claim 6, wherein: The passivation layer further comprises: a second passivation layer, the second passivation layer being disposed above the first passivation layer, a fifth via hole and a sixth via hole being disposed on the second passivation layer, the fifth via hole being located above the third via hole in the first display area, and the sixth via hole being located above the fourth via hole in the second display area; The fifth via hole is a via hole formed by the first via hole on the second passivation layer, and the sixth via hole is a via hole formed by the second via hole on the second passivation layer.

8. The display panel according to claim 7, wherein: The third electrode is located inside the third via hole and the fifth via hole and in a partial area above the second passivation layer close to the fifth via hole.

9. The display panel according to claim 7, wherein: The passivation layer further comprises: a third passivation layer, the third passivation layer being disposed above the second passivation layer, and the third passivation layer being provided with a seventh via hole at a position above the sixth via hole in the second display area; The seventh via hole is a via hole formed by the second via hole on the third passivation layer.

10. The display panel according to claim 9, wherein: The fourth electrode is disposed inside the fourth via hole, the sixth via hole, the seventh via hole, and in a partial area above the third passivation layer close to the seventh via hole.

Images