Memory semantic processing method and device, equipment, medium and product

Abstract

The embodiment of the invention provides a memory semantic processing method and device, equipment, a medium and a product. According to the method, a large memory semantic task can be split into a plurality of small sub-memory semantic tasks according to the memory semantic task and the core resource of the processor, so that the scale of the memory semantic task can be within the processing capacity of the processor, and the semantic bit width limitation of the processor can be broken through. According to the method, the sub-memory semantic tasks are allocated to the cores of the processor for parallel execution, so that the processing efficiency of the memory semantic tasks can be improved, and the problem that part of the cores are idle and the part of the cores are overloaded is avoided. In addition, by aggregating the messages corresponding to the sub-memory semantic tasks, a plurality of transmission tasks of a plurality of sub-memory semantic tasks can be completed through one-time transmission, consumption of transmission resources is reduced, and the efficiency of data operation is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and more specifically, to the field of distributed storage technology. The embodiments of the present application relate to a method for processing memory semantics, a device for processing memory semantics, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] With the evolution of internet technology and the surge in traffic, storage technology has gradually become a core component of system architecture. Distributed storage, with its advantages such as high scalability, high performance, and high reliability, has become the mainstream storage architecture. Distributed storage can decouple compute nodes from storage nodes, enabling independent expansion of storage and compute resources. For example, distributed storage can utilize idle memory to form a distributed memory pool. By centrally managing multi-tiered storage resources (such as internal memory and remote storage), memory capacity expansion can be decoupled from compute resources. Within the distributed memory pool, remote storage can be accessed using memory semantics. For example, data from a processor can be written to a target address in the memory pool using store memory semantics, or data can be read from the memory pool to the processor using load memory semantics. Summary of the Invention

[0003] The embodiments of the present application provide a memory semantic processing solution. According to the solution, a large memory semantic task can be split into multiple small sub-memory semantic tasks based on the memory semantic task and the core resources of the processor, so that the scale of the memory semantic task is within the processing capacity of the processor, thereby breaking through the semantic bit width limitation of the processor. Allocating multiple sub-memory semantic tasks to multiple cores of the processor for parallel execution can improve the processing efficiency of the memory semantic task and avoid the problem of some cores being idle and some cores being overloaded. In addition, by aggregating the messages corresponding to the sub-memory semantic tasks, multiple transmission tasks of multiple sub-memory semantic tasks can be completed through one transmission, reducing the consumption of transmission resources and improving the efficiency of data operations.

[0004] According to the first aspect of the present application, a method for processing memory semantics is provided. The method includes determining multiple sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor. The method also includes determining corresponding aggregated semantic messages by aggregating the execution results of multiple sub-memory semantic tasks, and the multiple sub-memory semantic tasks are executed in parallel by multiple cores of the processor. In addition, the method also includes sending the aggregated semantic message to a storage node.

[0005] In some embodiments of the first aspect, determining multiple sub-semantic tasks by splitting a memory semantic task includes: obtaining the field length corresponding to the memory semantic task and the number of cores of the processor; and determining multiple sub-memory semantic tasks by splitting the memory semantic task based on the field length and the number of cores. In this way, the granularity of the split can be determined in combination with the number of cores of the processor and the size of the memory semantic task, so that the memory semantic task can be split more accurately and more reasonably. In addition, determining the number of sub-memory semantic tasks to be split according to the number of cores can ensure that the split sub-memory semantic tasks are evenly distributed among the cores, avoiding overloading of some cores while other cores are idle.

[0006] In some embodiments of the first aspect, determining multiple sub-memory semantic tasks by splitting the memory semantic task also includes: determining a splitting method based on the address continuity of the memory semantic task, the splitting method including the size of the splitting granularity; and determining multiple sub-memory semantic tasks by splitting the memory semantic task based on the splitting method. In this way, the memory semantic task can be split according to the address continuity of the memory semantic task, and the address jumps across sub-memory semantic tasks can be reduced. In addition, the size of the sub-memory semantic task can be adjusted according to the address continuity to balance the load and memory access efficiency.

[0007] In some embodiments of the first aspect, determining multiple sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor also includes: determining whether the scale of the memory semantic task is greater than a preset scale; and in response to the scale of the memory semantic task being greater than the preset scale, determining multiple sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor. In this way, it is possible to determine whether to split the memory semantic task according to the preset scale, so that it can be flexibly applied to various memory semantic processing scenarios, thereby improving the processing flexibility and efficiency of the memory semantic task.

[0008] In some embodiments of the first aspect, determining the corresponding aggregated semantic message by aggregating the execution results of multiple sub-memory semantic tasks further includes: determining multiple target physical addresses corresponding to the multiple sub-semantic tasks based on a preset memory mapping relationship, wherein the preset memory mapping relationship is used to characterize the relationship between the virtual address and the physical address; and determining the corresponding aggregated semantic message based on the multiple target physical addresses. In this way, based on the memory mapping relationship, the aggregated semantic message can be correctly sent to the storage node, thereby ensuring that subsequent storage nodes can accurately access the corresponding memory location.

[0009] In some embodiments of the first aspect, each of the multiple sub-memory semantic tasks includes a data payload, and determining the corresponding aggregated semantic message includes: determining the corresponding aggregated semantic message by concatenating the data payloads included in each sub-memory semantic task. In this manner, data actually required for operation can be sent all at once, reducing addressing time when a storage node performs memory operations.

[0010] In some embodiments of the first aspect, the method further includes: determining whether multiple virtual addresses included in multiple sub-memory semantic tasks are continuous; and in response to the multiple virtual addresses being discontinuous, adding an identifier to the data payload of each sub-memory semantic task, the identifier being used to indicate whether a next sub-memory semantic task exists after the sub-memory semantic task. In this manner, the identifier can be used to assist the storage node in determining whether there are more sub-memory semantic tasks to be processed, thereby ensuring data integrity and sequentiality.

[0011] In some embodiments of the first aspect, the message format of the aggregated semantic message complies with the message format specified by the memory semantic network protocol, and the memory semantic tasks include loading memory semantics, storing memory semantics, and atomic operation memory semantics.

[0012] In some embodiments of the first aspect, the determination of the aggregate semantic message includes any one of the following situations: determining the corresponding aggregate semantic message by aggregating multiple sub-memory semantic messages, wherein the sub-memory semantic message is generated after the core of the processor executes the sub-memory semantic task at the corresponding virtual address; or determining the aggregate memory semantic task and the aggregate semantic message corresponding to the aggregate memory semantic task by aggregating the operation sets corresponding to multiple sub-memory semantic tasks.

[0013] According to a second aspect of the present application, a method for processing memory semantics is provided. The method includes receiving an aggregated semantic message from a device, where the aggregated semantic message is determined by aggregating the execution results of multiple sub-memory semantic tasks, where the multiple sub-memory semantic tasks are executed in parallel by multiple cores of a processor on the device. The method also includes operating the corresponding memory based on the aggregated semantic message.

[0014] In some embodiments of the second aspect, by parsing the aggregate semantic message, multiple sub-semantic operation instructions contained in the aggregate semantic message are determined, and the multiple sub-semantic operation instructions correspond one-to-one to the execution results of multiple sub-memory semantic tasks; in response to the multiple sub-semantic operation instructions, operations are performed on the memory corresponding to the multiple sub-semantic operation instructions, and the operations include read operations, write operations, and atomic operations.

[0015] According to a third aspect of the present application, an electronic device is provided, comprising: a processing unit and a memory, the processing unit executing instructions in the memory so that the electronic device executes a method, the method comprising: determining a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor; determining corresponding aggregated semantic messages by aggregating the execution results of the plurality of sub-memory semantic tasks, the plurality of sub-memory semantic tasks being executed in parallel by the plurality of cores of the processor; and sending the aggregated semantic message to a storage node.

[0016] According to the fourth aspect of the present application, a memory semantics processing device is provided, comprising: a splitting unit, a rendering mode aggregation unit, and a sending unit. The splitting unit is configured to determine a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor. The aggregation unit is configured to determine a corresponding aggregated semantic message by aggregating the execution results of the plurality of sub-memory semantic tasks, and the plurality of sub-memory semantic tasks are executed in parallel by the plurality of cores of the processor. The sending unit is configured to send the aggregated semantic message to the storage node.

[0017] According to a fifth aspect of the present application, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to enable the processor to perform the method according to the first aspect of the present application.

[0018] According to a sixth aspect of the present application, a computer program product is provided, comprising machine-executable instructions, which, when executed by a device, cause the device to perform the method according to the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other features, advantages and aspects of the embodiments of the present application will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0020] Figure 1 A schematic diagram illustrating an example environment in which various embodiments of the present application can be implemented;

[0021] Figure 2 A schematic flow chart of a method for processing memory semantics provided by an embodiment of the present application is shown;

[0022] Figure 3 An example workflow for processing memory semantics according to some embodiments of the present application is shown;

[0023] Figure 4 Another example workflow for processing memory semantics according to some embodiments of the present application is shown;

[0024] Figure 5 An example workflow for processing memory semantics according to some other embodiments of the present application is shown;

[0025] Figure 6 A schematic diagram showing whether to split memory semantic tasks according to some embodiments of the present application is shown;

[0026] Figure 7 A schematic diagram of an aggregated semantic message provided according to some embodiments of the present application; and

[0027] Figure 8 A schematic block diagram of a memory semantics processing device provided according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0028] The technical solutions of this application will be described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, rather than all the embodiments.

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means and / or. For example, A / B can mean A or B, or A and B. "And / or" in this article is only a way to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" or "multiple" refers to two or more than two.

[0030] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0031] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of this application and the appended claims, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one, two or more. The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0032] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "one embodiment," "some embodiments," "another embodiment," and "other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically stated. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically stated.

[0033] The numbers or numerical values ​​used in this specification are for illustrative purposes only and are intended only to facilitate understanding of the technology of the embodiments of this application and are in no way intended to limit the scope of this application.

[0034] As mentioned above, when processing store memory semantics, load memory semantics, or other memory semantics, the processor is often limited by the maximum access bit width of the processor's memory semantics. This means that the memory semantics cannot break through the processor's memory semantics bit width limitations, preventing more flexible memory access in input and output scenarios. This results in inefficiency in scenarios requiring larger or more flexible data access.

[0035] To this end, an embodiment of the present application provides a method for processing memory semantics. This method can split a large memory semantic task into multiple small sub-memory semantic tasks based on the memory semantic task and the core resources of the processor, so that the scale of the memory semantic task is within the processing capacity of the processor, thereby breaking through the semantic bit width limitation of the processor. Allocating multiple sub-memory semantic tasks to multiple cores of the processor for parallel execution can improve the processing efficiency of memory semantic tasks and avoid the problem of some cores being idle and some cores being overloaded. In addition, by aggregating the messages corresponding to the sub-memory semantic tasks, multiple transmission tasks of multiple sub-memory semantic tasks can be completed through one transmission, reducing the consumption of transmission resources and improving the efficiency of data operations.

[0036] The method provided in the embodiments of the present application can be applied to electronic devices such as mobile phones, tablet computers, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). The embodiments of the present application do not impose any restrictions on the specific types of electronic devices.

[0037] Now refer to Figure 1 , which shows a schematic diagram of an example environment 100 in which various embodiments of the present application can be implemented. Figure 1 As shown, the example environment 100 includes hosts 110 and storage nodes 120. The number of hosts 110 and the number of storage nodes 120 can be one or more. A host 110 can be connected to one or more storage nodes 120, and a storage node 120 can be connected to one or more hosts 110. This application does not specifically limit the number of hosts 110 and storage nodes 120. Host 110 can be a client, a terminal device, a physical server (such as a single server, a server cluster, etc.), or a virtual machine (VM) implemented based on a general physical server combined with network function virtualization technology. A virtual machine refers to a complete computer system with complete hardware system functions simulated by software and running in a completely isolated environment, and this application does not specifically limit this. Storage node 120 can be a storage server or a storage virtual machine. There can be multiple storage nodes 120, and different storage nodes 120 can be located in the same location, such as in the same data center. Alternatively, different storage nodes 120 can be located in different locations, such as any two storage nodes can be located in different data centers.

[0038] A communication connection can be established between the storage node 120 and the host 110, for example, a communication connection can be established in a wired or wireless manner. The communication method can be Remote Direct Memory Access (RDMA) communication, Direct Memory Access (DMA) communication or other communication methods. RDMA is a transport layer network protocol used to solve data processing delays in network transmission. The RDMA protocol can reduce the copying operation of data within the host 110 used to transmit data during data transmission, and does not require the intervention of the operating system of the host 110 used to transmit data. Therefore, the RDMA protocol can reduce the processing load of the host 110 used to transmit data. In some examples, the host 110 and the storage node 120 can establish a communication connection through a network card, which can include but is not limited to a remote direct memory access network card (RDMA enabled NIC, RNIC), or a network card or switch that supports InfiniBand (IB). The network card can be connected to the host 110 via a bus. The bus 140 can be a Peripheral Component Interconnect Express (PCIe) bus, a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc.

[0039] The storage node 120 may include multiple storage spaces 122. The storage spaces 122 may be storage spaces capable of persistently storing data. The multiple storage spaces may form a shared memory pool. The storage space 122 may be a non-volatile dual in-line memory module (NVDIMM), such as a double data rate synchronous dynamic random access memory (DDR), storage class memory (SCM), a NAND flash memory device, and the like. It is understood that the memory space 112 in the host 110 may be a software-based mapping of the storage space 122 in the storage node 120. That is, the memory space 112 (virtual address) corresponds to the storage space 122 (physical address). In some embodiments, the host 110 and the storage node 120 may store a correspondence or mapping between the storage space 122 and the memory space 112. In some embodiments, the memory mapping relationship may be stored in a page table of the memory management unit (MMU) of the host 110. Among them, MMU is a computer hardware responsible for the CPU's memory access requests, and the MM page table can record a set of mapping rules between addresses.

[0040] The functions of each storage node can be the same or different. For example, the multiple storage nodes have data synchronization capabilities, thereby achieving redundant copies of some or all files in the storage cluster, improving the ability to continuously provide file services in the event of a node failure. Furthermore, the multiple storage nodes in the storage cluster can be located in the same location, such as in the same data center. Alternatively, the multiple storage nodes in the storage cluster can be located in different locations, for example, any two storage nodes can be located in different data centers.

[0041] The host 110 may include a processor 114, a memory, and a controller. The processor 114 may be a central processing unit (CPU), which is used to process data from outside the host 110 or data generated inside the host 110. The controller may be the nerve center and command center of the host 110. It should be noted that the core of the processor 114 may be one or more. The core of the processor 114 is the core of the CPU, that is, the core chip in the middle of the CPU, which is responsible for completing all computing tasks in the host 110, receiving and storing commands, and processing data, etc. It is the core of data processing. A multi-core CPU refers to a central processing unit that contains multiple processor cores (CPU cores) in a single integrated circuit chip (or chipset). A multi-core CPU can execute instructions independently, while multiple cores can process multiple tasks in parallel, thereby improving computing efficiency.

[0042] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution. Memory can refer to a device for storing data, which can be a memory or a hard disk. Memory refers to an internal memory that directly exchanges data with the processor. It can read and write data at any time and at a very high speed. It serves as a temporary data storage for the operating system or other running programs. Memory includes at least two types of memory. For example, memory can be either random access memory or read-only memory (ROM). For example, random access memory can be dynamic random access memory (DRAM) or storage class memory (SCM).

[0043] In some embodiments, the memory space 112 in the host 110 can be accessed through memory semantics. Memory semantics include the execution order and visibility rules for operations on the memory space 112 (such as read, write, and atomic operations). Memory semantic tasks can be provided by the user or by an external device communicating with the host 110. However, due to the bit width limitation of a single memory access by the CPU, large-block memory operations not only require multiple accesses, but also increase latency and resource consumption. On this basis, the memory semantic tasks can be split to split large-block memory operations (such as 1024-byte memory semantic tasks) into multiple continuous small-block operations (such as 64-byte or 128-byte sub-memory semantic tasks). This can circumvent the limitations of the CPU and adapt to the single processing capabilities of the CPU. In addition, the multiple cores of the CPU can also execute the split sub-memory semantic tasks concurrently in batches. For example, the total field length of the memory semantic task can be divided by the number of cores to obtain the size and number of sub-tasks processed by each core. In one example, a CPU may include four cores, and the maximum bit width of a single memory access by the CPU may be 64 bytes. In this case, a 1024-byte memory semantic task may be split into 16 sub-memory semantic tasks (e.g., sub-memory semantic task 1, sub-memory semantic task 2, ... sub-memory semantic task 16). The 16 sub-memory semantic tasks may be divided into four batches and executed in parallel by the four cores. For example, in the first batch, core 1 of the CPU may execute sub-memory semantic task 1, and core 2 may execute sub-memory semantic task 2; in the second batch, core 1 of the CPU may execute sub-memory semantic task 5, and core 2 may execute sub-memory semantic task 6, and so on.

[0044] However, splitting the memory semantic task into multiple sub-memory semantic tasks will result in a problem, that is, during the operation, the transmission burden between the host 110 and the storage node 120 will be increased. For example, the number of outstanding requests (Outstanding) supported by a bus such as a PCIe bus is limited, which limits the concurrency capability and also increases the system resource consumption during data operations. On this basis, the aggregation module 116 can be used to aggregate the IO tasks corresponding to the sub-memory semantics executed by the kernel to determine the aggregated semantic message. The aggregated semantic message may include the operation data of each sub-memory semantic task, the storage address corresponding to the operation address, the operation type, etc. Among them, the aggregation module 116 can be located in the host 110, the aggregation module can be a separate module in the host 110, or it can be integrated into the processor 114 or the network card of the host. It should be noted that the aggregation module can support spatial aggregation (multi-task merging) or temporal aggregation (accumulation of tasks over a period of time).

[0045] The aggregation module can be composed of at least one general-purpose processor, such as a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0046] On this basis, the storage node 120 can be provided with a parsing module 124, which can also be an FPGA, CPLD, or other module. Parsing module 124 can parse the aggregated semantic message sent by the aggregation module, determine the multiple I / O tasks contained in the aggregated semantic message, and operate the storage space 122 at the corresponding location. For example, the aggregated semantic message can be decomposed into multiple direct memory access (DMA) instructions or other types of instructions, and written in parallel to multiple memory blocks in the storage node 120, such as multiple DDR memories.

[0047] It should be understood that the architecture and functionality of the example environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present application. Furthermore, other devices, systems, or components not shown may also exist in the example environment 100. Furthermore, the embodiments of the present application may also be applied to other environments having different structures and / or functionality, and the present application does not impose any limitation thereto.

[0048] In this way, large memory semantic tasks can be split and assigned to different processor cores, so that each processor core only needs to process a part of the memory semantic task, thereby reducing the computational burden of a single processor core. At the same time, since the multiple sub-semantic tasks obtained by splitting can be executed in parallel in batches, the computing power of the multi-core processor can be fully utilized to improve the efficiency of task processing. In addition, splitting large memory semantic tasks into multiple small sub-memory semantic tasks can also break through the processing power limitations of the processor, adapt to the single processing power of the processor, and improve the processing efficiency of memory semantics. Similarly, it can also reduce the number of preparation times for the communication queue, thereby reducing the system resource consumption during data operations and improving the efficiency of data operations.

[0049] Now refer to Figure 2, which shows a flow chart of an example method 200 for generating a program patch according to some embodiments of the present application. The example method 200 may be performed by, for example, Figure 1 It should be understood that the method 200 may also include additional actions not shown, and the scope of the present application is not limited in this respect. Figure 1 The method 200 is described in detail with reference to the example environment 100 of FIG. Figure 2 As shown, at 202, based on the size of the memory semantic task and the core resources of the processor, the memory semantic task is split to determine multiple sub-memory semantic tasks. A memory semantic task refers to a set of operations that access memory space, such as read, write, and modify. For example, the host 110 can access the memory space 112 using memory semantics. The memory space 112 refers to the largest physical address space that the processor 114 can access using memory semantics by traversing the permutations and combinations of its address lines. For example, memory semantics may include the execution order and visibility rules of memory operations performed by the processor 114, which can ensure that each processor in a multi-core processor system maintains consistent access to shared memory. In some embodiments, memory semantics may include load / store instructions, atomic operation instructions, etc. Load / Store instructions may be operations performed by the core of the processor 114 to access the memory space 112, including load operations (reading data from the memory space 112 into registers within the processor core) and store operations (writing data from registers within the processor core to the memory space 112). In some embodiments, atomic operation instructions refer to uninterruptible compound operations that ensure consistency of concurrent access by multiple cores.

[0050] It will be appreciated that the maximum bit width of a single memory semantic operation or a single processor access by processor 114 is fixed. For example, memory semantics supports a maximum bit width of 64 bits. However, the size of a memory semantic task is not fixed and may sometimes require operating on larger data blocks. To enable memory semantic tasks to overcome the bit width limitations of memory semantics, more flexibly address various memory access scenarios, and fully utilize the resources of multi-core processors, memory semantic tasks can be split. For example, a large memory semantic task can be split into multiple small sub-memory semantic tasks. The sub-memory semantic tasks are responsible for processing a portion of the memory operations in the original memory semantic task. In some embodiments, memory semantics can be split based on the size of the memory semantic task and the core resources of processor 114. The size of the memory semantic task refers to the size of the memory semantic task and can include the total amount of data being operated on. The total amount of data can be, for example, a small data block of a few bytes or a large data block of hundreds of bits or even wider, such as 1024 bits. The size of the memory semantic task can also include resource requirements, task complexity, and the like. The core resources of processor 114 can include the number of cores, the computing power of the cores (e.g., the speed at which instructions are processed, the ability to perform complex operations), cache levels, memory bandwidth, and the like. It can be understood that by splitting the memory semantic tasks, a large memory operation can be split into multiple continuous or discontinuous small operations.

[0051] In some embodiments, the sizes of the multiple sub-memory semantic tasks obtained by splitting can be the same or different. That is, the splitting can be fixed-size splitting, where a large memory block is split into fixed sizes (such as 64 bytes, 512 bytes, etc.), or dynamic-size splitting, where the size of the split is dynamically adjusted based on factors such as memory access patterns and data types.

[0052] In 204, the corresponding aggregated semantic message is determined by aggregating the execution results of multiple sub-memory semantic tasks, and the multiple sub-memory semantic tasks are executed in parallel by multiple cores of the processor. It can be understood that the multiple sub-memory semantic tasks obtained by splitting can be executed in parallel by multiple cores of the processor. In the process of executing the sub-memory semantic task, each processor core can generate one or more messages such as IO messages, which contain information such as the address, data, and operation type of the memory access. The message can be a carrier for the sub-memory semantic task to communicate with the remote memory node (such as the storage node 120). The format of the message can be determined according to the communication method. It can be understood that in order to improve the network bandwidth utilization and improve the efficiency of network transmission, multiple messages can be aggregated to determine the corresponding aggregated semantic message.

[0053] At 206, the aggregated semantic message is sent to the storage node. After receiving the aggregated semantic message, the storage node 120 can parse the aggregated semantic message to determine the operation type, operation data, and operation address corresponding to the different sub-semantic tasks. It is understood that the operation address can be the storage address of the storage node. Based on the operation type, such as the write type, the storage node 120 can write the corresponding operation data to the corresponding operation address.

[0054] In this way, large memory semantic tasks are split and assigned to different processor cores. Each processor core only needs to process a portion of the memory semantic task, reducing the computational burden on a single processor core. Furthermore, because the resulting sub-semantic tasks can be executed in parallel in batches, the computing power of multi-core processors can be fully utilized, improving task processing efficiency. Furthermore, splitting large memory semantic tasks into multiple smaller sub-semantic tasks can overcome processor processing limitations and improve memory semantic processing efficiency.

[0055] Now refer to Figure 3 , which shows an example workflow 300 for processing memory semantics according to some embodiments of the present application. The example workflow 300 can be an example implementation of the method 200 and is, for example, performed by Figure 1 The host 110 and storage node 120 shown in the figure are executed. It should be understood that the workflow 300 may also include additional actions not shown, or some of the actions may be omitted. Moreover, the order of the actions shown in the workflow 300 is only for example. In other embodiments, the order of execution of the actions may be changed without departing from the scope of the present application. Figure 1 The workflow 300 is described in detail with reference to the example environment 100 of FIG.

[0056] like Figure 3 As shown, a user or an external device (peripheral) can issue memory semantic tasks such as large-block remote memory read / write tasks. The peripheral device can be a hardware device other than the host 110, such as an input device, a display device, a printing device, and a network device. For example, a user can choose to read data from a remote storage node 120 or store data that requires persistent storage in the remote storage node 120. In some embodiments, the storage space 122 of the storage node 120, such as DDR, can be mapped to the memory space 112 of the host 110. The mapping relationship between the memory space 112 and the storage space 122 can be stored in the host 110 and the storage node 120 in the form of a page table. The page table can be a collection of virtual address and physical address mapping tables. The entries in the page table are records of specific correspondence between virtual addresses and independent addresses.

[0057] In some embodiments, the memory space 112 may be an address space such as a memory-mapped input / output (MMIO) space. MMIO is a technology for accessing hardware devices through memory addressing. In MMIO mapping, registers or memory areas of a hardware device may be mapped to the physical address space of the host 110. This means that the CPU can interact with hardware devices such as the storage node 120 by reading and writing specific physical addresses, just as it would access ordinary memory. It will be appreciated that one or more storage addresses within the storage space 122 of a storage node or other remote device may correspond one-to-one to one or more MMIO addresses within the MMIO address space.

[0058] In some embodiments, the processor 114 may include multiple cores, and one core may correspond to at least one thread. A thread is the smallest unit used by the operating system to execute business programs and perform scheduling. A thread refers to a single sequential execution flow. A thread can be responsible for performing various memory read and write tasks, such as loading and storing data. It can be understood that multiple threads can work in parallel to improve processing efficiency. For example, the processor 114 may include n threads (e.g., thread 1, thread 2...thread n, etc.). Different threads can be used to process different memory semantic tasks.

[0059] like Figure 3 As shown, in order to improve data processing efficiency and break through the processing power limitation of processor 114, the memory semantic task can be split by the splitting module of host 110. This is because the direct transmission and processing of large blocks of data may be limited by factors such as network bandwidth and processor processing power. Splitting memory operations into small blocks can make data processing more flexible and efficient. For example, a memory semantic task can be split into n sub-memory semantic tasks (such as sub-memory semantic task 1, sub-memory semantic task 2...sub-memory semantic task n, etc.). For example, a sub-semantic task can be {virtual address: 0x1000, remote key: 0xABCD, data: 0x12345678}. The n sub-memory semantic tasks can be executed by n threads. For example, thread 1 can be used to execute sub-memory semantic task 1, thread 2 can be used to execute sub-memory semantic task 2, thread 3 can be used to execute sub-memory semantic task 3, etc.

[0060] Taking a memory semantic task as a Store instruction as an example, the Store instruction may include a virtual storage address, such as a memory address, corresponding to the data to be read. Based on the correspondence between MMIO addresses and storage addresses, the virtual storage address included in the Store instruction can be mapped to the corresponding storage address. It is understood that the MMIO address does not actually store data; it is merely a mapping corresponding to the storage address in the storage space of storage node 120. Based on this, information corresponding to each sub-memory semantic task can be determined, such as the operation type (read, write, atomic operation, etc.), storage address (such as storage area 1 or DDR1 in the storage node), data length (corresponding data size, such as 64 bytes of data), and data content (specific data to be operated on). Based on this, the thread can execute the corresponding memory operation and generate the corresponding sub-message according to the instruction in the sub-memory semantic task. It is understood that different sub-memory semantic tasks correspond to different sub-memory semantic messages. The sub-memory semantic message can include various information corresponding to the sub-memory semantic task, such as the operation data and operation type.

[0061] In some embodiments, the host 110 may include a mapping module 302, which may be responsible for mapping physical addresses to virtual addresses. For example, the mapping module may be a remote memory management unit (RMMU), which may manage the mapping between physical addresses and MMIO addresses. For example, the virtual address space (MMIO address space) may be divided into multiple pages, and these pages may be mapped to a remote physical address space, such as storage space 122. In the remote memory management unit, a message refers to a data packet transmitted over a network. A data packet typically consists of a header and a payload. The header contains control information, such as the destination address and checksum, and serves as a guide during routing and transmission. The payload is the actual data content to be transmitted in the data packet. The RMMU may receive different sub-messages from different threads. The format of the message may be determined by the communication protocol; for example, the message may be an RDMA message. Subsequently, an aggregation module in the host 110 may receive multiple sub-messages from the RMMU and aggregate them. As described above, the aggregation module may be an FPGA, a CPLD, etc. The aggregation module may aggregate multiple small memory semantic messages into a large message.

[0062] In some embodiments, during the aggregation process, the aggregation module can merge the message headers of multiple memory semantic messages to determine the message header corresponding to the aggregated semantic message. For example, the message header of the aggregated semantic message may include an Internet Protocol Header (IP Header), a User Datagram Protocol Header (UDP Header), etc. The IP header can contain key information such as the source IP address, destination IP address, and protocol type. It is an important header at the network layer and is used to route data packets on the Internet. The UDP header can contain information such as the source port number, destination port number, length, and checksum. It is an important protocol at the transport layer and is used to transmit data between applications. In other words, by integrating this key information, the aggregated semantic message can ensure that data can be transmitted correctly and efficiently on the network. In other embodiments, the key information may also include the queue number of the first sub-memory semantic message, the virtual address of the first sub-memory semantic message, the data length of all sub-memory semantic messages, the remote key of the first message, etc. Among them, in protocols such as RDMA, the remote key can be used to verify access rights to the remote storage space 122. It can be understood that, in an aggregated semantic message, if multiple sub-memory semantic tasks involve operations on the same remote storage space 122, then the multiple aggregated sub-memory semantic messages can use the same remote key.

[0063] The aggregation module can also concatenate multiple sub-memory semantic messages. For example, it can sequentially concatenate the payload portions (i.e., the actual data to be transmitted) of multiple small messages to form the payload portion of a large message. This allows the server to conveniently split the payload portion into the original small message payloads after receiving the large message and perform corresponding processing. It is understood that the data addresses of a memory semantic task can be continuous, for example, storing data in the range of 0 to 0xFFFFFFFF. Of course, the data addresses of a memory semantic task can also be discontinuous. The addresses of the sub-memory semantic tasks thus split can be continuous or discontinuous. In the case of discontinuous memory addresses, identification information can be added to different sub-memory semantic messages. This identification information can be used to indicate whether another sub-memory semantic message follows the sub-memory semantic message. For example, identification information (0 or 1) can be added to a reserved bit in a sub-memory semantic message, such as Reserved 0. A 1 can be used to indicate that there is a next sub-memory semantic message following the sub-memory semantic message, while a 0 can be used to indicate that the sub-memory semantic task is the last one and there is no subsequent sub-memory semantic message. By adding identification information, data integrity and data quality can be guaranteed even when addresses are discontinuous, ensuring that all relevant messages can be correctly received and processed.

[0064] like Figure 3 As shown, the aggregated semantic message can be transmitted through a communication network such as an RDMA network between the host 110 and the storage node 120. After receiving the aggregated semantic message, the storage node 120 can parse the aggregated semantic message to determine multiple sub-memory semantic messages. For example, the aggregated semantic message can be parsed by a parsing module deployed in the storage node 120. The parsing module corresponds to the aggregation module, and the parsing module can also be an FPGA, CPLD, etc. After parsing to obtain multiple sub-memory semantic messages, corresponding memory operations such as reading data, writing data, modifying data, etc. can be performed at the corresponding storage location according to the information indicated by the sub-memory semantic message. It can be understood that the storage node 120 can feedback information to the host 110 after the memory operation is completed. For example, the storage node 120 can send back an acknowledgment character (ack) to the host 110. Alternatively, the storage node 120 may also send a completion queue entry (CQE) to the host 110. The CQE may include the result information of the memory operation, such as whether the operation is successful, the specific details of the operation (such as the operation type, operation address, operation data, etc.), and any error information that may occur. It can be understood that when the storage node successfully executes a batch of memory operations, a CQE receipt can be generated for each memory operation in the batch. These CQE receipts will be collected and packaged to form a full CQE receipt package. The full CQE receipt package can be returned to the host 110 via a communication network (such as an RDMA network). After receiving the full CQE receipt package, the host 110 can parse each CQE receipt therein to confirm the success of each memory operation and can process subsequent tasks as needed.

[0065] It should be noted that the aggregation module can be located at different locations on the host 110 or at different steps. Different aggregation locations may require different aggregation methods or information. For example, the aggregation module can be located behind the RMMU or before the network card of the host 110. Alternatively, packets can be aggregated while multiple threads execute sub-memory semantic tasks in batches.

[0066] Now refer to Figure 4 , which shows another example workflow 400 for processing memory semantics according to some embodiments of the present application. The example workflow 400 can be an example implementation of the method 200, and is, for example, performed by Figure 1The host 110 and storage node 120 shown in the figure are executed. It should be understood that the workflow 400 may also include additional actions not shown, or some of the actions may be omitted. Moreover, the order of the actions shown in the workflow 400 is only for example. In other embodiments, the order of execution of the actions may be changed without departing from the scope of the present application. Figure 1 The workflow 400 is described in detail with reference to the example environment 100 of FIG.

[0067] like Figure 4 As shown, the host 110 and the storage node 120 can communicate through the network card (NIC). Similarly, the host 110 can split the memory semantic task after receiving the memory semantic task. The splitting process can refer to the splitting process described in the above embodiment, and this application will not go into details here. Afterwards, different threads can execute different sub-memory semantic tasks in batches and in parallel. In this process, the CPU can write the instructions corresponding to different sub-memory semantic tasks into the queue 402 of the memory, for example, the instructions corresponding to the memory semantic task can be written into the task queue (Work Queue, WQ) of the memory. In some embodiments, the CPU can also write data to the doorbell (DB) to obtain the instructions to be executed from the WQ queue by notifying the aggregation module. For example, the CPU can ring the doorbell to the aggregation module to notify the aggregation module to read the instructions from the memory such as WQ. On this basis, the aggregation module can read the information related to the memory semantic task from the memory based on the doorbell action.

[0068] like Figure 4 As shown, the aggregation module can generate a corresponding aggregated semantic message based on the read information. The aggregated semantic message can be sent to the storage node 120 via the network card. After receiving the aggregated semantic message, the storage node 120 can parse the aggregated semantic message and perform operations at the corresponding location. For example, data 1 corresponding to sub-semantic message 1 is written to DDR1; data 2 corresponding to sub-semantic message 2 is written to DDR2. It is understood that DDR1 and DDR2 or other DDRs can be located in the same storage node or in different storage nodes. After completing the memory operation, the storage node 120 can feedback completion information to the host 110. For example, a full CQE receipt packet can be sent to the host 110 in the manner described above. In other embodiments, the execution result can also be written to the host's completion queue (CQ) to update the tail pointer of the CQ. In this process, the aggregation of messages occurs during the thread execution of load instructions or other memory semantic instructions, and the transmission of the aggregated semantic message is completed by the network card between the host 110 and the storage node 120.

[0069] Now refer to Figure 5, which shows an example workflow 500 for processing memory semantics according to some other embodiments of the present application. The example workflow 500 can be an example implementation of the method 200, and is, for example, performed by Figure 1 The host 110 and storage node 120 shown in the figure are executed. It should be understood that the workflow 500 may also include additional actions not shown, or some of the actions may be omitted. Moreover, the order of the actions shown in the workflow 500 is only for example. In other embodiments, the order of execution of the actions may be changed without departing from the scope of the present application. Figure 1 The workflow 500 is described in detail with reference to the example environment 100 of FIG.

[0070] like Figure 5 As shown, after the memory semantic task is obtained, the memory semantic task can be split to obtain multiple sub-memory semantic tasks. Multiple threads of the host 110 can execute multiple sub-memory semantic tasks in parallel. That is, each thread can independently perform load / store operations or atomic operations, etc. to process the split sub-tasks. In this process, the aggregation module can determine the number of resources of the actual memory semantic task and aggregate multiple sub-memory semantic operations into a single message. It can be understood that in this process, the aggregation method can be determined in combination with the address continuity of multiple sub-memory semantic tasks. For example, the aggregation module determines the continuous address range based on the address distribution of multiple sub-memory semantic tasks. In this way, continuous small-segment memory operations can be merged into a single large-block message such as an RDMA message. The address here can be a virtual address such as an MMIO address.

[0071] On this basis, memory mapping can be used to determine the storage address corresponding to the virtual address contained in the aggregated semantic message. For example, mapping can be performed using the MMIO physical address group to ensure that the thread can access the storage space of the storage node 120. The RMMU can be responsible for managing the mapping relationship between the storage space and the memory space of the host 110, ensuring that the storage node 120 can perform corresponding memory operations based on the aggregated RDMA message.

[0072] In this way, messages can be aggregated at various locations on various nodes, thereby increasing the applicability of message aggregation.

[0073] In some embodiments, the field lengths included in a memory semantic task can be determined, such as 512 bytes, 1024 bytes, or the like. For example, a memory semantic task can be writing 1024 bytes of data to a storage block on a remote storage node, or reading 216 bytes of data from a remote storage node. As described above, a processor's processing power is limited. Therefore, to improve processor processing efficiency, memory semantic tasks with field lengths exceeding the limit can be split into multiple sub-memory semantic tasks. This splitting can be based on various factors, such as the CPU's corresponding bit width limit, the CPU's corresponding minimum data transfer unit, and the transfer scale, such as the maximum data transfer volume specified by the bus. In some embodiments, memory semantic tasks can be split based on field length and the CPU's corresponding bit width limit. For example, if the bit width limit is 64 bytes, a 1024-byte task can be split into 16 64-byte sub-memory semantic tasks. These 16 sub-memory semantic tasks can be assigned to 16 cores for execution. When the processor has a large number of cores or threads, multiple sub-memory semantic tasks can be executed in batches. If the processor has four cores, the sub-memory semantic tasks can be executed in four batches. For example, in the first batch, core 1 can execute sub-memory semantic task 1, core 2 can execute sub-memory semantic task 2, core 3 can execute sub-memory semantic task 3, and core 4 can execute sub-memory semantic task 4. In the second batch, core 1 can execute sub-memory semantic task 5, core 2 can execute sub-memory semantic task 6, core 3 can execute sub-memory semantic task 7, and core 4 can execute sub-memory semantic task 8. Similarly, in the third and fourth batches, different cores can be used to execute different tasks. By executing multiple sub-memory semantic tasks in parallel in batches, memory semantic processing efficiency can be improved.

[0074] It can be understood that the splitting granularity of the memory semantic task can be fixed or not. Among them, the splitting granularity can be the basic unit or standard used when decomposing the memory semantic task into smaller subtasks. The splitting granularity can determine how the task is divided, managed and executed, and directly affect the system performance, resource utilization and processing efficiency. The splitting granularity can be fixed, for example, it can be 64 bytes. Of course, the splitting granularity can also be dynamically adjusted according to real-time conditions (such as current load, data distribution, hardware status). For example, the granularity can be reduced under high load to increase parallelism; the granularity can be increased under low load to reduce task scheduling overhead. The sizes of the multiple sub-memory semantic tasks obtained by splitting in this way can be the same or different.

[0075] In this way, it can flexibly adapt to complex environments, maximize resource utilization, and achieve a balance between performance and complexity.

[0076] It is understandable that whether to split the memory semantic task can be determined based on the size of the memory semantic task. For example, if the size of the memory semantic task is smaller than the bit width limit (such as 64 bits), the memory semantic task can be left unsplit, thereby reducing resource overhead; if the size of the memory semantic task is larger than the bit width limit, the memory semantic task can be split to improve the parallelism and efficiency of the task. For example, Figure 6 As shown, if the field length of a memory semantic task is greater than 64 bytes, the task can be split into sub-memory semantic tasks 1, 2, ..., and 9. If the field length of a memory semantic task is less than 64 bytes, the task can be executed by a single processor core without splitting the task. This allows for the proper division of data areas based on task characteristics and processor core resource availability, ensuring load balancing and preventing overloading of some processor cores while leaving others idle.

[0077] Figure 7 Schematic diagram of an aggregated semantic message according to some embodiments of the present application is shown. Figure 7 As shown, the address continuity of the memory semantic tasks is different, and the information contained in the aggregate semantic message 702 is different. In the case where the memory addresses contained in the memory semantic tasks are continuous, the aggregate semantic message may include but is not limited to a message header, payloads corresponding to multiple sub-memory semantic tasks (for example, payload 1 corresponding to sub-memory semantic task 1, payload 2 corresponding to sub-memory semantic task 2, payload 3 corresponding to sub-memory semantic task 3, etc.) and a check code. The message header may include multiple headers such as Ethernet L2 header, IP header, UDP header, etc. The check code can be in various forms, and the form of the check code varies depending on the check method. For example, the check code can be a cyclic redundancy check (CRC), a Hamming code, a parity check, or a frame check sequence (FCS). CRC is a redundant check technology based on polynomial division that detects burst errors in data transmission by adding redundant bits (CRC code). The frame check sequence is usually located at the end of the Ethernet frame and is used to detect whether an error occurs during the transmission of the entire frame, providing additional data integrity protection. On this basis, error detection can be achieved through the check code to ensure the integrity and accuracy of the transmitted data. In the case where the memory addresses contained in the memory semantic tasks are discontinuous, the aggregated semantic message 704 may include but is not limited to a message header, payloads corresponding to multiple sub-memory semantic tasks, and identifiers corresponding to multiple sub-memory semantic tasks. It is understood that the message header may be similar to the message header of the aggregated semantic message 702, for example, it may include an IP header, a UDP header, etc. Figure 7As shown, the identifier of sub-memory semantic message 1 may be identifier 1, and the payload may be payload 1; the identifier of sub-memory semantic message may be identifier 2, and the payload may be payload 2, etc. In this way, the identifier can be used to assist the storage node in determining whether there are more sub-memory semantic tasks to be processed, thereby ensuring the integrity and sequence of the data.

[0078] Figure 8 A schematic block diagram of a memory semantics processing device 800 according to an embodiment of the present application is shown. The memory semantics processing device 800 may be implemented at the host 110. The memory semantics processing device 800 may include a splitting unit 802, an aggregation unit 804, and a sending unit 806. The splitting unit 802 is configured to determine a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor. The aggregation unit 804 is configured to determine a corresponding aggregated semantic message by aggregating the execution results of the plurality of sub-memory semantic tasks, and the plurality of sub-memory semantic tasks are executed in parallel by the plurality of cores of the processor. The sending unit 806 is configured to send the aggregated semantic message to the storage node.

[0079] In some embodiments, the splitting unit 802 is further configured to: obtain the field length corresponding to the memory semantic task and the number of cores of the processor; and determine multiple sub-memory semantic tasks by splitting the memory semantic task based on the field length and the number of cores.

[0080] In some embodiments, the splitting unit 802 is further configured to: determine a splitting method based on the address continuity of the memory semantic task, the splitting method including the size of the splitting granularity; and determine multiple sub-memory semantic tasks by splitting the memory semantic task based on the splitting method.

[0081] In some embodiments, the splitting unit 802 is further configured to: determine whether the scale of the memory semantic task is greater than a preset scale; and in response to the scale of the memory semantic task being greater than the preset scale, determine multiple sub-memory semantic tasks by splitting the memory semantic task based on the scale of the memory semantic task and the core resources of the processor.

[0082] In some embodiments, the aggregation unit 804 is further configured to: determine multiple target physical addresses corresponding to multiple sub-semantic tasks based on a preset memory mapping relationship, wherein the preset memory mapping relationship is used to characterize the relationship between the virtual address and the physical address; and determine the corresponding aggregated semantic message based on the multiple target physical addresses.

[0083] In some embodiments, the aggregation unit 804 is further configured to determine a corresponding aggregated semantic message by concatenating the data payload included in each sub-memory semantic task.

[0084] In some embodiments, the device 800 also includes an identifier adding unit, which is configured to: determine whether the multiple virtual addresses contained in the multiple sub-memory semantic tasks are continuous; and in response to the multiple virtual addresses being discontinuous, add an identifier to the data load of each sub-memory semantic task, wherein the identifier is used to characterize whether there is a next sub-memory semantic task after the sub-memory semantic task.

[0085] In some embodiments, the message format of the aggregated semantic message complies with the message format specified by the memory semantic network protocol, and the memory semantic tasks include loading memory semantics, storing memory semantics, and atomic operation memory semantics.

[0086] In some embodiments, the determination of the aggregate semantic message includes any one of the following situations: determining the corresponding aggregate semantic message by aggregating multiple sub-memory semantic messages, where the sub-memory semantic message is generated after the core of the processor executes the sub-memory semantic task at the corresponding virtual address; or determining the aggregate memory semantic task and the aggregate semantic message corresponding to the aggregate memory semantic task by aggregating the operation sets corresponding to multiple sub-memory semantic tasks.

[0087] The present application may be a method, apparatus, system and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present application.

[0088] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0089] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0090] The computer program instructions for performing the operation of the present application can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data or source code or object code written in any combination of one or more programming languages, programming languages ​​include object-oriented programming languages-such as Smalltalk, C++ etc., and conventional procedural programming languages-such as " C " language or similar programming languages. Computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or executed completely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer by any type of network-including local area network (LAN) or wide area network (WAN), or can be connected to an external computer (such as utilizing an Internet service provider to connect by the Internet). In certain embodiments, by utilizing the state information of computer-readable program instructions to personalize electronic circuits, such as programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), the electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present application.

[0091] Various aspects of the present application are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0092] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0093] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0094] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the system, method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a special hardware-based system that performs the function or action of the specification, or can be implemented with a combination of special hardware and computer instructions.

[0095] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for processing memory semantics, comprising: Determining a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the size of the memory semantic task and the core resources of the processor; Determining a corresponding aggregated semantic message by aggregating execution results of the multiple sub-memory semantic tasks, wherein the multiple sub-memory semantic tasks are executed in parallel by multiple cores of the processor; as well as The aggregated semantic message is sent to a storage node.

2. The method according to claim 1, wherein determining a plurality of sub-memory semantic tasks by splitting the memory semantic task comprises: Obtaining the field length corresponding to the memory semantic task and the number of processor cores; as well as Based on the field length and the number of cores, the multiple sub-memory semantic tasks are determined by splitting the memory semantic task.

3. The method according to claim 2, wherein determining a plurality of sub-memory semantic tasks by splitting the memory semantic task further comprises: Determining a splitting method based on address continuity of the memory semantic task, wherein the splitting method includes a size of a splitting granularity; as well as Based on the splitting method, multiple sub-memory semantic tasks are determined by splitting the memory semantic task.

4. The method according to claim 1, wherein determining a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the size of the memory semantic task and the core resources of the processor further comprises: Determining whether the scale of the memory semantic task is greater than a preset scale; as well as In response to the size of the memory semantic task being larger than a preset size, a plurality of sub-memory semantic tasks are determined by splitting the memory semantic task based on the size of the memory semantic task and core resources of the processor.

5. The method according to claim 1, wherein determining a corresponding aggregated semantic message by aggregating the execution results of the plurality of sub-memory semantic tasks further comprises: Determining a plurality of target physical addresses corresponding to the plurality of sub-semantic tasks based on a preset memory mapping relationship, wherein the preset memory mapping relationship is used to characterize a relationship between a virtual address and a physical address; Based on the multiple target physical addresses, a corresponding aggregate semantic message is determined.

6. The method according to claim 1, wherein each of the plurality of sub-memory semantic tasks includes a data payload, and determining a corresponding aggregated semantic message includes: By splicing the data load contained in each sub-memory semantic task, the corresponding aggregate semantic message is determined.

7. The method according to claim 1, further comprising: Determining whether a plurality of virtual addresses included in the plurality of sub-memory semantic tasks are continuous; as well as In response to the multiple virtual addresses being discontinuous, an identifier is added to the data load of each sub-memory semantic task, where the identifier is used to indicate whether there is a next sub-memory semantic task after the sub-memory semantic task.

8. The method according to claim 1, wherein the message format of the aggregated semantic message complies with the message format specified by the memory semantic network protocol, and the memory semantic tasks include loading memory semantics, storing memory semantics, and atomic operation memory semantics.

9. The method according to claim 1, wherein the determining of the aggregated semantic message comprises any one of the following situations: Determining a corresponding aggregate semantic message by aggregating a plurality of sub-memory semantic messages, wherein the sub-memory semantic message is generated after a core of the processor executes a sub-memory semantic task at a corresponding virtual address; or By aggregating the operation sets corresponding to the multiple sub-memory semantic tasks, the aggregated memory semantic task and the aggregated semantic message corresponding to the aggregated memory semantic task are determined.

10. A method for processing memory semantics, comprising: receiving an aggregated semantic message from a device, where the aggregated semantic message is determined by aggregating execution results of a plurality of sub-memory semantic tasks, where the plurality of sub-memory semantic tasks are executed in parallel by a plurality of cores of a processor of the device; Based on the aggregated semantic message, the corresponding memory is operated.

11. The method according to claim 10, wherein operating the corresponding memory based on the aggregated semantic message comprises: Determining, by parsing the aggregate semantic message, a plurality of sub-semantic operation instructions contained in the aggregate semantic message, wherein the plurality of sub-semantic operation instructions correspond one-to-one to the execution results of the plurality of sub-memory semantic tasks; In response to the multiple sub-semantic operation instructions, operations are performed on memories corresponding to the multiple sub-semantic operation instructions, where the operations include read operations, write operations, and atomic operations.

12. An electronic device comprising: processing unit and memory, The processing unit executes the instructions in the memory, so that the electronic device performs a method, the method comprising: Determining a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the size of the memory semantic task and the core resources of the processor; Determining a corresponding aggregated semantic message by aggregating execution results of the multiple sub-memory semantic tasks, wherein the multiple sub-memory semantic tasks are executed in parallel by multiple cores of the processor; and The aggregated semantic message is sent to the server.

13. A memory semantics processing device, comprising: a splitting unit configured to determine a plurality of sub-memory semantic tasks by splitting the memory semantic task based on the size of the memory semantic task and the core resources of the processor; an aggregation unit configured to determine a corresponding aggregated semantic message by aggregating execution results of the multiple sub-memory semantic tasks, wherein the multiple sub-memory semantic tasks are executed in parallel by the multiple cores of the processor; as well as The sending unit is configured to send the aggregated semantic message to the storage node.

14. A computer-readable storage medium having one or more computer instructions stored thereon, wherein the one or more computer instructions are executed by a processor to cause the processor to perform the method according to any one of claims 1 to 11.

15. A computer program product comprising machine-executable instructions which, when executed by a device, cause the device to perform the method according to any one of claims 1 to 11.

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