Address management method and device for heterogeneous system and computer equipment

Abstract

The invention provides an address management method and device for a heterogeneous system and computer equipment, and relates to the technical field of computers, in particular to the fields of data processing, data transmission and the like. According to the implementation scheme, a second virtual address space of a data transmission module is divided into second sub-virtual address spaces with the same number as that of data processing modules, and the size of the second sub-virtual address spaces is the same as that of first virtual address spaces of the data processing modules; distributing a unique identifier to the data processing module, wherein the unique identifier is a natural number; for the first virtual address space, the first virtual address space is offset by a preset offset through the unique identifier, so that a second sub-virtual address space corresponding to the first virtual address space is determined in the second sub-virtual address space, and the preset offset is a product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between the first virtual address space and the corresponding second sub-virtual address space.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the fields of data processing and data transmission, and more particularly to an address management method, apparatus, computer equipment, computer-readable storage medium, and computer program product for heterogeneous systems. Background Art

[0002] Heterogeneous devices typically refer to systems containing multiple hardware modules with different functions and architectures, such as coders / decoders (CODECs), direct memory access (DMA), and graphics processing units (GPUs). These modules have distinct memory requirements and management methods due to their functional differences. The memory management unit (MMU) is responsible for translating virtual addresses into physical addresses. Virtual addresses represent program logical addresses, while physical memory represents actual storage units. The page table records the mapping between the two.

[0003] In the existing technology, the memory management of heterogeneous devices is independent of each other, resulting in low resource utilization. The address management logic across devices is complex and prone to conflicts, further limiting the collaborative work efficiency and stability of heterogeneous systems. Summary of the Invention

[0004] The present disclosure provides an address management method, apparatus, computer device, computer-readable storage medium, and computer program product for a heterogeneous system.

[0005] According to one aspect of the present disclosure, there is provided an address management method for a heterogeneous system, wherein the heterogeneous system includes at least one data processing module and a data transmission module, wherein the size of the first virtual address space of each data processing module in the at least one data processing module is the same, and the size of the second virtual address space of the data transmission module is greater than or equal to the sum of the first virtual address spaces of all the at least one data processing modules, and the method includes: dividing the second virtual address space of the data transmission module into at least one second sub-virtual address space which is the same as the number of the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module; assigning a unique identifier to each data processing module, wherein the unique identifier is a natural number; for each first virtual address space, offsetting the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

[0006] According to one aspect of the present disclosure, the above-mentioned address management method for heterogeneous systems also includes: allocating a first physical address space to each data processing module by applying for discrete physical memory page addresses at a page granularity, and the size of the first physical address space is equal to the size of the first virtual address space.

[0007] According to one aspect of the present disclosure, a first physical address space is allocated to each data processing module by applying for discrete physical memory page addresses at a page granularity, including: constructing multiple physical memory page address queues, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a group of physical memory page addresses, and the group of physical memory page addresses are the same in the address bits exceeding the first virtual address space; for each physical memory page obtained in the application, based on the address bits of the physical memory page address exceeding the first virtual address space, determining the physical memory page address queue corresponding to the physical memory page in the multiple physical memory page address queues; and in response to any physical memory page address queue in the multiple physical memory page address queues reaching the threshold capacity first, selecting a group of physical memory page addresses stored in the physical memory page address queue.

[0008] According to one aspect of the present disclosure, the above-mentioned address management method for heterogeneous systems also includes: reserving a first sub-virtual address space in the first virtual address space of each data processing module, wherein the size of each first sub-virtual address space is the same; and mapping the first sub-virtual address space of at least one data processing module to the same first sub-physical address space within the first physical address space, wherein the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

[0009] According to one aspect of the present disclosure, the above-mentioned address management method for heterogeneous systems further includes: in response to an external data storage module providing a target physical address to any data processing module in at least one data processing module, searching a preset cache list for a target virtual address corresponding to the currently provided target physical address, or redetermining a target virtual address corresponding to the currently provided target physical address, the target virtual address being in a first virtual address space, wherein the cache list records a mapping relationship between at least one target physical address already provided by the external data storage module and the corresponding target virtual address, as well as a timestamp when the mapping relationship is established.

[0010] According to one aspect of the present disclosure, searching for a target virtual address corresponding to a target physical address from a preset cache list includes: in response to determining that a target virtual address corresponding to a currently provided target physical address exists in the cache list, obtaining the target virtual address from the cache list; and updating a corresponding timestamp in the cache list based on the time when the target virtual address is obtained.

[0011] According to one aspect of the present disclosure, redetermining a target virtual address corresponding to a currently provided target physical address includes: in response to determining that a target virtual address corresponding to the currently provided target physical address does not exist in a cache list, reallocating a corresponding target virtual address for the target physical address; and updating the cache list based on a mapping relationship between the currently provided target physical address and the reallocated target virtual address, and a timestamp when the mapping relationship is established.

[0012] According to another aspect of the present disclosure, an address management device for a heterogeneous system is provided. The heterogeneous system includes at least one data processing module and a data transmission module. The size of the first virtual address space of each data processing module in the at least one data processing module is the same, and the size of the second virtual address space of the data transmission module is greater than or equal to the sum of the first virtual address spaces of all the at least one data processing modules. The device includes: a partitioning unit configured to partition the second virtual address space of the data transmission module into at least one second sub-virtual address space, the same number as the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module; an identifier allocation unit configured to allocate a unique identifier to each data processing module, wherein the unique identifier is a natural number; an offset unit configured to offset the first virtual address space by a preset offset via the unique identifier for each first virtual address space, so as to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space; and a relationship establishment unit configured to establish a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

[0013] According to another aspect of the present disclosure, a computer device is provided, comprising: at least one processor; and a memory on which a computer program is stored. When the computer program is executed by the at least one processor, the at least one processor executes the method provided above in the present disclosure.

[0014] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the processor executes the method provided above in the present disclosure.

[0015] According to another aspect of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the processor is caused to perform the method provided above in the present disclosure.

[0016] According to one or at least one embodiment of the present disclosure, device memory can be shared between heterogeneous devices, thereby completing data transfer without copying data, dynamically allocating and reclaiming device memory to various hardware devices, and realizing unified device memory management for the entire system.

[0017] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings illustrate exemplary embodiments and constitute a part of the specification. Together with the text of the specification, they are used to explain exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the present disclosure. In all figures, the same reference numerals refer to similar, but not necessarily identical, elements.

[0019] Figure 1 is a flowchart illustrating an address management method for a heterogeneous system according to an exemplary embodiment.

[0020] Figure 2 is a schematic diagram illustrating a second virtual address space partitioning method according to an exemplary embodiment.

[0021] Figure 3 FIG. 1 is a schematic diagram illustrating discrete physical memory page addresses according to an exemplary embodiment.

[0022] Figure 4 is a schematic diagram illustrating mapping of a first sub-virtual address space and a first sub-physical address space according to an exemplary embodiment.

[0023] Figure 5 is a schematic diagram illustrating a mapping relationship cache according to an exemplary embodiment.

[0024] Figure 6 is a schematic block diagram illustrating an address management apparatus for a heterogeneous system according to an exemplary embodiment.

[0025] Figure 7 is a block diagram illustrating an exemplary computer device that can be used with the exemplary embodiments. DETAILED DESCRIPTION

[0026] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be appreciated by those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0027] In this disclosure, unless otherwise specified, the use of terms such as "first" and "second" to describe various elements is not intended to limit the positional relationship, temporal relationship, or importance relationship of these elements. Such terms are only used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, while in some cases, based on the context of the description, they may also refer to different instances.

[0028] The terms used in the description of the various examples described in this disclosure are for the purpose of describing specific examples only and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or at least one. As used herein, the term "at least one" means two or more, and the term "based on" should be interpreted as "based at least in part on". In addition, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations.

[0029] In related technologies, memory management on heterogeneous devices is independent of each other, requiring pre-division of memory areas and inability to dynamically allocate free memory, resulting in low resource utilization. Furthermore, the virtual address spaces of different devices vary greatly, lacking a unified conversion logic, making management complex and prone to conflicts. These issues restrict the performance and resource utilization of heterogeneous systems. For example, in a heterogeneous system, the codec module and the GPU module each independently manage device memory, resulting in their free device memory being unavailable to the other module, and data transfer between modules relies on replication, limiting data transmission and operational efficiency.

[0030] To this end, an embodiment of the present disclosure provides an address management method for a heterogeneous system. In a heterogeneous system composed of heterogeneous devices, a unified device memory and address management method can be used to achieve data transmission and data sharing between heterogeneous devices without the need for data copying or transfer, thereby improving memory utilization efficiency.

[0031] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Before describing in detail the address management method for heterogeneous systems according to the embodiments of the present disclosure, an exemplary system in which the method can be implemented is first described.

[0032] Figure 1 is a flow chart illustrating an address management method 100 for a heterogeneous system according to an exemplary embodiment.

[0033] like Figure 1 As shown, the method 100 includes steps S101 , S102 , S103 and S104 .

[0034] In this example, a heterogeneous system can refer to a collection of at least one data processing module and one data transmission module. The data processing module can be an entity that undertakes the core task of data processing and executes specific algorithmic logic. For example, in a media processing scenario, it can be concretized as a codec instance that undertakes video and audio encoding and decoding, and implements content format conversion and processing by performing operations such as encoding compression and decoding restoration on the input media data stream. The data transmission module can focus on data transmission between hardware and rely on direct memory access mechanisms such as DMA to efficiently transmit data, so as to quickly move data between different hardware components, such as codec chips and memory, or codec chips and display chips, thereby improving data flow efficiency.

[0035] In the example, the first virtual address space can be an independent continuous address space used for addressing and memory management within the data processing module. The size of the space is strictly consistent in multiple data processing modules of the same type, such as multiple parallel encoding and decoding instances, to ensure the unified address mapping logic between modules and lay the foundation for cross-module data interaction; the second virtual address space can be the virtual address range of the data transmission module, which needs to cover the address requirements of the entire data interaction link. The size of the space can be designed to be greater than or equal to the sum of the first virtual address spaces of all data processing modules to ensure that the data transmission module can accommodate the address mapping relationships of all data processing modules, and provide conflict-free and scalable address mapping support for operations such as DMA transmission between encoding and decoding instances and other hardware.

[0036] In step S101, the second virtual address space of the data transmission module is divided into at least one second sub-virtual address space, the number of which is the same as that of the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module.

[0037] In the example, by dividing the second virtual address space of the data transmission module into second sub-virtual address spaces with the same number as the data processing modules, and the size of each second sub-virtual address space is consistent with the first virtual address space, not only can each data processing module have an independent virtual address area, thereby avoiding address conflicts between different data processing modules in the data transmission module; at the same time, the second virtual address space is equally divided according to the size of the first virtual address space, and the address range of each sub-space and the corresponding data processing module can be clear and the size can be adapted.

[0038] In step S102 , a unique identifier is assigned to each data processing module, where the unique identifier is a natural number.

[0039] In this example, the unique identifier can be used to uniquely distinguish each data processing module, allowing the data transmission module to accurately identify the address area corresponding to each data processing module and avoid confusion during address conversion. The unique identifier can be assigned using natural numbers, such as starting from 0 and assigning values ​​in ascending order.

[0040] In step S103, for each first virtual address space, the first virtual address space is offset by a preset offset via a unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space.

[0041] In the example, for each first virtual address space, it can be offset by a preset offset through a unique identifier, so as to determine the corresponding second sub-virtual address space in the second virtual address space. The setting of the preset offset can simplify the virtual address conversion into a simple mathematical operation: since the preset offset is essentially the starting address of the second sub-virtual address space corresponding to the data processing module in the second virtual address space, the virtual address corresponding to the address in the data transmission module can be directly obtained through the mathematical calculation of "first virtual address + preset offset", without the need for other system components or complex table lookup or mapping logic, which can greatly improve the efficiency of address conversion.

[0042] Specifically, the preset offset can be set to "unique identifier x size of the first virtual address space", so that the first virtual address space in the data processing module can be used to locate the corresponding second sub-virtual address space in the data transmission module via the offset. For example, if the unique identifier of a data processing module is N, then by offsetting its first virtual address space by N times the size of the first virtual address space, the corresponding second sub-virtual address space in the data transmission module can be obtained after the offset.

[0043] In step S104, a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space is established.

[0044] In the example, after the mapping relationship is established, the physical memory accessed by the data processing module through the first virtual address can also be directly accessed by the data transmission module through the corresponding second sub-virtual address. In other words, the first virtual address space of the data processing module and the corresponding second sub-virtual address space of the data transmission module can point to the same physical memory, thereby achieving efficient data interaction without the need for data copying.

[0045] Therefore, through the orderly division of the second virtual address space, the identification of the data processing module by a unique identifier, the establishment of address conversion and mapping relationships, efficient address coordination between the data processing module and the data transmission module in the heterogeneous system is achieved, the copy operation in data transmission is avoided, the system data interaction efficiency is improved, and the complexity of multi-module address management is simplified.

[0046] Figure 2 is a schematic diagram illustrating a second virtual address space partitioning method according to an exemplary embodiment.

[0047] like Figure 2 As shown above, in a memory address management scenario for a heterogeneous system, a data processing module can be embodied as a codec instance, such as a video codec task process. Each codec instance can independently process video stream data. To address the address coordination requirements of these codec instances, a mapping relationship can be established between a second virtual address space 202 (shown on the left in the figure) and the first virtual address spaces 201 of multiple codec instances (shown on the right in the figure, corresponding to the multiple codec instances, with multiple 4GB virtual address spaces). First, since the first virtual address space 201 of a single codec instance is 4GB in size, the second virtual address space 202 of the data transmission module can be divided into multiple 4GB second sub-virtual address spaces 203, based on the number of codec instances. For example, as shown in the figure, the 4GB intervals have starting addresses of 0G, 4G, 8G, ..., N × 4G. Next, each codec instance can be assigned a unique identifier, such as 0, 1, 2, ..., N, to distinguish the address spaces of different instances. Afterwards, the formula dma_va=video_va+id<<32 can be used to map the first virtual address space 201 of each codec instance, i.e., video_va, to the corresponding second sub-virtual address space 203, i.e., dma_va, in the second virtual address space 202, using the offset calculated by the unique identifier. Here, id<<32 is a bit operation, which means shifting the binary representation of id to the left by 32 bits. In the diagram, since the 4G address space corresponds to a 32-bit address length, "id<<32" can be equivalent to "id×4G", so that the first virtual address space of the Nth codec instance, after being offset by N×4G, can accurately fall into the 4G subspace allocated to it in the second virtual address space 202, i.e., the second sub-virtual address space 203. Specifically, for example, the codec instance with a unique identifier of 0 can be mapped to the second sub-virtual address space 203 of 0~4G after offsetting 0×4G, and the codec instance with a unique identifier of 1 can be mapped to the second sub-virtual address space 203 of 4~8G after offsetting 1×4G (i.e., id<<32).

[0048] In some embodiments, the above Figure 1The address management method 100 for heterogeneous systems shown may further include: allocating a first physical address space to each data processing module by applying for discrete physical memory page addresses at a page granularity, wherein the size of the first physical address space is equal to the size of the first virtual address space.

[0049] In the example, the granularity may refer to the granularity of a preset memory page, which may be pre-set by a unified memory management unit according to the hardware architecture and performance requirements, such as 4KB, etc., as the minimum unit of memory allocation. Discrete physical memory pages may indicate that the requested physical memory pages are not continuously distributed in the actual physical address space, but are scattered in different physical address locations. The use of a discrete allocation method can avoid allocation failures caused by insufficient continuous memory blocks, and can also improve the overall utilization of physical memory. The first physical address space may be an actual physical storage area allocated to the data processing module, used to carry data accessed by the module through the first virtual address space, and its size may be equal to the first virtual address space to ensure that each address in the virtual address space can correspond to a unique physical address, thereby meeting the memory capacity requirements of the data processing module.

[0050] Therefore, through discrete page allocation and page granularity management, while ensuring that the data processing module obtains sufficient physical memory, the utilization and allocation flexibility of physical memory are improved, the limitations of continuous memory allocation are avoided, and the effectiveness of data access is ensured by adapting to the virtual address mapping mechanism.

[0051] In some embodiments, a first physical address space is allocated to each data processing module by applying for discrete physical memory page addresses at a page granularity, including: constructing multiple physical memory page address queues, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a group of physical memory page addresses, and the group of physical memory page addresses are the same in the address bits exceeding the first virtual address space; for each physical memory page address obtained in the application, based on the address bits of the physical memory page address exceeding the first virtual address space, determining the physical memory page address queue corresponding to the physical memory page address in the multiple physical memory page address queues; and in response to any physical memory page address queue in the multiple physical memory page address queues reaching the threshold capacity first, selecting a group of physical memory page addresses stored in the physical memory page address queue.

[0052] In the example, the physical memory page address queue may refer to a collection for centrally storing physical memory page addresses. The preset threshold capacity of each queue is equal to the size of the first physical address space, that is, it can just accommodate all the physical memory pages required by each data processing module, so that the physical pages that meet specific address characteristics can be classified and managed, which facilitates the rapid screening of available memory. The address bits exceeding the first virtual address space may refer to the bit segment in the address of the physical memory page that is higher than the maximum address of the first virtual address space. For example, if the maximum address of the first virtual address space is 32 bits, the address bits exceeding are 33 bits and above. The address bits exceeding the first virtual address space of the physical page addresses in the same queue are the same, which can represent that these physical page addresses belong to the same high address segment, thereby satisfying the hardware constraints of the data processing module on the physical address.

[0053] In the example, when constructing multiple physical memory page address queues, queues can be pre-created based on different possible high address segments. Each queue only stores physical page addresses with the same address bits exceeding the first virtual address space, and the threshold capacity of the queue is set to the total number of physical pages corresponding to the first physical address space. This type of grouping management can reduce the complexity of subsequent screening. Specifically, for the address of each requested physical memory page, the address bits exceeding the first virtual address space can be extracted, compared with the characteristics of the address bits of each queue, and the physical page address can be assigned to the corresponding queue, thereby ensuring that the physical page addresses of the same queue always meet the conditions of high address segment consistency.

[0054] In the example, when the number of physical pages of a queue among multiple queues reaches the threshold capacity first, since the physical page address of the queue can both meet the hardware constraints of high address segment consistency and meet the memory capacity requirements of the data processing module, all physical page addresses stored in the queue can be selected to form the first physical address space.

[0055] Therefore, through queue management and address bit screening, the allocated physical memory page addresses are ensured to meet the hardware constraints of the data processing module and efficiently match the capacity requirements, thereby improving the accuracy and efficiency of physical memory allocation and reducing the risk of hardware anomalies caused by address incompatibility.

[0056] Figure 3 is a schematic diagram illustrating applying discrete physical memory page addresses according to an exemplary embodiment.

[0057] like Figure 3As shown, taking a codec instance that handles data processing tasks such as video encoding and decoding as an example, when allocating the first physical address space for the codec instance, discrete physical memory page addresses can be requested at a page granularity. First, multiple physical memory page address queues 301 (e.g., queues 0 through 3) can be constructed. The threshold capacity of each queue can be consistent with the size of the first physical address space required by each codec instance. Each physical memory page address queue 301 can store a set of physical memory page addresses 302 (e.g., page address 0 to page address M, page address 0 to page address N, page address 0 to page address P, and page address 0 to page address Y). Each physical memory page address queue 301 is identical in the address bits that exceed the first virtual address space of the codec instance to accommodate the codec hardware's constraints on the high-address bits of physical addresses. When requesting discrete physical memory pages, the physical memory page address 302 can be assigned to the corresponding physical memory page address queue 301 based on the address bits that exceed the first virtual address space, ensuring that the physical page addresses in the same queue meet the high-address bit consistency requirement. Once a physical memory page address queue 301 reaches the threshold capacity first, the discrete physical memory page addresses of the queue may be selected and allocated to the codec instance, and other physical memory address pages of other queues that have not reached the threshold capacity may be released.

[0058] In some embodiments, the above Figure 1 The address management method 100 shown for heterogeneous systems may also include: reserving a first sub-virtual address space in the first virtual address space of each data processing module, wherein the size of each first sub-virtual address space is the same; and mapping the first sub-virtual address space of at least one data processing module to the same first sub-physical address space within the first physical address space, wherein the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

[0059] In the example, the first sub-virtual address space may refer to a specific range pre-demarcated in the first virtual address space of each data processing module, and its size may be consistent in all data processing modules. The first sub-physical address space may refer to an independent storage area in the physical memory, the size of which is equal to that of the first sub-virtual address space, and serves as a physical carrier for data shared by all data processing modules. The reservation operation may be completed during the module initialization phase, for example, by demarcating continuous address segments in the first virtual address space. In addition, the first sub-virtual address space reserved for each data processing module is of the same size, which can ensure that the virtual address logic of each module accessing shared data is consistent, thereby simplifying address recognition across modules.

[0060] Therefore, by reserving the mapping between the first sub-virtual address and the corresponding first sub-physical address, direct sharing between data processing modules without the need for data copying is achieved, which not only ensures the consistency and stability of the shared address, but also reduces cross-module data interaction, thereby improving system sharing efficiency and data consistency.

[0061] Figure 4 is a schematic diagram illustrating mapping of a first sub-virtual address space and a first sub-physical address space according to an exemplary embodiment.

[0062] like Figure 4 As shown, still taking the data processing module as an example of a codec instance (such as an independent process that performs video codec tasks), as shown on the left side of the figure, each codec instance can have an independent first virtual address space. During the initialization phase, in order to achieve efficient data sharing between codec instances, a fixed-size first sub-virtual address space 401 of, for example, 0 to 512M can be reserved in the first virtual address space of each codec instance. This address space is the same size in each codec instance to serve as a virtual entry for shared data access. When codec instances need to exchange, for example, encoding parameters or intermediate frame data, access can be initiated through the first sub-virtual address space 401 in their respective first virtual address spaces. At the same time, as shown on the right side of the figure, the first sub-virtual address space 401 of all codec instances can be mapped to the same first sub-physical address space 402, which also has a space size of 512M. In this way, there is no need to copy data between codec instances. By mapping virtual addresses to shared physical space, real-time collaboration needs can be achieved.

[0063] In some embodiments, the above Figure 1 The address management method 100 shown for heterogeneous systems may also include: in response to an external data storage module providing a target physical address to any data processing module in at least one data processing module, searching a preset cache list for a target virtual address corresponding to the currently provided target physical address, or redetermining a target virtual address corresponding to the currently provided target physical address, the target virtual address being in a first virtual address space, wherein the cache list records a mapping relationship between at least one target physical address already provided by the external data storage module and the corresponding target virtual address, as well as a timestamp when the mapping relationship is established.

[0064] In the example, the external data storage module may point to an independent storage unit that provides the data to be processed to the data processing module, which can transfer data through the physical address; the target physical address may refer to the storage location identifier of the external data in the physical memory; the target virtual address may refer to the address within the first virtual address space accessible to the data processing module, for establishing a mapping between the target virtual address and the target physical address; the cache list may refer to a set of preset dynamic mapping records, in which the mapping relationship between the established target physical address and the target virtual address and the timestamp corresponding to the creation of the mapping can be stored.

[0065] In this example, direct memory access by the external data storage module has a relatively high latency, limited data bandwidth, and is managed by the external data storage module for both allocation and release. Therefore, the lifecycle of the external data storage module is invisible to the data processing module (e.g., the camera, network, file system, etc., which are only responsible for the allocation, filling, and release of physical memory). It is impossible to synchronize the allocation and release of the data processing module's virtual memory with the external data storage module's physical memory. The only solution is to allocate the corresponding virtual memory before use and release it after use. This solution results in frequent CPU access to device memory to update the codec page table. For these reasons, a cache list mechanism can be used to reduce the overhead associated with page table updates.

[0066] In the example, further, since the cache list capacity is limited, when inserting a new mapping will cause the cache list to exceed the preset capacity, the cache list can be traversed to filter out the mapping entry with the earliest timestamp, that is, the mapping entry that has not been accessed for the longest time, and the target virtual address occupied by it can be released and re-marked as free for subsequent reuse, and the old entry can be removed from the cache list to make room for the new mapping.

[0067] Therefore, by recording or reusing mapping relationships in the cache list, redundant operations of repeatedly allocating virtual addresses and updating page tables are avoided, reducing the performance overhead caused by address mapping; the timestamp cache elimination mechanism ensures that the mapping relationships of frequently accessed data are retained first, maximizing address reuse efficiency within limited cache capacity, and improving the efficiency of data interaction between data processing modules and external storage in heterogeneous systems.

[0068] In some embodiments, searching for a target virtual address corresponding to a target physical address from a preset cache list includes: in response to determining that a target virtual address corresponding to a currently provided target physical address exists in the cache list, obtaining the target virtual address from the cache list; and updating the corresponding timestamp in the cache list based on the time when the target virtual address is obtained.

[0069] In this example, when the external data storage module passes the target physical address to the data processing module, it can prioritize searching the cache list to take advantage of the repeated access characteristics of the external data and reduce duplicate address mappings. Specifically, the currently input target physical address can be matched one by one with the physical addresses recorded in the cache list. If an identical entry exists, the corresponding target virtual address can be directly extracted, and the timestamp of the entry is marked as the most recent access time, ensuring that the frequently accessed mapping relationships in the cache list are retained longer.

[0070] Therefore, by reusing the existing mapping relationships and the timestamp update mechanism, we can not only reduce the number of repeated accesses and optimize cache management, but also improve the efficiency of the data processing module in accessing external data and ensure that the frequently used mapping relationships in the cache list are retained.

[0071] In some embodiments, redetermining the target virtual address corresponding to the currently provided target physical address includes: in response to determining that the target virtual address corresponding to the currently provided target physical address does not exist in the cache list, reallocating the corresponding target virtual address for the target physical address; and updating the cache list based on the mapping relationship between the currently provided target physical address and the reallocated target virtual address, and the timestamp when the mapping relationship is established.

[0072] In the example, when it is determined after retrieving the cache list that there is no target virtual address corresponding to the current target physical address, the corresponding target virtual address can be reallocated for the target physical address. Specifically, an unoccupied virtual address can be screened out in the first virtual address space of the first data processing module and determined as the corresponding target virtual address. Then, based on the mapping relationship between the target virtual address and the target physical address, as well as the corresponding timestamp, the cache list can be updated to ensure that the data processing module can access external data through the target virtual address.

[0073] Therefore, by dynamically creating new address mappings and updating the cache list, we ensure that the data processing module can effectively access the new target physical address and lay the foundation for reuse for subsequent repeated accesses. At the same time, combining timestamps to manage cache resources further improves the flexibility and overall efficiency of the system's address mapping.

[0074] Figure 5 is a schematic diagram illustrating a mapping relationship cache according to an exemplary embodiment.

[0075] like Figure 5As shown, the data processing module can be, for example, a codec instance that independently handles video stream encoding and decoding tasks, and the external data storage module can be, for example, a storage unit that stores raw video frames and encoding configuration parameters. A cache list 504 records the target physical address 501 previously provided by the external data storage module to the codec instance, the corresponding target virtual address 502 within the first virtual address space of the codec instance, and the timestamp 503 of the mapping establishment. When the external data storage module provides the codec instance with the target physical address 501, i.e., the physical memory location corresponding to the codec data to be processed, the address mapping can be determined based on the preset cache list 504. Specifically, the codec instance can first search the cache list 504. If the target physical address 501 already has a corresponding record, it can directly obtain the target virtual address 502 in the first virtual address space to access the data, and simultaneously update the timestamp 503 of the record to mark the latest access time. If the corresponding mapping relationship record does not exist in the cache list 504, it can apply for a new target virtual address 502 in the first virtual address space of the codec instance, and establish a mapping between the target virtual address 502 and the target physical address 501 by updating the page table. At the same time, the mapping in the cache list 504 that has not been accessed by the codec instance for the longest time is removed, the corresponding target virtual address 502 is released, and the new mapping relationship (including the target physical address 501, the target virtual address 502, and the current timestamp 503) is inserted into the cache list 504. In this way, with the help of cache reuse and dynamic updates, the address requirements of the codec instance for data access can be adapted, the efficiency of data interaction in the codec process can be improved, and the smooth execution of the codec task can be ensured.

[0076] An embodiment of the present disclosure also provides an address management device for a heterogeneous system.

[0077] Figure 6 is a schematic block diagram illustrating an address management apparatus 600 for a heterogeneous system according to an exemplary embodiment.

[0078] The division unit 601 is configured to divide the second virtual address space of the data transmission module into at least one second sub-virtual address space, the same number as the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module.

[0079] The identifier allocating unit 602 is configured to allocate a unique identifier to each data processing module, wherein the unique identifier is a natural number.

[0080] The offset unit 603 is configured to offset the first virtual address space by a preset offset via a unique identifier for each first virtual address space, so as to determine a second sub-virtual address space corresponding to the first virtual address space among at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space.

[0081] The relationship establishing unit 604 is configured to establish a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

[0082] The operations of the above-mentioned division unit 601, identifier allocation unit 602, offset unit 603 and relationship establishment unit 604 can be combined with Figure 1 The operations of steps S101, S102, S103 and S104 are the same, so details of each aspect thereof will not be repeated here. In addition, the apparatus 600 and the above-mentioned units may further include further submodules.

[0083] In some embodiments, the device 600 may further include an address space allocation unit 605, which is configured to allocate a first physical address space to each data processing module by applying for discrete physical memory page addresses at a page granularity, and the size of the first physical address space is equal to the size of the first virtual address space.

[0084] In some embodiments, the address space allocation unit 605 may include a queue construction unit 6051, which is configured to construct multiple physical memory page address queues, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a group of physical memory page addresses, and the group of physical memory page addresses are the same in the address bits exceeding the first virtual address space; a queue determination unit 6052, which is configured to determine, for each physical memory page address obtained in the application, the physical memory page address queue corresponding to the physical memory page in the multiple physical memory page address queues based on the address bits of the physical memory page address exceeding the first virtual address space; a storage unit 6053, which is configured to select a group of physical memory page addresses stored in the physical memory page address queue in response to any physical memory page address queue in the multiple physical memory page address queues reaching the threshold capacity first.

[0085] In some embodiments, the device 600 may further include a reservation unit 606, configured to reserve a first sub-virtual address space in the first virtual address space of each data processing module, wherein the size of each first sub-virtual address space is the same; a mapping unit 607, configured to map the first sub-virtual address space of at least one data processing module to the same first sub-physical address space in the first physical address space, wherein the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

[0086] In some embodiments, the device 600 may also include an address determination unit 608, which is configured to, in response to the external data storage module providing a target physical address to any data processing module of at least one data processing module, search for a target virtual address corresponding to the currently provided target physical address from a preset cache list, or redetermine the target virtual address corresponding to the currently provided target physical address, where the target virtual address is in the first virtual address space, wherein the cache list records the mapping relationship between at least one target physical address already provided by the external data storage module and the corresponding target virtual address and the timestamp when the mapping relationship is established.

[0087] In some embodiments, the address determination unit 608 may include an acquisition unit 6081, a timestamp update unit 6082, a reallocation unit 6083, and a list update unit 6084. The acquisition unit 6081 is configured to acquire the target virtual address from the cache list in response to determining that the target virtual address corresponding to the currently provided target physical address exists in the cache list. The timestamp update unit 6082 is configured to update the corresponding timestamp in the cache list based on the time when the target virtual address was acquired. The reallocation unit module 6083 is configured to reallocate the corresponding target virtual address to the target physical address in response to determining that the target virtual address corresponding to the currently provided target physical address does not exist in the cache list. The list update unit 6084 is configured to update the cache list based on the mapping relationship between the currently provided target physical address and the reallocated target virtual address, as well as the timestamp when the mapping relationship is established.

[0088] While specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the various modules discussed herein may be separated into multiple modules, and / or at least some functions of multiple modules may be combined into a single module. A specific module as discussed herein performing an action may include the specific module itself performing the action, or alternatively, the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the specific module). Thus, a specific module that performs an action may include the specific module itself that performs the action and / or another module that the specific module calls or otherwise accesses to perform the action.

[0089] It should also be understood that the above Figure 6The various modules described can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer program code / instructions that are configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuits. For example, these modules can be implemented together in a system on chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a central processing unit (CPU), a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), a memory, one or more communication interfaces, and / or one or more components in other circuits), and may optionally execute the received program code and / or include embedded firmware to perform the functions.

[0090] According to one aspect of the present disclosure, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any one of the method embodiments described above.

[0091] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any method embodiment described above are implemented.

[0092] According to one aspect of the present disclosure, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps of any one of the method embodiments described above are implemented.

[0093] In the following, combined Figure 7 Illustrative examples of such a computer device, non-transitory computer-readable storage medium, and computer program product are described.

[0094] Figure 7 An example configuration of a computer device 700 is shown that may be used to implement the methods described herein.

[0095] Computer device 700 can be a variety of different types of devices. Examples of computer device 700 include, but are not limited to, a desktop computer, a server computer, a laptop or netbook computer, a mobile device (e.g., a tablet computer, a cellular or other wireless phone (e.g., a smartphone), a notepad computer, a mobile station), a wearable device (e.g., eyeglasses, a watch), an entertainment device (e.g., an entertainment appliance, a set-top box communicatively coupled to a display device, a game console), a television or other display device, an automobile computer, and the like.

[0096] Computer device 700 may include at least one processor 702, memory 704, communication interface(s) 706, a display device 708, other input / output (I / O) devices 710, and one or more mass storage devices 712, all capable of communicating with one another, such as through a system bus 714 or other appropriate connection.

[0097] The processor 702 may be a single processing unit or multiple processing units, all of which may include a single or multiple computing units or multiple cores. The processor 702 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operational instructions. Among other capabilities, the processor 702 may be configured to retrieve and execute computer-readable instructions stored in the memory 704, mass storage device 712, or other computer-readable media, such as program code for an operating system 716, program code for application programs 718, program code for other programs 720, and the like.

[0098] Memory 704 and mass storage device 712 are examples of computer-readable storage media for storing instructions that are executed by processor 702 to implement the various functions described above. For example, memory 704 may generally include both volatile memory and non-volatile memory (e.g., RAM, ROM, etc.). Additionally, mass storage device 712 may generally include a hard drive, a solid-state drive, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, and the like. Memory 704 and mass storage device 712 may be collectively referred to herein as memory or computer-readable storage media and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by processor 702 as a specific machine configured to implement the operations and functions described in the examples herein.

[0099] A number of programs may be stored on the mass storage device 712. These programs include an operating system 716, one or more application programs 718, other programs 720, and program data 722, and may be loaded into the memory 704 for execution. Examples of such applications or program modules may include, for example, Figure 1 Computer program logic (eg, computer program code or instructions) of the illustrated method 100 and / or further embodiments described herein.

[0100] Although Figure 7704 of computer device 700, but operating system 716, application programs 718, other programs 720, and program data 722, or portions thereof, may be implemented using any form of computer-readable media that can be accessed by computer device 700. As used herein, "computer-readable media" includes at least two types of computer-readable media, namely, computer-readable storage media and communication media.

[0101] Computer-readable storage media includes volatile and nonvolatile, removable and non-removable media implemented by any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVDs), or other optical storage devices, magnetic cassettes, magnetic tape, magnetic disk storage devices, or other magnetic storage devices, or any other non-transmission media that can be used to store information for access by a computer device. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism. Computer-readable storage media, as defined herein, does not include communication media.

[0102] One or more communication interfaces 706 are used to exchange data with other devices, such as through a network, a direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), a wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth TM The communication interface 706 may include a wireless network interface, a near field communication (NFC) interface, and the like. The communication interface 706 may facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, and the like. The communication interface 706 may also provide for communication with external storage devices (not shown) such as storage arrays, network attached storage, storage area networks, and the like.

[0103] In some examples, a display device 708 such as a monitor may be included for displaying information and images to the user. Other I / O devices 710 may be devices that receive various inputs from the user and provide various outputs to the user, and may include a touch input device, a gesture input device, a camera, a keyboard, a remote control, a mouse, a printer, an audio input / output device, and the like.

[0104] The techniques described herein can be supported by these various configurations of computer device 700 and are not limited to the specific examples of the techniques described herein. For example, the functionality can also be implemented in whole or in part in a "cloud" using a distributed system. The cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the cloud's hardware (e.g., servers) and software resources. Resources can include applications and / or data that can be used when performing computing processing on servers remote from computer device 700. Resources can also include services provided over the Internet and / or through subscriber networks such as cellular or Wi-Fi networks. The platform can abstract resources and functionality to connect computer device 700 with other computer devices. Therefore, the implementation of the functionality described herein can be distributed throughout the cloud. For example, functionality can be implemented partially on computer device 700 and partially through a platform that abstracts the functionality of the cloud.

Claims

1. An address management method for a heterogeneous system, characterized in that: The heterogeneous system includes at least one data processing module and a data transmission module, the size of a first virtual address space of each of the at least one data processing module is the same, and the size of a second virtual address space of the data transmission module is greater than or equal to the sum of the first virtual address spaces of all the at least one data processing module. The method includes: Divide the second virtual address space of the data transmission module into at least one second sub-virtual address space, the number of which is the same as the number of the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module; Assigning a unique identifier to each data processing module, wherein the unique identifier is a natural number; for each first virtual address space, offsetting the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and a size of the first virtual address space; and A mapping relationship is established between each first virtual address space and the corresponding second sub-virtual address space.

2. The method according to claim 1, characterized in that The method further comprises: By applying for discrete physical memory page addresses at a page granularity, a first physical address space is allocated to each data processing module, where the size of the first physical address space is equal to the size of the first virtual address space.

3. The method according to claim 2, characterized in that The method of allocating a first physical address space to each data processing module by applying for discrete physical memory page addresses at a page granularity includes: constructing a plurality of physical memory page address queues, wherein a threshold capacity of each physical memory page address queue is the same as a size of the first physical address space and is used to store a set of physical memory page addresses, the set of physical memory page addresses being identical in address bits exceeding the first virtual address space; For each physical memory page address obtained by the application, determining a physical memory page address queue corresponding to the physical memory page address in the plurality of physical memory page address queues based on an address bit of the physical memory page address exceeding the address bit of the first virtual address space; and In response to any physical memory page address queue of the plurality of physical memory page address queues reaching the threshold capacity first, the set of physical memory page addresses stored in the physical memory page address queue is selected.

4. The method according to claim 2 or 3, characterized in that The method further comprises: reserving a first sub-virtual address space in the first virtual address space of each data processing module, wherein the sizes of each first sub-virtual address space are the same; and The first sub-virtual address space of all the at least one data processing modules is mapped to the same first sub-physical address space in the first physical address space, and the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

5. The method according to any one of claims 1 to 3, characterized in that The method further comprises: In response to an external data storage module providing a target physical address to any data processing module among the at least one data processing module, a target virtual address corresponding to the currently provided target physical address is searched from a preset cache list, or a target virtual address corresponding to the currently provided target physical address is re-determined, and the target virtual address is in the first virtual address space, wherein the cache list records the mapping relationship between at least one target physical address already provided by the external data storage module and the corresponding target virtual address and the timestamp when the mapping relationship is established.

6. The method according to claim 5, wherein The searching for the target virtual address corresponding to the target physical address from a preset cache list includes: In response to determining that the target virtual address corresponding to the currently provided target physical address exists in the cache list, acquiring the target virtual address from the cache list; and The corresponding timestamp in the cache list is updated based on the time when the target virtual address is acquired.

7. The method according to claim 5, wherein The re-determining the target virtual address corresponding to the currently provided target physical address includes: In response to determining that the target virtual address corresponding to the currently provided target physical address does not exist in the cache list, reallocating a corresponding target virtual address for the target physical address; and The cache list is updated based on a mapping relationship between the currently provided target physical address and the reallocated target virtual address, and a timestamp when the mapping relationship is established.

8. An address management device for a heterogeneous system, characterized in that: The heterogeneous system includes at least one data processing module and a data transmission module, the size of a first virtual address space of each of the at least one data processing module is the same, and the size of a second virtual address space of the data transmission module is greater than or equal to the sum of the first virtual address spaces of all the at least one data processing module, and the device includes: a dividing unit, configured to divide the second virtual address space of the data transmission module into at least one second sub-virtual address space, the number of which is the same as the number of the at least one data processing module, wherein a size of each second sub-virtual address space is the same as a size of the first virtual address space of each data processing module; an identifier allocating unit, configured to allocate a unique identifier to each data processing module, wherein the unique identifier is a natural number; an offset unit configured to, for each first virtual address space, offset the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and a size of the first virtual address space; and The relationship establishing unit is configured to establish a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

9. A computer device, characterized in that: The computer device comprises: at least one processor; and A memory having a computer program stored thereon, wherein when the computer program is executed by the at least one processor, the at least one processor is caused to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 7.

11. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 7.

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