Processor data cache side channel attack protection architecture based on rapid flashing

Abstract

The invention discloses a processor data cache side channel attack protection architecture based on rapid flashing. The main purpose of the invention is to reduce extra performance loss caused by protection measures while protecting the channel attack on the cache side based on a rapid flashing mode. By introducing the design of the survival time, rows in the cache are selectively written back through comparison of the survival time and the global time mark when the cache is flashed, and high write-back overhead is hidden in the period of multiple times of flashing and processor execution. Compared with a classic cache flashing method, the method has the advantages that the cache flashing efficiency is improved while the side channel attack protection capability is ensured, and the additional performance overhead of a flashing-based cache side channel attack protection scheme is effectively reduced.

Description

Technical field:

[0001] The invention discloses a processor data cache side channel attack protection architecture based on fast flash writing, relates to processor data cache side channel attack protection technology, and belongs to the field of computer technology. Background technology:

[0002] With the continuous development of the information age, cache-mediated side-channel attacks are becoming an increasingly significant threat to processor security, leading to the leakage of sensitive data and private information. Designing specific hardware architectures to effectively defend against cache side-channel attacks has become a hot topic in the field of processor security.

[0003] Existing protection methods against cache side-channel attacks are mainly divided into two categories: cache flushing-based methods and address randomization-based methods.

[0004] 1) Cache side-channel attack protection method based on cache flushing

[0005] The cache side-channel attack protection method based on cache flushing refers to the process of invalidating all valid data lines in the cache through the cache flushing method provided by the processor at the end of the victim program execution, erasing the victim's execution traces in the cache to prevent attackers from obtaining sensitive information through the cache state. This method is mainly used in the first-level cache and the second-level cache, where the performance loss caused by cache flushing is relatively small. However, the implementation of this method requires traversing and processing each line of data in the cache one by one. When the cache adopts a write-back strategy, the modified data line needs to be written back to the next level of storage unit. This mechanism blocks the execution of the pipeline during flushing, inevitably introducing a high performance overhead. Especially in cache structures with large capacity and a large number of lines, the performance loss is particularly significant, seriously affecting the overall execution efficiency of the processor.

[0006] 2) Cache side-channel attack protection method based on address randomization

[0007] The cache side-channel attack protection method based on address randomization refers to the process of randomizing the mapping of the group number in the memory access address to the group address in the cache through certain encryption and decryption operations. Dynamic address randomization mapping is achieved through a dynamically changing key and address remapping mechanism, isolating the attacker from the victim's cache and achieving protection against side-channel attacks. This method is mainly used in last-level caches, where the performance loss caused by cache flushing is relatively high. However, the implementation of the address randomization method usually requires additional hardware resources to perform complex encryption and decryption operations and address remapping processes, increasing the complexity and cost of hardware implementation. At the same time, the dynamic operation process of address mapping and remapping may also cause additional performance loss, further increasing the overall performance overhead of the processor system.

[0008] In summary, existing cache side-channel attack methods use different protection methods at different cache levels. They isolate the cache states between the attacker and the victim through cache flushing or address randomization, preventing the attacker from obtaining sensitive information through the cache state after the victim's execution, thereby achieving a protective effect. However, existing flushing-based methods introduce higher additional processor performance overhead in the first-level cache, while randomization-based methods introduce higher additional hardware and performance overhead. Summary of the invention:

[0009] This paper discloses a processor data cache side-channel attack protection architecture based on fast flushing. The architecture comprises four components: a time-to-live array, which stores the time-to-live of each cache line; a global time flag, which identifies the current execution time of the data cache and determines whether cache lines need to be written back to the next level of storage during the flushing process; a flushing control unit, which controls the data cache's cache flushing behavior; and a write-back unit, which writes back lines that should be written back during cache idle time. Each component is described in detail below.

[0010] 1) Time-to-Live Array: Since the capacity of the primary data cache is limited, the number of bits for the time-to-live should not incur a high additional hardware overhead. In this invention, the number of bits for the time-to-live is set to 3 bits, which can be flexibly configured in different processor configurations and is not limited to the 3 bits in this invention. This invention introduces a TTL bit for each line in the data cache to record the time-to-live, and the number of bits is also 3 bits. This invention adopts a storage and access method similar to the cache tag array (TAG Array), supports multi-port read and write, and is decoupled from data storage. The TTL flag in the cache line is initialized to 0 during cache initialization. When this line is first fetched into the cache, the TTL flag in the cache line is recorded as the value in the current Time register plus a random value when written. This random value is generated by a simple timer that increments by one each cycle and has a maximum value of 2. When the value after adding the random value is greater than the maximum value of TTL, the maximum value of TTL is written. When the pipeline accesses this line again, the TTL is updated to the value in the current Time register plus the same random value.

[0011] 2) Global Time Flag: This invention adds a register in the data cache, denoted as the Time register. The number of bits of this register is also 3 bits. The global time Time register in the cache is initialized to 0 during initialization and increments by one each time the cache flush is triggered. After reaching the maximum value, it continues to count from 0. After introducing the time-to-live, when the cache performs Tag comparison, the time-to-live is compared simultaneously. The TTL recorded in the cache line is compared with the global time Time. When TTL < Time, it is regarded as a cache miss, even if the valid value in the cache is 1 and the Tag hits at this time. If this line has been modified (the dirty bit is 1), the data is written back when this line is hit or evicted.

[0012] 3) Flush Control Unit: The trigger condition for cache flushing is the explicit call of the program, such as the data cache flush instruction supported by the processor, etc. After the pipeline recognizes this instruction, it passes the flush command to the data cache through the load / store unit as the start flag of cache flushing. The end flag of cache flushing is that the cache traverses to the last cache line and all the lines that should be written back in the write-back unit have been written back to the next-level storage.

[0013] The flush control unit represents the cache line number currently being flushed through a counter. This counter is set to 0 when the processor issues a cache flush request to the data cache. Then, the flush control unit accesses this cache line according to the line number recorded by the counter. The specific process is as follows:

[0014] (3.1) The flush control unit reads the time-to-live of this line stored in the time-to-live array

[0015] (3.2) Compare the read TTL with the value in the Time register.

[0016] (3.3) When TTL < Time, no processing is done on this cache line at this time; when TTL >= Time, perform a normal write-back operation on this cache line, set the valid bit of this cache line to 0, and at the same time add the modified cache line (dirty bit is 1) to the write-back queue for write-back operation.

[0017] (3.4) Repeat the operations in (1.1), (1.2), and (1.3) until the counter in the write-back control unit reaches the maximum value.

[0018] 4) Write-back unit: Based on the original write-back module of the data cache in the present invention, add control logic dedicated to write-back when the cache is idle. When the processor is executing normally and the cache is idle, write back the cache lines that should have been written back but were not during the write-back process to the next-level storage.

[0019] The advantages of the present invention include:

[0020] A processor data cache side-channel attack protection architecture based on fast write-back proposed by the present invention, compared with the prior art, its advantages are:

[0021] The existing methods for protecting processor cache side-channel attacks by using address randomization are not applicable to the first-level data cache with limited resources. The method of using cache write-back occupies a large number of clock cycles during data write-back, introducing a relatively high additional performance overhead. In view of the above problems, the present invention proposes a fast write-back mechanism for data cache based on the survival time, selectively writes off the content in the cache by comparing the survival time, and through the semi-randomized writing of the cache line survival time and write-back when the cache is idle, disperses the cache write-back time in multiple write-backs and the processor execution process, effectively reducing the additional performance overhead while protecting against cache side-channel attacks. Brief description of the drawings:

[0022] Figure 1 Schematic diagram of a processor data cache side-channel attack protection architecture based on fast write-back.

[0023] Figure 2 Example diagram of fast write-back of cache based on survival time. Detailed implementation manners:

[0024] The present invention will be further described in detail below with reference to the accompanying drawings.

[0025] As Figure 1As shown in the figure, it is a schematic diagram of the protection architecture for processor data cache side-channel attacks with fast flashing. When the flush signal from the processor core pipeline reaches the data cache, the counter in the flush control unit is set to 0 and incremented after flushing a cache line. When the value in the counter is less than the maximum line number of the counter cache, the signal generation logic in the flush control unit continuously sends flush signals to the flush control unit pipeline. The flush control pipeline continuously reads the TTL from the time-to-live array and compares it with the Time recorded in the Time register. When TTL < Time, no additional operations are performed on this cache line. When TTL >= Time, normal flushing operations are performed on this cache line, the valid bit of this cache line is set to 0, and at the same time, the modified cache line (dirty bit is 1) is added to the write-back queue in the write-back unit for write-back operations. In addition, during the normal execution phase of the processor, during the cache idle time, the write-back unit writes back the cache lines that should have been written back but have not been written back during the flush phase to the next-level storage.

[0026] As Figure 2 As shown in the figure, it is an example diagram of fast cache flashing based on time-to-live. Initially, there are multiple cache lines with different states in the cache. The time-to-live stored in the current Time register is 3. When a program needs to flush the cache state, it executes a flush instruction to flush the content in the data cache. At this time, the time-to-live stored in the Time register is incremented by 1 and becomes 4. And the flush structure traverses each line in the cache. For cache lines with TTL less than the Time register, such as cache line 0 and cache line 2, they are regarded as directly invalid lines and no additional operations are performed. For cache lines with TTL greater than or equal to the Time register, such as cache line 3 and cache line 5, the cache performs normal flush operations. The cache line 3 is invalidated and written back, and the cache line 5 is invalidated. After the flush instruction is executed, the program executes normally. When the program accesses the data cache again, different state cache lines have different behaviors. For newly filled cache lines, such as cache line 3, the TTL recorded in its cache tag is the current time-to-live 4 in the Time register plus a random value 1. For cache lines with the TTL field less than the time-to-live and not modified (Dirty bit is 0), such as cache line 4, it is regarded as a cache miss at this time and a cache miss operation is executed. For cache lines with the TTL field less than the time-to-live and modified (Dirty bit is 1), such as cache line 2, when this line is evicted, a cache miss and write-back operation behavior will be executed. When the next flush command arrives, the cache continues to perform the above operations to complete fast flushing.

[0027] Finally, it should be noted that the present invention may also have many other application scenarios. Without departing from the spirit and essence of the present invention, technical personnel familiar with the field can make various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the present invention.

Claims

1. A processor data cache side channel attack protection architecture based on fast flashing, characterized in that: Based on the introduction of the time-to-live, selective writing is performed during cache writing. While protecting against common cache side-channel attacks through the cache writing mechanism, the writing efficiency is improved, and the relatively high additional performance overhead brought by the writing method is reduced, including: a time-to-live array for storing the time-to-live of each cache line; a global time flag for identifying the current execution time of the data cache, which is used to determine whether a cache line needs to be written back to the next-level storage during the writing process; a writing control unit for controlling the data cache to perform cache writing operations; a write-back unit for writing back the lines that should be written back during the cache idle time; The process of the processor data cache side-channel attack protection architecture based on fast writing during cache writing is as follows: A counter is used to represent the cache line number currently being written. This counter is set to 0 when the processor issues a cache flushing request to the data cache. Then, the writing control unit accesses the cache line according to the line number recorded by the counter. First, it reads the time-to-live of this line stored in the time-to-live array, and then compares the read time-to-live TTL with the value in the Time register. When TTL < Time, no processing is performed on this cache line at this time; when TTL >= Time, a normal writing operation is performed on this cache line, the valid bit of this cache line is set to 0, and at the same time, the modified cache line is added to the write-back queue for write-back operation. Finally, the cache writing operation is repeated until the counter in the writing control unit reaches the maximum value.

2. The processor data cache side channel attack protection architecture based on fast flashing according to claim 1, characterized in that: The structure of the cache line time-to-live TTL is introduced in the processor data cache side-channel attack protection architecture based on fast writing. A time-to-live array is added to the cache, and selective write-back is performed during cache writing. Whether a real write-back is required is judged by comparing with the global time Time.

3. The processor data cache side channel attack protection architecture based on fast flashing according to claim 1, characterized in that: The TTL flag in the cache line of the time-to-live array is initialized to 0 during cache initialization. When this line is first fetched into the cache, the TTL flag in the cache line is recorded as the value in the current Time register plus a random value when being written. This random value is generated by a simple timer that increments by one each cycle and has a maximum value of 2. When the value after adding the random value is greater than the maximum value of TTL, the maximum value of TTL is written. When the pipeline accesses this line again, the TTL is updated to the value in the current Time register plus the same random value.

4. The processor data cache side channel attack protection architecture based on fast flashing according to claim 1, characterized in that: The global time flag Time is initialized to 0 during initialization and increments by one each time a cache writing is triggered. After reaching the maximum value, it continues to count from 0; after introducing the time-to-live, when the cache performs Tag comparison, the time-to-live comparison is also performed simultaneously. The TTL recorded in the cache line is compared with the global time Time. When TTL < Time, it is regarded as a cache miss, even if the valid bit in the cache is 1 and the Tag hits at this time. If this line has been modified, the data is written back when this line is hit or evicted.

5. The processor data cache side channel attack protection architecture based on fast flashing according to claim 1, characterized in that: The write-back unit adds control logic dedicated to writing back when the cache is idle based on the original write-back module of the data cache. When the processor is executing normally and the cache is idle, the cache lines that should have been written back but were not written back during the flush process are written back to the next level of storage.

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