Chip function verification method and device, hardware simulation equipment and storage medium

Abstract

The invention relates to the technical field of chips, and provides a chip function verification method and device, hardware simulation equipment and a storage medium. The method comprises the following steps: in each round of verification process, taking each random number in a random number library as an initial random number in sequence; then performing multiple times of variation processing on the initial random number to obtain a plurality of variation random numbers so as to generate a plurality of test case sets; performing function verification by utilizing each test case set to obtain a label and a verification result of each variation random number, and determining whether to replace the initial random number in the random number library or not according to the labels of all variation random numbers; and finally, if the verification result reaches a preset condition, or if the verification result does not reach the preset condition and the verification round reaches a preset number of times, ending chip function verification. Therefore, the efficiency and the coverage range of chip function verification are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip function verification method, device, hardware simulation equipment and storage medium. Background Art

[0002] During the chip design phase, software platforms such as EDA (Electronic Design Automation) are typically used to test and verify simulated chip functions. This approach, also known as pre-simulation (pre-simulation), is particularly useful for verifying individual functional points and is not suitable for high-load, large-scale system-level testing. In addition to pre-simulation, hardware emulation devices such as EMUs (Emulators) can also be used to verify chip functions. However, the EMU runtime environment (which can only run C / C++ code) has limited support for randomization strategies, making random verification of simulated chip functions within the EMU a significant challenge. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a chip function verification method, apparatus, hardware simulation device and storage medium.

[0004] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0005] In a first aspect, the present invention provides a chip function verification method, which is applied to a hardware simulation device, wherein the hardware simulation device is used to simulate a chip with a set function, and the method comprises:

[0006] In each round of verification, each random number in the preset random number library is used as the initial random number in turn;

[0007] Performing multiple mutations on the initial random number to obtain multiple mutated random numbers, and generating respective test case sets based on the initial random number and each mutated random number;

[0008] Perform functional verification using each test case set to obtain a label for each mutated random number and a verification result, and determine whether to replace the initial random number in the random number library based on the labels of all mutated random numbers;

[0009] If the verification result meets the preset condition, or if the verification result does not meet the preset condition and the verification rounds reach the preset number of times, the chip function verification is terminated.

[0010] In an optional embodiment, the initial random number is subjected to multiple mutation processes to obtain multiple mutated random numbers, including:

[0011] In each of the multiple mutation processes performed on the initial random number, the initial random number is used as the random number to be processed, and the first mutation behavior of the preset mutation sequence is used as the mutation behavior to be executed;

[0012] Randomly obtain at least one position number from a preset position number set and use it as the target position number;

[0013] According to the mutation behavior to be executed and the sequence number of each target position, a mutation operation is performed on each target byte at the corresponding position in the random number to be processed to obtain a processed random number;

[0014] If the mutation behavior to be executed is not the last mutation behavior in the mutation sequence, then the next mutation behavior in the mutation sequence is used as the new mutation behavior to be executed, and after using the processed random number as the new random number to be processed, the process returns to the step of randomly obtaining at least one position number from a preset position number set and using the position number as the target position number.

[0015] If the mutation behavior to be executed is the last mutation behavior of the mutation sequence, the processed random number is used as the mutation random number until the multiple mutation random numbers are obtained.

[0016] In an optional embodiment, the variation behavior includes at least one of the following:

[0017] Invert each bit of the target byte;

[0018] Replace the target bytes with the preset sensitive bytes;

[0019] Randomly replace the target bytes;

[0020] Delete the target bytes;

[0021] Copy the target byte and add it before or after the target byte;

[0022] Add multiple identical random bytes before or after the target bytes.

[0023] In an optional embodiment, generating a respective test case set based on the initial random number and each variant random number includes:

[0024] Taking any one of the initial random number and all the variant random numbers as the target random number;

[0025] According to the bytes in the target random number, multiple target test case templates are selected from a preset multiple functional case library, and each test case is generated based on each target test case template to obtain a test case set for the target random number;

[0026] The initial random number and each mutated random number are traversed to obtain respective test case sets for the initial random number and each mutated random number.

[0027] In an optional embodiment, functional verification is performed using each test case set to obtain a label for each mutated random number and a verification result, including:

[0028] Perform functional verification using the test case set of the initial random number to obtain various test results and test coverage corresponding to the initial random number, and use the test coverage as a reference coverage;

[0029] Use the test case set of each mutated random number to perform functional verification in turn, and obtain the test results and test coverage corresponding to each mutated random number;

[0030] If all test results corresponding to the mutated random number are passed and the test coverage exceeds the reference coverage, the test coverage corresponding to the mutated random number is used as the new reference coverage, and the label of the mutated random number is set to valid;

[0031] If any of the test results corresponding to the mutated random number fails, or if the test coverage corresponding to the mutated random number does not exceed the reference coverage, the label of the mutated random number is set to invalid;

[0032] The reference coverage obtained by traversing all test case sets is used as the verification result.

[0033] In an optional embodiment, determining whether to replace the initial random number in the random number library according to the labels of all mutated random numbers includes:

[0034] If there is a variant random number with a valid label among all the variant random numbers, the initial random number is replaced with the variant random number with a valid label in the random number library;

[0035] If there are multiple variant random numbers with valid labels among all the variant random numbers, then the initial random number is replaced with the variant random number with valid label and the highest test coverage in the random number library;

[0036] If there is no mutated random number with a label of valid among all the mutated data numbers, the initial random number is retained in the random number library.

[0037] In an optional embodiment, the method further comprises:

[0038] During the M-round verification process, if no random numbers in the random number library are replaced, multiple random arrays are obtained based on all the random numbers in the random number library, and a cross operation is performed on the two random numbers in each random array to obtain two new random numbers, and the random number library is updated based on all the new random numbers; where M is a positive integer and is less than the preset number of times.

[0039] In a second aspect, the present invention provides a chip function verification device, which is applied to a hardware simulation device, wherein the hardware simulation device is used to simulate a chip with a set function, and the device includes:

[0040] The acquisition module is used to use each random number in the preset random number library as the initial random number in turn during each round of verification;

[0041] A verification module, configured to perform multiple mutations on the initial random number to obtain multiple mutated random numbers, and generate respective test case sets based on the initial random number and each mutated random number;

[0042] Perform functional verification using each test case set to obtain a label for each mutated random number and a verification result, and determine whether to replace the initial random number in the random number library based on the labels of all mutated random numbers;

[0043] If the verification result meets the preset condition, or if the verification result does not meet the preset condition and the verification rounds reach the preset number of times, the chip function verification is terminated.

[0044] In a third aspect, the present invention provides a hardware simulation device, comprising a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip function verification method described in any one of the aforementioned embodiments is implemented.

[0045] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the chip function verification method described in any one of the aforementioned embodiments is implemented.

[0046] The chip function verification method, device, hardware simulation equipment and storage medium provided by the embodiment of the present invention include: in each round of verification process, each random number in the preset random number library is used as the initial random number in turn; then the initial random number is mutated multiple times to obtain multiple mutated random numbers to generate multiple test case sets; then each test case set is used to perform function verification, and the label and verification result of each mutated random number are obtained, and it is determined whether to replace the initial random number in the random number library based on the labels of all mutated random numbers; finally, if the verification result meets the preset conditions, or if the verification result does not meet the preset conditions and the number of verification rounds reaches the preset number, the chip function verification is terminated. The embodiment of the present invention performs function verification by performing multiple mutation processes on random numbers and generating multiple test case sets, that is, adopting the random number mutation mechanism and the method of dynamically adjusting the random number library, thereby improving the diversity and coverage of test cases, thereby improving the efficiency and accuracy of chip function verification.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 FIG1 shows one of the flow charts of the chip function verification method provided by an embodiment of the present invention;

[0050] Figure 2 FIG2 shows a second flow chart of a chip function verification method provided by an embodiment of the present invention;

[0051] Figure 3 A block diagram of a hardware emulation device provided by an embodiment of the present invention is shown;

[0052] Figure 4 The figure shows a functional module diagram of a chip function verification device provided by an embodiment of the present invention.

[0053] Icons: 100 - hardware simulation device; 110 - processor; 120 - memory; 130 - communication module; 300 - chip function verification device; 310 - acquisition module; 330 - verification module. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0056] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0057] See also Figure 1 , is a flow chart of a chip function verification method provided by an embodiment of the present invention.

[0058] Step S202: In each round of verification, each random number in the preset random number library is used as an initial random number in turn.

[0059] Step S204: perform multiple mutation processes on the initial random number to obtain multiple mutated random numbers, and generate respective test case sets based on the initial random number and each mutated random number.

[0060] Step S206 , performing functional verification using each test case set, obtaining a label of each mutated random number and a verification result, and determining whether to replace the initial random number in the random number library based on the labels of all mutated random numbers.

[0061] Step S208: If the verification result meets the preset condition, or if the verification result does not meet the preset condition and the number of verification rounds reaches the preset number, then the chip function verification ends.

[0062] In this embodiment, a random number library can be pre-set and store multiple random numbers with different data lengths. Based on this random number library, multiple rounds of chip verification may be performed. For the sake of simplicity, this embodiment of the present invention uses a single round of verification as an example.

[0063] During a verification round, a random number is selected from a preset random number library as the initial random number. It's understood that if the chip functional verification termination criteria aren't met during this round, each random number in the random number library is sequentially traversed, meaning each random number is processed similarly. For ease of understanding, the following example uses a single random number as the initial random number.

[0064] First, the initial random number is mutated multiple times to generate multiple variant random numbers. Specifically, each mutation of the initial random number yields one variant random number. The number of mutations can be set, for example, k times, to yield k variant random numbers. Next, based on the initial random number and all the variant random numbers (k+1 random numbers), k+1 test case sets are generated. Each random number generates a separate test case set.

[0065] The generated k+1 test case sets are then used to verify the chip's functionality. Specifically, each test case set is used to perform functional verification on the chip, generating a label for each mutated random number and the corresponding verification results for these k+1 random numbers. This verification result represents the highest test coverage among the initial random number and all mutated random numbers. Furthermore, based on the labels of all mutated random numbers, a decision is made as to whether to replace the original initial random number in the random number library to optimize the data quality of the random number library.

[0066] Finally, the verification result is determined to meet the preset conditions. Specifically, the highest test coverage of the initial random number and all variant random numbers represented by the verification result is determined to meet the preset coverage threshold. If the verification result reaches the coverage threshold, it indicates that most chip functions have been verified, i.e., the set chip verification expectations have been met, and the chip function verification is terminated. If the verification result does not reach the coverage threshold, a further determination is made as to whether the preset number of verification rounds has been reached.

[0067] If the verification rounds reach the preset number, it means that the chip verification expectations cannot be met after a large number of verifications, and the chip functional verification is terminated to facilitate subsequent analysis and optimization of the test case. If the verification rounds do not reach the preset number, then the next random number in the random number library is used as the initial random number, and the process returns to step S204 to perform mutation processing again, generate a test case set and perform functional verification, and determine whether to replace the data. In addition, since the verification rounds do not reach the preset number, after traversing all the random numbers in the random number library in this round, it will enter the next round of verification until the end condition of the chip functional verification is met.

[0068] It can be understood that the embodiment of the present invention performs functional verification by performing multiple mutation processing on random numbers and generating multiple test case sets, that is, adopting the random number mutation mechanism and the dynamic adjustment of the random number library, thereby improving the diversity and coverage of test cases, thereby improving the efficiency and accuracy of chip functional verification.

[0069] Optionally, for the process of performing multiple mutation processes on the initial random number to obtain multiple mutated random numbers in step S204, an embodiment of the present invention provides a possible implementation method.

[0070] Step S204-1: In each of multiple mutation processes performed on the initial random number, the initial random number is used as the random number to be processed, and the first mutation behavior of the preset mutation sequence is used as the mutation behavior to be executed.

[0071] Step S204-2: randomly obtain at least one position number from a preset position number set and use it as the target position number.

[0072] Step S204-3: performing a mutation operation on each target byte at the corresponding position in the random number to be processed according to the mutation behavior to be executed and the sequence number of each target position, to obtain a processed random number.

[0073] Step S204-4: If the mutated behavior to be executed is not the last mutated behavior in the mutated sequence, the next mutated behavior in the mutated sequence is used as the new mutated behavior to be executed, and the processed random number is used as the new random number to be processed, and then the process returns to step S204-2.

[0074] Step S204 - 5 : If the mutation behavior to be executed is the last mutation behavior in the mutation sequence, the processed random number is used as the mutation random number until multiple mutation random numbers are obtained.

[0075] It is understandable that the embodiment of the present invention performs mutation processing on the initial random number in a similar manner each time. For the sake of brief description, one mutation processing is used as an example for explanation below.

[0076] First, an initial random number, such as A0, is used as the random number to be processed. The first mutation behavior is obtained from a preset set of mutation behaviors as the current mutation behavior to be executed. Then, at least one position number is randomly selected from a preset set of position numbers as the target position number. These target position numbers are used to determine the specific byte positions in the random number A0 to be processed that need to be mutated.

[0077] Next, based on the obtained target position sequence number and the mutation behavior to be executed, each target byte at the corresponding position in the random number to be processed A0 is mutated to obtain a processed random number such as A1. It is then determined whether the mutation behavior to be executed is the last mutation behavior in the mutation sequence.

[0078] If the mutation behavior to be executed is not the last mutation behavior in the mutation sequence, it means that there are still unexecuted mutation behaviors in the mutation sequence. In this case, the next mutation behavior in the mutation sequence is used as the new mutation behavior to be executed, and the processed random number A1 is used as the new data number to be processed. Then, the process returns to step S204-2 to execute the process of selecting the position number, executing the mutation operation, and determining whether it is the last mutation behavior again.

[0079] If the mutation behavior to be executed is the last mutation behavior in the mutation sequence, it means that all mutation behaviors in the mutation sequence have been executed, and the processed random number A1 is used as a mutation random number. In a similar way, the initial random number is mutated k times to obtain k mutation random numbers.

[0080] It can be understood that the embodiment of the present invention generates multiple mutated random numbers according to the mutation sequence and randomly selected positions by performing multiple mutation processes on the initial random number, thereby improving data diversity and providing a rich data foundation for subsequent functional verification.

[0081] Optionally, the mutation behavior includes at least one of the following: (1) inverting each bit of the target byte. (2) replacing the target byte with a preset sensitive byte. (3) performing a random replacement on the target byte. (4) deleting the target byte. (5) copying the target byte and adding it before or after the target byte. (6) adding multiple identical random bytes before or after the target byte.

[0082] For ease of understanding, the six aforementioned mutation behaviors are described below.

[0083] For mutation behavior (1), it means performing an inversion operation on each bit in the target byte to change the binary value of the target byte to obtain a new random number. For mutation behavior (2), it means replacing the target byte with a sensitive byte. Among them, the sensitive byte can be understood as a hexadecimal number converted from some pre-set values ​​that may cause chip failures in the verification scenario of the chip. That is, through mutation behavior (2), it is helpful to test potential abnormal conditions of the chip to improve the test coverage.

[0084] Mutation behavior (3) replaces the target byte with a randomly generated byte. Mutation behavior (3) ensures the diversity of random numbers, thereby increasing the diversity of test cases. This avoids the limitation of random number coverage caused by mutation behavior (2) replacing bytes with certain sensitive bytes. Mutation behavior (4) deletes the target byte, which makes the generated mutated random numbers structurally diverse.

[0085] Mutation behavior (5) means inserting the target byte before or after the target byte. Mutation behavior (6) means inserting multiple identical random bytes before or after the target byte. Through mutation behaviors (5) and (6), the length and content of the mutated random number can be diversified, thereby increasing the complexity of the mutated random number and improving the diversity of test cases.

[0086] It is understandable that multiple variation behaviors can be randomly selected from the above six variation behaviors to form a variation sequence, or the above six variation behaviors can be used together to form a variation sequence, and the order of each variation behavior in the variation sequence can also be set according to actual conditions, which is not limited in the embodiment of the present invention.

[0087] It can be understood that the embodiment of the present invention performs different mutation operations on the target bytes in the initial random number by setting multiple mutation behaviors to generate mutated random numbers of different forms and characteristics, providing a rich data source for subsequent functional verification and improving the coverage and effectiveness of chip functional verification.

[0088] Optionally, for the process of generating respective test case sets based on the initial random number and each mutated random number in step S204, an embodiment of the present invention provides a possible implementation method.

[0089] Step S204-6: Use any one of the initial random number and all the mutated random numbers as the target random number.

[0090] Step S204-7, selecting multiple target test case templates from multiple preset functional case libraries according to the bytes in the target random number, and generating each test case based on each target test case template to obtain a test case set for the target random number.

[0091] Step S204-8, traverse the initial random number and each mutated random number to obtain a test case set for the initial random number and each mutated random number.

[0092] In this embodiment, the types of functions to be verified can be pre-set, such as I2C (Inter-Integrated Circuit) function, SPI (Serial Peripheral Interface) function, Timer function and DMA (Direct Memory Access) function, etc. Among them, the I2C function represents the I2C interface function of the verification chip, the SPI function represents the SPI interface function of the verification chip, the Timer function represents the timer function of the verification chip, and the DMA function represents the direct memory access function of the verification chip. In addition, each function has a corresponding function use case library, which contains a plurality of pre-set test case templates for testing this function. It should be understood that the types of functions to be verified and the test case templates in the function use case library can be set according to actual conditions, and the embodiments of the present invention do not limit them.

[0093] It is understood that the generation methods of the test case sets for the initial random number and each variant random number in the embodiments of the present invention are similar. For the sake of simplicity, the target random number is used as an example for explanation. First, the first unused byte of the target random number is used as a calibration byte. Then, based on the calibration byte, a target functional use case library is selected from multiple preset functional use case libraries, and the byte following the calibration byte is obtained to obtain a selected byte. Based on the selected byte, a target test case template is selected from the target functional use case library.

[0094] For example, a mapping relationship between bytes, function case libraries, and test case templates can be pre-established, and the mapping relationship can be used to select a target function case library and a target test case template. Alternatively, a target function case library can be selected by converting a calibrated byte into a decimal number to obtain a first value, and calculating the remainder between the first value and the total number of function case libraries. Alternatively, a target test case template can be selected by converting a selected byte into a decimal number to obtain a second value, and calculating the remainder between the second value and the total number of test case templates in the target function case library.

[0095] Next, the calibrated bytes and the selected bytes are taken as consumed bytes, and the total number of unconsumed bytes in the target random number is determined. Subsequently, the total number of unconsumed bytes in the target random number is compared with the number of input bytes of the target test case template.

[0096] If the total number of unconsumed bytes in the target random number is greater than the number of input bytes of the target test case template, then the corresponding input bytes are obtained in the bytes after the selected byte of the target random number according to the input byte number. For example, if the number of input bytes is w, then the w bytes after the selected byte in the target random number are taken together as input bytes. And based on the input bytes and the target test case template, a test case is generated and added to the test case set of the target random number. Subsequently, the input byte is used as the consumed byte to re-determine the unconsumed bytes in the target random number, and then the step of using the first unconsumed byte in the target random number as the calibration byte is returned to execute again the process of selecting the target function case library and the target test case template, determining the total number of unconsumed bytes and comparing it with the input byte number of the target test case template.

[0097] If the total number of unconsumed bytes in the target random number is equal to the number of input bytes of the target test case template, then the corresponding input bytes are obtained in the bytes after the selected byte of the target random number according to the input byte number. For example, if the number of input bytes is w, then the w bytes after the selected byte in the target random number are taken as the input bytes. And based on the input bytes and the target test case template, a test case is generated and added to the test case set of the target random number, that is, the test case set of the target random number is obtained. If the total number of unconsumed bytes in the random number is less than the number of input bytes of the target test case template, then the test case set of the target random number is directly obtained.

[0098] By processing the initial random number and each mutated random number in a similar manner, respective test case sets for the initial random number and each mutated random number can be obtained.

[0099] It can be understood that the embodiments of the present invention achieve efficient and flexible test case generation by parsing random numbers byte by byte and combining them with a functional test case library. This also fully utilizes the diversity of random numbers, improves test coverage, and enhances the accuracy and reliability of chip functional verification.

[0100] Optionally, for the process of performing functional verification using each test case set in step S206 to obtain a label of each mutated random number and a verification result, an embodiment of the present invention provides a possible implementation method.

[0101] Step S206 - 1 , performing function verification using the test case set of the initial random number, obtaining various test results and test coverage corresponding to the initial random number, and using the test coverage as a reference coverage.

[0102] Step S206 - 2 , performing functional verification using the test case set of each mutated random number in turn, and obtaining various test results and test coverage corresponding to each mutated random number.

[0103] Step S206-3: If all test results corresponding to the mutated random number are passed and the test coverage exceeds the reference coverage, the test coverage corresponding to the mutated random number is used as a new reference coverage, and the label of the mutated random number is set to valid.

[0104] Step S206 - 4 : If any of the test results corresponding to the mutated random number fail, or if the test coverage corresponding to the mutated random number does not exceed the reference coverage, the label of the mutated random number is set to invalid.

[0105] Step S206-5: The reference coverage obtained by traversing all test case sets is used as the verification result.

[0106] In this embodiment, functional verification is first performed using a test case set for the initial random number. The chip is then recorded for any abnormalities such as comparison errors to obtain the test results and test coverage corresponding to the initial random number. The test coverage corresponding to the initial random number is then used as a reference coverage, serving as a comparison benchmark for functional verification of subsequent variant random numbers. Functional verification is then performed using a test case set for the first variant random number to obtain the test results and test coverage corresponding to the variant random number, and to determine the label of the variant random number.

[0107] If all the test results corresponding to the mutated random number are passed and its test coverage exceeds the reference coverage, it means that the test case set of the mutated random number is better than the test case set of the previous random number, that is, the mutated random number is helpful in discovering functional scenarios that have not been tested. Then the label of the mutated random number is set to valid, such as "interesting", and the test coverage corresponding to the mutated random number is used as the new reference coverage, which serves as a comparison benchmark for the functional verification of the next mutated random number.

[0108] If any of the test results corresponding to the mutated random number fail, or if the test coverage corresponding to the mutated random number does not exceed the reference coverage, it means that the test case set of the mutated random number is worse than the test case set of the previous random number, then the label of the mutated random number is set to invalid, such as "uninteresting".

[0109] In a similar way, the test case set of each mutated random number is processed in turn to obtain the final reference coverage, and the highest test coverage among the initial random number and all mutated random numbers is obtained and used as the verification result.

[0110] It can be understood that the embodiment of the present invention performs functional verification on a set of test cases for each random number, and combines its test results and coverage to determine the label and adjust the reference coverage, thereby facilitating the screening of higher-quality variant random numbers to improve the efficiency of chip functional verification.

[0111] Optionally, for the process of determining whether to replace the initial random number in the random number library according to the labels of all the mutated random numbers in step S206, an embodiment of the present invention provides a possible implementation method.

[0112] Step S206-6: If there is a variant random number with a valid label among all the variant random numbers, the initial random number in the random number library is replaced with the variant random number with the valid label.

[0113] Step S206-7: If there are multiple variant random numbers with valid labels among all the variant random numbers, the initial random number in the random number library is replaced with a variant random number with valid labels and the highest test coverage.

[0114] Step S206-8: If there is no mutated random number with a label of valid among all the mutated data numbers, the initial random number is retained in the random number library.

[0115] In this embodiment, if there is a variant random number with a label of valid among all the variant random numbers, then it is necessary to further determine the variant random number to be used.

[0116] For example, if only one variant has a valid tag among all the variants, then that variant is used to replace the initial random number in the random number library. If multiple variants have valid tags among all the variants, then the variant with the highest test coverage is selected from these variants and used to replace the initial random number in the random number library.

[0117] If there is no mutated random number labeled as valid among all the mutated random numbers, it means that these mutated random numbers have failed to improve the test coverage or failed to pass the functional verification. In this case, the initial random number in the random number library will be retained, that is, no replacement operation will be performed.

[0118] This embodiment of the present invention comprehensively evaluates the labels and test coverage of all mutated random numbers to determine whether to replace the initial random numbers in the random number library. This not only effectively optimizes the contents of the random number library but also gradually improves test coverage during functional verification, providing reliable support for chip functional verification.

[0119] Optionally, after the above step S206, the embodiment of the present invention further provides a possible implementation method, please refer to Figure 2 .

[0120] Step S210: During M rounds of verification, if no random numbers in the random number library are replaced, multiple random number arrays are obtained based on all the random numbers in the random number library, and a crossover operation is performed on the two random numbers in each random number array to obtain two new random numbers, and the random number library is updated based on all the new random numbers; wherein M is a positive integer and is less than a preset number of times.

[0121] It is understandable that if no random numbers in the random number library are replaced during each of the M rounds of verification, it indicates that the data quality of the random number library is low, resulting in the random numbers obtained after mutation being worse than the initial random numbers. Therefore, in this case, the embodiment of the present invention will update the random number library through a crossover operation so that subsequent verification can be performed based on the updated random number library.

[0122] First, multiple random arrays are generated based on all the random numbers in the random number library. Each random array contains two random numbers, and these random arrays will become the basic units of the subsequent crossover operation. Then, a crossover operation is performed on the two random numbers in each random array to generate two new random numbers.

[0123] For example, for random numbers B0 and C0, we can randomly select a position to separate random number B0 into a front part and a back part, and randomly select a position to separate random number C0 into a front part and a back part. Then, we combine the front part of random number B0 with the back part of random number C0 to form a new random number, and at the same time, we combine the front part of random number C0 with the back part of random number B0 to form another new random number. In other words, we get two new random numbers based on random number B0 and random number C0.

[0124] In a similar way, a crossover operation is performed on each random number array to merge the partial features of the two random numbers to obtain multiple new random numbers. These new random numbers are then used to replace all the random numbers in the random number library, thus updating the random number library.

[0125] It can be understood that, through the cross-operation mechanism, the embodiments of the present invention can maintain the continuous optimization capability of the verification process by generating new random numbers even when no valid mutation is found in the random number library. This ensures that the verification process can continue to explore new possibilities even when encountering optimization bottlenecks, further improving test coverage and verification effectiveness.

[0126] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a chip function verification device is given below. Figure 3, is a functional module diagram of a chip function verification device provided by an embodiment of the present invention. It should be noted that the basic principles and technical effects of the chip function verification device 300 provided in this embodiment are the same as those of the above embodiment. For the sake of simplicity, any matters not mentioned in this embodiment can be referred to the corresponding contents of the above embodiment. The chip function verification device 300 includes:

[0127] The acquisition module 310 is configured to use each random number in a preset random number library as an initial random number in sequence during each round of verification.

[0128] The verification module 330 is used to perform multiple mutations on the initial random number to obtain multiple mutated random numbers, and generate respective test case sets based on the initial random number and each mutated random number; use each test case set to perform functional verification to obtain the label of each mutated random number and the verification result, and determine whether to replace the initial random number in the random number library based on the labels of all mutated random numbers; if the verification result meets the preset conditions, or if the verification result does not meet the preset conditions and the number of verification rounds reaches the preset number, the chip functional verification is terminated.

[0129] Optionally, the verification module 330 is further used to: in each of multiple mutation processes on the initial random number, use the initial random number as the random number to be processed, and use the first mutation behavior of the preset mutation sequence as the mutation behavior to be executed; randomly obtain at least one position number from the preset position number set and use it as the target position number; perform a mutation operation on each target byte at the corresponding position in the random number to be processed according to the mutation behavior to be executed and each target position number to obtain a processed random number; if the mutation behavior to be executed is not the last mutation behavior of the mutation sequence, then use the next mutation behavior in the mutation sequence as the new mutation behavior to be executed, and after using the processed random number as the new random number to be processed, return to execute the step of randomly obtaining at least one position number from the preset position number set and using it as the target position number; if the mutation behavior to be executed is the last mutation behavior of the mutation sequence, then use the processed random number as the mutation random number, until multiple mutation random numbers are obtained.

[0130] Optionally, the mutation behavior includes at least one of the following: inverting each bit of the target byte; replacing the target byte with a preset sensitive byte; randomly replacing the target byte; deleting the target byte; copying the target byte and adding it before or after the target byte; adding multiple identical random bytes before or after the target byte.

[0131] Optionally, the verification module 330 is also used to: take any one of the initial random number and all the mutated random numbers as the target random number; select multiple target test case templates from a preset multiple functional case library based on the bytes in the target random number, and generate each test case based on each target test case template to obtain a test case set for the target random number; traverse the initial random number and each mutated random number to obtain a test case set for the initial random number and each mutated random number.

[0132] Optionally, the verification module 330 is also used to: perform functional verification using the test case set of the initial random number to obtain the test results and test coverage corresponding to the initial random number, and use the test coverage as the reference coverage; perform functional verification using the test case set of each variant random number in turn to obtain the test results and test coverage corresponding to each variant random number; if all the test results corresponding to the variant random number are passed and the test coverage exceeds the reference coverage, then the test coverage corresponding to the variant random number is used as the new reference coverage, and the label of the variant random number is set to valid; if any of the test results corresponding to the variant random number fail, or if the test coverage corresponding to the variant random number does not exceed the reference coverage, then the label of the variant random number is set to invalid; and the reference coverage obtained by traversing all the test case sets is used as the verification result.

[0133] Optionally, the verification module 330 is also used to: if there is a variant random number with a valid label among all the variant random numbers, then the initial random number in the random number library will be replaced with the variant random number with the valid label; if there are multiple variant random numbers with valid labels among all the variant random numbers, then the initial random number in the random number library will be replaced with a variant random number with a valid label and the highest test coverage; if there is no variant random number with a valid label among all the variant data numbers, then the initial random number will be retained in the random number library.

[0134] Optionally, the verification module 330 is also used to: during M rounds of verification, if no random numbers in the random number library are replaced, obtain multiple random arrays based on all the random numbers in the random number library, perform a cross operation on the two random numbers in each random array to obtain two new random numbers, and update the random number library based on all the new random numbers; wherein M is a positive integer and is less than a preset number of times.

[0135] See also Figure 4 , is a block diagram of a hardware emulation device provided in an embodiment of the present invention. Hardware emulation device 100 includes a processor 110, a memory 120, and a communication module 130. Each component is electrically connected to each other, directly or indirectly, to enable data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0136] The processor 110 is used to read / write data or programs stored in the memory 120 and execute corresponding functions. It can be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it can also be a DSP digital signal processor, an ASIC application-specific integrated circuit, an FPGA off-the-shelf programmable gate array or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0137] The memory 120 is used to store programs or data, and can be RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0138] The communication module 130 is used to communicate signaling or data with other devices.

[0139] It is understandable that Figure 4 The structure shown is only a schematic diagram of the structure of the hardware simulation device 100. The hardware simulation device 100 may also include Figure 4 More or fewer components than shown, or with Figure 4 Different configurations shown. Figure 4 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0140] The memory of the hardware simulation device in the embodiment of the present invention stores a computer program, and when the processor executes the computer program, the chip function verification method disclosed in the embodiment of the present invention is implemented.

[0141] An embodiment of the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the chip function verification method disclosed in the embodiment of the present invention is implemented.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0143] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0144] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0145] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip function verification method, characterized in that: Applied to a hardware emulation device, the hardware emulation device is used to simulate a chip with a set function, the method comprising: In each round of verification, each random number in the preset random number library is used as the initial random number in turn; Performing multiple mutations on the initial random number to obtain multiple mutated random numbers, and generating respective test case sets based on the initial random number and each mutated random number; Perform functional verification using each test case set to obtain a label for each mutated random number and a verification result, and determine whether to replace the initial random number in the random number library based on the labels of all mutated random numbers; If the verification result meets the preset condition, or if the verification result does not meet the preset condition and the verification rounds reach the preset number of times, the chip function verification is terminated.

2. The chip function verification method according to claim 1, characterized in that: The initial random number is subjected to multiple mutation processes to obtain multiple mutated random numbers, including: In each of the multiple mutation processes performed on the initial random number, the initial random number is used as the random number to be processed, and the first mutation behavior of the preset mutation sequence is used as the mutation behavior to be executed; Randomly obtain at least one position number from a preset position number set and use it as the target position number; According to the mutation behavior to be executed and the sequence number of each target position, a mutation operation is performed on each target byte at the corresponding position in the random number to be processed to obtain a processed random number; If the mutation behavior to be executed is not the last mutation behavior in the mutation sequence, then the next mutation behavior in the mutation sequence is used as the new mutation behavior to be executed, and after using the processed random number as the new random number to be processed, the process returns to the step of randomly obtaining at least one position number from a preset position number set and using the position number as the target position number. If the mutation behavior to be executed is the last mutation behavior of the mutation sequence, the processed random number is used as the mutation random number until the multiple mutation random numbers are obtained.

3. The chip function verification method according to claim 2, characterized in that: The mutation behavior includes at least one of the following: Invert each bit of the target byte; Replace the target bytes with the preset sensitive bytes; Randomly replace the target bytes; Delete the target bytes; Copy the target byte and add it before or after the target byte; Add multiple identical random bytes before or after the target bytes.

4. The chip function verification method according to claim 1, characterized in that: Based on the initial random number and each mutated random number, a respective test case set is generated, including: Taking any one of the initial random number and all the variant random numbers as the target random number; According to the bytes in the target random number, multiple target test case templates are selected from a preset multiple functional case library, and each test case is generated based on each target test case template to obtain a test case set for the target random number; The initial random number and each mutated random number are traversed to obtain respective test case sets for the initial random number and each mutated random number.

5. The chip function verification method according to claim 1, characterized in that: Use each test case set to perform functional verification and obtain the label of each mutated random number and verification results, including: Perform functional verification using the test case set of the initial random number to obtain various test results and test coverage corresponding to the initial random number, and use the test coverage as a reference coverage; Use the test case set of each mutated random number to perform functional verification in turn, and obtain the test results and test coverage corresponding to each mutated random number; If all test results corresponding to the mutated random number are passed and the test coverage exceeds the reference coverage, the test coverage corresponding to the mutated random number is used as the new reference coverage, and the label of the mutated random number is set to valid; If any of the test results corresponding to the mutated random number fails, or if the test coverage corresponding to the mutated random number does not exceed the reference coverage, the label of the mutated random number is set to invalid; The reference coverage obtained by traversing all test case sets is used as the verification result.

6. The chip function verification method according to claim 5, characterized in that: Determining whether to replace the initial random number in the random number library according to the labels of all the mutated random numbers includes: If there is a variant random number with a valid label among all the variant random numbers, the initial random number is replaced with the variant random number with a valid label in the random number library; If there are multiple variant random numbers with valid labels among all the variant random numbers, then the initial random number is replaced with the variant random number with valid label and the highest test coverage in the random number library; If there is no mutated random number with a label of valid among all the mutated data numbers, the initial random number is retained in the random number library.

7. The chip function verification method according to claim 1, characterized in that: The method further comprises: During the M-round verification process, if no random numbers in the random number library are replaced, multiple random arrays are obtained based on all the random numbers in the random number library, and a cross operation is performed on the two random numbers in each random array to obtain two new random numbers, and the random number library is updated based on all the new random numbers; where M is a positive integer and is less than the preset number of times.

8. A chip function verification device, characterized in that: Applied to a hardware emulation device, the hardware emulation device is used to simulate a chip with a set function, the device comprising: The acquisition module is used to use each random number in the preset random number library as the initial random number in turn during each round of verification; A verification module, configured to perform multiple mutations on the initial random number to obtain multiple mutated random numbers, and generate respective test case sets based on the initial random number and each mutated random number; Perform functional verification using each test case set to obtain a label for each mutated random number and a verification result, and determine whether to replace the initial random number in the random number library based on the labels of all mutated random numbers; If the verification result meets the preset condition, or if the verification result does not meet the preset condition and the verification rounds reach the preset number of times, the chip function verification is terminated.

9. A hardware simulation device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip function verification method according to any one of claims 1 to 7 is implemented.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the chip function verification method according to any one of claims 1 to 7.

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