Method for optimizing circuit board wiring

Abstract

The application discloses a circuit board wiring optimization method, relates to the technical field of circuit board wiring, and comprises the following steps: obtaining wiring data based on monitoring weights; outputting corresponding wiring quality values by using a pre-constructed wiring quality evaluation model; detecting whether the wiring quality values are less than a certain quality threshold value, and when the wiring quality values are less than the certain quality threshold value, counting the duration for which the wiring quality values are less than a preset quality threshold value, and judging whether the duration is greater than a certain time length; if the duration is greater than the certain time length, triggering a suspension instruction, and generating suspension data in response to the suspension instruction; optimizing initial wiring instructions by using a pre-constructed graph neural network model to obtain final wiring instructions, and wiring a circuit board according to the final wiring instructions to obtain a wiring result of the circuit board, so that the technical problems that the wiring cannot be suspended in time, repetitive work is prone to occur, and a large amount of manpower and time cost are consumed are solved, the technical effects of improving wiring efficiency, actively suspending an inefficient path and reducing wiring cost are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board wiring, and in particular to a circuit board wiring optimization method. BACKGROUND

[0002] In related technologies, automatic wiring software can be used to realize automatic wiring of a circuit board; a blind hole process can be optimized to improve wiring density and thus improve wiring results; and arc-shaped fan-out signal lines can be designed between the gaps of two adjacent vias to improve wiring space utilization and reduce time costs.

[0003] However, in related technologies, the wiring process of the wiring software is not transparent, and the wiring path and intermediate state cannot be monitored in real time, which causes the system to be unable to actively terminate invalid processes, so that the wiring system enters an infinite loop system, wasting a large amount of manpower and time costs; improving wiring density does not involve dynamic monitoring and termination mechanisms of the wiring process; and the use of arc-shaped fan-out signal lines depends on static rules and lacks real-time quality evaluation, which needs to be improved. SUMMARY

[0004] The present application provides a circuit board wiring optimization method to at least solve the problems in related technologies that the wiring software cannot be terminated in time, is prone to repetitive work, causes low wiring efficiency, and wastes a large amount of manpower and time costs; improving wiring density does not involve dynamic monitoring and termination mechanisms of the wiring process; and the use of arc-shaped fan-out signal lines depends on static rules and lacks real-time quality evaluation.

[0005] The present application provides a circuit board wiring optimization method, including the following steps: based on the monitoring weight of at least one circuit board layer in a circuit board, obtaining wiring data corresponding to the monitoring weight; inputting the wiring data into a pre-constructed wiring quality evaluation model to output a wiring quality value in response to the initial wiring instruction; detecting whether the wiring quality value is less than a preset quality threshold, and in the case where it is detected that the wiring quality value is less than the preset quality threshold, based on the circuit board, counting the duration for which the wiring quality value is less than the preset quality threshold, and judging whether the duration is greater than a preset time length; if the duration is greater than the preset time length, triggering a termination instruction of the circuit board, in response to the termination instruction, generating termination data of the circuit board; inputting the termination data into a pre-constructed graph neural network model to optimize the initial wiring instruction using the pre-constructed graph neural network model to obtain a final wiring instruction of the circuit board, and wiring the circuit board according to the final wiring instruction to obtain a wiring result of the circuit board.

[0006] The application further provides an optimization device for circuit board wiring, comprising: a first acquisition module, configured to acquire wiring data corresponding to a monitoring weight of at least one circuit board layer in a circuit board based on the monitoring weight; a first output module, configured to input the wiring data into a pre-constructed wiring quality evaluation model to output a wiring quality value in response to the initial wiring instruction; a detection module, configured to detect whether the wiring quality value is less than a preset quality threshold, and in a case where it is detected that the wiring quality value is less than the preset quality threshold, based on the circuit board, to count a duration for which the wiring quality value is less than the preset quality threshold, and to judge whether the duration is greater than a preset time length; a generation module, configured to trigger a suspension instruction of the circuit board when the duration is greater than the preset time length, to generate suspension data of the circuit board in response to the suspension instruction; and a second output module, configured to input the suspension data into a pre-constructed graph neural network model, to optimize the initial wiring instruction by using the pre-constructed graph neural network model to obtain a final wiring instruction of the circuit board, and to wire the circuit board according to the final wiring instruction to obtain a wiring result of the circuit board.

[0007] The application further provides an electronic device, comprising: a memory configured to store a computer program; and a processor configured to implement the steps of any of the above-mentioned optimization methods for circuit board wiring when executing the computer program.

[0008] The application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the above-mentioned optimization methods for circuit board wiring.

[0009] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the above-mentioned optimization methods for circuit board wiring.

[0010] By the present application, the corresponding wiring data can be obtained based on different monitoring weights, and the wiring quality value responding to the initial wiring instruction is obtained by using the pre-constructed wiring quality evaluation model, and whether the wiring quality value is less than a certain quality threshold is detected, and in the case that the wiring quality value is less than a certain quality threshold and the duration is greater than a certain time length, the suspension instruction is triggered, the suspension data is generated, and then the initial wiring instruction is optimized by using the pre-constructed graph neural network model to obtain the final wiring instruction, and the wiring is performed according to the final wiring instruction, so that the wiring result is obtained. Therefore, the technical problems in the related art that the wiring software cannot be suspended in time, the repetitive work is prone to occur, the wiring efficiency is low, a large amount of manpower and time cost are consumed, the dynamic monitoring and suspension mechanism of the wiring process is not involved in the improvement of the wiring density, the arc-shaped fan-out signal line efficiency depends on the static rules and lacks real-time quality evaluation, and the like can be solved. The technical effects of improving the wiring efficiency, shortening the wiring period, actively suspending the inefficient path, avoiding resource waste, reducing invalid calculation, improving the wiring path, reducing the wiring cost, and optimizing resource allocation are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1 A block schematic diagram of the circuit board wiring suspension optimization system provided according to an embodiment of the present application is shown.

[0013] Figure 2 A flowchart of the circuit board wiring optimization method provided by an embodiment of the present application is shown.

[0014] Figure 3 A flowchart of the circuit board wiring optimization method provided according to another embodiment of the present application is shown.

[0015] Figure 4 A flowchart of the specific process of the circuit board wiring optimization method provided according to another embodiment of the present application is shown.

[0016] Figure 5 A block schematic diagram of the circuit board wiring optimization device provided according to an embodiment of the present application is shown.

[0017] Reference signs:

[0018] 10 - circuit board wiring optimization system; 101 - monitoring module, 102 - decision module, 103 - execution module, 104 - restoration module; 20 - circuit board wiring optimization device; 100 - first acquisition module, 200 - first output module, 300 - detection module, 400 - generation module, 500 - second output module. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0020] It should be noted that in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0021] Before introducing the circuit board wiring optimization method proposed in the embodiments of the present application, a circuit board wiring optimization system involved in the embodiments of the present application is introduced.

[0022] Specifically, Figure 1 A block diagram of the circuit board wiring optimization system provided according to an embodiment of the present application is shown.

[0023] As Figure 1 shown, the circuit board wiring optimization system 10 includes a monitoring module 101, a decision module 102, an execution module 103 and a restoration module 104.

[0024] The monitoring module 101 is configured to determine a monitoring weight and acquire wiring data.

[0025] The decision module 102 is configured to process the wiring data until a certain data condition is met, input the wiring data meeting the certain data condition into a pre-constructed wiring quality evaluation model, calculate a corresponding wiring quality value, detect whether the wiring quality value is less than a certain quality threshold, and in the case of less than, count a duration that the wiring quality value is less than the certain quality threshold, and determine whether the duration is greater than a certain time length, and in the case of greater than, trigger an abort instruction.

[0026] The execution module 103 is configured to generate suspension data in response to the suspension instruction.

[0027] The reduction module 104 is configured to optimize the initial routing instruction by using the pre-constructed graph neural network model, thereby obtaining the final routing instruction of the circuit board, and thereby obtaining the corresponding routing result.

[0028] In order to enable those skilled in the art to better understand the present application scheme, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0029] The embodiment of the present application provides an optimization method for circuit board routing, which is described in detail in combination with the execution process of the optimization method for circuit board routing.

[0030] Specifically, Figure 2 A flowchart of the optimization method for circuit board routing according to the embodiment of the present application is provided.

[0031] As Figure 2 shown, the optimization method for circuit board routing comprises the following steps:

[0032] In step S201, the routing data corresponding to the monitoring weight is obtained based on the monitoring weight of at least one circuit board layer in the circuit board.

[0033] It can be understood that in the embodiment of the present application, the routing data can include but is not limited to network routing rate, critical path delay, interlayer via density and design rule violation times, etc., which are not limited in the present application.

[0034] The network routing rate can be understood as the proportion of the number of routed networks to the total routing number, which can reflect the current routing progress and identify the unrouted networks. Further, in the embodiment of the present application, if the routing rate of the high monitoring weight layer is low, the routing strategy can be prioritized or adjusted, which is not limited in the present application.

[0035] The critical path delay can be understood as the transmission delay of the signal path with the most stringent timing requirement, which ensures that the critical signal meets the timing constraint and guarantees signal integrity. Further, in the embodiment of the present application, if the critical path delay of the high monitoring weight layer is over-standard, the routing length or layer allocation can be optimized, which is not limited in the present application.

[0036] The interlayer via density can be understood as the number of vias per unit area, which can reflect the frequency of interlayer switching. Further, in the embodiment of the present application, if the via density of the high monitoring weight layer is over-standard, the routing strategy can be adjusted, such as reducing layer switching or using blind holes, which is not limited in the present application.

[0037] The number of design rule violations can be understood as the total number of violations of design rules (such as line width, spacing, via size, etc., which are not specifically limited in the present application), which can be used to identify potential manufacturing or performance problems and ensure design manufacturability. Further, in the embodiments of the present application, the violations of the high monitoring weight layer need to be repaired first to avoid affecting the overall design quality.

[0038] In some embodiments, the embodiments of the present application can obtain wiring data corresponding to the monitoring weight in the circuit board including at least one circuit board layer according to the monitoring weight of each circuit board layer.

[0039] For example, the embodiments of the present application can obtain wiring data based on the monitoring weight of each circuit board layer through an EDA (Electronic Design Automation) software API (Application Programming Interface) interface (such as a Cadence SKILL API (Cadence SKILL Application Programming Interface), an Altium Scripting API (Altium Scripting Application Programming Interface)), wherein the wiring data may, but is not limited to, include network routing rate, critical path delay, interlayer via density, and number of design rule violations, etc., which are not specifically limited in the present application.

[0040] Optionally, in an embodiment of the present application, based on the monitoring weight of at least one circuit board layer in the circuit board, the wiring data corresponding to the monitoring weight is obtained, including: determining the actual complexity of the circuit board and the target complexity of the target circuit board based on the number of networks, the number of layers and the element density of the circuit board; based on the circuit board, obtaining the proportion of high-speed signals of the circuit board; and calculating the monitoring weight based on the actual complexity, the target complexity and the proportion of high-speed signals.

[0041] It can be understood that in the embodiments of the present application, the complexity of different circuit boards can be determined by the number of networks, the number of layers and the element density of the circuit board, which can be set by a person skilled in the art according to the actual situation, and the present application is not specifically limited.

[0042] In some embodiments, the embodiments of the present application can determine the complexity of the circuit board according to the number of networks, the number of layers and the element density of the circuit board.

[0043] For example, the embodiments of the present application can represent the number of networks of the circuit board as , the number of layers of the circuit board is represented as , the element density of the circuit board is represented as , and the actual complexity of the corresponding circuit board is obtained, and the calculation process can be but is not limited to represented as:

[0044] ,

[0045] Further, the embodiment of the present application can obtain the target complexity of the target circuit board, i.e. the reference circuit board , such as the 8-layer HDI board (High Density Interconnector, high-density interconnection board) .

[0046] In addition, it should be noted that in the embodiment of the present application, the high-speed signal ratio can be understood as the proportion of the number of high-speed signals of each layer of the circuit board layer to the total number of total traces.

[0047] In some embodiments, the embodiment of the present application can calculate the monitoring weight according to the actual complexity, the target complexity and the high-speed signal ratio. Wherein, the expression of the monitoring weight can be but is not limited to:

[0048] ,

[0049] Wherein, is the actual complexity of the circuit board, is the target complexity of the target circuit board, is the adjustment coefficient (value range 0.1~0.5, default 0.2), is the high-speed signal ratio corresponding to the wiring of the i-th layer of the circuit board layer.

[0050] The embodiment of the present application can determine the actual complexity of the circuit board and the target complexity of the target circuit board based on the number of networks, the number of layers and the element density of the circuit board, and then combine the high-speed signal ratio to calculate the monitoring weight by using the monitoring weight calculation formula, calculate the actual complexity by comprehensively calculating the number of networks, the number of layers and the element density, and compare the target complexity, assign higher monitoring weight as needed, prioritize optimizing wiring, adjust computing resources, realize dynamic resource scheduling, improve wiring efficiency and success rate, shorten design cycle, support intelligent and adaptive design, and adapt to diversified needs.

[0051] Optionally, in an embodiment of the present application, based on the monitoring weight of at least one circuit board layer in the circuit board, the wiring data corresponding to the monitoring weight is obtained, comprising: based on the size of the monitoring weight, the size of the data amount of the wiring data is determined, wherein the size of the monitoring weight is positively correlated with the size of the data amount; and the wiring data containing at least one of the network routing rate, the critical path delay, the via density and the number of design rule violations is obtained according to the data amount.

[0052] It can be understood that the monitoring weight in the embodiment of the present application can be used to reflect the importance or complexity of different circuit board layers in the circuit system, and then when obtaining the wiring data, more computing resources can be allocated to the circuit board layer with a large monitoring weight to process and generate more detailed wiring data. The size of the monitoring weight is positively correlated with the size of the data amount, which can be understood as that the larger the monitoring weight is, the larger the data amount corresponding to the wiring data is; the smaller the monitoring weight is, the smaller the data amount corresponding to the wiring data is.

[0053] In some embodiments, the embodiment of the present application can obtain the corresponding wiring data according to the data amount positively correlated with the size of the monitoring weight.

[0054] For example, the monitoring weight of the circuit board layer 1 is 0.3, and the monitoring weight of the circuit board layer 2 is 0.4, so the data amount of the wiring data of the circuit board layer 1 is smaller than that of the circuit board layer 2.

[0055] The embodiment of the present application can realize reasonable optimization of resource allocation according to the size of the monitoring weight, avoid wiring errors or unreasonable caused by insufficient computing resources, improve the overall wiring quality, and improve the stability and reliability of the circuit.

[0056] Optionally, in an embodiment of the present application, the wiring data corresponding to the monitoring weight is obtained, comprising: based on the circuit board, the wiring index of the wiring data is obtained; based on the board layer information of the circuit board, the update time of the wiring data is determined; and based on the wiring index and the update time, the wiring data is updated.

[0057] It can be understood that in the embodiment of the present application, the wiring index can include but is not limited to line width, spacing, via parameter, pad diameter and mounting hole diameter, etc., which is not limited in the present application.

[0058] In addition, in the embodiment of the present application, the update time of the wiring data can be determined by the board layer information of the circuit board, for example, the structure of the circuit board layer 3 is relatively complex, and the corresponding update time can be set to 5 seconds; the structure of the circuit board layer 4 is relatively simple, and the corresponding update time can be set to 10 seconds, which is not limited in the present application.

[0059] The board layer information can include, but is not limited to, structure information, function information, and physical property information of the circuit board, and can be set by a person skilled in the art according to actual conditions, and the application does not make specific limitations.

[0060] In some embodiments, the embodiments of the application can update the routing data after obtaining the routing index and the update time, and then obtain the updated routing data.

[0061] For example, the embodiments of the application can start the routing software, load the circuit board design file, parse the design routing index through the regular expression, generate the line width / spacing matrix and the three-dimensional model of the layer structure, adopt the distributed sampling strategy, update the routing data every 10 seconds to reduce the system load, and send the routing data obtained according to the card layering to the monitoring device, and multiple monitoring devices jointly monitor the data.

[0062] The embodiments of the application can update the routing data according to the routing index and the update time of the routing data, dynamically adapt to the design stage requirements, improve the routing efficiency, accelerate the routing convergence through accurate update of the key layer data, enhance the signal integrity and reliability, reduce the late risk, and support flexible response to complex design scenarios.

[0063] Optionally, in an embodiment of the application, before the routing data is input into the pre-constructed routing quality evaluation model, it further includes: judging whether the routing data meets the preset data condition; if the routing data does not meet the preset data condition, processing the routing data until the routing data meeting the preset data condition is obtained, and allowing the routing data meeting the preset data condition to be input into the pre-constructed routing quality evaluation model; if the routing data meets the preset data condition, allowing the routing data to be input into the pre-constructed routing quality evaluation model.

[0064] In actual execution process, the embodiments of the application can judge whether the routing data meets a certain data condition before the routing data is input into the pre-constructed routing quality evaluation model, and process the routing data when it does not meet the certain data condition until it meets the certain data condition, and allow the routing data meeting the certain data condition to be input into the pre-constructed routing quality evaluation model; and when it meets, allow the routing data to be input into the pre-constructed routing quality evaluation model.

[0065] The certain data condition can be set by a person skilled in the art according to actual conditions, and the application does not make specific limitations.

[0066] Exemplarily, the embodiment of the present application can adopt a distributed computing framework to process the wiring data that does not meet certain data conditions, and obtain wiring data that meets certain data conditions by cleaning, classifying, regressing, clustering, etc. of the data.

[0067] Before the wiring data is input into the pre-constructed wiring quality evaluation model, the embodiment of the present application determines whether the wiring data meets certain data conditions, and processes the wiring data when it does not meet certain data conditions until wiring data that meets certain data conditions is obtained, filters invalid data, avoids model misjudgment, improves model evaluation quality, speeds up the evaluation process, and reduces design risk.

[0068] Optionally, in an embodiment of the present application, before the wiring data is input into the pre-constructed wiring quality evaluation model, it further includes: determining the target network routing rate, the target average wire length and the target via density of the circuit board based on the target wiring data; determining the first weight coefficient corresponding to the target network routing rate, the second weight coefficient corresponding to the target average wire length and the third weight coefficient corresponding to the target via density based on the target network routing rate, the target average wire length and the target via density; and constructing the wiring quality evaluation model based on the target network routing rate, the target average wire length, the target via density, the first weight coefficient, the second weight coefficient and the third weight coefficient.

[0069] In some embodiments, the embodiment of the present application can determine the target network routing rate, the target average wire length and the target via density of the circuit board according to the target wiring data, and then determine the first weight coefficient corresponding to the target network routing rate, the second weight coefficient corresponding to the target average wire length and the third weight coefficient corresponding to the target via density, so as to construct the wiring quality evaluation model. The expression of the pre-constructed wiring quality evaluation model can be, but is not limited to:

[0070]

[0071] wherein, the first weight coefficient is, the second weight coefficient is, the third weight coefficient is, , the number of routed networks is, the total number of wires is, the average wire length reflects the wire efficiency, the via density is, and the larger the value is, the worse the wiring quality is.

[0072] Exemplarily, for an 8-layer HDI board, , , .​

[0073] The embodiment of the present application can determine the target network routing rate, the target average wire length and the target via density of the circuit board based on the target routing data, and then determine the corresponding weight coefficient, so as to construct a routing quality evaluation model, dynamically adapt to different design requirements, avoid "one-size-fits-all" evaluation, clearly contain target indicators and corresponding weight coefficients, can intuitively understand the contribution of each indicator to the evaluation result, quickly locate the optimization direction, improve the evaluation interpretability, speed up the design iteration and model deployment, support incremental model updating, and reduce the maintenance cost.

[0074] Optionally, in an embodiment of the present application, before the suspension data is input into the pre-constructed graph neural network model, it further includes: obtaining historical suspension data of the circuit board; determining structure information and training information of the graph neural network model based on the historical suspension data; training the graph neural network model using the historical suspension data based on the structure information and the training information, to construct a graph neural network model meeting a preset training condition.

[0075] It can be understood that in the embodiment of the present application, the historical suspension data can be understood as the suspension data in the past three months, half a year or a year, which can be set by a person skilled in the art according to the actual situation, and the present application does not make specific limitation.

[0076] In addition, in the case that the circuit board does not have historical suspension data, the embodiment of the present application can use the suspension data of similar or similar circuit board layers as the suspension data of the circuit board layer; it can also generate similar suspension data randomly; it can also be obtained by other means, which is not limited in the present application.

[0077] In some embodiments, the embodiment of the present application can first obtain the historical suspension data of the circuit board, and then determine the structure information and the training information of the graph neural network model, so as to train the graph neural network model using the historical suspension data, and construct a graph neural network model meeting a certain training condition. The certain training condition can be set by a person skilled in the art according to the actual situation, and the present application does not make specific limitation.

[0078] It should be noted that in the embodiment of the present application, the structure information can include but is not limited to node embedding dimension, for example, the embodiment of the present application can select a 32-dimensional or 64-dimensional vector to represent each circuit board layer, which is not limited in the present application; the number of graph convolution layers, for example, the embodiment of the present application can select a 2-layer or 3-layer graph convolution network, which is not limited in the present application; the type of aggregation function, for example, the embodiment of the present application can select a summation, average or maximum aggregation function, which is not limited in the present application.

[0079] The training information can include, but is not limited to, a loss function, for example, the embodiments of the present application can select a cross-entropy loss function for a classification task, and the present application does not make specific limitations; an optimizer, for example, the embodiments of the present application can select an Adam optimizer, and the present application does not make specific limitations; a learning rate, for example, the embodiments of the present application can select a learning rate of 0.001 or 0.01, and the present application does not make specific limitations; and a number of training rounds, for example, the embodiments of the present application can select 100 rounds or 200 rounds of training, and the present application does not make specific limitations.

[0080] The embodiments of the present application can obtain historical suspension data of the circuit board before inputting the suspension data into the pre-constructed graph neural network model, and then determine the structure information and the training information of the graph neural network model, so as to train the graph neural network model using the historical suspension data, and then construct a graph neural network model that meets certain training conditions. By statistically analyzing the distribution of suspension reasons in each scenario, the structure and training parameters of the graph neural network model are dynamically adjusted, so that the model can capture the suspension risk features in different scenarios, avoid false negatives of fixed structure models in specific scenarios, improve prediction accuracy, reduce real-time training costs based on historical data pre-training, accelerate model training and deployment, balance precision and efficiency, identify potential suspension risks in advance, and enhance reliability.

[0081] In step S202, the wiring data is input into the pre-constructed wiring quality evaluation model to output a wiring quality value in response to the initial wiring instruction.

[0082] In some embodiments, the embodiments of the present application can input the wiring data into the pre-constructed wiring quality evaluation model to obtain a wiring quality value in response to the initial wiring instruction.

[0083] For example, the embodiments of the present application can first initialize the parameters of the pre-constructed wiring quality evaluation model, and then input the wiring data into the pre-constructed wiring quality evaluation model to obtain a wiring quality value in response to the initial wiring instruction.

[0084] In step S203, it is detected whether the wiring quality value is less than a preset quality threshold, and in the case where it is detected that the wiring quality value is less than the preset quality threshold, the duration for which the wiring quality value is less than the preset quality threshold is counted based on the circuit board, and it is determined whether the duration is greater than a preset time length.

[0085] It can be understood that in the embodiments of the present application, the certain quality threshold can be dynamically adjusted according to the type of the circuit board, for example, the certain quality threshold of a general board can be set to 0.6, and the certain quality threshold of an HDI board can be set to 0.7. The specific settings can be made by those skilled in the art according to actual conditions, and the present application does not make specific limitations.

[0086] In addition, in the embodiment of the present application, the certain time length is negatively correlated with the complexity of the circuit board. For example, the certain time length of the HDI board can be set to 10 minutes, and the certain time length of the backboard can be set to 5 minutes. The specific setting can be made by a person skilled in the art according to the actual situation. The present application does not make specific limitations. Dynamic quality detection avoids the accumulation of design defects, improves data value, and supports accurate analysis and automatic decision-making.

[0087] In some embodiments, the embodiment of the present application can detect whether the wiring quality value is less than a certain quality threshold, and in the case of detecting that the wiring quality value is less than a certain quality threshold, the duration that the wiring quality value is less than a certain quality threshold is counted, and it is judged whether the duration is greater than a certain time length.

[0088] For example, the certain quality threshold can be represented as , the certain time length can be represented as , the wiring quality value of the HDI board is 10 minutes, and the wiring quality value of the backboard is 5 minutes. The wiring quality value of the HDI board is detected, and when , the duration that the wiring quality value is less than a certain quality threshold is counted , and it is judged whether is greater than .

[0089] In step S204, if the duration is greater than the preset time length, the suspension instruction of the circuit board is triggered. In response to the suspension instruction, the suspension data of the circuit board is generated.

[0090] In some embodiments, the embodiment of the present application can trigger the suspension instruction of the circuit board when the duration is greater than a certain time length, and in response to the suspension instruction, the suspension data of the circuit board is generated.

[0091] For example, the embodiment of the present application triggers the suspension instruction when , and in response to the suspension instruction, the corresponding suspension data is generated.

[0092] In step S205, the suspension data is input into the pre-constructed graph neural network model, the initial wiring instruction is optimized by using the pre-constructed graph neural network model to obtain the final wiring instruction of the circuit board, and the circuit board is wired according to the final wiring instruction to obtain the wiring result of the circuit board.

[0093] In some embodiments, the embodiments of the present application can input the suspension data into the pre-constructed graph neural network model, and then optimize the initial routing instructions by using the pre-constructed graph neural network model, so as to obtain the final routing instructions of the circuit board, and route the circuit board according to the final routing instructions, thereby obtaining the routing result of the circuit board.

[0094] For example, the embodiments of the present application can input the suspension data into the pre-constructed graph neural network model to analyze the unfinished network topology, and then optimize the initial routing instructions, so as to obtain the final routing instructions of the circuit board, and automatically call the EDA interface, and then import the final routing instructions into the routing software through the API interface of the routing software, restart the routing software, continue the subsequent routing, and then obtain the routing result of the circuit board.

[0095] It should be noted that, in addition to optimizing the initial routing instructions by using the pre-constructed graph neural network model, the embodiments of the present application can also use other intelligent auxiliary systems and intelligent analysis modules for optimization analysis, which can be set by a person skilled in the art according to actual conditions, and the present application does not make specific limitations.

[0096] Optionally, in an embodiment of the present application, in response to the suspension instruction, the suspension data of the circuit board is generated, including: determining the suspension stage of the initial routing instruction based on the instruction information of the suspension instruction; and generating the suspension data under different stage features based on the stage features of the suspension stage.

[0097] It can be understood that, in the embodiments of the present application, the instruction information can include but is not limited to specific parameters and identifiers corresponding to the suspension stage, and the present application does not make specific limitations.

[0098] In some embodiments, the embodiments of the present application can determine the corresponding suspension stage according to the instruction information of the suspension instruction, and then generate the corresponding suspension data by using the stage features of different suspension stages. The stage features can be first stage features such as priority, second stage features such as valid routing tasks and invalid routing tasks, and third stage features such as heat maps and resource consumption statistics, which can be set by a person skilled in the art according to actual conditions, and the present application does not make specific limitations.

[0099] The embodiments of the present application can determine the suspension stage of the initial routing instruction by analyzing the instruction information of the suspension instruction, realize fast and accurate determination, generate the suspension data based on the suspension stage, and process the data of different stages, thereby enhancing the flexibility of the system.

[0100] Optionally, in an embodiment of the present application, based on the plurality of stage characteristics of the abort stage, abort data under different stage characteristics is generated, including: based on a first stage characteristic in the plurality of stage characteristics, determining that, in the case that the abort stage is the first stage, the task level of at least one routing task of the initial routing instruction is reduced to a preset level to obtain abort data under the first stage characteristic; based on a second stage characteristic in the plurality of stage characteristics, determining that, in the case that the abort stage is the second stage, based on the routing quality value of different routing tasks, the routing task satisfying a preset invalid condition is frozen, and the routing task satisfying a preset valid condition is released to form a final task to obtain abort data under the second stage characteristic; based on a third stage characteristic of the plurality of stage characteristics, determining that, in the case that the abort stage is the third stage, at least one of a spatial distribution heat map, an unfinished network priority list and a resource consumption statistics table is generated to obtain abort data under the third stage characteristic.

[0101] In some embodiments, the embodiments of the present application can respond to the abort instruction, adopt a gradual abort manner, and generate abort data under corresponding stage characteristics based on different stage characteristics. The process can be divided into three stages:

[0102] The first stage: reducing the task level of the routing task to a certain level.

[0103] The certain level can be set by a person skilled in the art according to actual conditions, and the present application does not make specific limitations.

[0104] For example, based on the first stage characteristic, the embodiments of the present application determine that, in the case that the abort stage is the first stage, the task level of the routing task numbered 001 in the initial routing instruction is reduced to a low priority. For example, if the routing task 001 has a high priority before responding to the abort instruction, the high priority can be reduced to a low priority after responding to the abort instruction. The specific setting can be made by a person skilled in the art according to actual conditions, and the present application does not make specific limitations, and then the abort data under the corresponding characteristic is obtained.

[0105] The second stage: freezing invalid routing tasks and releasing valid routing tasks.

[0106] In the second stage, the embodiments of the present application can determine, based on the second stage characteristic, that, in the case that the abort stage is the second stage, based on the routing quality value of different routing tasks, the routing task satisfying a certain invalid condition is frozen, and the routing task satisfying a certain valid condition is released to form a final task, and then the abort data under the corresponding characteristic is obtained. The certain invalid condition and the certain valid condition can be set by a person skilled in the art according to actual conditions, and the present application does not make specific limitations.

[0107] For example, in the embodiment of the present application, if the wiring quality value of the wiring task 002 is less than a certain threshold value, it can be determined that the wiring task 002 is an invalid wiring task, and the wiring task 002 can be frozen; if the wiring task 003 is greater than a certain threshold value, it can be determined that the wiring task 003 is a valid wiring task, and the wiring task 003 can be released. Wherein, the certain threshold value can be set by the person skilled in the art according to the actual situation, and the present application does not make specific limitation.

[0108] The third stage: generating a spatial distribution heat map, an unfinished network priority list and a resource consumption statistical table.

[0109] It can be understood that the spatial distribution heat map in the embodiment of the present application can highlight the design rule check violation area, and the present application does not make specific limitation; the unfinished network priority list can be sorted according to the signal integrity requirement, and the present application does not make specific limitation; the resource consumption statistical table can include processor occupancy, memory usage, wiring time length, etc., and the present application does not make specific limitation, and other data can also be generated. The specific can be set by the person skilled in the art according to the actual situation, and the present application does not make specific limitation.

[0110] Wherein, based on the characteristics of the third stage, the present application embodiment can determine that in the suspension stage, the spatial distribution heat map, the unfinished network priority list and the resource consumption statistical table are generated in the third stage, and then the suspension data corresponding to the characteristics is obtained.

[0111] The embodiment of the present application can adopt a gradual three-stage suspension mode to generate corresponding suspension data, optimize resource allocation, improve suspension data quality, and realize supporting accurate analysis and design recovery.

[0112] The optimization method of the circuit board wiring provided by the embodiment of the present application will be introduced below in combination with multiple embodiments.

[0113] Figure 3 The flow chart of the optimization method of the circuit board wiring provided according to another embodiment of the present application.

[0114] Figure 4 The flow chart of the specific process of the optimization method of the circuit board wiring provided according to another embodiment of the present application.

[0115] Step S301: obtaining wiring data by using EDA software based on the monitoring weight of at least one circuit board layer.

[0116] Wherein, in combination with Figure 4 The embodiment of the present application includes:

[0117] Step S401: loading a circuit board design file.

[0118] Step S402: Analyzing the design rule to generate a constraint matrix.

[0119] Step S403: Initializing a pre-constructed routing quality evaluation model.

[0120] Step S404: Configuring a threshold value.

[0121] In the embodiments of the present application, the threshold value can include and .

[0122] Step S405: Starting monitoring.

[0123] Step S406: API obtaining routing data.

[0124] Step S302: Starting the routing software and performing the suspension analysis.

[0125] In combination with the schematic diagram shown in Figure 4 , the embodiments of the present application include:

[0126] Step S407: Calculating the actual complexity of the circuit board.

[0127] Step S408: Dynamically adjusting the weight coefficient.

[0128] In the embodiments of the present application, the weight coefficient can include but is not limited to a first weight coefficient, a second weight coefficient, and a third weight coefficient, and the present application does not make specific limitations.

[0129] Step S409: Calculating the routing quality value.

[0130] Step S410: Judging whether the routing quality value is less than a certain quality threshold value.

[0131] In the embodiments of the present application, step S411 is performed in the case of less than; otherwise, step S406 is performed.

[0132] Step S411: Counting the duration.

[0133] Step S412: Judging whether the duration is greater than a certain time length.

[0134] In the embodiments of the present application, step S413 is performed in the case of greater than; otherwise, step S406 is performed.

[0135] Step S413: Triggering the suspension instruction.

[0136] In summary, the embodiment of the present application can start the wiring software, and then calculate the corresponding wiring quality value by using the pre-constructed wiring quality evaluation model, detect whether the wiring quality value is less than a certain quality threshold, and in the case of less than, count the duration that the wiring quality value is less than the certain quality threshold, and judge whether the duration is greater than a certain time length, and in the case of greater than, trigger the suspension instruction.

[0137] Step S303: suspending the wiring software, and generating suspension data.

[0138] As shown in Figure 4 The embodiment of the present application includes:

[0139] Step S414: three-stage suspension.

[0140] Step S415: reducing the task level.

[0141] Step S416: freezing invalid tasks.

[0142] Step S417: generating suspension data.

[0143] In summary, the embodiment of the present application can trigger the suspension instruction, suspend the wiring software, and generate the suspension data.

[0144] Step S304: optimizing the initial wiring instruction.

[0145] As shown in Figure 4 The embodiment of the present application includes:

[0146] Step S418: generating the wiring suggestion by using the pre-constructed graph neural network model.

[0147] It can be understood that the embodiment of the present application can optimize the initial wiring instruction by using the pre-constructed graph neural network model, and then obtain the final wiring instruction of the circuit board.

[0148] Step S305: re-importing the EDA software, and starting the wiring software.

[0149] As shown in Figure 4 The embodiment of the present application includes:

[0150] Step S419: automatically restarting the wiring software.

[0151] Step S420: judging whether to continue.

[0152] In the embodiment of the present application, if the continuation is performed, the step S401 is executed; otherwise, the step S421 is executed.

[0153] Step S421: completing the wiring, and generating the wiring result.

[0154] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment.

[0155] According to the circuit board wiring optimization method provided by the embodiment of the application, the corresponding wiring data can be obtained based on different monitoring weights, the wiring quality value responding to the initial wiring instruction is obtained by using the pre-constructed wiring quality evaluation model, and whether the wiring quality value is less than a certain quality threshold is detected. In the case that the wiring quality value is less than a certain quality threshold and the duration is greater than a certain time length, the stop instruction is triggered, the stop data is generated, and then the initial wiring instruction is optimized by using the pre-constructed graph neural network model to obtain the final wiring instruction, and the wiring is performed according to the final wiring instruction, so that the wiring result is obtained. Therefore, the technical problems in the related art that the wiring software cannot be stopped in time, the repetitive work is prone to occur, the wiring efficiency is low, a large amount of manpower and time cost are consumed, the dynamic monitoring and stopping mechanism of the wiring process is not involved in the improvement of the wiring density, the arc-shaped fan-out signal line efficiency depends on the static rules and lacks real-time quality evaluation, and the like can be solved. The technical effects of improving the wiring efficiency, shortening the wiring period, actively stopping the inefficient path, avoiding resource waste, reducing invalid calculation, improving the wiring path, reducing the wiring cost, and optimizing resource allocation are achieved.

[0156] The embodiment of the application further provides a circuit board wiring optimization device.

[0157] Figure 5 A block schematic diagram of the circuit board wiring optimization device provided by the embodiment of the application is shown.

[0158] As shown in Figure 5 The circuit board wiring optimization device 20 includes a first acquisition module 100, a first output module 200, a detection module 300, a generation module 400, and a second output module 500.

[0159] The first acquisition module 100 is configured to acquire wiring data corresponding to the monitoring weight based on the monitoring weight of at least one circuit board layer in the circuit board.

[0160] The first output module 200 is configured to input the wiring data into a pre-constructed wiring quality evaluation model to output a wiring quality value responding to an initial wiring instruction.

[0161] The detection module 300 is configured to detect whether the wiring quality value is less than the preset quality threshold value, and in a case where it is detected that the wiring quality value is less than the preset quality threshold value, count a duration for which the wiring quality value of the circuit board is less than the preset quality threshold value, and determine whether the duration is greater than a preset time length.

[0162] The generation module 400 is configured to, in a case where the duration is greater than the preset time length, trigger a suspension instruction of the circuit board, and generate suspension data of the circuit board in response to the suspension instruction.

[0163] The second output module 500 is configured to input the suspension data into a pre-constructed graph neural network model, optimize the initial wiring instruction by using the pre-constructed graph neural network model to obtain a final wiring instruction of the circuit board, and wire the circuit board according to the final wiring instruction to obtain a wiring result of the circuit board.

[0164] Optionally, in an embodiment of the present application, the first acquisition module 100 further includes a first determination unit, a second determination unit and a calculation unit.

[0165] The first determination unit is configured to, before the wiring data is input into the pre-constructed wiring quality evaluation model, determine a target network routing rate, a target average wire length and a target via density of the circuit board based on the target wiring data.

[0166] The second determination unit is configured to determine a first weight coefficient corresponding to the target network routing rate, a second weight coefficient corresponding to the target average wire length and a third weight coefficient corresponding to the target via density based on the target network routing rate, the target average wire length and the target via density.

[0167] The first construction module is configured to construct the wiring quality evaluation model based on the target network routing rate, the target average wire length, the target via density, the first weight coefficient, the second weight coefficient and the third weight coefficient.

[0168] Optionally, in an embodiment of the present application, the first acquisition module 100 includes a first determination unit and a first acquisition unit.

[0169] The first determination unit is configured to determine the size of the wiring data based on the size of the monitoring weight, wherein the size of the monitoring weight is positively correlated with the size of the data.

[0170] The first acquisition unit is configured to obtain the wiring data containing at least one of the network routing rate, the critical path delay, the interlayer via density and the number of design rule violations according to the data quantity.

[0171] Optionally, in an embodiment of the present application, the first acquisition module 100 includes a second determination unit, a second acquisition unit and a calculation unit.

[0172] The second determining unit is configured to determine an actual complexity of the circuit board and a target complexity of a target circuit board based on a network quantity, a layer quantity and an element density of the circuit board.

[0173] The second obtaining unit is configured to obtain a high-speed signal proportion of the circuit board based on the circuit board.

[0174] The calculating unit is configured to calculate a monitoring weight based on the actual complexity, the target complexity and the high-speed signal proportion.

[0175] Optionally, in an embodiment of the present application, the method further includes a judging module, a first input module and a second input module.

[0176] The judging module is configured to judge whether the wiring data meets a preset data condition before the wiring data is input into the pre-constructed wiring quality evaluation model.

[0177] The first input module is configured to process the wiring data until wiring data meeting the preset data condition is obtained, and allow the wiring data meeting the preset data condition to be input into the pre-constructed wiring quality evaluation model when the wiring data does not meet the preset data condition.

[0178] The second input module is configured to allow the wiring data to be input into the pre-constructed wiring quality evaluation model when the wiring data meets the preset data condition.

[0179] Optionally, in an embodiment of the present application, the generating module 400 includes a third determining unit and a generating unit.

[0180] The third determining unit is configured to determine an abort stage of the initial wiring instruction based on instruction information of the abort instruction.

[0181] The generating unit is configured to generate abort data under different stage features based on a plurality of stage features of the abort stage.

[0182] Optionally, in an embodiment of the present application, the generating unit includes a reducing subunit, a first generating subunit and a second generating subunit.

[0183] The reducing subunit is configured to determine, based on a first stage feature in the plurality of stage features, that the abort stage is the first stage, and reduce a task level of at least one wiring task of the initial wiring instruction to a preset level to obtain the abort data under the first stage feature.

[0184] The first generation subunit is configured to determine, based on the second stage feature in the multiple stage features, that in the case of the second stage as the abort stage, based on the wiring quality value of different wiring tasks, freeze the wiring tasks meeting the preset invalid condition, release the wiring tasks meeting the preset valid condition, form a final task, and obtain the abort data under the second stage feature.

[0185] The second generation unit is configured to determine, based on the third stage feature in the multiple stage features, that in the case of the third stage as the abort stage, generate at least one of a spatial distribution heat map, an unfinished network priority list, and a resource consumption statistical table, and obtain the abort data under the third stage feature.

[0186] Optionally, in an embodiment of the present application, the circuit board wiring optimization device further comprises a second acquisition module, a second determination module, and a second construction module.

[0187] The second acquisition module is configured to acquire historical abort data of the circuit board before the abort data is input to the pre-constructed graph neural network model.

[0188] The second determination module is configured to determine structure information and training information of the graph neural network model based on the historical abort data.

[0189] The second construction module is configured to train the graph neural network model using the historical abort data based on the structure information and the training information, and construct the graph neural network model meeting the preset training condition.

[0190] Optionally, in an embodiment of the present application, the first acquisition module 100 comprises a third acquisition unit, a fourth determination unit, and a fourth acquisition unit.

[0191] The third acquisition unit is configured to acquire wiring indicators of the wiring data based on the circuit board.

[0192] The fourth determination unit is configured to determine an update time of the wiring data based on board layer information of the circuit board.

[0193] The fourth acquisition unit is configured to update the wiring data based on the wiring indicators and the update time.

[0194] The features of the embodiments of the circuit board wiring optimization device can be referred to the related descriptions of the embodiments of the circuit board wiring optimization method, which will not be repeated here.

[0195] The circuit board wiring optimization device provided in the embodiment of the present application can obtain corresponding wiring data based on different monitoring weights, obtain a wiring quality value in response to an initial wiring instruction by using a pre-constructed wiring quality evaluation model, detect whether the wiring quality value is less than a certain quality threshold, and in the case that the wiring quality value is less than the certain quality threshold and the duration is greater than a certain time length, trigger a suspension instruction to generate suspension data, and then optimize the initial wiring instruction by using a pre-constructed graph neural network model to obtain a final wiring instruction, and perform wiring according to the final wiring instruction to obtain a wiring result. Therefore, the technical problems in the related art that the wiring software cannot be suspended in time, repetitive work is prone to occur, the wiring efficiency is low, a large amount of manpower and time cost are consumed, wiring density is not involved in the dynamic monitoring and suspension mechanism of the wiring process, arc fan-out signal lines rely on static rules and lack real-time quality evaluation, and the like can be solved, and the technical effects of improving the wiring efficiency, shortening the wiring period, actively suspending an inefficient path, avoiding resource waste, reducing invalid calculation, improving the wiring path, reducing the wiring cost, and optimizing resource allocation are achieved.

[0196] The embodiment of the present application also provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-mentioned circuit board wiring optimization method embodiments.

[0197] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned circuit board wiring optimization method embodiments when running.

[0198] In an example embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0199] The embodiment of the present application also provides a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned circuit board wiring optimization method embodiments.

[0200] The embodiment of the present application also provides another computer program product, which includes a non-volatile computer readable storage medium, the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned circuit board wiring optimization method embodiments.

[0201] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed application. Accordingly, modifications and / or additions, other than those explicitly described herein, can be obvious to those skilled in the art in the light of this disclosure. The claimed application is intended to embrace all such modifications and / or additions.

[0202] The above has carried out the detailed introduction to the optimization method of the circuit board wiring provided by the application. The principle and implementation mode of the application are described by applying specific examples in this paper, and the above example description is only used to help understand the method and its core idea of the application. It should be pointed out that for ordinary skilled in the art, some improvements and modifications can be made to the application without departing from the principle of the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims

1. A method of optimizing a circuit board layout, characterized by, The method comprises the following steps: obtaining wiring data corresponding to a monitoring weight of at least one circuit board layer in a circuit board based on the monitoring weight; inputting the wiring data into a pre-constructed wiring quality evaluation model to output a wiring quality value in response to an initial wiring instruction; detecting whether the wiring quality value is less than a preset quality threshold, and if the wiring quality value is less than the preset quality threshold, counting a duration for which the wiring quality value is less than the preset quality threshold, and determining whether the duration is greater than a preset time length; if the duration is greater than the preset time length, triggering a suspension instruction of the circuit board, and generating suspension data of the circuit board in response to the suspension instruction; inputting the suspension data into a pre-constructed graph neural network model to optimize the initial wiring instruction by using the pre-constructed graph neural network model to obtain a final wiring instruction of the circuit board, and wiring the circuit board according to the final wiring instruction to obtain a wiring result of the circuit board.

2. The method according to claim 1, characterized in that Before inputting the wiring data into the pre-constructed wiring quality evaluation model, the method further comprises: determining a target network routing rate, a target average wire length, and a target via density of the circuit board based on target wiring data; determining a first weight coefficient corresponding to the target network routing rate, a second weight coefficient corresponding to the target average wire length, and a third weight coefficient corresponding to the target via density based on the target network routing rate, the target average wire length, and the target via density; constructing the wiring quality evaluation model based on the target network routing rate, the target average wire length, the target via density, the first weight coefficient, the second weight coefficient, and the third weight coefficient.

3. The method of claim 1, wherein, The method of obtaining wiring data corresponding to a monitoring weight of at least one circuit board layer in a circuit board based on the monitoring weight comprises: determining a size of a data amount of the wiring data based on a size of the monitoring weight, wherein the size of the monitoring weight is positively correlated with the size of the data amount; obtaining wiring data containing at least one of a network routing rate, a critical path delay, an interlayer via density, and a design rule violation frequency according to the data amount.

4. The method of claim 1, wherein, The method of obtaining wiring data corresponding to a monitoring weight of at least one circuit board layer in a circuit board based on the monitoring weight comprises: determining an actual complexity of the circuit board and a target complexity of a target circuit board based on a number of networks, a number of layers, and a component density of the circuit board; obtaining a proportion of high-speed signals of the circuit board based on the circuit board; calculating the monitoring weight based on the actual complexity, the target complexity, and the proportion of high-speed signals.

5. The method of claim 1, wherein, Before inputting the wiring data into the pre-constructed wiring quality evaluation model, the method further comprises: determining whether the wiring data satisfies a preset data condition; If the wiring data does not meet the preset data condition, the wiring data is processed until wiring data meeting the preset data condition is obtained, and the wiring data meeting the preset data condition is allowed to be input into the pre-constructed wiring quality evaluation model; If the wiring data meets the preset data condition, the wiring data is allowed to be input into the pre-constructed wiring quality evaluation model.

6. The method of claim 1, wherein, The response to the suspension instruction includes generating suspension data of the circuit board, comprising: Based on the instruction information of the suspension instruction, the suspension stage of the initial wiring instruction is determined; Based on the multiple stage characteristics of the suspension stage, suspension data under different stage characteristics is generated.

7. The method of claim 6, wherein, The suspension data under different stage characteristics is generated based on the multiple stage characteristics of the suspension stage, comprising: Based on the first stage characteristic in the multiple stage characteristics, if the suspension stage is the first stage, the task level of at least one wiring task of the initial wiring instruction is reduced to a preset level to obtain suspension data under the first stage characteristic; Based on the second stage characteristic in the multiple stage characteristics, if the suspension stage is the second stage, based on the wiring quality value of different wiring tasks, the wiring task meeting the preset invalid condition is frozen, and the wiring task meeting the preset valid condition is released to form a final task to obtain suspension data under the second stage characteristic; Based on the third stage characteristic in the multiple stage characteristics, if the suspension stage is the third stage, at least one of the spatial distribution heat map, the unfinished network priority list and the resource consumption statistical table is generated to obtain suspension data under the third stage characteristic.

8. The method of claim 1, wherein, Before inputting the suspension data into the pre-constructed graph neural network model, further comprising: Obtaining historical suspension data of the circuit board; Based on the historical suspension data, the structure information and training information of the graph neural network model are determined; Based on the structure information and the training information, the graph neural network model is trained using the historical suspension data to construct a graph neural network model meeting the preset training condition.

9. The method of claim 1, wherein, The wiring data corresponding to the monitoring weight is obtained, comprising: Based on the circuit board, the wiring index of the wiring data is obtained; Based on the board layer information of the circuit board, the update time of the wiring data is determined; Based on the wiring index and the update time, the wiring data is updated.

10. An electronic device, comprising: Comprising: A memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the optimization method of the circuit board wiring according to any one of claims 1-9.

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