Active display device and pulse width modulation driving method

Abstract

The invention relates to an active display device. The active display device comprises a gate driving circuit; a data driving circuit; the logic module is configured to at least receive the global signal and the first row-by-row enable signal and perform different logic transformations, so that one or more light emitting operations are executed after analog display signals are written into each row of pixels; and a pixel array including a pixel circuit that performs a light emitting operation based at least on the analog display signal and control of an output of the logic module. The invention also relates to electronic equipment and a pulse width modulation driving method.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an active display device and a pulse width modulation driving method. Background Art

[0002] In recent years, research on micro-light-emitting diode (Micro-LED) display technology has attracted widespread attention. Compared with traditional displays such as liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs), Micro-LED displays offer advantages such as ultra-high brightness, high contrast, fast switching response speeds, and potentially better stability.

[0003] However, due to the unique optoelectronic properties of Micro-LEDs, the Pulse Amplitude Modulation (PAM) method used in traditional displays is not suitable for Micro-LED displays. The reasons include that the current-voltage characteristic curve of Micro-LEDs is steep, much steeper than that of traditional OLED displays, making it difficult to accurately control the display grayscale by controlling the amplitude of current or voltage. The external quantum efficiency (EQE) of Micro-LEDs varies with the driving current, especially at low driving currents, where the EQE decreases significantly. In addition, the emission wavelength of Micro-LEDs varies with the driving current, and a more obvious color shift occurs at low driving currents.

[0004] Pulse Width Modulation (PWM) maintains a constant luminous current and uses PWM signals with different duty cycles to control the duration of the Micro-LED drive current. By changing the average current in a frame, the luminous brightness of the Micro-LED is controlled, thereby controlling the displayed grayscale.

[0005] Compared to PAM drive, existing Micro-LEDs utilize PWM drive, which maintains high luminous efficiency and a constant wavelength. This not only addresses the issues of low luminous efficiency and wavelength shift inherent in PAM drive, but also allows for optimal Micro-LED display performance. PWM drive also allows for more precise control of average display brightness in small grayscales. This approach is applicable not only to Micro-LEDs but also to active-emission display applications such as Mini-LED, OLED, and QLED.

[0006] However, existing PWM drive methods are also unsuitable for high-resolution, long-lighting-time Micro-LED display devices. Therefore, a new drive method and corresponding display driver circuit are needed to support the further development of Micro-LED displays. Summary of the Invention

[0007] In response to the technical problems existing in the prior art, the present application proposes an active display device, including a gate drive circuit configured to at least receive a global signal and generate a first row-by-row enable signal; a data drive circuit, receiving display data and converting it into an analog display signal; a logic module, configured to at least receive the global signal and the first row-by-row enable signal and perform different logical transformations, so that after each row of pixels writes the analog display signal, one or more light-emitting operations are performed, and the total light-emitting time within a frame corresponds to the corresponding display signal; wherein the global signal includes a reference signal and a charging signal; the reference signal includes a reset part and a comparison part, wherein the value of the reference signal in the reset part remains unchanged, and the value of the reference signal in the comparison part changes from its minimum value to its maximum value; the reset part of the reference signal lasts for a fixed time; the charging signal is valid in the reset part of the reference signal; when the first row-by-row enable signal is valid, it corresponds to a reset part and a continuous or discontinuous but complete comparison part of the reference signal; and a pixel array, including a pixel circuit, performing a light-emitting operation based on at least the control of the analog display signal and the output of the logic module.

[0008] In particular, the active display device, wherein the logic module includes a logic AND unit, configured to perform a logic AND operation on the transformed charging signal and the first row-by-row enable signal; and a data selection unit, configured to select the value or low level of the reference signal as the first reference signal under the control of the first row-by-row enable signal or its deformation.

[0009] Particularly, in the active display device, the logic module includes a logic OR unit configured to perform a logic OR operation on the charging signal and the variation of the first row-by-row enable signal.

[0010] Particularly, in the active display device, the logic module is located in the gate driving circuit or the pixel circuit of the pixel array; or, a part of the logic module is located in the gate driving circuit, and the other part is located in the pixel circuit.

[0011] In particular, the active display device, wherein the pixel circuit includes the light-emitting element; a PWM generation module, configured to receive at least the first reference signal and display data, and output a PWM signal; a constant current module, configured to provide a light-emitting current to the light-emitting element; a switch module, coupled between the constant current module and the light-emitting element; and configured to control the on or off state of the switch module using the PWM signal generated by the PWM signal generation module.

[0012] In particular, the active display device, wherein the PWM generation module of the pixel circuit includes a first transistor (T223, T423 or T516) and a first capacitor (C221, C421 or C51); the control electrode of the first transistor (T223, T423 or T516) receives the variation of the first row-by-row enable signal, the first electrode of the first transistor (T223, T423 or T516) receives display data from the data driving circuit, the second electrode of the first transistor (T223, T423 or T516) is coupled to the first end of the first capacitor; the second electrode of the first capacitor is coupled to the first end of the first capacitor. an output terminal of the data selection unit; a second transistor (T221, T421 or T511), a control electrode of the second transistor (T221, T421 or T511) is coupled between the second electrode of the first transistor (T223, T423 or T516) and the first end of the first capacitor (C221, C421 or C51), a first electrode is coupled to the output terminal of the PWM generation module, and a second electrode is grounded; and wherein the switch module includes a third transistor (T230, T430 or T540), a control electrode of the third transistor is coupled to the output terminal of the PWM generation module, and a first electrode of the third transistor is coupled to the constant current module.

[0013] In particular, in the active display device, the PWM generation module of the pixel circuit further includes a fourth transistor (T222); the control electrode of the fourth transistor (T222) receives the output of the logic OR unit, the first electrode receives a high level, and the second electrode is coupled to the output end of the PWM generation module.

[0014] In particular, the active display device, wherein the logic OR unit includes a fifth transistor (T4221 or T512) and a sixth transistor (T4223 or T513); the first electrode of the fifth transistor (T4221 or T512) is coupled to the first electrode of the sixth transistor (T4223 or T513) and receives a high level, the control electrode of the fifth transistor (T4221 or T512) receives the charging signal, and the control electrode of the sixth transistor (T4223 or T513) receives the first row-by-row enable signal; the second electrode of the fifth transistor (T4221 or T512) is coupled to the second electrode of the sixth transistor (T4223 or T513) and coupled to the output end of the PWM generation module 220 as the output end of the logic OR unit.

[0015] In particular, in the active display device described in 7, the PWM generation module of the pixel circuit also includes a seventh transistor (T240 or T440); the control electrode of the seventh transistor (T240 or T440) receives the output of the logic AND unit, the first electrode is coupled to the second electrode of the third transistor (T230, T430), and the second electrode is coupled to the light-emitting element.

[0016] In particular, the active display device, wherein the logic AND unit includes an eighth transistor (T531) and a ninth transistor (T532) connected in series with each other; the first electrode of the eighth transistor (T531) is coupled to the second electrode of the third transistor (T540) as the input end of the logic AND unit, the control electrode receives the deformation of the charging signal, and the second electrode is coupled to the first electrode of the ninth transistor (T532); the control electrode of the ninth transistor (T532) receives the first row-by-row enable signal output by the gate drive circuit, and the second electrode serves as the output end of the logic AND unit and is coupled to the light-emitting element.

[0017] In particular, the active display device, wherein the data selection unit includes a tenth transistor (T514) and an eleventh transistor (T515); the first electrode of the tenth transistor (T514) receives a reference signal, the control electrode receives the first row-by-row enable signal, the second electrode is coupled to the first electrode of the eleventh transistor (T515) and serves as the output end of the data selection unit; the control electrode of the eleventh transistor (T515) receives a variation of the first row-by-row enable signal, and the second electrode is grounded.

[0018] In particular, the active display device, wherein the constant current module includes a twelfth transistor (T527) and a second capacitor (C522); the control electrode of the twelfth transistor (T527) is coupled to the first end of the second capacitor (C522), the first electrode receives a high level, and the second electrode is coupled to the first electrode of the third transistor (T540); the first end of the second capacitor (C522) is grounded; and a thirteenth transistor (T528), the control electrode receives a variation of the first row-by-row enable signal, the first electrode receives constant current data, and the second electrode is coupled between the control electrode of the twelfth transistor (T527) and the first end of the second capacitor (C522).

[0019] In particular, the active display device, wherein the pixel circuit includes the light-emitting element; a PWM generation module, configured to receive at least the first reference signal and display data, and output a PWM signal; a constant current module, configured to provide a light-emitting current to the light-emitting element; a switch module, coupled between the constant current module and the light-emitting element; and configured to control the on or off state of the switch module using the PWM signal generated by the PWM signal generation module.

[0020] In particular, the active display device, wherein the PWM generation module in the pixel circuit includes a fourteenth transistor (T61) and a fifteenth transistor (T62), wherein the control electrode of the fourteenth transistor (T61) is coupled to the control electrode of the fifteenth transistor (T62), the second electrode of the fourteenth transistor (T61) receives a high level, the first electrode of the fourteenth transistor (T61) is coupled to the first electrode of the fifteenth transistor (T62) and serves as the output end of the PWM generation module; the second electrode of the fifteenth transistor (T62) is grounded; wherein the fourteenth transistor (T61) and the fifteenth transistor (T62) are of opposite types; and a sixteenth transistor (T613), wherein the first electrode of the sixteenth transistor (T613) receives the display signal, the second electrode of the sixteenth transistor (T613) is coupled to the control electrodes of the fourteenth transistor (T61) and the fifteenth transistor (T62), and the control electrode of the sixteenth transistor (T613) receives the scan signal; and a third capacitor (C612), wherein the first end of the capacitor receives the first reference signal and the second end of the capacitor is coupled to the second electrode of the sixteenth transistor (T613).

[0021] In particular, the active display device, wherein the PWM generation module in the pixel circuit includes a sixteenth transistor (T71) and a seventeenth transistor (T72); the control electrode of the sixteenth transistor (T71) is coupled to the control electrode of the seventeenth transistor (T72) and the first electrode of the sixteenth transistor (T71), and the second electrode is coupled to the second electrode of the seventeenth transistor (T72) and receives a high level; the first electrode of the seventeenth transistor (T72) is coupled to the first electrode of the eighteenth transistor (T74) as the output end of the PWM generation module; the second electrode of the eighteenth transistor (T74) is coupled to the second electrode of the nineteenth transistor (T73), and the control electrode is coupled to the first electrode of the twentieth transistor (T712); the first electrode of the nineteenth transistor (T73) is coupled to the sixteenth transistor (T71). The present invention relates to a circuit comprising a first electrode of a transistor (T71) and a control electrode thereof receiving the first reference signal; a first electrode of a twentieth transistor (T712) receiving a display signal, a control electrode receiving the scan signal, a second electrode coupled to a first end of a fourth capacitor (C713), and a second end of the fourth capacitor (C713) being grounded; and a twenty-first transistor (T75) and a twenty-second transistor (T76); a control electrode of the twenty-first transistor (T75) being coupled to its first electrode and to the control electrode of the twenty-second transistor (T76), a second electrode coupled to the second electrode of the twenty-second transistor (T76) and grounded, and a second electrode of the twenty-first transistor (T75) being coupled to the second electrode of the twenty-second transistor (T76); and a first electrode of the twenty-first transistor (T75) being coupled to a bias current source.

[0022] In particular, the active display device, wherein the constant current module of the pixel circuit includes a twenty-third transistor (T621 or T721) and a current bias unit, the first electrode of the twenty-third transistor (T621 or T721) receives a high level through the current bias unit, the control electrode thereof receives the output of the logic AND unit, and the second electrode thereof is coupled to the switching module; and the switching module includes a twenty-fourth transistor (T630 or T730), the first electrode of the twenty-fourth transistor (T630 or T730) is coupled to the second electrode of the twenty-third transistor (T621 or T721), the control electrode of the twenty-fourth transistor (T630 or T730) is coupled to the output end of the PWM generation module, and the second electrode is coupled to the light-emitting element.

[0023] The present application also provides an electronic device, which includes a Micro-LED display pixel array, a timing control circuit, a gate drive circuit, and a data drive circuit, and the electronic device includes any active display device as described above.

[0024] The present application also provides a pulse width modulation driving method, comprising: receiving a reference signal; the global signal comprises a reference signal and a charging signal; the reference signal comprises a reset part and a comparison part, wherein the value of the reference signal in the reset part remains unchanged, and the value of the reference signal in the comparison part changes from its minimum value to its maximum value; the reset phase of the reference signal lasts for a fixed time; the luminous time within a frame corresponds to at least one reset part of the reference signal and a complete comparison part obtained continuously or by splicing; receiving a display signal, wherein the display signal comprises a voltage corresponding to the value of the display signal; writing the display signal into the pixel circuit during the display signal writing phase of a frame; and, driving the light-emitting element in the pixel circuit to emit light based on the display signal.

[0025] In particular, the driving method further includes comparing the display signal with a reference signal in each subframe, and when the relative relationship between the display signal and the reference signal changes, the luminous state of the light-emitting element changes.

[0026] In particular, the driving method, wherein the luminous time of the light-emitting element in one frame includes at least two sub-frames, the luminous time of the light-emitting element in each sub-frame is less than or equal to the longest luminous time of one frame, and the sum of the luminous times of each sub-frame is equal to the longest luminous time of one frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1A is a schematic diagram of an active display device module according to an embodiment of the present application; Figure 1B yes Figure 1A A schematic diagram of the working timing of the active display device shown; Figure 2A is a circuit diagram of an active display device according to another embodiment of the present application; Figure 2B yes Figure 2A A schematic diagram of the working timing of the active display device shown; Figure 3 is a circuit diagram of an active display device according to another embodiment of the present application; Figure 4 is a schematic diagram of a pixel circuit according to an embodiment of the present application; Figure 5A is a circuit diagram of an active display device according to another embodiment of the present application; Figure 5B yes Figure 5A A schematic diagram of the working timing of the active display device shown; Figure 6is a schematic diagram of an active display device circuit according to another embodiment of the present application; and, Figure 7 Shown is a schematic structural diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0030] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0031] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be single crystal silicon, hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using single crystal silicon, amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process. The following description takes the high level as the effective level as an example for explanation.

[0032] Existing pixel circuit drive methods can be categorized as synchronous or row-by-row. Both the row-by-row and synchronous drive methods write display data into the pixel circuit row by row. The difference is that with the synchronous drive method, all light-emitting elements emit light simultaneously after all rows of display data are written; whereas with the row-by-row drive method, the light-emitting elements in a row begin emitting light only after the display data for that row is written.

[0033] The existing PWM driving methods of synchronous luminescence mode are divided into digital PWM and analog PWM. The existing digital PWM driving method divides the external input binary data into N sub-frames according to a fixed number of bits and inputs them into pixels. Each sub-frame determines the luminescence duration of the corresponding pixel. The commonly used analog PWM driving method directly converts the binary data into the corresponding analog voltage value, and converts the analog voltage value into a PWM signal with different duty cycles that determines the luminescence duration of the pixel. The analog PWM driving method only needs to write data once row by row within a frame, while the digital PWM driving method needs to write multiple times within a frame. Therefore, the analog PWM driving method of the synchronous luminescence mode can be used for luminescence in a frame for a longer time than the digital PWM driving method, but the luminescence time still cannot meet some practical needs.

[0034] Typically, the signals received by the pixel array are divided into global signals and row-by-row signals. A global signal is the same signal applied to all rows. A row-by-row signal is a signal in which the waveform of each row is delayed by a fixed time interval relative to the waveform of the previous row. As the number of rows increases, the waveform is delayed row by row.

[0035] In the existing progressive illumination mode, when the pixel circuit in the pixel array uses a single transistor as a dynamic comparator, the comparator can only perform one comparison after completing a reset within a frame. Therefore, the reference signal must be a monotonic function. To ensure the monotonicity of the reference signal, the reference signal received by each row is output to the pixel circuit in each row after a fixed time delay relative to the previous row. The waveform of the reference signal received by each row of pixel circuits is the same, so that all grayscale levels can be expressed. This increases the area of ​​the gate drive circuit and the cost.

[0036] The present application proposes an active display device that implements row-by-row light emission control based on an analog PWM drive method, solving the problems of short light emission time and high cost in the row-by-row light emission mode in the existing synchronous light emission PWM drive method, thereby achieving a better display effect under this drive method.

[0037] The row-by-row lighting method proposed in the present application uses a global signal as the reference signal. The reference signal includes a reset phase and a lighting phase. Since the row-by-row enable signal that directly controls the lighting time of each row is a row-by-row signal, the lighting time of one frame inevitably includes the reset phase of the reference signal. The lighting time of one frame is divided into two or more sub-frames, and the reference signals received by the pixel circuits in each sub-frame are spliced ​​to obtain a complete reference signal. When such a signal is applied to the existing row-by-row lighting mode, the comparator in the pixel circuit cannot perform multiple comparisons within one frame, resulting in the lighting time of one frame being shortened to one sub-frame time. Therefore, the pixel circuit of the present application performs an intra-frame reset between each sub-frame, and the pixel circuit can compare the reference signal and the analog display signal in each sub-frame. The sum of the lighting time of all sub-frames is the lighting time corresponding to the display signal within one frame. The number of reset phases and sub-frames can be increased to achieve other beneficial effects.

[0038] The embodiments of this application are based on a Micro-LED active pixel array as an example. The transistors in the pixel circuit are not limited to n-type TFT transistors. Based on the similarity of basic display principles, the pixel circuit disclosed in this application can be applied to applications such as LTPO, single-crystal silicon CMOS processes, and other active display arrays.

[0039] The pixel circuit of the present application adopts a mechanism of row-by-row writing and row-by-row lighting. Therefore, after the pixel circuit of the first row completes the display signal writing operation within one frame, that is, after the pixel circuit of this row receives the first frame of analog display signal, the pixel circuit starts the lighting stage within one frame.

[0040] Figure 1A Schematic diagram of an active display device module according to an embodiment of the present application.

[0041] According to one embodiment, Figure 1AAs shown, the active display device includes a gate drive circuit 11, which is configured to receive at least a global signal and generate a row-by-row enable signal EM[i] (not shown). The gate drive circuit 11 may include a logic module 110, which is configured to receive at least the global signal and the row-by-row enable signal EM[i] and perform different logical transformations and generate at least a first reference signal. According to one embodiment, the gate drive circuit 11 may include I logic modules 110, and the pixel circuits in the same row share one logic module 110, where I is an integer greater than 0. I row of pixel circuits receive the output of the logic module 110 corresponding to it. According to one embodiment, the logic module 110 can reduce the pixel area within the gate circuit.

[0042] According to one embodiment, the active display device shown in FIG1 further includes a data driving circuit 12 configured to receive display data and convert the data into an analog display signal. According to one embodiment, the display data corresponds to an N-bit X-ary number in a frame, and the analog display signal can be an electrical quantity, such as a voltage, corresponding to the value of the display data.

[0043] According to one embodiment, J columns of pixel circuits may receive display signals DATA[j] from the data driving circuit 12. Accordingly, the data driving circuit 12 may include J digital-to-analog conversion (DAC) units, and pixel circuits in the same column share one DAC unit, where J is an integer greater than 0.

[0044] According to one embodiment, the active display device further includes a pixel circuit 13. The pixel circuit 13 is configured to receive at least a first reference signal output by the logic module 110 and a display signal from the data driving circuit 12. Display pixels in the same row share the same first reference signal.

[0045] In one embodiment of the present application, the logic module 110 may be located within the pixel circuit 13. In this case, the pixel circuit receives at least the global signal and the row-by-row enable signal EM[i] output by the gate driver circuit. The logic module within the pixel circuit can improve the accuracy of the reference signal.

[0046] In another embodiment of the present application, a portion of the logic module 110 is located in the pixel circuit, and another portion is located in the gate driving circuit.

[0047] According to one embodiment, the global signal may include a reference signal VSWEEP and may also include a charging signal CHG. The reference signal VSWEEP includes two parts: a reset phase and a light-emitting phase. The reset phase of the reference signal VSWEEP lasts for a fixed time, such as a line time, and the line time may include the display signal writing time or the threshold compensation time of a row of pixels. The value of the reference signal VSWEEP in the reset phase is equal to the reset value, and the rest of the time is the light-emitting phase. In the light-emitting phase of the reference signal VSWEEP, the value of the reference signal may be a ramp signal, a triangle wave signal, a step signal, etc. that changes with time. According to one embodiment, when the reference signal VSWEEP jumps from the light-emitting phase to the reset value of the reset phase, the charging signal CHG jumps from a low level to a high level, and the high level duration is a line time to reset the pixel circuit or reset within the frame.

[0048] According to one embodiment, the row-by-row enable signal EM[i] is a row-by-row signal. Within a frame, when the row-by-row enable signal EM[i] is at a low level, the pixel circuit enters the display signal writing phase. At this time, the display signal is written into the pixel circuit. The first reference signal output by the logic module 110 is at a low level.

[0049] According to one embodiment, within a frame, when the row-by-row enable signal EM[i] is at a high level, the pixel circuit enters a light-emitting phase. The first reference signal output by the logic module 110 is the value of the reference signal received by the logic circuit 110. The duration of the high level of the row-by-row enable signal EM[i] is the longest light-emitting time of each row of pixels within a frame. During the light-emitting phase, the first reference signal corresponding to the row-by-row enable signal EM[i] includes at least a reset phase of the reference signal and a complete light-emitting phase that is continuous or discontinuous but can be spliced ​​together, ensuring that a complete reference signal can be obtained by splicing the reference signals received by the pixel circuit within a frame, thereby ensuring the integrity of the grayscale expression.

[0050] According to one embodiment, during the display signal writing phase of the pixel circuit, the charging signal is at a high level, realizing simultaneous writing of the display signal to the pixel circuit and resetting the pixel circuit. During the light emitting phase of the pixel circuit, the charging signal is at a high level, realizing intra-frame resetting of the pixel circuit.

[0051] According to one embodiment, the pixel circuit 13 includes a PWM generation module 131 coupled to the data driver circuit 12 and the gate driver circuit 11. The module receives at least a display signal from the data driver circuit 12 and a first reference signal output by the logic module, and outputs a PWM signal. According to one embodiment, the PWM generation module 131 may include a comparison unit 1311 configured to compare the display signal with the first reference signal and, based on the comparison result, output a PWM signal to control the light emission of the pixel circuit 12.

[0052] According to one embodiment, the pixel circuit 13 may further include a light-emitting element 136, a first switch module 134, and a second switch module 135. According to one embodiment of the present application, the light-emitting element 136 may include an OLED, an LED, a Micro-LED, a QLED, etc., determined according to actual needs. The first switch module 134 is controlled to be turned on or off based on the PWM signal output by the PWM generation module 131. The second switch module is configured to be turned on or off under the control of the output of the gate drive circuit 11. When the second switch module is turned on, the light-emitting element enters the light-emitting stage.

[0053] According to one embodiment, the pixel circuit 13 may further include a constant current (PAM) module 133 coupled to the light emitting element 136 via a first switch module 134 and a second switch module 135 , configured to provide a constant light emitting current to the light emitting element 136 .

[0054] Figure 1B yes Figure 1A According to one embodiment, the reference signal may be as follows: Figure 1B According to one embodiment, in one frame, the pixel circuit includes a display signal writing phase and a light emitting phase.

[0055] During the display signal writing phase, the row-by-row enable signal EM[i] is at a low level, and the display signal is written into the pixel circuit. The first reference signal output by the logic module is at a low level. At this point, the PWM signal output by the PWM generation module 131 of the pixel circuit 13 is also at a low level. During this phase, when the charge signal CHG is also at a high level, the display signal is written and reset simultaneously into the pixel circuit.

[0056] According to one embodiment, after the pixel circuits in the first row complete the display signal writing operation, the row-by-row enable signal EM[2] of the pixel circuits in the second row is at a low level and begins to enter the display signal writing phase until the first row.

[0057] In the light-emitting phase, the first reference signal output by the logic module is the value of the reference signal VSWEEP. The enable signal EM[i] is high level row by row. The pixel circuit 13 can generate a PWM signal that changes the conduction state of the light-emitting element 136 when the magnitude relationship between the reference signal and the display signal changes. Figure 1B The light emitting phase of the pixel circuits in the first row within one frame shown includes two sub-frames.

[0058] According to one embodiment of the present application, Figure 1BAs shown, the luminous time of the pixel circuits in row 1 within a frame is divided into two subframes sF1 and sF2, and an intra-frame reset sFR, by the reset phase of the reference signal. In subframe sF1, the comparison unit 1311 compares the display signal DATA[j] with the reference signal VSWEEP. When the reference signal VSWEEP is less than the display signal DATA[j], the comparison unit 1311 outputs a high level and controls the first switch module 134 to conduct. Simultaneously, the output of the gate drive circuit 11 controls the second switch module 135 to conduct, causing the light-emitting element 136 to emit light. When the reference signal VSWEEP is greater than the display signal DATA[j], the comparison unit 1311 outputs a low level, controlling the light-emitting element 136 to stop emitting light. After the luminous period of subframe sF1 ends, the reference signal VSWEEP enters the reset phase. At this point, the pixel circuit 13 performs an intra-frame reset sFR under the control of the charging signal CHG. The charging signal CHG resets the comparison unit 1311, causing the comparator to complete the comparison operation between the reference signal and the display signal in the second subframe sF2.

[0059] According to one embodiment, after the pixel circuit completes the intra-frame reset, the charging signal CHG is at a low level, and the reference signal VSWEEP enters the light-emitting phase. The pixel circuit starts the light-emitting phase of the second subframe until the enable EM[i] signal transitions to a low level row by row or the magnitude relationship between the first reference signal and the display signal changes.

[0060] Figure 2A is a circuit diagram of an active display device according to another embodiment of the present application.

[0061] According to one embodiment, an active display device includes a logic module 210 located in a gate driving circuit corresponding to a pixel circuit in a first row, and a pixel circuit 22. The pixel circuit 22 includes a PWM generation module 220, a PAM module 250, a first switch module, a second switch module, and a light-emitting element 260.

[0062] According to one embodiment, the logic module 210 receives the reference signal VSWEEP and the charging signal CHG, the row-by-row enable signal EM[i], and the row-by-row enable signal EMB[i] from the gate driver circuit, and performs logical transformation to generate the row-by-row enable signal EMB*[i], the row-by-row enable signal EM*[i], and the first reference signal VSWEEP*[i]. The row-by-row enable signal EMB[i] may include, for example, a signal obtained by performing an inversion operation on the row-by-row enable signal EM[i]. According to one embodiment, the row-by-row enable signal EMB[i] may be directly from the gate driver circuit, or may be obtained by the logic module 210 receiving the row-by-row enable signal EM[i] from the gate driver circuit and performing a logical inversion operation on it.

[0063] In one embodiment, the logic module 210 includes a logic OR unit 211 configured to perform a logic OR operation on the charging signal CHG and the row-by-row enable signal EMB[i] to generate the row-by-row enable signal EMB*[i].

[0064] According to one embodiment, the logic module 210 may further include a logic AND unit 212 configured to perform a logic AND operation on the signal CHGB obtained by performing a logic inversion operation on the charging signal CHG and the row-by-row enable signal EM[i] to form a row-by-row enable signal EM*[i].

[0065] According to one embodiment, the logic module 210 may further include a data selection unit 213 configured to output the value or low level of the reference signal VSWEEP under the control of the row-by-row enable signal EMB[i] to form a first reference signal VSWEEP*[i]. When the row-by-row enable signal EM[i] is low, the row-by-row enable signal EMB[i] is high, and the first reference signal VSWEEP*[i] is low. Conversely, when the row-by-row enable signal EM[i] is high, the row-by-row enable signal EMB[i] is low, and the value of the first reference signal VSWEEP*[i] is the value of the reference signal VSWEEP. According to one embodiment, the reference signal VSWEEP is a global signal, the row-by-row enable signal EM[i] is a row-by-row signal, and the moment when the pixel circuit in each row receives the high level of the row-by-row enable signal is delayed row by row. The moment when the row-by-row enable signal EM[i] jumps to a high level determines the value of the reference signal VSWEEP received by the logic circuit and the waveform of the first reference signal VSWEEP*[i].

[0066] According to one embodiment, the PWM generation module 220 of the pixel circuit 22 corresponding to the logic module 210 may include a capacitor C221 and a comparison unit. The comparison unit includes a transistor T221 serving as a comparator. The control electrode of transistor T221 is coupled to the first terminal of capacitor C221, and the second terminal is grounded. The second terminal of capacitor C221 receives the first reference signal VSWEEP*[i] from the logic module 210. The control electrode of transistor T223 receives the row-by-row enable signal EMB[i] from the logic module 210, the first electrode of transistor T223 receives the display signal DATA[j], and the second electrode is coupled between the control electrode of transistor T221 and the first terminal of capacitor C221. According to one embodiment, the PWM generation module 220 further includes a transistor T222, the first electrode of which receives the high voltage level VGH, the control electrode of which receives the row-by-row enable signal EMB*[i] from the logic module 210, and the second electrode of transistor T222 coupled to the first electrode of transistor T221 at point B, which serves as the output terminal of the PWM generation module 220.

[0067] According to one embodiment, the pixel circuit 22 further includes a first switching module and a PAM module 250. The first switching module includes a switching transistor 230. The control electrode of the switching transistor 230 is coupled to the output terminal of the PWM generation module 220, the first electrode is coupled to the second terminal of the PAM module 250, and the second electrode is coupled to the first electrode of the transistor 240. The switching transistor 230 is configured to be turned on under the control of the PWM signal. The first terminal of the PAM module 250 receives a high voltage level VGH and is configured to provide a constant light-emitting current to the light-emitting element 260. The pixel circuit 22 further includes a second switching module, which includes a transistor T240. The control electrode of the transistor T240 receives the row-by-row enable signal EM*[i] from the logic module 210, and the second electrode is coupled to the anode of the light-emitting element 260. In one embodiment, the switching transistor 230 and the transistor 240 cooperate to control the light-emitting element 260 to emit light.

[0068] According to one embodiment, some or all transistors in the pixel circuit 22 may include pure N-type thin film transistors (TFTs).

[0069] According to one embodiment, when the row enable signal EM[i] is at a low level, the row enable signal EMB[i] is at a high level and controls the transistor T223 to be turned on. The potential level of the second electrode (node ​​A) of the transistor T223 reaches the value of the display signal DATA[j], and the display signal is written into the pixel circuit.

[0070] According to one embodiment, during the display signal writing phase, when the CHG signal is also at a high level, the row-by-row enable signal EMB*[i] is at a high level, turning on the transistor T222. The potential at point B is at a high level, thereby writing the display signal to the pixel circuit and resetting the pixel circuit simultaneously.

[0071] According to one embodiment, when the row-by-row enable signal EM[i] is high, the pixel circuit enters a light-emitting phase within a frame. The light-emitting period of the pixel circuit within a frame includes the reset period of the reference signal VSWEEP. The reset period of VSWEEP divides the light-emitting period of the pixel circuit within a frame into two or more subframes. In this case, when the charging signal CHG is high, between two adjacent subframes, the row-by-row enable signal EMB*[i] controls the conduction of transistor T222 and sets point B to a high level, achieving an intra-frame reset of the pixel circuit.

[0072] According to one embodiment, when the value of the display signal written to the pixel circuit is lower than the threshold voltage Vth1 of transistor T221, transistor T221 is turned off, and the potential of node B reaches a high level VGH-Vth2, where Vth2 is the threshold voltage of transistor T222. The PWM signal output by node B is high.

[0073] According to one embodiment, when the value of the display signal written to the pixel circuit exceeds the threshold voltage Vth1 of transistor T221, transistor T221 turns on and pulls the potential of node B down to a low level. At this point, the potential at point B is lower than the threshold voltage of switching transistor T230, and switching transistor T230 turns off. After entering the light-emitting phase, transistor T222 turns off, the potential at point B remains low, the PWM signal output by PWM generation module 220 is low, switching transistor T230 turns off, and light-emitting element 260 does not emit light.

[0074] According to one embodiment, during the intra-frame reset, the light emitting element does not emit light. Since the charging time is short, it can be ignored for the light emitting time in one frame.

[0075] Figure 2B yes Figure 2A Schematic diagram of the operating timing of an active display device shown. According to one embodiment of the present application, the pixel circuit 22 includes a display signal writing phase and a light-emitting phase in a frame. According to one embodiment, the light-emitting phase of the pixel circuit includes an intra-frame reset of the pixel circuit. According to one embodiment, the display signal writing phase of the pixel circuit includes resetting the pixel circuit.

[0076] During the display signal writing phase of the pixels in the first row of the pixel array, the corresponding row-by-row enable signal EM[1] received in the logic module 210 is at a low level, and the charging signal CHG is at a high level. The transistor T222 in the pixel circuit 22 is turned on under the control of the high-level row-by-row enable signal EMB*[1], and transmits the high-level VGH to the node B. The transistor T223 in the pixel circuit 22 receives the high-level row-by-row enable signal EMB[1] and turns on, transmitting the display signal DATA[1] to the node A. At this time, the potential VA[1] at point A is the value of the display signal DATA[1]. At this stage, the logic module 210 outputs a low-level first reference signal VSWEEP*[1] which is applied to one end of the capacitor C221. The row-by-row enable signal EM*[1] is at a low level, the transistor T240 is turned off, and the current I flowing through the light-emitting element 260 LED [1, j] is at a low level, and the light-emitting element 260 does not emit light.

[0077] According to one embodiment, after the pixel circuits in the first row complete the display signal writing operation, the row-by-row enable signal EM[2] of the pixel circuits in the second row is at a low level and begins to enter the display signal writing phase until the first row.

[0078] During the light-emitting phase of the pixels in row 1 of the pixel array, the row-by-row enable signal EM[i] received by the corresponding logic module 210 is at a high level, the charging signal CHG is at a low level, and the value of the first reference signal VSWEEP*[i] output by the logic module 210 is the value of the reference signal VSWEEP. The row-by-row enable signal EMB*[i] and the row-by-row enable signal EMB[i] are at a low level, and the transistors T222 and T223 in the pixel circuit in row 1 are turned off. At this time, the potential VA[1] of node A in the pixel circuit in row 1 is DATA[1]+VSWEEP. When the potential VA[1] at point A is lower than the threshold voltage Vth1[1] of transistor T221, transistor T221 is turned off. Under the control of node B, the switching transistor T230 is turned on, and the row-by-row enable signal EM*[i] controls the transistor T240 to turn on, causing the light-emitting element 260 to emit light. As the reference signal VSWEEP gradually increases, when the potential VA[1] at point A exceeds the threshold voltage Vth1[1] of transistor T221, node B is discharged to a low level through the conducting transistor T221. At this time, the switching transistor T230 is turned off, and the light-emitting element 260 stops emitting light.

[0079] According to one embodiment of the present application, in the pixel circuits of the first row, within a frame, the first reference signal VSWEEP*[i] is divided into two parts by the reset phase of the reference signal VSWEEP. Accordingly, the light-emitting time of the frame is divided into two sub-frames. The intra-frame reset phase of the pixel circuits may be included between the two sub-frames.

[0080] According to one embodiment of the present application, during the display signal writing phase for the pixel circuits in row 1, the pixel circuits receive a low-level row-by-row enable signal EM[i]. Transistor T223 in the pixel circuits in row 1 initiates the display signal writing phase for the first frame. At this point, the first reference signal VSWEEP*[i] output by the logic module corresponding to the pixel circuits in row 1 is low, and the potential at point A, VA[i], is the value of the display signal DATA[j].

[0081] According to one embodiment of the present application, after the display signal writing phase is completed, the row-by-row enable signal EM[i] received by the pixel circuit in row I is at a high level. The first reference signal VSWEEP*[i] received by the pixel circuit in row I is the value of the reference signal VSWEEP, and the potential VA[i] of node A in the pixel circuit in row I is DATA[1]+VSWEEP. At this time, the charging signal CHG is at a low level, the pixel circuit 22 enters the light-emitting phase and turns on the light-emitting phase of the first subframe, and the light-emitting element 260 begins to emit light. As VSWEEP gradually increases, when the potential VA[i] at point A is higher than the threshold voltage of transistor T221, transistor T221 is turned on, and the potential at point B is discharged to a low level through transistor T221, the light-emitting element 260 stops emitting light, and the first subframe ends.

[0082] According to one embodiment of the present application, when the reference signal VSWEEP transitions to the reset value of the reset phase, the charging signal CHG transitions to a high level. At this point, the row-by-row enable signal EM[i] remains high, and the row-by-row enable signal EMB*[i] output by the logic module 210 corresponding to the pixel circuit in the first row is high, controlling transistor T222 to conduct, causing the potential of node B to rise to a high level VGH or VGH-Vth2[i], where Vth2[i] is the threshold voltage of transistor T222 in the pixel circuit in the first row, thereby achieving an intra-frame reset of the pixel circuit. During the intra-frame reset, the control electrode potential VA[i] of transistor T221 falls back to the DATA[j] level, the row-by-row enable signal EM*[i] is low, and the light-emitting element 260 does not emit light.

[0083] According to one embodiment, after the intra-frame reset is completed, the charging signal CHG is at a low level, and the transistors T222 and T223 in the pixel circuit are turned off. At this point, the reference signal VSWEEP enters the light-emitting phase again from the reset phase. The first reference signal VSWEEP*[i] received by the pixel circuits in row I then rises. The pixel circuits enter the second sub-frame light-emitting phase. When the row-by-row enable signal EM[i] reaches a low level, the light-emitting elements 260 in the pixel circuits in row I stop emitting light.

[0084] According to one embodiment, any one or two of the logic AND unit, the logic OR unit, and the data selection unit in the logic module 210 may be located in the gate driving circuit, and the other units may be located in the pixel circuit, depending on actual needs.

[0085] Figure 3 FIG. 1 is a schematic diagram of an active display device circuit according to another embodiment of the present application. Figure 3 As shown in FIG, the active display device includes a gate drive circuit 41 and a pixel circuit 42. Figure 3 In the active display device shown, a portion of the logic module is located in the gate driver circuit 41, and another portion is located in the pixel circuit 42. The pixel circuit 42 can receive the charging signal CHG, the row-by-row enable signal EM[i] from the gate driver circuit, and the display signal DATA[j] from the data driver circuit. According to one embodiment, the row-by-row enable signal EMB[i] can be directly generated by the gate driver circuit, or it can be obtained by the pixel circuit 42 receiving the row-by-row enable signal EM[i] from the gate driver circuit and performing a logical inversion operation.

[0086] According to one embodiment, the gate driver circuit 41 includes a logic AND unit 412 and a data selection unit 413, which receive at least a reference signal VSWEEP and a charging signal CHG from the gate driver circuit, as well as a row-by-row enable signal EM[i]. The logic AND unit 412 is configured to perform a logic AND operation on a signal CHGB obtained by, for example, performing a logical inversion operation on the charging signal CHG, and the row-by-row enable signal EM[i] to form the row-by-row enable signal EM*[i]. The data selection unit 413 is configured to select a value of the reference signal VSWEEP or output a low level under the control of the row-by-row enable signal EMB[i] to form the first reference signal VSWEEP*[i].

[0087] According to one embodiment, the pixel circuit 42 includes a PWM generation module 420 , a PAM module 450 , a first switch module, a second switch module, and a light emitting element 460 .

[0088] The PWM generation module 420 includes a logic OR unit 422, which includes transistors T4221 and T4223. The first electrode of transistor T4221 is coupled to the first electrode of transistor T4223 and receives a high voltage level VGH. The control electrode of transistor T4221 receives the charge signal CHG, and the control electrode of transistor T4223 receives the row-by-row enable signal EMB[i], which is the inverted row-by-row enable signal EM[i]. The second electrode of transistor T4221 is coupled to the second electrode of transistor T4223 as the output of the logic OR unit 4221, which is coupled to node B. The logic OR unit 422 is configured to perform a logic OR operation on the charge signal CHG and the row-by-row enable signal EMB[i]. In one embodiment, when the charge signal CHG and / or the row-by-row enable signal EMB[i] are high, the potential at point B is a high voltage level VGH. Point B, as the output of the PWM generation module 220, is coupled to the control electrode of transistor T230.

[0089] In such Figure 3 In the illustrated embodiment, the logic module includes a logic AND unit 412 of the gate drive circuit, a data selection unit 413, and a logic OR unit 422 in the pixel circuit. Each pixel circuit in a row may receive a corresponding first reference signal VSWEEP*[i], a row-by-row enable signal EMB[i], and a row-by-row enable signal EM*[i] from the gate drive circuit 41. Accordingly, the gate drive circuit 41 may include one logic AND unit and one data selection unit, and the pixel circuits in the same row may share the logic AND unit and the data selection unit. According to one embodiment, the pixel circuit 42 may also receive the row-by-row enable signal EM[i] from the gate drive circuit 41, and obtain the row-by-row enable signal EMB[i] by performing an inverted logic operation on the row-by-row enable signal EM[i].

[0090] According to one embodiment, the PWM generation module 420 of the pixel circuit 42 corresponding to the logical AND unit 412 and the data selection unit 413 may include a comparison module, a transistor T423, and a capacitor C421. The comparison module includes a transistor T421 as a comparator, wherein the control electrode of the transistor T421 is coupled between a first terminal of the capacitor C421 and a second terminal of the transistor T423. The second terminal of the capacitor C421 receives the first reference signal VSWEEP*[i] from the data selection unit 413. The control electrode of the transistor T423 receives the row-by-row enable signal EMB[i], and the first electrode thereof receives the display signal DATA[j].

[0091] According to one embodiment, the first switching module in pixel circuit 42 includes a switching transistor T430, and the second switching module includes a transistor T440. According to one embodiment, one terminal of the PAM module 450 receives a high voltage level VGH, and the other terminal is coupled to the first electrode of transistor T430, configured to provide a constant light-emitting current to the light-emitting element. The control electrode of transistor T440 receives the row-by-row enable signal EM*[i] from the logical AND unit 412, and the second electrode of transistor T440 is coupled to the first electrode of the light-emitting element 460.

[0092] According to one embodiment, some or all transistors in the pixel circuit 42 may include pure N-type thin film transistors (TFTs).

[0093] According to one embodiment of the present application, Figure 3 The working sequence of the active display device shown is similar to Figure 2B The pixel circuit operates in a similar timing.

[0094] Figure 4 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Figure 4 The pixel circuit shown includes a logic module, and the gate driver circuit coupled to the pixel circuit can be a conventional driver circuit. The pixel circuit receives a charging signal CHG, a reference signal SWEEP, a row-by-row enable signal EM[i], and / or a row-by-row enable signal EMB[i] from the gate driver circuit. According to one embodiment, the pixel circuit 50 includes a PWM generation module 510, a PAM module 520, a logic AND unit 530, a first switch module, and a light-emitting element 550.

[0095] According to one embodiment, the PWM generation module 510 includes a logic OR unit 5101. The logic OR unit 5101 includes transistors T512 and T513. The first electrode of transistor T512 is coupled to the first electrode of transistor T513 and receives a high voltage level VGH. The control electrode of transistor T512 receives the charging signal CHG, and the control electrode of transistor T513 receives the row-by-row enable signal EMB[i]. The second electrode of transistor T512 is coupled to the second electrode of transistor T513 as the output of the logic OR unit 5101, which is coupled to the output of the PWM generation module (node ​​B). The logic OR unit 5101 is configured to perform a logic OR operation on the charging signal CHG and the row-by-row enable signal EMB[i]. In one embodiment, when the charging signal CHG and / or the row-by-row enable signal EMB[i] are high, the potential at point B is a high voltage level VGH.

[0096] According to one embodiment, the PWM generation module 510 may further include a data selection unit 5102. The data selection unit 5102 includes a transistor T514 and a transistor T515 connected in series. A first electrode of transistor T514 receives a reference signal VSWEEP, a control electrode receives a row-by-row enable signal EM[i], and a second electrode coupled to the first electrode of transistor T515, serving as an output terminal of the data selection unit 5101. A control electrode of transistor T515 receives the row-by-row enable signal EMB[i], and a second electrode is grounded. The data selection unit 5102 is configured to output the value of the reference signal VSWEEP or a low level under the control of the row-by-row enable signal EMB[i], forming a first reference signal VSWEEP*[i]. In one embodiment, when the row-by-row enable signal EM[i] is high, the row-by-row enable signal EMB[i] is low, and the data selection unit 5101 outputs the value of the reference signal VSWEEP. When the row-by-row enable signal EM[i] is low, the row-by-row enable signal EMB[i] is high, and the data selection unit 5101 outputs a low level.

[0097] According to one embodiment, the PWM generation module 510 includes a comparison unit, which includes a transistor T511 serving as a comparator. A first electrode of transistor T511 is coupled to the output terminal of the PWM generation module, a control electrode is coupled between the first terminal of capacitor C51 and the second terminal of transistor T516, and a second electrode is grounded. A second terminal of capacitor C51 is coupled to the output terminal of the data selection unit 5102. The control electrode of transistor T516 receives the row-by-row enable signal EMB[i], and a first electrode receives the display signal DATA[j].

[0098] According to one embodiment, the first switch module of the pixel circuit 50 includes a switch transistor T540 , whose control electrode is coupled to the output of the PWM generation module 510 , a first electrode is coupled to the output of the PAM module 520 , and a second electrode is coupled to the input of the logic AND unit 530 .

[0099] According to one embodiment, the pixel circuit 50 further includes a PAM module 520. The PAM module 520 may include a transistor T527. The first electrode of transistor T527 receives a high voltage level VGH, the control electrode is coupled between the second electrode of transistor T528 and the first end of capacitor C522 (point C), and the second electrode, serving as the output of the PAM module 520, is coupled to the first electrode of transistor T540. The first electrode of transistor T528 receives a constant current display signal DATAPAM, and the control electrode receives a row-by-row enable signal EMB[i]. The second end of capacitor C522 is grounded. The constant current display signal DATAPAM received by transistor T528 can adjust the control electrode voltage of transistor T527, thereby varying the magnitude of the light-emitting current ILED[i,j] flowing through the light-emitting elements 550 in different rows to meet device usage requirements. The light-emitting current ILED[i,j] of the light-emitting elements 550 can vary in different columns and be the same within the same column. According to embodiments of the present application, transistors T527 and T528 may be pure N-type transistors.

[0100] According to one embodiment, the pixel circuit 50 further includes a logic AND unit 530. The logic AND unit 530 includes a transistor T531, whose first electrode, serving as an input of the logic AND unit 530, is coupled to the second electrode of the switch transistor T540. Its control electrode receives the signal CHGB, which is the inverted version of the charge signal CHG. Its second electrode is coupled to the first electrode of a transistor T532. The control electrode of transistor T532 receives the row-by-row enable signal EM[i]. Its second electrode, serving as an output of the logic AND unit 530, is coupled to the anode of the light-emitting element 550. The logic AND unit 530 is configured to perform a logic AND operation on the signal CHGB, obtained by performing a logical inversion operation on the charge signal CHG, for example, and the row-by-row enable signal EM[i]. In one embodiment, when the charge signal CHG is low and the row-by-row enable signal EM[i] is high, transistors T531 and T532 are turned on. In this case, when the switch transistor T540 and transistor T527 are also turned on, the light-emitting element 550 emits light.

[0101] In such Figure 4 In the illustrated embodiment, the logic module includes a logic AND unit 530 of the gate driving circuit, a data selection unit 5102 and a logic OR unit 5101 in the pixel circuit.

[0102] According to an embodiment of the present application, some or all transistors in the pixel circuit 50 may include pure N-type thin film transistors (TFTs).

[0103] According to one embodiment of the present application, Figure 4 The working timing of the pixel circuit shown is similar to Figure 2B The pixel circuit has a similar working sequence, wherein the constant current display signal DATAPAM in the PAM module 520 regulates the magnitude of the light-emitting current ILED[i,j] flowing through the light-emitting element 550 without affecting the working sequence of the pixel circuit.

[0104] Figure 5A FIG. 1 is a schematic diagram of an active display device circuit according to another embodiment of the present application. Figure 5A As shown, the active display device includes a gate driving circuit 60 and a pixel circuit 61. The logic module of the active display device includes a logic AND unit 601 and a data selection unit 602. The logic module is located in the gate driving circuit 60.

[0105] According to one embodiment, the logic module receives a reference signal VSWEEP and a charging signal CHG from a gate driver circuit, as well as a row-by-row enable signal EM[i]. A logic AND unit 601 is configured to perform a logic AND operation on a signal CHGB obtained by, for example, performing a logical inversion operation on the charging signal CHG, and the row-by-row enable signal EM[i] to form a row-by-row enable signal EM*[i]. The data selection unit 602 is configured to output the value of the reference signal VSWEEP or a low level under the control of the row-by-row enable signal EMB[i] to form a first reference signal VSWEEP*[i].

[0106] like Figure 5A As shown, the pixel circuit 61 may include a PWM signal generating module 610, a constant current module 620, a light emitting element 640, and a first switch module coupled to the PWM signal generating module 610. The PWM generating module 610 may include a comparing unit 6111.

[0107] According to one embodiment of the present application, the PWM signal generating module 610 may include a transistor T613 and a comparison unit 6111. Figure 5AAs shown, the comparison unit 6111 may include transistors T61 and T62 of opposite types connected in series to form an inverter. Transistors T62 and T613 are N-type transistors, and T61 is a P-type transistor. The control electrode of transistor T61 is coupled to the control electrode of transistor T62, the second electrode of transistor T61 receives the high level VGH, the first electrode of transistor T61 is coupled to the first electrode of transistor T62 and serves as the output end of the PWM generation module 610. The second electrode of transistor T62 is grounded. For the pixel in the i-th row and j-th column, the first electrode of transistor T613 receives the display signal DATA[j] corresponding to the pixel, and the second electrode thereof is coupled to the control electrodes of transistors T61 and T62, and the control electrode thereof is configured to receive the scan signal SCAN of the row where the pixel is located. PWM [i].

[0108] In one embodiment, the scan signal SCAN PWM [i] may be a row-by-row signal from the gate drive circuit 60 or a row-by-row enable signal EMB[i].

[0109] According to one embodiment of the present application, the PWM generation module 610 may further include a capacitor C612, a first end of which receives the first reference signal VSWEEP*[i], a second end of which is coupled to the second electrode of the transistor T613 at point A, i.e., the input end of the comparison unit 6111, and is coupled to the control electrodes of the transistors T61 and T62.

[0110] According to one embodiment of the present application, the PAM module 620 may include a transistor T621 and a current bias unit 622. The control electrode of the transistor T621 receives a row-by-row enable signal EM*[i]. The second electrode is coupled to the first electrode of the switching transistor T630 to control the conduction of the light-emitting element 640. The first electrode of the transistor T621 is coupled to the current bias unit 622, which receives a high voltage level VGH, to provide a light-emitting current to the light-emitting element 640.

[0111] According to one embodiment of the present application, the first switching module of the pixel circuit 61 includes a switching transistor T630, whose control electrode is coupled to the output terminal of the PWM generation module 610, that is, the coupling point with the first electrode of the transistor T61 and the first electrode of the transistor T62, and receives the PWM signal output by the PWM generation module 610. The first electrode is coupled to the second electrode of the transistor T621, and the second electrode is coupled to the anode of the light-emitting element 640. According to an embodiment of the present application, the transistor T621 and the switching transistor T630 may be N-type transistors.

[0112] According to an embodiment of the present application, the transistors T61 , T62 , T613 , T621 , and T630 may be made of thin film transistors (TFTs), for example, low temperature polycrystalline oxide thin film transistors (LTPO TFTs).

[0113] Figure 5B yes Figure 5A Figure 1 shows a schematic diagram of the operating timing of an active display device. According to one embodiment of the present application, the pixel circuit 61 in the i-th row and j-th column includes a display signal writing phase and a light-emitting phase in a frame. The light-emitting phase of a frame can include at least two subframes, and the sum of the light-emitting times of each subframe corresponds to the light-emitting time corresponding to the display signal.

[0114] In the display signal writing phase, the enable signal EM[i] is low level row by row. Figure 5A and 5B As shown, the transistor T613 receives the high level scan signal SCAN of the first row. PWM [i] and turns on, transmitting the display signal DATA[j] to the input terminal A of the comparison unit 6111. At this time, the potential VA[i] at point A is DATA[j] and is lower than the threshold voltage Vth3[i] of the transistor T62. The transistor T61 is turned on. At this time, the row-by-row enable signal EM*[i] output by the logical OR module is at a low level, and the transistor T621 is turned off. The first reference signal VSWEEP*[i] output by the data selection unit 602 applied to the capacitor C612 is at a low level.

[0115] During the light-emitting phase, the row-by-row enable signal EM[i] is always high. The first reference signal VSWEEP*[i] output by the data selection unit is the value of the reference signal VSWEEP. When the charging signal CHG is also low, the row-by-row enable signal EM*[i] output by the logical OR module is high, turning on transistor T621. The first reference signal VSWEEP*[i] output by the data selection unit 602 is the value of the reference signal VSWEEP. At this time, the reference signal VSWEEP is provided at the first end of capacitor C612, and the potential VA at the second end of capacitor C612 is correspondingly changed to VA[i] = VSWEEP + DATA[j], which serves as the input of the comparison unit 6111. When the potential VA[i] at point A is less than the threshold voltage Vth3[i] of transistor T62, it means that the value of the display signal DATA[j] is less than the value of the reference signal VSWEEP. At this time, T62 is turned off, T61 is turned on, and the high voltage VGH is transmitted to the switching transistor T630 through the turned-on transistor T61, turning on the switching transistor T630. At this time, the transistor T621 is also turned on, and the light-emitting element 640 can receive the constant light-emitting current ILED[i,j] from the current bias unit 621 and start to emit light.

[0116] According to one embodiment, the first reference signal VSEWEEP*[i] gradually rises along with the reference signal VSWEEP. When VA[i] is greater than the threshold voltage of T62, T62 is turned on and T61 is turned off. The PWM generation module 610 outputs a low level to the switching transistor T630, the switching transistor T630 is turned off, the light-emitting element 640 stops emitting light, and the first subframe light emission ends.

[0117] According to one embodiment, during the light-emitting phase, when the reference signal VSWEEP jumps to the reset value, the first reference signal VSWEEP*[i] also jumps to the reset value of VSWEEP. At this time, the charging signal CHG is high, the row-by-row enable signal EM*[i] is low, transistor T621 is turned off, and the light-emitting element stops emitting light. The potential VA[i] at point A reaches the DATA[j] level and is less than the threshold voltage of transistor T62. T61 turns on, and the high voltage VGH is transmitted to the switching transistor T630 again through the turned-on switching transistor T630, turning on transistor T630. This achieves an intra-frame reset in the pixel circuit.

[0118] According to one embodiment, when the reference signal VSWEEP returns from the reset phase to the reference signal light-emitting phase, the first reference signal VSWEEP*[i] also rises. CHG transitions to a low level, the row-by-row enable signal EM*[i] transitions to a high level, transistor T621 turns on, and the light-emitting element 640 begins emitting light in the second subframe until the row-by-row enable signal EM[i] transitions to a low level. At this point, transistor T621 turns off, causing the light-emitting element 640 to stop emitting light, thus ending the second subframe.

[0119] Figure 6 FIG is a schematic diagram of the structure of an active display device according to another embodiment of the present application. Figure 6 As shown, the active display device includes a gate driving circuit 70 and a pixel circuit 71. The logic module of the active display device includes a logic AND unit 701 and a data selection unit 702, and the logic module is located in the gate driving circuit 70. Figure 6 As shown, the pixel circuit 71 may include a PWM generation module 710 , a PAM module 720 , a light emitting element 740 , and a switching transistor T730 .

[0120] According to one embodiment, the logic module receives a reference signal VSWEEP and a charging signal CHG from a gate driver circuit, as well as a row-by-row enable signal EM[i]. A logic AND unit 701 is configured to perform a logic AND operation on a signal CHGB obtained by, for example, performing a logical inversion operation on the charging signal CHG, and the row-by-row enable signal EM[i] to form a row-by-row enable signal EM*[i]. The data selection unit 702 is configured to output the value of the reference signal VSWEEP or a low level under the control of the row-by-row enable signal EMB[i] to form a first reference signal VSWEEP*[i].

[0121] The PWM generation module 710 may include a comparison unit 7111 and T712, as well as a bias current source Ibias. The comparison unit 7111 may include a dual-input operational amplifier circuit formed by transistors T71, T72, T73, T74, T75, and T76, for comparing a display signal with a reference signal. According to one embodiment of the present application, transistors T71 and T72 may be P-type transistors, while T73, T74, T75, T76, and T712 may be N-type transistors. The PWM generation module 710 may also include a capacitor C713.

[0122] like Figure 6 As shown, the control electrode of transistor T71 is coupled to the control electrode of T72 and the first electrode of T71, and the second electrode is coupled to the second electrode of transistor T72 to receive the high level VGH. The first electrode of transistor T72 is coupled to the first electrode of transistor T74 and the control electrode of transistor T730 at point B, which is the output end of the PWM generation module 710. The second electrode of transistor T74 is coupled to the second electrode of transistor T73, and the control electrode is coupled to the first electrode of transistor T712. The first electrode of transistor T73 is coupled to the first electrode of transistor T71, and the control electrode receives the first reference signal VSWEEP*[i]. The first electrode of transistor T712 receives the display signal DATA[j], and the control electrode receives the scan signal SCAN PWM [i], the second electrode is coupled to the first end of the capacitor C713. The second end of the capacitor C713 is grounded.

[0123] According to one embodiment, the control electrode of transistor T75 is coupled to its first electrode and the control electrode of transistor T76, and the second electrode is coupled to the second electrode of transistor T76 and grounded. The second electrode of transistor T75 is coupled to the second electrode of transistor T76 to form a current mirror. The first electrode of transistor T75 is also coupled to a bias current source Ibias to provide a bias current to transistor T76, thereby maintaining normal operation of comparison unit 7111.

[0124] According to one embodiment of the present application, the bias current source I bias It may be located outside the pixel circuit 70 .

[0125] According to one embodiment, the PAM module 720 may include a transistor T721 and a current bias unit. The control electrode of transistor T721 receives a row-by-row enable signal EM*[i]. The second electrode of transistor T721 is coupled to the first electrode of switching transistor T730 to control the conduction state of light-emitting element 740. The first electrode of transistor T721 is coupled to the current bias unit to receive a constant current signal to provide a light-emitting current to light-emitting element 740.

[0126] According to one embodiment of the present application, the pixel circuit 70 may further include a switching transistor T730, whose control electrode is coupled to the output terminal of the PWM generation module 710 and receives the PWM signal output by the PWM generation module 710. The first electrode of the switching transistor T730 is coupled to the second electrode of the transistor T721, and the second electrode is coupled to the anode of the light-emitting element 740. According to an embodiment of the present application, the transistors T721 and T730 may be N-type transistors.

[0127] According to one embodiment of the present application, Figure 6 The working sequence of the active display device shown is similar to Figure 5B The pixel circuit operates in a similar timing.

[0128] Figure 7 FIG. 1 is a schematic diagram of a display device structure according to an embodiment of the present application. Figure 7 As shown, the display device includes a timing control circuit, a gate driving circuit, a data driving circuit, and a display pixel array with I rows and J columns. The gate driving circuit and the pixel circuit include any of the logic circuits described above.

[0129] According to an embodiment of the present application, the timing control circuit receives external display data and control signals, and transmits the display data to the data driver circuit and the charging signal to the gate driver circuit. According to one embodiment of the present application, pixel circuits in the same column of the pixel array receive their respective display signals from the data driver circuit.

[0130] Compared to existing synchronous PWM drive methods, the pulse width modulation drive method and active display device proposed in this application can increase the light-emitting time to approximately the entire frame. For example, under driving conditions of 120Hz FHD (full high definition, 1080 lines) and a 5µs threshold voltage write or extract time for each line of display signal, the total light-emitting time within a frame of the progressive PWM drive mode is: The total lighting time within one frame of the synchronous lighting mode PWM driving mode is: Wherein, Tem is the luminescence time of the pixel circuit within one frame. Tscan is the display signal writing or threshold compensation time. T is the duration of one frame, including the display signal writing phase and the luminescence phase. f is the refresh frame rate of the display device.

[0131] From the above calculations, it can be seen that the row-by-row PWM driving method significantly increases the luminous time of the entire frame, effectively improving the performance of the active display device.

[0132] The present application also provides a pulse width modulation driving method, which may include the following operations.

[0133] A reference signal is received. The reference signal is a global signal and includes a reset phase and a light-emitting phase. The reset phase lasts for a fixed time, and during each reset phase, the reference signal has a reset value. The value of the reference signal during the light-emitting phase varies over time. The reset phase of the reference signal lasts for a fixed time, including the display signal writing time or the threshold compensation time. The maximum light-emitting time of the pixel circuit within a frame corresponds to one reset phase of the reference signal and one complete light-emitting phase, either continuous or discontinuous but obtained through splicing.

[0134] A display signal is received, which includes a voltage corresponding to a value of display data.

[0135] The display signal is written into the pixel circuit during a display signal writing phase of one frame.

[0136] A light-emitting element in a pixel circuit is driven to emit light based on a display signal. During the light-emitting phase of the light-emitting element, the display signal is compared with a reference signal. When the relative relationship between the display signal and the reference signal changes, the light-emitting state of the light-emitting element changes. The light-emitting time of the light-emitting element is divided into at least two subframes by the reset phase of the reference signal. The display signal is compared with the reference signal in each subframe. The sum of the light-emitting times of the subframes is equal to the light-emitting time corresponding to the display signal in a frame. The light-emitting time of each subframe of the light-emitting element is less than or equal to the longest light-emitting time in a frame.

[0137] The active display device and pulse-width modulation driving method disclosed in this application enable each pixel to emit light immediately after the PWM and PAM display signals for its row are written. The total light-emitting time is equal to the frame time minus the writing time for a row, making the total light-emitting time within a frame approximately equal to the frame time. This significantly increases the light-emitting time of the Micro-LED, improves the brightness and contrast of the active display device, and enhances the accuracy of grayscale control, thereby achieving optimal performance for active displays represented by Micro-LEDs. The display array shares a reference level signal generated by a single external device, eliminating the need for row-by-row transmission, significantly reducing the complexity of the external circuitry.

[0138] Specifically targeting oxide TFT backplanes and large-scale Micro-LED display applications, this application offers advantages such as low cost, suitability for large-area backplane fabrication, and comprehensive applicability to large, medium, and small displays. Furthermore, it effectively addresses limitations of oxide TFTs in mobility and electrical stability, enabling high-precision grayscale control and high-resolution Micro-LED display driving, even with oxide TFTs.

[0139] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. An active display device comprising: a gate drive circuit configured to receive at least a global signal and generate a first row-by-row enable signal; A data driving circuit receives display data and converts it into an analog display signal; a logic module configured to receive at least a global signal and a first row-by-row enable signal and perform different logical transformations, so that after each row of pixels is written with an analog display signal, one or more light-emitting operations are performed, and the total light-emitting time within a frame corresponds to the corresponding display signal; wherein the global signal includes a reference signal and a charging signal; the reference signal includes a reset portion and a comparison portion, wherein the value of the reference signal in the reset portion remains unchanged, and the value of the reference signal in the comparison portion varies from its minimum value to its maximum value; and the reset portion of the reference signal lasts for a fixed time; The charging signal is valid during the reset portion of the reference signal; When the first row-by-row enable signal is valid, it corresponds to a reset portion and a continuous or discontinuous but complete comparison portion of the reference signal; and The pixel array includes a pixel circuit and performs a light emitting operation based on at least the analog display signal and the control of the output of the logic module.

2. The active display device according to claim 1, wherein Logic modules include a logic AND unit configured to perform a logic AND operation on the transformed charging signal and the first row-by-row enable signal; as well as The data selection unit is configured to select the value or low level of the reference signal as the first reference signal under the control of the first row-by-row enable signal or a variation thereof.

3. The active display device according to claim 2, wherein: Logic modules include A logic OR unit is configured to perform a logic OR operation on the charging signal and the variation of the first row-by-row enable signal.

4. The active display device according to claim 3, wherein the logic module is located in the gate driving circuit or the pixel circuit of the pixel array; or A portion of the logic module is located in the gate driving circuit, and another portion is located in the pixel circuit.

5. The active display device according to claim 3, wherein: The pixel circuit includes the light-emitting element; a PWM generation module configured to receive at least the first reference signal and display data, and output a PWM signal; a constant current module, configured to provide a light-emitting current to the light-emitting element; A switch module is coupled between the constant current module and the light-emitting element, and is configured to control the on or off state of the switch module using the PWM signal generated by the PWM signal generating module.

6. The active display device according to claim 5, wherein: The PWM generation module of the pixel circuit includes a first transistor (T223, T423, or T516) and a first capacitor (C221, C421, or C51); a control electrode of the first transistor (T223, T423, or T516) receives a variation of the first row-by-row enable signal; a first electrode of the first transistor (T223, T423, or T516) receives display data from a data driving circuit; a second electrode of the first transistor (T223, T423, or T516) is coupled to a first end of the first capacitor; and a second end of the first capacitor receives the first reference signal; a second transistor (T221, T421, or T511), wherein a control electrode of the second transistor (T221, T421, or T511) is coupled between the second electrode of the first transistor (T223, T423, or T516) and the first end of the first capacitor (C221, C421, or C51), a first electrode is coupled to the output end of the PWM generation module, and a second electrode is grounded; and The switch module includes a third transistor (T230, T430 or T540), a control electrode of which is coupled to the output end of the PWM generation module, and a first electrode of which is coupled to the constant current module.

7. The active display device according to claim 6, wherein: The PWM generation module of the pixel circuit further comprises a fourth transistor (T222); the control electrode of the fourth transistor (T222) receives the output of the logic OR unit, the first electrode receives a high level, and the second electrode is coupled to the output end of the PWM generation module.

8. The active display device according to claim 6, wherein: The logic OR unit includes a fifth transistor (T4221 or T512) and a sixth transistor (T4223 or T513); a first electrode of the fifth transistor (T4221 or T512) is coupled to a first electrode of the sixth transistor (T4223 or T513) and receives a high level, a control electrode of the fifth transistor (T4221 or T512) receives the charging signal, and a control electrode of the sixth transistor (T4223 or T513) receives the first row-by-row enable signal; a second electrode of the fifth transistor (T4221 or T512) is coupled to a second electrode of the sixth transistor (T4223 or T513) and coupled to an output end of the PWM generation module 220 as an output end of the logic OR unit.

9. The active display device according to claim 7 or 8, wherein: The PWM generation module of the pixel circuit also includes a seventh transistor (T240 or T440); the control electrode of the seventh transistor (T240 or T440) receives the output of the logic AND unit, the first electrode is coupled to the second electrode of the third transistor (T230, T430), and the second electrode is coupled to the light-emitting element.

10. The active display device according to claim 8, wherein: The logic AND unit includes an eighth transistor (T531) and a ninth transistor (T532) connected in series; the first electrode of the eighth transistor (T531) is coupled to the second electrode of the third transistor (T540) as the input end of the logic AND unit, the control electrode receives the deformation of the charging signal, and the second electrode is coupled to the first electrode of the ninth transistor (T532); the control electrode of the ninth transistor (T532) receives the first row-by-row enable signal output by the gate drive circuit, and the second electrode serves as the output end of the logic AND unit and is coupled to the light-emitting element.

11. The active display device according to claim 10, wherein: The data selection unit includes a tenth transistor (T514) and an eleventh transistor (T515); a first electrode of the tenth transistor (T514) receives a reference signal, a control electrode receives the first row-by-row enable signal, a second electrode is coupled to the first electrode of the eleventh transistor (T515) and serves as an output end of the data selection unit; a control electrode of the eleventh transistor (T515) receives a variation of the first row-by-row enable signal, and a second electrode is grounded.

12. The active display device according to claim 11, wherein: The constant current module includes a twelfth transistor (T527) and a second capacitor (C522); a control electrode of the twelfth transistor (T527) is coupled to a first end of the second capacitor (C522), the first electrode receives a high level, and the second electrode is coupled to a first electrode of a third transistor (T540); the first end of the second capacitor (C522) is grounded; and, The thirteenth transistor (T528) has a control electrode receiving a variation of the first row-by-row enable signal, a first electrode receiving constant current data, and a second electrode coupled between the control electrode of the twelfth transistor (T527) and the first end of the second capacitor (C522).

13. The active display device according to claim 2, wherein: The pixel circuit includes the light-emitting element; a PWM generation module configured to receive at least the first reference signal and display data, and output a PWM signal; a constant current module, configured to provide a light-emitting current to the light-emitting element; A switch module is coupled between the constant current module and the light-emitting element, and is configured to control the on or off state of the switch module using the PWM signal generated by the PWM signal generating module.

14. The active display device according to claim 13, wherein: The PWM generation module in the pixel circuit includes a fourteenth transistor (T61) and a fifteenth transistor (T62), wherein the control electrode of the fourteenth transistor (T61) is coupled with the control electrode of the fifteenth transistor (T62), the second electrode of the fourteenth transistor (T61) receives a high level, the first electrode of the fourteenth transistor (T61) is coupled with the first electrode of the fifteenth transistor (T62) and serves as an output end of the PWM generation module; the second electrode of the fifteenth transistor (T62) is grounded; wherein the fourteenth transistor (T61) and the fifteenth transistor (T62) are of opposite types; and a sixteenth transistor (T613), wherein a first electrode of the sixteenth transistor (T613) receives the display signal, a second electrode of the sixteenth transistor (T613) is coupled to the control electrodes of the fourteenth transistor (T61) and the fifteenth transistor (T62), and a control electrode of the sixteenth transistor (T613) receives a scan signal; A third capacitor (C612) has a first end receiving the first reference signal and a second end coupled to the second electrode of the sixteenth transistor (T613).

15. The active display device according to claim 13, wherein: The PWM generation module in the pixel circuit includes a sixteenth transistor (T71) and a seventeenth transistor (T72); the control electrode of the sixteenth transistor (T71) is coupled to the control electrode of the seventeenth transistor (T72) and the first electrode of the sixteenth transistor (T71), and the second electrode is coupled to the second electrode of the seventeenth transistor (T72) and receives a high level; the first electrode of the seventeenth transistor (T72) is coupled to the first electrode of the eighteenth transistor (T74) as the output end of the PWM generation module; the second electrode of the eighteenth transistor (T74) is coupled to the second electrode of the nineteenth transistor (T73), and the control electrode is coupled to the first electrode of the twentieth transistor (T712); the first electrode of the nineteenth transistor (T73) is coupled to the first electrode of the sixteenth transistor (T71), and the control electrode thereof receives the first reference signal; the first electrode of the twentieth transistor (T712) receives a display signal, the control electrode receives the scan signal, the second electrode is coupled to the first end of a fourth capacitor (C713), and the second end of the fourth capacitor (C713) is grounded; and A twenty-first transistor (T75) and a twenty-second transistor (T76); the control electrode of the twenty-first transistor (T75) is coupled to its first electrode and the control electrode of the twenty-second transistor (T76), the second electrode of the twenty-first transistor (T75) is coupled to the second electrode of the twenty-second transistor (T76) and is grounded, the second electrode of the twenty-first transistor (T75) is coupled to the second electrode of the twenty-second transistor (T76); the first electrode of the twenty-first transistor (T75) is coupled to a bias current source.

16. The active display device according to claim 14 or 15, wherein: The constant current module of the pixel circuit includes a twenty-third transistor (T621 or T721) and a current bias unit, wherein a first electrode of the twenty-third transistor (T621 or T721) receives a high level through the current bias unit, a control electrode thereof receives an output of the logic AND unit, and a second electrode thereof is coupled to the switch module; and The switch module includes a twenty-fourth transistor (T630 or T730), a first electrode of the twenty-fourth transistor (T630 or T730) is coupled to the second electrode of the twenty-third transistor (T621 or T721), a control electrode of the twenty-fourth transistor (T630 or T730) is coupled to the output end of the PWM generation module, and a second electrode is coupled to the light-emitting element.

17. An electronic device comprising a Micro-LED display pixel array, a timing control circuit, a gate drive circuit, and a data drive circuit, wherein the electronic device comprises any active display device according to claims 1-16.

18. A pulse width modulation driving method, comprising: receiving a reference signal; The global signal includes a reference signal and a charging signal; The reference signal includes a reset part and a comparison part, wherein the value of the reference signal in the reset part remains unchanged, and the value of the reference signal in the comparison part changes from its minimum value to its maximum value; The reset phase of the reference signal lasts for a fixed time; the luminous time within a frame corresponds to at least one reset portion of the reference signal and a complete comparison portion that is continuous or obtained by splicing; receiving a display signal, wherein the display signal includes a voltage corresponding to a value of the display signal; Writing the display signal into the pixel circuit during a display signal writing phase of a frame; as well as The light-emitting element in the pixel circuit is driven to emit light based on the display signal.

19. The driving method according to claim 18, further comprising: A display signal is compared with a reference signal in each subframe, and when a relative relationship between the display signal and the reference signal changes, the light emitting state of the light emitting element changes.

20. The driving method according to claim 19, wherein: The luminous time of the luminous element in one frame includes at least two subframes. The luminous time of the luminous element in each subframe is less than or equal to the longest luminous time of one frame. The sum of the luminous times of each subframe is equal to the longest luminous time of one frame.

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