Display driving circuit and display device

Abstract

The invention discloses a display driving circuit and a display device. The display driving circuit comprises a scanning control module and an output module, the scanning control module comprises a forward control unit, a reverse control unit and a first control node which are symmetrically arranged; wherein the forward control unit comprises a first transistor and a first leakage protection module, and the reverse control unit comprises a second transistor and a second leakage protection module; the forward control unit and the reverse control unit are used for enabling the scanning control module to realize a forward and reverse scanning function according to signals input into the control ends of the transistors, and outputting a first control signal to the output module through a first control node; and the output module is used for performing pull-up control and / or pull-down control according to the first control signal so as to output a driving signal. Therefore, according to the technical scheme, the display driving circuit is optimized, electric leakage can be avoided or electric leakage current can be reduced, and therefore the output stability of the driving signal is ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit and a display device. Background Art

[0002] After the existing GOA circuit has been operating for a long time, the threshold voltage of the thin film transistor may drift and easily cause leakage, which in turn causes the GOA circuit to malfunction. Figure 1 This is a schematic diagram of the structure of the pull-up control circuit in the existing display drive circuit. Figure 1 During the pull-up and bootstrap phases of the GOA circuit, when the scan control node Qn' in each display driver circuit is at a high potential, several leakage paths may exist. For example, in the forward scan mode, the leakage paths are thin-film transistors t2 and t12; in the reverse scan mode, the leakage paths are thin-film transistors t1 and the sixth thin-film transistor t12. This causes the potential of the scan control node Qn' to decrease during the pull-up phase, resulting in insufficient turn-on of the thin-film transistors in the output circuit controlled by the signal output from the scan control node Qn'. This increases the time required for the voltage at the signal output terminal of the output circuit to change (for example, the voltage drops from 90% to 10%), potentially leading to mischarging or insufficient charging, which seriously affects the output stability of the gate drive signal. Therefore, how to optimize the display driver circuit to avoid leakage or reduce leakage current is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0003] The purpose of the present application is to provide a display driving circuit and a display device, which can optimize the display driving circuit to avoid leakage or reduce leakage current.

[0004] An embodiment of the present application provides a display driving circuit, comprising: a scanning control module and an output module; the scanning control module comprises a symmetrically arranged forward control unit, a reverse control unit, and a first control node; wherein the forward control unit comprises a first transistor and a first leakage protection module, the first path end of the first transistor being used to receive a forward scanning voltage, the second path end of the first transistor being connected to the first control node, and the first leakage protection module being connected to the first path end and / or the first control node of the first transistor; wherein the reverse control unit comprises a second transistor and a second leakage protection module, the first path end of the second transistor being used to receive a reverse scanning voltage, the second path end of the second transistor being connected to the first control node, and the second leakage protection module being connected to the first path end and / or the first control node of the second transistor; the forward control unit and the reverse control unit being used to enable the scanning control module to implement forward and reverse scanning functions according to signals input to the control ends of each transistor, and to output a first control signal to the output module through the first control node; the output module being used to perform pull-up control and / or pull-down control according to the first control signal to output a driving signal.

[0005] In one embodiment, the output module includes a level maintaining unit; the level maintaining unit includes an inverter and a second control node; the inverter is used to perform level maintenance control according to the first control signal in the non-display stage to output the second control signal through the second control node, so that the driving signal output by the output module is maintained in a low level state or a high level state; and / or, the output module includes a first level control unit; the first level control unit is used to perform one of pull-up control and pull-down control according to the second control signal output by the level maintaining unit, so that the output module outputs a driving signal representing one of a low level and a high level; and / or, the output module includes a stage transmission unit; the stage transmission unit includes a third transistor, the control end of the third transistor is connected to the first control node to receive the first control signal, the first path end of the third transistor receives the first clock control signal, and the second path end of the third transistor outputs the stage transmission signal.

[0006] In one embodiment, an output module includes at least two first-level control units; the output module also includes a second-level control unit, a first output node, a third-level control unit, a second output node, and an isolation unit; the isolation unit is used to isolate control signals of the second-level control unit and the third-level control unit; when one of the at least two first-level control units is used to perform one of pull-up control and pull-down control, it outputs a first drive signal representing one of a low level and a high level to the first output node; when the second-level control unit is used to perform the other of the pull-up control and pull-down control, it outputs a first drive signal representing the other of the low level and the high level to the first output node; when the other of the at least two first-level control units is used to perform one of the pull-up control and pull-down control, it outputs a second drive signal representing the other of the low level and the high level to the second output node; when the third-level control unit is used to perform the other of the pull-up control and pull-down control, it outputs a second drive signal representing the other of the low level and the high level to the second output node; wherein the first drive signal and the second drive signal are respectively used to drive two adjacent levels of horizontal scan lines in a display panel.

[0007] In one embodiment, the output module further includes a fourth level control unit connected to the first control node and the second control node, and configured to adjust the level of the first control signal outputted by the first control node according to the second control signal outputted by the level maintaining unit.

[0008] In one embodiment, the first leakage protection module includes a fourth transistor and a fifth transistor, the control terminal of the fourth transistor receives a second clock control signal, and the first channel terminal of the first transistor receives a forward scanning voltage through a channel formed with the fourth transistor, the control terminal of the fifth transistor is connected to the first control node, the first channel terminal of the fifth transistor receives a first reference voltage, and the second channel terminal of the fifth transistor is connected to the channel between the first transistor and the fourth transistor; and / or, the second leakage protection module includes a sixth transistor and a seventh transistor, the control terminal of the sixth transistor receives the second clock control signal, and the first channel terminal of the second transistor receives a reverse scanning voltage through a channel formed with the sixth transistor, the control terminal of the seventh transistor is connected to the first control node, the first channel terminal of the seventh transistor receives the first reference voltage, and the second channel terminal of the seventh transistor is connected to the channel between the second transistor and the sixth transistor; and / or, the inverter includes a single-stage inverter and a source follower cascaded therewith, and the level maintaining unit further includes a second control control node; wherein, the single-stage inverter includes an eighth transistor and a ninth transistor, the control terminal of the eighth transistor receives the first reference voltage or is connected to the first control node, the first channel terminal of the eighth transistor receives the first reference voltage, the second channel terminal of the eighth transistor is connected to the first channel terminal of the ninth transistor, the second channel terminal of the ninth transistor receives the second reference voltage, and the control terminal of the ninth transistor is connected to the first control node; wherein, the source follower includes a tenth transistor and an eleventh transistor, the control terminal of the tenth transistor is connected to the second channel terminal of the eighth transistor, the first channel terminal of the tenth transistor receives the first reference voltage, the second channel terminal of the tenth transistor is connected to the second control node, the control terminal of the eleventh transistor is connected to the first control node, the first channel terminal of the eleventh transistor is connected to the second control node, and the second channel terminal of the eleventh transistor receives the second reference voltage; wherein, the first reference voltage is one of a reference high voltage and a reference low voltage, and the second reference voltage is the other of the reference high voltage and the reference low voltage.

[0009] In one embodiment, the fourth level control unit includes a twelfth transistor and a third leakage protection module; the control end of the twelfth transistor is connected to the second control node of the level maintaining unit to receive the second control signal, the first path end of the twelfth transistor is connected to the first control node, and the second path end of the twelfth transistor is used to receive a second reference voltage; the third leakage protection module includes a thirteenth transistor and a fourteenth transistor, the control end of the thirteenth transistor receives the second clock control signal, and the second path end of the twelfth transistor receives the second reference voltage through a path formed with the thirteenth transistor, the control end of the fourteenth transistor is connected to the first control node, the first path end of the fourteenth transistor receives the first reference voltage, and the second path end of the fourteenth transistor is connected to the path between the twelfth transistor and the thirteenth transistor.

[0010] In one embodiment, the second level control unit includes a fifteenth transistor, a first capacitor, and a first output node, the control terminal of the fifteenth transistor is connected to the first control node, and the control terminal of the fifteenth transistor is also connected to the first output node through the first capacitor, the first channel end of the fifteenth transistor receives the first clock control signal, and the second channel end of the fifteenth transistor is connected to the first output node; the first level control unit connected to the first output node includes an eighteenth transistor, the control terminal of the eighteenth transistor is connected to the second control node to receive the second control signal, the first channel end of the eighteenth transistor is connected to the first output node, and the second channel end of the eighteenth transistor receives the second reference voltage; the third level control unit includes a sixteenth transistor, a second capacitor, and a second output node, the control terminal of the sixteenth transistor is connected to the second output node through the second capacitor an output node, a first channel end of a sixteenth transistor receives a third clock control signal, and a second channel end of the sixteenth transistor is connected to a second output node; a first level control unit connected to the second output node includes a nineteenth transistor, a control end of the nineteenth transistor is connected to the second control node to receive a second control signal, a first channel end of the nineteenth transistor is connected to the second output node, and a second channel end of the nineteenth transistor receives a second reference voltage; an isolation unit includes a seventeenth transistor, a control end of the seventeenth transistor receives a first reference voltage, a first channel end of the seventeenth transistor is connected to the control end of the fifteenth transistor, and a second channel end of the seventeenth transistor is connected to the control end of the sixteenth transistor; wherein the capacitance value of the first capacitor is greater than 0 and less than or equal to 500fF, and the capacitance value of the second capacitor is greater than 0 and less than or equal to 300fF.

[0011] In one embodiment, the display driving circuit uses an eight-phase clock to provide each clock control signal; and / or, in the eight-phase clock, the kth clock is T / 8 ahead of the k+1th clock, where 1≤k<8; and / or, the duty cycle of the high level in each clock control signal is T / 4; and / or, the phase difference between the first driving signal and the second driving signal is T / 8.

[0012] An embodiment of the present application further provides a display device, including a display panel and at least one display driving circuit as described above, wherein each display driving circuit is electrically connected to the display panel to output a driving signal to drive a horizontal scan line in the display panel.

[0013] In one embodiment, multiple display driving circuits are connected via a multi-stage transmission method, and the multiple display driving circuits are used to drive all or part of the pixel rows in the display panel; each display driving circuit is used to generate a first driving signal and a second driving signal for driving two pixel rows; wherein the phase difference between the driving signals of adjacent pixel rows in the display panel is T / 8.

[0014] The embodiment of the present application provides a display driver circuit and a display device. The display driver circuit is provided with leakage protection modules at key positions of the forward control unit and the reverse control unit, respectively, to form a symmetrical low-leakage structure, which effectively prevents or reduces leakage during the operation of pulling up or pulling down the potential of the first control node, thereby achieving better forward and reverse scanning functions, so that the potential of the first control node meets the expected design of each stage, and further enables the thin-film transistor controlled by the first control signal output by the first control node in the output module to be fully turned on, so as to ensure that the time required for the voltage change of the drive signal output by the output module meets the expected design, avoid mischarging or insufficient charging, and thus ensure the output stability of the drive signal. Therefore, the technical solution of the present application optimizes the display driver circuit, can avoid leakage or reduce leakage current, thereby ensuring the output stability of the drive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0016] Figure 1 It is a structural diagram of a pull-up control circuit in an existing display driving circuit.

[0017] Figure 2 2 is a schematic structural diagram of a display driving circuit provided in the first embodiment of the present application.

[0018] Figure 3 It is a schematic diagram of the structural framework of the display driving circuit provided in the second embodiment of the present application.

[0019] Figure 4 This is a schematic structural diagram of a display driving circuit provided by some current implementations.

[0020] Figure 5 This is an operating timing diagram of a display driving circuit provided by some current implementations.

[0021] Figure 6 Schematic diagram of the structure of the display driving circuit according to an embodiment of the present application.

[0022] Figure 7 This is a schematic structural diagram of the display driving circuit of Example 1 of this application.

[0023] Figure 8 This is a working timing diagram of the display driving circuit of Example 1 of this application.

[0024] Figure 9 This is a schematic diagram of the packaging of the display driving circuit of Example 1 of this application.

[0025] Figure 10This is a schematic diagram of the cascade connection of multiple display driving circuits provided by this application.

[0026] Figure 11 Schematic diagram of the cascade structure of the five-stage display driver circuit in the middle of the example GOA circuit.

[0027] Figure 12 This is a structural diagram of the display driving circuit of Example 2 of this application.

[0028] Figure 13 This is a working timing diagram of the display driving circuit of Example 2 of this application.

[0029] Figure 14 This is a structural diagram of the display driving circuit of Example 3 of this application.

[0030] Figure 15 This is a structural diagram of the display driving circuit of Example 4 of this application.

[0031] Figure 16 This is a structural diagram of the display driving circuit of Example 5 of this application. DETAILED DESCRIPTION

[0032] First embodiment

[0033] Figure 2 Schematic diagram of the structure of the display driving circuit provided by the first embodiment of the present application. Figure 2, is a structural diagram of a display driver circuit provided in the first embodiment of the present application. The display driver circuit provided in this embodiment includes: a scan control module 101 and an output module 100. The scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n. The forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1. The first path end of the first transistor T1 is used to receive a forward scan voltage VBD, the second path end of the first transistor T1 is connected to the first control node Q1n, and the first leakage protection module M1 is connected to the first path end of the first transistor T1 and / or the first control node Q1n. The reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2. The first path end of the second transistor T2 is used to receive a reverse scan voltage VFD, the second path end of the second transistor T2 is connected to the first control node Q1n, and the second leakage protection module M2 is connected to the first path end of the second transistor T2 and / or the first control node Q1n. The forward control unit 1011 and the reverse control unit 1012 are configured to enable the scan control module 101 to implement forward and reverse scan functions based on signals input to the control terminals of the transistors, and to output a first control signal to the output module 100 via the first control node Q1n. The output module 100 is configured to perform pull-up control and / or pull-down control based on the first control signal to output a drive signal.

[0034] In one embodiment, the first leakage protection module M1 and the second leakage protection module M2 can be separate components that implement the leakage protection function, or they can be a combination of multiple components to implement the leakage protection function. For example, a high-threshold transistor with an inverted width-to-length ratio is specially selected in the leakage protection module to utilize the low leakage characteristics of the device to reduce the impact of leakage. For another example, the leakage protection module includes two transistors, the control terminal of one of the two transistors receives a second clock control signal, and the first path terminal of the first transistor T1 or the second transistor T2 receives a scan voltage through a path formed with one of the two transistors, the control terminal of the other of the two transistors is connected to the first control node Q1n, the first path terminal of the other of the two transistors receives a reference high voltage, and the second path terminal of the other of the two transistors is connected to the path between the first transistor T1 and one of the two transistors.

[0035] The technical solution of this embodiment optimizes the display driver circuit, which can avoid leakage or reduce leakage current, thereby ensuring the output stability of the drive signal. In addition, under conditions of low temperature and the presence of electrical bias stress, the threshold voltage of the thin film transistor is easily forward biased, resulting in an increase in the off-state leakage current, which will cause the potential of the first control node Q1n to further decrease during the pull-up phase, making the thin film transistor controlled by the first control signal output by the first control node Q1n in the output module 100 less fully turned on. The time required for the voltage change of the drive signal output by the output module 100 (for example, the voltage drops from 90% to 10%) is longer, which is more likely to cause mischarging or insufficient charging, thereby seriously affecting the output stability of the drive signal. Therefore, in the technical solution of this embodiment, the display driver circuit is provided with leakage protection modules at key positions of the forward control unit 1011 and the reverse control unit 1012, which can also avoid or improve the above-mentioned problems, thereby achieving the function of normal startup at low temperatures.

[0036] Second embodiment

[0037] Figure 3 Schematic diagram of the structure of the display driving circuit provided by the second embodiment of the present application. Figure 3 , is a schematic diagram of the structural framework of the display driving circuit provided in the second embodiment of the present application. The display driving circuit provided in this embodiment includes: a scanning control module 101 and an output module 100. The scanning control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n. The forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1. The first path end of the first transistor T1 is used to receive the forward scanning voltage VBD, the second path end of the first transistor T1 is connected to the first control node Q1n, and the first leakage protection module M1 is connected to the first path end of the first transistor T1 and / or the first control node Q1n. The reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2. The first path end of the second transistor T2 is used to receive the reverse scanning voltage VFD, the second path end of the second transistor T2 is connected to the first control node Q1n, and the second leakage protection module M2 is connected to the first path end of the second transistor T2 and / or the first control node Q1n. The forward control unit 1011 and the reverse control unit 1012 are configured to enable the scan control module 101 to implement forward and reverse scan functions based on signals input to the control terminals of the transistors, and to output a first control signal to the output module 100 via the first control node Q1n. The output module 100 is configured to perform pull-up control and / or pull-down control based on the first control signal to output a drive signal.

[0038] In one embodiment, the output module 100 may include a level maintaining unit 102; the level maintaining unit 102 includes an inverter and a second control node Q2n; the inverter is used to perform level maintenance control according to the first control signal in the non-display stage to output the second control signal through the second control node Q2n, so that the driving signal output by the output module 100 is maintained in a low level state or a high level state.

[0039] In one embodiment, when the transistor in the level maintaining unit 102 is of N-type, it is a pull-down maintaining unit; and when the transistor in the level maintaining unit 102 is of P-type, it is a pull-up maintaining unit.

[0040] In one embodiment, the inverter may include a cascaded single-stage inverter and a source follower. The technical solution of this embodiment, through the inverter in the output module 100, can enhance the level maintenance capability (e.g., enhanced pull-down maintenance capability or enhanced pull-up maintenance capability) during the non-display phase, thereby suppressing the multi-gate problem caused by clock feedthrough.

[0041] In one embodiment, the output module 100 also includes a first level control unit 103; the first level control unit 103 is used to perform one of pull-up control and pull-down control according to the second control signal output by the level maintaining unit 102, so that the output module 100 outputs a driving signal representing one of a low level and a high level.

[0042] In one embodiment, when the first level control unit 103 is a single-type NMOS / PMOS circuit, the second control signal can be used to perform either pull-up control or pull-down control. Alternatively, when the first level control unit 103 is a CMOS circuit, the first control signal outputted from the first control node Q1n can be directly used to perform either pull-up control or pull-down control.

[0043] In one embodiment, the output module 100 includes at least two first level control units 103; the output module 100 also includes a second level control unit 104, a first output node, a third level control unit 105, a second output node and an isolation unit 106; the isolation unit 106 is used to isolate the control signals of the second level control unit 104 and the third level control unit 105; when one of the at least two first level control units 103 is used to perform one of the pull-up control and the pull-down control, the output represents a first drive signal of one of the low level and the high level to the first output node; the second level control unit 104 is used to perform the pull-up control and the pull-down control. When the other of the two pull-up control and the pull-down control is performed, the first driving signal representing the other of the low level and the high level is output to the first output node; when the other of the at least two first level control units 103 is used to perform one of the pull-up control and the pull-down control, the second driving signal representing the other of the low level and the high level is output to the second output node; when the third level control unit 105 is used to perform the other of the pull-up control and the pull-down control, the second driving signal representing the other of the low level and the high level is output to the second output node; wherein the first driving signal and the second driving signal are respectively used to drive the horizontal scan lines of two adjacent levels in the display panel.

[0044] In this way, the technical solution of this embodiment allows each display driver circuit in the GOA circuit to reuse a portion of the functional modules and / or their control nodes (for example, the scan control module 101, the first control node Q1n, the level maintaining unit 102 in the output module 100, etc.), and output two drive signals for respectively driving the horizontal scan lines of two adjacent levels in the display panel. Specifically, the control signals of the second level control unit 104 and the third level control unit 105 are isolated by the isolation unit 106, so that the second level control unit 104 and the third level control unit 105 can output two drive signals without bootstrapping loss. Therefore, the technical solution of this embodiment not only improves the circuit operation efficiency of the display driver circuit, but also enables the display device equipped with the display driver circuit of this embodiment to achieve a narrow-frame design.

[0045] In one embodiment, the output module 100 further includes a fourth level control unit 108, which is connected to the first control node Q1n and the second control node Q2n and is configured to adjust the level of the first control signal outputted from the first control node Q1n according to the second control signal outputted by the level maintaining unit 102.

[0046] The technical solution of this embodiment helps maintain the level of the first control signal in high / low states through the fourth level control unit 108, thereby reducing the impact of the intermediate state caused by leakage on the signal.

[0047] In one embodiment, the output module 100 further includes a stage transmission unit 107; the stage transmission unit 107 includes a third transistor, the control end of the three transistors is connected to the first control node Q1n to receive the first control signal, the first pass end of the third transistor receives the first clock control signal, and the second pass end of the third transistor outputs the stage transmission output signal.

[0048] Thus, in the technical solution of this embodiment, the display driver circuit can reduce the pressure on its own drive node to drive the load through the level transmission unit 107, and can improve the low-temperature level transmission capability. Thus, in the technical solution of this embodiment, the display driver circuit can reduce the pressure on its own drive node to drive the load through the level transmission unit 107. The second level signal control unit 104 and the third level control unit 105 are responsible for charging and discharging the internal circuit of the pixel in the display panel, while the level transmission process within the GOA circuit is handled by the level transmission unit 107. Under low temperature and positive threshold voltage drift conditions, the GOA circuit can still drive the corresponding load. Therefore, the technical solution of this embodiment can improve the low-temperature level transmission capability.

[0049] Based on the technical concept of the above technical solution, the following circuit structure is used to illustrate the above technical solution:

[0050] In some current implementations (see Figure 1 、 Figures 4 and 5 ), the GOA circuit includes a plurality of cascaded GOA units, each level of GOA unit corresponding to driving a level of horizontal scan line of the display panel (ie, the GOA unit is similar to the display driving circuit in this embodiment). Figure 4 The main structure of the GOA unit includes a pull-up control circuit (Pull-up control part) 101' and an output module 100', wherein the output module 100 includes a pull-up circuit (Pull-up part) 104', a pull-down circuit (KeyPull-down Part) 103', and a pull-down holding circuit (Pull-down Holding Part) 102'. The pull-up circuit also includes a bootstrap capacitor C1' responsible for raising the potential. The pull-up control circuit adopts an existing design (such as Figure 1 shown). Figure 4 The structure of the GOA unit shown has the following disadvantages:

[0051] 1. After long-term operation of the GOA circuit in some current implementations, the threshold voltage drift of the thin film transistor in the GOA unit is very likely to cause leakage, which in turn causes the GOA circuit to malfunction. Figure 4 and Figure 5As shown, during the pull-up and bootstrap phases of the GOA circuit, the scan control node Qn' of each GOA unit is at a high potential, with several leakage current paths. For example, the scan control node Qn' can leak current to the level signal VGL through thin-film transistors t1, t2, and t12. It should be noted that in the forward scan mode, the leakage path is through thin-film transistor t1 and the sixth thin-film transistor t12; in the reverse scan mode, the leakage path is through thin-film transistor t2 and t12. However, under conditions of reduced temperature and electrical bias stress, the threshold voltage of the thin-film transistor can easily become positively biased, resulting in increased off-state leakage current, which in turn causes the potential of the scan control node Qn' to decrease during the pull-up phase. This makes the thin-film transistor t15 in the pull-up circuit 104' less fully turned on, and the time required for the voltage of the signal output terminal Gn to drop from 90% to 10% becomes longer, resulting in mischarging or insufficient charging, which will seriously affect the output stability of the gate drive signal Gn.

[0052] 2. In some current implementations, the GOA units in the GOA circuits may be affected by clock feedthrough, which may result in multi-gate (i.e., a row of pixels outputs scan signals multiple times within one frame), leading to malfunction of the GOA circuit. Figure 4 and Figure 5 As shown, due to the clock feedthrough of the first clock control signal CT1_n to the thin-film transistor t15, the thin-film transistor t15 is abnormally turned on. The driving signal output by the signal output terminal Gn is repeatedly erroneously coupled from the normal potential to the high potential during the non-display time, resulting in abnormal in-plane charging and affecting the normal display of the display panel. In addition, under conditions of elevated temperature and electrical bias stress, the threshold voltage of the thin-film transistor is easily negatively biased, which further aggravates the clock feedthrough phenomenon, reduces the stability of the driving signal output by the signal output terminal Gn, and even causes output errors. 3. Because the driving signal output by the signal output terminal Gn is turned on for a very short time, the pull-down action time of the two adjacent GOA units and the point waveform of the scan control node Qn' are basically similar, and the two adjacent GOA units have the same complex circuit structure, it is disadvantageous for achieving a narrow bezel of the panel.

[0053] Therefore, in order to solve the technical problems existing in the GOA unit in the GOA circuit in some current implementations, and based on the technical concept of the technical solution of the above embodiment, a display driving circuit is exemplified below. Figure 6 This is a schematic diagram of the structure of the display driving circuit of the embodiment of the present application, see Figure 6, comprising: a scan control module 101 and an output module 100; the scan control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012 and a first control node Q1n; wherein the forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1, and the first leakage protection module M1 includes a fourth transistor T4 and a fifth transistor T5; the control end of the first transistor T1 receives the first-stage input signal Cn+, the first path end of the first transistor T1 is used to receive the forward scan voltage VBD, and the second path end of the first transistor T1 is connected to the first control node Q1n; the control end of the fourth transistor T4 receives the second clock control signal CT2-n, and the first path end of the first transistor T1 receives the forward scan voltage VBD through a path formed with the fourth transistor T4; the control end of the fifth transistor T5 is connected to the first control node Q1n, the first path end of the fifth transistor T5 receives the first reference voltage VG1, and the second path end of the fifth transistor T5 is connected to the path between the first transistor T1 and the fourth transistor T4. The structure of the first leakage protection module can provide leakage protection for the first control node Q1n: when the first control node Q1n is high and the forward scanning voltage VBD is low, the first control node Q1n needs to maintain a high voltage for a period of time to await the start of the bootstrap phase. During this hold time, a leakage path exists between the first transistor T1, the fourth transistor T4, and the forward scanning voltage VBD. However, because the fifth transistor T5 is turned on when the first control node Q1n is high, the second path end N2 of the fifth transistor T5 (the path between the first transistor T1 and the fourth transistor T4) receives the first reference voltage VG1 at a high level, blocking the leakage path of the first control node Q1n and achieving leakage protection for the first control node Q1n. In which, the reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2, and the second leakage protection module M2 includes a sixth transistor T6 and a seventh transistor T7; the control end of the second transistor T2 receives the second-stage input signal Cn-, the first path end of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second path end of the second transistor T2 is connected to the first control node Q1n; the control end of the sixth transistor T6 receives the second clock control signal CT2-n, and the first path end of the second transistor T2 receives the reverse scan voltage VFD through the path formed with the sixth transistor T6, the control end of the seventh transistor T7 is connected to the first control node Q1n, the first path end of the seventh transistor T7 receives the first reference voltage VG1, and the second path end of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.The second leakage protection module's structure provides leakage protection for the first control node Q1n. When the first control node Q1n is high and the reverse scan voltage VFD is low, the first control node Q1n needs to maintain a high voltage for a period of time to await the start of the bootstrap phase. During this hold time, a leakage path exists between the second transistor T2, the sixth transistor T6, and the reverse scan voltage VFD. However, because the seventh transistor T7 is turned on when the first control node Q1n is high, the second path end N1 of the seventh transistor T7 (the path between the second transistor T2 and the sixth transistor T6) receives the high first reference voltage VG1, blocking the leakage path of the first control node Q1n and implementing leakage protection for the first control node Q1n.

[0054] In one embodiment, the forward scan voltage VBD may be one of the reference high voltage VGH and the reference low voltage VGL, and the reverse scan voltage VFD may be the other of the reference high voltage VGH and the reference low voltage VGL.

[0055] Thus, in the technical solution of this example, when the scan control module 101 of the display driving circuit outputs a control signal to cause a specific component in the output module 100 to perform pull-up control, the scan control module 101 is equivalent to a pull-up control module, and the scan control module 101 forms a symmetrical low-leakage structure by symmetrically configuring two leakage protection modules. This not only avoids or improves the problem of leakage caused by the threshold voltage drift of the transistors in the scan control module 101 after long-term operation, but also avoids or improves the problem of increased off-state leakage current caused by the threshold voltage of the transistors in the scan control module 101 being forward biased under conditions of reduced temperature and the presence of electrical bias stress. Therefore, the scan control module 101 can better and stably output the first control signal to the output module 100 in accordance with the expected design, thereby fully turning on the relevant transistors of the output module 100, ensuring that the time required for the voltage change of the driving signal output by the output module 100 meets the expected design, avoiding the occurrence of mischarging or insufficient charging, and thus ensuring the stability of the driving signal output by the output module 100.

[0056] In one embodiment, the output module 100 may include a level maintaining unit 102 , which includes a cascaded single-stage inverter and a source follower and a second control node Q2n;

[0057] The single-stage inverter includes an eighth transistor T8 and a ninth transistor T9. The control terminal of the eighth transistor T8 receives the first reference voltage VG1 or is connected to the first control node Q1n. The first channel terminal of the eighth transistor T8 receives the first reference voltage VG1. The second channel terminal of the eighth transistor T8 is connected to the first channel terminal of the ninth transistor T9. The second channel terminal of the ninth transistor T9 receives the second reference voltage VG2. The control terminal of the ninth transistor T9 is connected to the first control node Q1n.

[0058] The source follower includes a tenth transistor T10 and an eleventh transistor T11, the control terminal of the tenth transistor T10 is connected to the second pass terminal of the eighth transistor T8, the first pass terminal of the tenth transistor T10 receives the first reference voltage VG1, the second pass terminal of the tenth transistor T10 is connected to the second control node Q2n, the control terminal of the eleventh transistor T11 is connected to the first control node Q1n, the first pass terminal of the eleventh transistor T11 is connected to the second control node Q2n, and the second pass terminal of the eleventh transistor T11 receives the second reference voltage VG2.

[0059] In one embodiment, the first reference voltage VG1 is one of a reference high voltage VGH and a reference low voltage VGL, and the second reference voltage VG2 is the other of the reference high voltage VGH and the reference low voltage VGL.

[0060] In the technical solution of this embodiment, a two-stage inverter is formed by the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11, wherein the gain of the first stage corresponding to the single-stage inverter is relatively small, and the gain of the second stage corresponding to the source follower is greater than the gain of the first stage, so as to achieve a step-by-step increase in gain, thereby enabling the aforementioned inverter to have a stronger level maintenance capability.

[0061] In one embodiment, the inverter can achieve input and output inversion. Optionally, the inverter can include an NMOS transistor.

[0062] Thus, in the technical solution of this example, the inverter included in the level maintenance unit 102 in the output module 100 of the display driver circuit can have a strong level maintenance capability (e.g., pull-down maintenance capability) in the non-display phase, thereby being able to suppress the multi-gate phenomenon caused by clock feedthrough. In addition, under conditions of temperature rise and the presence of electrical bias stress, when the threshold voltage of the transistor in the output module 100 is prone to negative bias, the multi-gate phenomenon caused by clock feedthrough can also be effectively suppressed. The level maintenance unit 102 in the output module 100 of the display driver circuit can enable the output module 100 to ensure the stability and correctness of the output drive signal.

[0063] When the output control signal causes a specific component in the output module 100 to perform pull-up control, the scanning control module 101 is equivalent to a pull-up control module, and the scanning control module 101 symmetrically configures two leakage protection modules, so that the scanning control module 101 forms a symmetrical low leakage structure, which can not only avoid or improve the problem of leakage caused by the threshold voltage drift of the transistor in the scanning control module 101 after long-term operation, but also avoid or improve the problem of the threshold voltage of the transistor in the scanning control module 101 being positively biased and causing an increase in the off-state leakage current under conditions of reduced temperature and the presence of electrical bias stress. Therefore, the scanning control module 101 can better output the first control signal to the output module 100 stably according to the expected design, so that the relevant transistors of the output module 100 are fully turned on, ensuring that the time required for the voltage change of the drive signal output by the output module 100 is in line with the expected design, avoiding the occurrence of mischarging or insufficient charging, thereby ensuring the stability of the drive signal output by the output module 100.

[0064] In one embodiment, the output module 100 or the scan control module 101 may further include a fourth level control unit 108 including a twelfth transistor T12 and a third leakage protection module, and the third leakage protection module includes a thirteenth transistor T13 and a fourteenth transistor T14;

[0065] The control terminal of the twelfth transistor T12 is connected to the second control node Q2n of the level maintaining unit 102 to receive the second control signal, the first pass terminal of the twelfth transistor T12 is connected to the first control node Q1n, and the second pass terminal of the twelfth transistor T12 is used to receive the second reference voltage VG2;

[0066] A control terminal of the thirteenth transistor T13 receives the second clock control signal CT2-n, and a second path terminal of the twelfth transistor T12 receives the second reference voltage VG2 via a path formed with the thirteenth transistor T13. A control terminal of the fourteenth transistor T14 is connected to the first control node Q1n, a first path terminal of the fourteenth transistor T14 receives the first reference voltage VG1, and a second path terminal of the fourteenth transistor T14 is connected to the path between the twelfth transistor T12 and the thirteenth transistor T13.

[0067] The structure of the third leakage protection module can provide leakage protection for the first control node Q1n: when the first control node Q1n is high and the second reference voltage VG2 is low, the first control node Q1n needs to maintain a high voltage for a period of time to wait for the bootstrap phase to arrive. During this hold time, a leakage path exists between the twelfth transistor T12, the thirteenth transistor T13, and the second reference voltage VG2. However, because the fourteenth transistor T14 is turned on when the first control node Q1n is high, the second path end N3 of the fourteenth transistor T14 (the path between the twelfth transistor T12 and the thirteenth transistor T13) receives the high first reference voltage VG1, blocking the leakage path of the first control node Q1n and achieving leakage protection for the first control node Q1n.

[0068] In this way, in the technical solution of this example, the leakage protection module in the fourth level control unit 108 can cooperate with the leakage protection module of the scanning control module 101 to further avoid or improve the problem of leakage caused by the threshold voltage drift of the transistor in the scanning control module 101 after long-term operation.

[0069] In one embodiment, the output module 100 may include two first level control units 103 , a second level control unit 104 , a first output node Gn1 , a third level control unit 105 , a second output node Gn2 , and an isolation unit 106 ;

[0070] The second level control unit 104 includes a fifteenth transistor T15, a first capacitor C1, and a first output node Gn1. The control terminal of the fifteenth transistor T15 is connected to the first control node Q1n. The control terminal of the fifteenth transistor T15 is also connected to the first output node Gn1 via the first capacitor C1 (which acts as a bootstrap). A first channel terminal of the fifteenth transistor T15 receives the first clock control signal CT1-n, and a second channel terminal of the fifteenth transistor T15 is connected to the first output node Gn1. In this way, the second level control unit 104 can perform pull-up control or pull-down control on the first drive signal output from the first output node Gn1.

[0071] The first level control unit 103 connected to the first output node Gn1 includes an eighteenth transistor T18. The control terminal of the eighteenth transistor T18 is connected to the second control node Q2n to receive the second control signal (output by the level maintaining unit 102). A first channel terminal of the eighteenth transistor T18 is connected to the first output node Gn1, and a second channel terminal of the eighteenth transistor T18 receives the second reference voltage VG2. In this way, the first level control unit 103 connected to the first output node Gn1 can perform either pull-up control or pull-down control on the first driving signal output from the first output node Gn1 (the opposite of the second level control unit 104).

[0072] The third level control unit 105 includes a sixteenth transistor T16, a second capacitor C2, and a second output node Gn2. The control terminal of the sixteenth transistor T16 is connected to the second output node Gn2 via the second capacitor C2 (which acts as a bootstrap). A first channel terminal of the sixteenth transistor T16 receives the third clock control signal CT3-n, and a second channel terminal of the sixteenth transistor T16 is connected to the second output node Gn2. In this way, the third level control unit 105 can perform pull-up control or pull-down control on the second driving signal output from the second output node Gn2.

[0073] The first level control unit 103 connected to the second output node Gn2 includes a nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is connected to the second control node Q2n to receive the second control signal. The first channel terminal of the nineteenth transistor T19 is connected to the second output node Gn2, and the second channel terminal of the nineteenth transistor T19 receives the second reference voltage VG2. In this way, the first level control unit 103 connected to the second output node Gn2 can perform the other of pull-up control and pull-down control on the second drive signal output from the second output node Gn2 (the opposite of the third level control unit 105).

[0074] The isolation unit 106 includes a seventeenth transistor T17 , a control terminal of which receives the first reference voltage VG1 , a first pass terminal of which is connected to the control terminal of the fifteenth transistor T15 , and a second pass terminal of which is connected to the control terminal of the sixteenth transistor T16 .

[0075] In the technical solution of this example, the two first level control units 103, the second level control unit 104, the first output node Gn1, the third level control unit 105, the second output node Gn2 and the isolation unit 106 in the output module 100 of the display driving circuit, the above-mentioned circuit coordination method can enable the display driving circuit to multiplex the scanning control module 101 and the level maintaining unit 102 to generate driving signals (first driving signal and second driving signal) for two pixel rows (or two horizontal scanning lines) in the display panel. Therefore, the technical solution of this example can improve the circuit efficiency of the entire display driving circuit and can also meet the narrow frame design requirements of the display device.

[0076] Specifically, the display driving circuit multiplexes the scanning control module 101 and the level maintaining circuit, and can complete the normal output of the first driving signal for the pixel row of the nth level while completing the output of the second driving signal for the pixel row of the n+1th level without bootstrap loss.

[0077] In one embodiment, the seventeenth transistor T17 in the isolation unit 106 can be a normally-on isolation transistor. A first channel end of the seventeenth transistor T17 is connected to the control terminal of the fifteenth transistor T15, equivalent to being connected to the first control node Q1n. A second channel end of the seventeenth transistor T17 is connected to the control terminal of the sixteenth transistor T16, equivalent to forming a third control node Q3n at the control terminal of the sixteenth transistor T16. Because the third control node Q3n controls the third level control unit 105, the seventeenth transistor T17 can reduce bootstrap losses caused by node sharing. Furthermore, the second drive signal output by the third level control unit 105 will not be miscoupled (e.g., miscoupled during pull-up) by the first drive signal output by the second level control unit 104, preventing the second drive signal from being coupled from a normally high potential to a higher potential. This prevents abnormal charging within the display panel and ensures normal display of the display panel.

[0078] In one embodiment, the output module 100 may further include a stage transmission unit 107 , and the stage transmission unit 107 includes a third transistor T3 ;

[0079] The control terminal of the third transistor T3 is connected to the first control node Q1n to receive the first control signal. The first pass terminal of the third transistor T3 receives the first clock control signal CT1-n. The second pass terminal of the third transistor T3 outputs a signal Cn.

[0080] In one embodiment, the output module 100 may further include a fifth level control unit 109 connected to the stage transfer unit 107, and the fifth level control unit 109 includes a twentieth transistor T20; the control end of the twentieth transistor T20 is connected to the second control node Q2n (level maintaining unit 102), the first channel end of the twentieth transistor T20 is connected to the second channel end of the third transistor, and the second channel end of the twentieth transistor T20 receives the second reference voltage VG2.

[0081] In this way, the technical solution of this example can reduce the pressure of the display driving circuit driving load and improve the low-temperature transmission capability by designing the transmission unit 107 in the output module 100.

[0082] The first reference voltage VG1 may be one of a reference high voltage VGH and a reference low voltage VGL, and the second reference voltage VG2 may be the other of the reference high voltage VGH and the reference low voltage VGL.

[0083] The first level control module, the fourth level control module, and the fifth level control unit 109 all control the signals they transmit to maintain the desired design potential at the correct time period through the second control signal output by the level maintaining unit 102 through the second control node Q2n. The two first level control units 103 can maintain the first drive signal and the second drive signal at a preset design potential, such as pulling them down to the reference low voltage VGL, at the correct time period under the control of the second control signal. The fourth level control unit 108 can maintain the first control signal at the desired design potential (e.g., pulling it down to the reference low voltage VGL) at the correct time period under the control of the second control signal. The fifth level control unit 109 ( Figure 3 (not shown) can maintain the stage output signal Cn at a desired design potential (eg, pull it down to the reference low voltage VGL) during a correct period under the control of the second control signal.

[0084] In one embodiment, the capacitance value of the first capacitor C1 may be greater than 0 and less than or equal to 500 fF, and the capacitance value of the second capacitor C2 may be greater than 0 and less than or equal to 300 fF.

[0085] In one embodiment, a display driver circuit or a display device equipped with such a display driver circuit uses an eight-phase clock to provide each clock control signal. In one embodiment, in the eight-phase clock, the kth clock advances the k+1th clock by T / 8, where 1≤k<8. In one embodiment, the duty cycle of the high level in each clock control signal is T / 4. In one embodiment, the phase difference between the first drive signal and the second drive signal is T / 8.

[0086] It should be understood that the aforementioned various nodes (such as the first control node Q1n, the second control node Q2n, the third control node Q3n, etc.) can be virtual nodes set up to facilitate clear description of the circuit structure; in addition, the aforementioned various nodes can also be physical ports set according to actual needs.

[0087] In summary, the above-mentioned display driver circuit enables the GOA circuit to optimize the leakage path while having forward and reverse scanning functions, and suppress the impact of clock feedthrough, thereby solving the problem of thin-film transistor threshold voltage shift caused by temperature changes and electrical bias stress. In addition, because the same display driver circuit can output two drive signals to drive two pixel rows of the display panel, the number of display driver circuits in the display device can be reduced, thereby facilitating the display device to achieve a narrow bezel design. Therefore, the above-mentioned display driver circuit solves the technical problem that the GOA circuit in some current implementations is prone to functional failure over a wide temperature range, thereby causing the display panel driven by the GOA circuit to exhibit display abnormalities.

[0088] Based on the circuit structure of the above display driving circuit, further examples are given below:

[0089] Example 1:

[0090] Figure 7 This is a schematic diagram of the structure of the display driving circuit of Example 1 of this application. Figure 7 This example provides a display driving circuit composed of N-type thin film transistors (for example, LTPO TFTs), including: a scanning control module 101 and an output module 100; the scanning control module 101 includes a symmetrically arranged forward control unit 1011, a reverse control unit 1012, and a first control node Q1n; wherein the forward control unit 1011 includes a first transistor T1 and a first leakage protection module M1, and the first leakage protection module M1 includes a fourth transistor T4 and a fifth transistor T5; the control terminal of the first transistor T1 receives a first-stage input signal Cn+, the first channel terminal of the first transistor T1 is used to receive a forward scanning voltage VBD, and the second channel terminal of the first transistor T1 is connected to the first control node Q1n; the control terminal of the fourth transistor T4 receives a second clock control signal CT2-n, and the first channel terminal of the first transistor T1 receives the forward scanning voltage VBD through a channel formed with the fourth transistor T4; the control terminal of the fifth transistor T5 is connected to the first control node Q1n, and the first channel terminal of the fifth transistor T5 receives a reference high voltage VGH, the second channel end of the fifth transistor T5 is connected to the path between the first transistor T1 and the fourth transistor T4; wherein the reverse control unit 1012 includes a second transistor T2 and a second leakage protection module M2, and the second leakage protection module M2 includes a sixth transistor T6 and a seventh transistor T7; the control end of the second transistor T2 receives the second-stage input signal Cn-, the first channel end of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second channel end of the second transistor T2 is connected to the first control node Q1n; the control end of the sixth transistor T6 receives the second clock control signal CT2-n, and the first channel end of the second transistor T2 receives the reverse scan voltage VFD through the path formed with the sixth transistor T6; the control end of the seventh transistor T7 is connected to the first control node Q1n, the first channel end of the seventh transistor T7 receives the reference high voltage VGH, and the second channel end of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.

[0091] In one embodiment, the output module 100 may include a level maintaining unit 102, two first level control units 103, a second level control unit 104, a third level control unit 105, an isolation unit 106, a fourth level control unit 108, a stage transmission unit 107, and a fifth level control unit 109; wherein the level maintaining unit 102 includes a cascaded single-stage inverter and a source follower and a second control node Q2n; the single-stage inverter includes an eighth transistor T8 and a ninth transistor T9, the control terminal of the eighth transistor T8 receives a reference high voltage VGH, the first channel terminal of the eighth transistor T8 receives the reference high voltage VGH, the second channel terminal of the eighth transistor T8 is connected to the first channel terminal of the ninth transistor T9, and the second channel terminal of the eighth transistor T8 is connected to the first channel terminal of the ninth transistor T9. The channel terminals of the ninth transistor T9 are connected, the second channel terminal of the ninth transistor T9 receives the reference low voltage VGL, and the control terminal of the ninth transistor T9 is connected to the first control node Q1n; the source follower includes a tenth transistor T10 and an eleventh transistor T11, the control terminal of the tenth transistor T10 is connected to the second channel terminal of the eighth transistor T8, the first channel terminal of the tenth transistor T10 receives the reference high voltage VGH, the second channel terminal of the tenth transistor T10 is connected to the second control node Q2n, the control terminal of the eleventh transistor T11 is connected to the first control node Q1n, the first channel terminal of the eleventh transistor T11 is connected to the second control node Q2n, and the second channel terminal of the eleventh transistor T11 receives the reference low voltage VGL.

[0092] In one embodiment, the output module 100 may further include a fourth level control unit 108 including a twelfth transistor T12 and a third leakage protection module. The third leakage protection module includes a thirteenth transistor T13 and a fourteenth transistor T14. The control terminal of the twelfth transistor T12 is connected to the second control node Q2n of the level maintaining unit 102 to receive the second control signal. The first channel terminal of the twelfth transistor T12 is connected to the first control node Q1n. The second channel terminal of the twelfth transistor T12 is configured to receive a reference low voltage VGL. The control terminal of the thirteenth transistor T13 receives the second clock control signal CT2-n. The second channel terminal of the twelfth transistor T12 receives the reference low voltage VGL via a path formed with the thirteenth transistor T13. The control terminal of the fourteenth transistor T14 is connected to the first control node Q1n. The first channel terminal of the fourteenth transistor T14 receives the reference high voltage VGH. The second channel terminal of the fourteenth transistor T14 is connected to the path between the twelfth transistor T12 and the thirteenth transistor T13.

[0093] The second level control unit 104 includes a fifteenth transistor T15, a first capacitor C1, and a first output node Gn1. The control end of the fifteenth transistor T15 is connected to the first control node Q1n, and the control end of the fifteenth transistor T15 is also connected to the first output node Gn1 through the first capacitor C1 (which acts as a bootstrap). The first path end of the fifteenth transistor T15 receives the first clock control signal CT1-n, and the second path end of the fifteenth transistor T15 is connected to the first output node Gn1. In this way, the second level control unit 104 can pull up the first driving signal outputted from the first output node Gn1. The first level control unit connected to the first output node Gn1 The control unit 103 includes an eighteenth transistor T18, the control terminal of the eighteenth transistor T18 is connected to the second control node Q2n to receive the second control signal (output by the level maintaining unit 102), the first channel terminal of the eighteenth transistor T18 is connected to the first output node Gn1, and the second channel terminal of the eighteenth transistor T18 receives the reference low voltage VGL; thus, the first level control unit 103 connected to the first output node Gn1 can pull down the first driving signal outputted from the first output node Gn1 (opposite to the second level control unit 104); the third level control unit 105 includes a sixteenth transistor T16, a second capacitor C2, and a second output Node Gn2, the control end of the sixteenth transistor T16 is connected to the second output node Gn2 through the second capacitor C2 (which acts as a bootstrap), the first path end of the sixteenth transistor T16 receives the third clock control signal CT3-n, and the second path end of the sixteenth transistor T16 is connected to the second output node Gn2; in this way, the third level control unit 105 can pull up the second drive signal output by the second output node Gn2; the first level control unit 103 connected to the second output node Gn2 includes a nineteenth transistor T19, the control end of the nineteenth transistor T19 is connected to the second control node Q2n to receive the second control signal, and the nineteenth transistor T1 9 is connected to the second output node Gn2, and the second pass end of the nineteenth transistor T19 receives the reference low voltage VGL; thus, the first level control unit 103 connected to the second output node Gn2 can perform pull-down control on the second driving signal output by the second output node Gn2 (opposite to the third level control unit 105); the isolation unit 106 includes a seventeenth transistor T17, the control end of the seventeenth transistor T17 receives the reference high voltage VGH (normally on), the first pass end of the seventeenth transistor T17 is connected to the control end of the fifteenth transistor T15, and the second pass end of the seventeenth transistor T17 is connected to the control end of the sixteenth transistor T16.

[0094] The level transfer unit 107 includes a third transistor T3; the control terminal of the third transistor T3 is connected to the first control node Q1n to receive the first control signal, the first channel terminal of the third transistor T3 receives the first clock control signal CT1-n, and the second channel terminal of the third transistor T3 outputs the level transfer output signal Cn. A fifth level control unit 109 is connected to the level transfer unit 107 and includes a twentieth transistor T20; the control terminal of the twentieth transistor T20 is connected to the second control node Q2n (level maintaining unit 102), the first channel terminal of the twentieth transistor T20 is connected to the second channel terminal of the third transistor T3, and the second channel terminal of the twentieth transistor T20 receives the reference low voltage VGL.

[0095] The capacitance value of the first capacitor C1 can be greater than 0 and less than or equal to 500fF, and the capacitance value of the second capacitor C2 can be greater than 0 and less than or equal to 300fF. The display driving circuit uses an eight-phase clock to provide each clock control signal. In the eight-phase clock, the kth clock is T / 8 ahead of the k+1th clock, where 1≤k<8. The duty cycle of the high level in each clock control signal is T / 4. The phase difference between the first drive signal and the second drive signal is T / 8.

[0096] Figure 8 This is the working timing diagram of the display driving circuit of Example 1 of this application. Figure 8 The working timing of the display driving circuit of Example 1 includes:

[0097] (1) T1 stage: the second clock control signal CT2-n and the second-stage transmission input signal Cn- provide a high potential, and the first clock control signal CT1-n provides a low potential; in the scan control module 101 (or called the pull-up control circuit), the sixth transistor T6, the second transistor T2, and the seventh transistor T7 are turned on, and the first control node Q1n is charged to a high level; in the level maintaining unit 102 (or called the pull-up maintaining circuit), the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second control node Q2n outputs a low level opposite to the first control node Q1n; the seventeenth transistor T17 of the isolation unit 106 is turned on, the fifteenth transistor T15 in the second level control unit 104 is turned on, the third transistor T3 of the stage transmission unit 107 is turned on, and the sixteenth transistor T16 in the third level control unit 105 is turned on, the first output node Gn1 outputs a first drive signal representing a low level, and the second output node Gn2 outputs a second drive signal representing a low level.

[0098] The voltage of the first capacitor C1 (bootstrap capacitor) and the voltage of the second capacitor C2 (bootstrap capacitor) are the differences between the voltage level of the first control node Q1n and the reference low voltage VGL, ie, VGH-VGL.

[0099] (2) T2 stage: the first clock control signal CT1-n, the second clock control signal CT2-n and the second-stage input signal Cn- provide a low potential, and the third clock control signal CT3-n begins to rise to a high level; at this time, the voltage of the second capacitor C2C2 maintains VGH-VGL; the sixteenth transistor T16 pushes the third control node Q3n to a higher level due to the bootstrap effect, and the second output node Gn2 outputs a second drive signal representing a high level; it should be noted that when the third control node Q3n is bootstrapped to a potential higher than VGH, the seventeenth transistor T17 (isolation transistor) is turned off, and the first control node Q1n will not rise along with the third control node Q3n, thereby avoiding subsequent adverse problems such as bootstrap level loss.

[0100] (3) T3 stage: the first clock control signal CT1-n provides a high potential, the second clock control signal CT2-n and the second-stage input signal Cn- provide a low potential, and the third clock control signal CT3-n begins to drop back to a low level; the bootstrap effect of the third control node Q3n disappears as the third clock control signal CT3-n returns to a low level, and the second output node Gn2 outputs the second drive signal representing a low level; at this time, the voltage of the first capacitor C1 maintains VGH-VGL, and the fifteenth transistor T15 pushes the first control node Qn1 to a higher level due to the bootstrap effect, and the first output node Gn1 outputs the first drive signal representing a high level.

[0101] (4) T4 stage: the first clock control signal CT1-n, the second clock control signal CT2-n and the second-stage input signal Cn- provide a low potential; the bootstrap effect of the first control node Q1n disappears as the first clock control signal CT1-n returns to low, and the first output node Gn1 outputs the first drive signal representing a low level.

[0102] (5) T5 stage: the second clock control signal CT2-n and the first-stage transmission input signal Cn+ provide a high potential, and the first clock control signal CT1-n and the second-stage transmission input signal Cn- provide a low potential; the fourth transistor T4, the first transistor T1, and the fifth transistor T5 in the scanning control module 101 are turned on, and the first control node Q1n is discharged to a low level; in the level maintaining unit 102 (or called the pull-down maintaining circuit), the inverter composed of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 outputs a high level opposite to the first control node Q1n, and maintains the first control node Q1n at the reference low level VGL during the non-display time.

[0103] In one embodiment, the display driving unit may be packaged. Figure 9 This is a schematic diagram of the packaging of the display driving circuit of Example 1 of this application. Figure 9 , wherein the first clock control signal CT1-n, the second clock control signal CT2-n and the third clock control signal CT3-n can be provided by an eight-phase clock, for example, the first clock control signal CT1-n is the first clock signal CLK1 in the eight-phase clock, the second clock control signal CT2-n is the fifth clock signal CLK5 in the eight-phase clock, and the third clock control signal CT3-n is the second clock signal CLK2 or the eighth clock signal CLK8 or the seventh clock signal CLK7 in the eight-phase clock, etc.

[0104] Figure 10 1 is a schematic diagram of a cascade of multiple display driving circuits provided by the present application. In one embodiment, when the GOA circuit adopts Figure 10 The display driving circuits shown are cascaded and use an eight-phase clock. Each display driving circuit is controlled by three clock signal lines, namely CT1-n, CT2-n, and CT3-n.

[0105] Figure 11 Schematic diagram of the cascade structure of the 5-stage display driver circuit in the middle of the example GOA circuit. Figure 11 , illustrates the cascade structure of the 5-level display driver circuit in the middle of the GOA circuit; combined with Figure 11 It can be seen that in the several cascade structures of the display driving circuits in the middle of the aforementioned five stages of the GOA circuit, the first clock control signal CT1-n of the display driving circuit of the nth stage is provided by the first clock signal line CLK1, the second clock control signal CT2-n is provided by the fifth clock signal line CLK5, and the third clock control signal CT3-n is provided by the eighth clock signal line CLK8; the first clock control signal CT1-n of the display driving circuits of the n-4th stage and the n+4th stage is provided by the fifth clock signal line CLK5, the second clock control signal CT2-n is provided by the first clock signal line CLK1, and the third clock control signal CT3-n is provided by the fourth clock signal line CLK4; the first clock control signal CT1-n of the display driving circuit of the n-2th stage is provided by the seventh clock signal line CLK7, the second clock control signal CT2-n is provided by the third clock signal line CLK3, and the third clock control signal CT3-n is provided by the sixth clock signal line CLK6. The first clock control signal CT1-n of the n+2-stage display driving unit is provided by the third clock signal line CLK3, the second clock control signal CT2-n is provided by the seventh clock signal line CLK7, and the first clock control signal CT1-n is provided by the second clock signal line CLK2; the stage transmission output signals Cn-4 and Cn+4 of the n-4-stage and n+4-stage display driving circuits serve as the stage transmission input signals of the n-stage display driving unit, and at the same time, the stage transmission output signals of the n-stage display driving unit serve as the stage transmission input signals of the n-4-stage and n+4-stage display driving circuits.

[0106] Figure 11 Different options for loading clock control signals are provided, showing different output results brought about by different implementations when the third clock control signal CT3-n is loaded with the seventh clock signal CLK7, the eighth clock signal CLK8 and the first clock signal CLK1 respectively; when the second clock control signal CT2-n is loaded with the seventh clock signal CLK7, the second drive signal Gn2 outputs Gn-2; when the second clock control signal CT2-n is loaded with the eighth clock signal CLK8, the second drive signal Gn2 outputs Gn-1; when the second clock control signal CT2-n is loaded with the first clock signal CLK1, the second drive signal Gn2 outputs Gn+1.

[0107] It can be understood that the GOA circuit provided in the above embodiment uses 8 clock signal lines (eight-phase clock) for control, and for other GOA circuits that use 4 clock signal lines, 6 clock signal lines, etc. for control, a similar structure as above can also be adopted, which will not be repeated here.

[0108] Example 2:

[0109] Figure 12 This is a schematic diagram of the structure of the display driving circuit of Example 2 of this application. Figure 12 This example provides a display driving circuit, which replaces the N-type thin film transistor in Example 1 with a P-type transistor (for example, using an LTPS TFT), and interchanges the reference high voltage VGH and the reference low voltage VGL in Example 1, which can achieve the normal operation requirements of the display driving circuit in the GOA circuit.

[0110] Figure 13 This is the working timing diagram of the display driving circuit of Example 2 of this application. Figure 13 The working timing of the display driving circuit of Example 2 includes:

[0111] (1) T1 stage: the second clock control signal CT2-n and the second-stage transmission input signal Cn- provide a low potential, and the first clock control signal CT1-n provides a high potential; in the scan control module 101 (or called the pull-up control circuit), the sixth transistor T6, the second transistor T2, and the seventh transistor T7 are turned on, and the first control node Q1n is charged to a low level; in the level maintaining unit 102 (or called the pull-down maintaining circuit), the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second control node Q2n outputs a high level opposite to the first control node Q1n; the seventeenth transistor T17 of the isolation unit 106 is turned on, the fifteenth transistor T15 of the second level control unit 104 is turned on, the second transistor T2 of the stage transmission unit 107 is turned on, and the sixteenth transistor T16 of the third level control unit 105 is turned on, the first output node Gn1 outputs a first drive signal representing a high level, and the second output node Gn2 outputs a second drive signal representing a high level.

[0112] The voltage of the first capacitor C1 (bootstrap capacitor) and the voltage of the second capacitor C2 (bootstrap capacitor) are the differences between the voltage level of the first control node Q1n and the reference high voltage VGH, ie, VGL-VGH.

[0113] (2) T2 stage: the first clock control signal CT1-n, the second clock control signal CT2-n and the second-stage input signal Cn- provide a high potential, and the third clock control signal CT3-n begins to rise to a low level; at this time, the voltage of the second capacitor C2 maintains VGL-VGH; the sixteenth transistor T16 pushes the third control node Q3n to a lower level due to the bootstrap effect, and the second output node Gn2 outputs a second drive signal representing a low level; it should be noted that when the third control node Q3n is bootstrapped to a potential lower than VGH, the seventeenth transistor T17 (isolation transistor) is turned off, and the first control node Q1n will not decrease along with the third control node Q3n, avoiding subsequent adverse problems such as bootstrap level loss.

[0114] (3) T3 stage: the first clock control signal CT1-n provides a low potential, the second clock control signal CT2-n and the second-stage input signal Cn- provide a high potential, and the third clock control signal CT3-n begins to rise back to a high level; the bootstrap effect of the third control node Q3n disappears as the third clock control signal CT3-n returns to a high level, and the second output node Gn2 outputs the second drive signal representing a high level; at this time, the voltage of the first capacitor C1 maintains VGL-VGH, and the fifteenth transistor T15 pushes the first control node Qn1 to a lower level due to the bootstrap effect, and the first output node Gn1 outputs the first drive signal representing a low level.

[0115] (4) T4 stage: the first clock control signal CT1-n, the second clock control signal CT2-n and the second-stage input signal Cn- provide a high potential; the bootstrap effect of the first control node Q1n disappears as the first clock control signal CT1-n returns to high, and the first output node Gn1 outputs the first drive signal representing a high level.

[0116] (5) T5 stage: the second clock control signal CT2-n and the first-stage transmission input signal Cn+ provide a low potential, and the first clock control signal CT1-n and the second-stage transmission input signal Cn- provide a high potential; the fourth transistor T4, the first transistor T1, and the fifth transistor T5 in the scanning control module 101 are turned on, and the first control node Q1n is discharged to a high level; in the level maintaining unit 102 (or called the pull-down maintaining circuit), the inverter composed of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 outputs a low level opposite to the first control node Q1n, and maintains the first control node Q1n at the reference high level VGH during the non-display time.

[0117] In one embodiment, the first clock control signal CT1-n, the second clock control signal CT2-n and the third clock control signal CT3-n can be provided by an eight-phase clock. For example, the first clock control signal CT1-n is the first clock signal CLK1 in the eight-phase clock, the second clock control signal CT2-n is the fifth clock signal CLK5 in the eight-phase clock, and the third clock control signal CT3-n is the second clock signal CLK2 or the eighth clock signal CLK8 or the seventh clock signal CLK7 in the eight-phase clock.

[0118] Example 3:

[0119] Figure 14 This is a schematic diagram of the structure of the display driving circuit of Example 3 of this application. Figure 14 This example provides a display driver circuit that changes the inverter of the level maintaining unit 102 in Example 1 from a unipolar MOS (N-type or P-type) to a CMOS type (i.e., the eighth transistor T8 uses an LTPS TFT), and the remaining transistors use oxide TFTs. Compared to the eighth transistor T8 in Example 1, the control terminal of the eighth transistor T8 in this example is connected to the first control node Q1n (not receiving the reference high voltage VGH). The specific driving timing diagram is the same as the first embodiment, see Figure 8 .

[0120] Example 4

[0121] Figure 15 Schematic diagram of the structure of the display driving circuit of Example 4 of this application. Figure 15This example provides a display driving circuit formed by combining N-type thin film transistors (for example, LTPO TFTs) and P-type thin film transistors (for example, LTPS TFTs), including: an output module 100, a scan control module 101 composed of N-type thin film transistors; the scan control module 101 includes a symmetrically arranged forward control unit, a reverse control unit, and a first control node Q1n; wherein the forward control unit includes a first transistor T1 and a first leakage protection module, and the first leakage protection module includes a fourth transistor T4 and a fifth transistor T5; the control terminal of the first transistor T1 receives a first-stage input signal Cn+, the first channel terminal of the first transistor T1 is used to receive a forward scan voltage VBD, and the second channel terminal of the first transistor T1 is connected to the first control node Q1n; the control terminal of the fourth transistor T4 receives a second clock control signal CT2-n, and the first channel terminal of the first transistor T1 receives the forward scan voltage VBD through a channel formed with the fourth transistor T4; the control terminal of the fifth transistor T5 is connected to the first control node Q1n, and the first channel terminal of the fifth transistor T5 receives a reference high voltage. The reverse control unit includes a second transistor T2 and a second leakage protection module M2, and the second leakage protection module M2 includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the second transistor T2 receives the second-stage input signal Cn-, the first channel end of the second transistor T2 is used to receive the reverse scan voltage VFD, and the second channel end of the second transistor T2 is connected to the first control node Q1n. The control terminal of the sixth transistor T6 receives the second clock control signal CT2-n, and the first channel end of the second transistor T2 receives the reverse scan voltage VFD through a path formed with the sixth transistor T6. The control terminal of the seventh transistor T7 is connected to the first control node Q1n, the first channel end of the seventh transistor T7 receives the reference high voltage VGH, and the second channel end of the seventh transistor T7 is connected to the path between the second transistor T2 and the sixth transistor T6.

[0122] In one embodiment, the output module 100 may include two first level control units 103, a second level control unit 104, a third level control unit 105, an isolation unit 106, a stage transfer unit 107 and a fifth level control unit 109; wherein, the output module 100 of this example differs from the output module 100 in Example 1 in that the level maintaining unit 102 and the fourth level control unit 108 are not configured, and the two first level control units 103 and the fifth level control unit 109 both include P-type thin film transistors.

[0123] Thus, compared with the display driving circuit of Example 1, the display driving circuit of this example does not need to construct a second control node Q2n with a voltage level opposite to that of the first control node Q1n to control the node pull-down; the display driving circuit of this example configures the transistors in the two first level control units 103 and the fifth level control unit 109 for implementing pull-down control as P-type thin film transistors (for example, LTPS TFTs), and directly uses the first control node Q1n to control the P-type thin film transistors, thereby completing the pull-down. The operating timing of the display driving circuit of this example can refer to the operating timing of Example 1 (see Figure 8 ).

[0124] Example 5:

[0125] Figure 16 Schematic diagram of the structure of the display driving circuit of Example 5 of this application. Figure 16 This example provides a display driver circuit composed of a combination of N-type thin-film transistors (e.g., LTPO TFTs) and P-type thin-film transistors (e.g., LTPS TFTs), including: an output module 100, and a scan control module 101 composed of P-type thin-film transistors. In one embodiment, the output module 100 may include two first-level control units 103, a second-level control unit 104, a third-level control unit 105, an isolation unit 106, a stage transfer unit 107, and a fifth-level control unit 109. The difference between the output module 100 of this example and the output module 100 of Example 4 is that the two first-level control units 103 and the fifth-level control unit 109 both include N-type thin-film transistors. Therefore, the transistor type configuration in the display driver circuit of this example is exactly the opposite of the transistor type configuration of the display driver circuit provided in Example 4.

[0126] Thus, compared with the display driving circuit of Example 2, the display driving circuit of this example does not need to construct a second control node Q2n with a voltage level opposite to that of the first control node Q1n to control the node pull-up; the display driving circuit of this example configures the transistors in the two first level control units 103 and the fifth level control unit 109 for implementing pull-up control as N-type thin film transistors (for example, LTPO TFTs), and directly uses the first control node Q1n to control the N-type thin film transistors, thereby completing the pull-up. The operating timing of the display driving circuit of this example can refer to the operating timing of Example 2 (see Figure 13 ).

[0127] An embodiment of the present application also provides a display device, including a display panel and at least one display driving circuit as described in any one of the above embodiments, each display driving circuit is electrically connected to the display panel to output a driving signal to drive the horizontal scan line in the display panel.

[0128] In one embodiment, multiple display driver circuits are connected via a multi-stage transmission method and are used to drive all or some of the pixel rows within a display panel. Each display driver circuit is used to generate a first drive signal and a second drive signal for driving two pixel rows. In one embodiment, the phase difference between the drive signals for adjacent pixel rows within the display panel is T / 8.

[0129] In one embodiment, the display device may be a display device for in-cell touch LCD display applications. In-cell touch LCD is a technology that integrates a touch sensor into a liquid crystal display (LCD).

[0130] The technical features of the above-described embodiments can be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above description is only a specific embodiment of the present application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of this application.

Claims

1. A display driving circuit, characterized in that: include: Scan control module and output module; The scanning control module includes a symmetrically arranged forward control unit, a reverse control unit and a first control node; The forward control unit includes a first transistor and a first leakage protection module, wherein the first path end of the first transistor is used to receive a forward scanning voltage, the second path end of the first transistor is connected to the first control node, and the first leakage protection module is connected to the first path end of the first transistor and / or the first control node; The reverse control unit includes a second transistor and a second leakage protection module, wherein the first path end of the second transistor is used to receive a reverse scan voltage, the second path end of the second transistor is connected to the first control node, and the second leakage protection module is connected to the first path end of the second transistor and / or the first control node; The forward control unit and the reverse control unit are configured to enable the scan control module to implement forward and reverse scan functions according to the signals input to the control terminals of the transistors, and output a first control signal to the output module through the first control node; The output module is used to perform pull-up control and / or pull-down control according to the first control signal to output a driving signal.

2. The display driving circuit according to claim 1, wherein: The output module includes a level maintaining unit; the level maintaining unit includes an inverter and a second control node; the inverter is used to perform level maintenance control according to the first control signal in a non-display phase to output a second control signal through the second control node, so that the driving signal output by the output module is maintained in a low level state or a high level state; and / or, The output module includes a first level control unit; the first level control unit is used to perform one of the pull-up control and the pull-down control according to the second control signal output by the level maintaining unit, so that the output module outputs the driving signal representing one of the low level and the high level; and / or, The output module includes a stage transmission unit; the stage transmission unit includes a third transistor, the control end of the third transistor is connected to the first control node to receive the first control signal, the first path end of the third transistor receives the first clock control signal, and the second path end of the third transistor outputs the stage transmission signal.

3. The display driving circuit according to claim 2, wherein: The output module includes at least two first level control units; The output module further includes a second level control unit, a first output node, a third level control unit, a second output node and an isolation unit; The isolation unit is used to isolate the control signals of the second level control unit and the third level control unit; When one of the at least two first level control units is used to perform one of the pull-up control and the pull-down control, the at least two first level control units output a first drive signal representing one of a low level and a high level to the first output node; when the second level control unit is used to perform the other of the pull-up control and the pull-down control, the at least two first level control units output a first drive signal representing the other of the low level and the high level to the first output node; When the other of the at least two first level control units is used to perform one of the pull-up control and the pull-down control, the at least two first level control units output a second drive signal representing one of a low level and a high level to the second output node; when the third level control unit is used to perform the other of the pull-up control and the pull-down control, the at least two first level control units output a second drive signal representing the other of a low level and a high level to the second output node; The first driving signal and the second driving signal are respectively used to drive two adjacent levels of horizontal scan lines in the display panel.

4. The display driving circuit according to claim 2, wherein: The output module further includes a fourth level control unit connected to the first control node and the second control node, and configured to adjust the level of the first control signal output by the first control node according to the second control signal output by the level maintaining unit.

5. The display driving circuit according to any one of claims 1 to 4, characterized in that: The first leakage protection module includes a fourth transistor and a fifth transistor, wherein a control terminal of the fourth transistor receives a second clock control signal, and a first channel terminal of the first transistor receives the positive scanning voltage through a channel formed with the fourth transistor, a control terminal of the fifth transistor is connected to the first control node, a first channel terminal of the fifth transistor receives a first reference voltage, and a second channel terminal of the fifth transistor is connected to the channel between the first transistor and the fourth transistor; and / or, The second leakage protection module includes a sixth transistor and a seventh transistor, wherein a control terminal of the sixth transistor receives the second clock control signal, and a first channel terminal of the second transistor receives the reverse scan voltage via a channel formed with the sixth transistor, a control terminal of the seventh transistor is connected to the first control node, a first channel terminal of the seventh transistor receives the first reference voltage, and a second channel terminal of the seventh transistor is connected to the channel between the second transistor and the sixth transistor; and / or, The inverter includes a single-stage inverter and a source follower cascaded therewith, and the level maintaining unit further includes a second control node; wherein the single-stage inverter includes an eighth transistor and a ninth transistor, the control terminal of the eighth transistor receives the first reference voltage or is connected to the first control node, the first channel terminal of the eighth transistor receives the first reference voltage, the second channel terminal of the eighth transistor is connected to the first channel terminal of the ninth transistor, the second channel terminal of the ninth transistor receives the second reference voltage, and the control terminal of the ninth transistor is connected to the first control node; wherein, The source follower includes a tenth transistor and an eleventh transistor, the control terminal of the tenth transistor is connected to the second path terminal of the eighth transistor, the first path terminal of the tenth transistor receives the first reference voltage, the second path terminal of the tenth transistor is connected to the second control node, the control terminal of the eleventh transistor is connected to the first control node, the first path terminal of the eleventh transistor is connected to the second control node, and the second path terminal of the eleventh transistor receives the second reference voltage; wherein, the first reference voltage is one of the reference high voltage and the reference low voltage, and the second reference voltage is the other of the reference high voltage and the reference low voltage.

6. The display driving circuit according to claim 5, wherein: The fourth level control unit includes a twelfth transistor and a third leakage protection module; The control terminal of the twelfth transistor is connected to the second control node of the level maintaining unit to receive the second control signal, the first pass terminal of the twelfth transistor is connected to the first control node, and the second pass terminal of the twelfth transistor is used to receive the second reference voltage; The third leakage protection module includes a thirteenth transistor and a fourteenth transistor, the control end of the thirteenth transistor receives the second clock control signal, and the second path end of the twelfth transistor receives the second reference voltage through the path formed with the thirteenth transistor, the control end of the fourteenth transistor is connected to the first control node, the first path end of the fourteenth transistor receives the first reference voltage, and the second path end of the fourteenth transistor is connected to the path between the twelfth transistor and the thirteenth transistor.

7. The display driving circuit according to claim 5, wherein: The second level control unit includes a fifteenth transistor, a first capacitor, and a first output node, wherein the control terminal of the fifteenth transistor is connected to the first control node, and the control terminal of the fifteenth transistor is also connected to the first output node via the first capacitor, a first pass terminal of the fifteenth transistor receives a first clock control signal, and a second pass terminal of the fifteenth transistor is connected to the first output node; a first level control unit connected to the first output node including an eighteenth transistor, a control terminal of the eighteenth transistor connected to the second control node to receive the second control signal, a first pass terminal of the eighteenth transistor connected to the first output node, and a second pass terminal of the eighteenth transistor receiving the second reference voltage; The third level control unit includes a sixteenth transistor, a second capacitor, and a second output node, wherein the control terminal of the sixteenth transistor is connected to the second output node via the second capacitor, the first channel terminal of the sixteenth transistor receives a third clock control signal, and the second channel terminal of the sixteenth transistor is connected to the second output node; a first level control unit connected to the second output node including a nineteenth transistor, wherein a control terminal of the nineteenth transistor is connected to the second control node to receive the second control signal, a first pass terminal of the nineteenth transistor is connected to the second output node, and a second pass terminal of the nineteenth transistor receives the second reference voltage; The isolation unit includes a seventeenth transistor, a control terminal of the seventeenth transistor receives the first reference voltage, a first pass terminal of the seventeenth transistor is connected to the control terminal of the fifteenth transistor, and a second pass terminal of the seventeenth transistor is connected to the control terminal of the sixteenth transistor; The capacitance value of the first capacitor is greater than 0 and less than or equal to 500 fF, and the capacitance value of the second capacitor is greater than 0 and less than or equal to 300 fF.

8. The display driving circuit according to claim 7, wherein: The display driving circuit uses an eight-phase clock to provide clock control signals; and / or, Among the eight-phase clocks, the kth clock is T / 8 ahead of the k+1th clock, where 1≤k<8; and / or, The duty cycle of the high level in each clock control signal is T / 4; and / or, The phase difference between the first driving signal and the second driving signal is T / 8.

9. A display device, characterized in that: The device comprises a display panel and at least one display driving circuit according to any one of claims 1 to 8, wherein each display driving circuit is electrically connected to the display panel to output a driving signal to drive a horizontal scan line in the display panel.

10. The display device according to claim 9, wherein The plurality of display driving circuits are connected in a multi-stage transmission manner, and the plurality of display driving circuits are used to drive all or part of the pixel rows in the display panel; Each of the display driving circuits is used to generate a first driving signal and a second driving signal for driving two pixel rows; Wherein, the phase difference between the driving signals of adjacent pixel rows in the display panel is T / 8.

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