DDR test signal detection method, apparatus and device, and computer readable storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses a DDR test signal detection method, device and equipment and a computer readable storage medium. According to the method, test commands in test signals of different DDR chips can be converted to obtain target test commands in a unified format, then a starting test command and an ending test command are determined in the target test commands according to target time sequence parameters, a target measurement mode is determined according to the starting test command and the ending test command, and the test accuracy is improved. Measuring a time sequence parameter measurement value according to the target measurement mode; therefore, different detection modules do not need to be switched when test signals of different types of DDR chips are measured, commands of different DDR types are converted to unify command formats and determine corresponding measurement modes for detection, time sequence parameter measurement methods of different DDR chips can be unified, and time sequence parameter measurement schemes are simplified.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present invention claims priority to patent application number CN118588153A filed with the Patent Office of China on June 12, 2024, entitled “DFI interface signal detection method, device and storage medium in DDR chip testing”, and claims priority to patent application number CN119007797A filed with the Patent Office of China on August 6, 2024, entitled “A DDR timing parameter measurement method, device, system, medium and product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of chip testing technology, and in particular to a DDR test signal detection method, apparatus, device, and computer-readable storage medium. Background Art

[0004] During the DDR chip testing process, ensuring that the test signals are error-free is a necessary condition for ensuring test accuracy. Therefore, it is necessary to detect the signal sequence used for DDR chip testing.

[0005] However, since different types of DDR chips have different internal structures and test signals, when testing the test signals of different types of DDR chips, different testing equipment needs to be switched for each type of DDR chip for separate testing, which makes the testing of the test signals of DDR chips more complicated. Summary of the Invention

[0006] In view of this, the purpose of this application is to overcome the deficiencies in the prior art and provide a DDR test signal detection method, characterized in that the method is applied to a test device, the test device comprising: a processor, a DDR controller, a DFI interface, a port physical layer for connecting to a DDR chip to be tested, and a detection module, the processor, the DDR controller, the DFI interface, and the port physical layer being connected in sequence, the DFI interface being further connected to the detection module, the method comprising:

[0007] In the process of sending the test signal to the DDR chip to be tested, inputting the test signal into the detection module from the DFI interface;

[0008] According to the type of the DDR chip to be tested, the test command in the test signal is converted to obtain a target test command;

[0009] Determining a start test command and an end test command in the target test command according to the target timing parameter based on the detection module, determining a target measurement mode based on the start test command and the end test command, and measuring a measurement value of the target timing parameter according to the target measurement mode;

[0010] Detecting a command sequence of the test commands in the test signal based on the detection module;

[0011] A detection result of the test signal is determined according to the timing parameter measurement value and the command sequence.

[0012] The present application further provides a DDR test signal detection device, characterized in that the DDR test signal detection device comprises:

[0013] An input module, configured to input the test signal into the detection module from the DFI interface during the process of sending the test signal to the DDR chip to be tested;

[0014] A conversion module, configured to convert the test command in the test signal according to the type of the DDR chip to be tested to obtain a target test command;

[0015] a measurement module, configured to determine a start test command and an end test command in the target test command according to a target timing parameter based on the detection module, determine a target measurement mode based on the start test command and the end test command, and measure a measurement value of the target timing parameter according to the target measurement mode;

[0016] a detection module, configured to detect a command sequence of the test commands in the test signal based on the detection module;

[0017] A determination module is used to determine a detection result of the test signal according to the measured value of the target timing parameter and the command sequence.

[0018] The present application also provides a computer device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the above-mentioned DDR test signal detection method.

[0019] The present application also provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and when the computer program is run on a processor, the above-mentioned DDR test signal detection method is executed.

[0020] The embodiments of the present application have the following beneficial effects:

[0021] The method can convert test commands in test signals of different DDR chips to obtain target test commands in a unified format, further determine a start test command and an end test command in the target test command according to target timing parameters, determine a target measurement method according to the start test command and the end test command, and further measure timing parameter measurement values ​​according to the target measurement method. When measuring test signals of different types of DDR chips, there is no need to switch different detection modules, but commands of different DDR types are converted to a unified command format, and corresponding measurement methods are determined for detection. This can unify the timing parameter measurement methods of different DDR chips and simplify the timing parameter measurement scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solution of this application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be considered as limiting the scope of protection of this application. Those skilled in the art can also derive other relevant drawings based on these drawings without inventive effort.

[0023] Figure 1 is a first structural schematic diagram of the test equipment provided by this application;

[0024] Figure 2 1 is a schematic diagram of a first embodiment of a DDR test signal detection method provided by the present application;

[0025] Figure 3 is a second structural schematic diagram of the test equipment provided by this application;

[0026] Figure 4 2 is a schematic diagram of a second embodiment of a DDR test signal detection method provided by the present application;

[0027] Figure 5 This is a schematic diagram of the distribution structure of the storage matrix group in the DDR chip to be tested provided by this application;

[0028] Figure 6 This is a schematic diagram of the distribution structure of the memory matrix in the DDR chip to be tested provided by this application;

[0029] Figure 7 2 is a schematic diagram of a third embodiment of a DDR test signal detection method provided by the present application;

[0030] Figure 8 2 is a schematic diagram of a fourth embodiment of a DDR test signal detection method provided by the present application;

[0031] Figure 9 This is a schematic diagram of the clock frequency ratio between the DFI interface and the DDR chip under test provided by this application;

[0032] Figure 10 2 is a schematic diagram of a fifth embodiment of a DDR test signal detection method provided by the present application;

[0033] Figure 11 This is a schematic diagram of different measurement results presented within the same DFI clock provided by this application;

[0034] Figure 12 2 is a schematic diagram of a sixth embodiment of a DDR test signal detection method provided by the present application;

[0035] Figure 13 is a third structural schematic diagram of the test equipment provided by this application;

[0036] Figure 14 It is a structural diagram of the DDR test signal detection device provided in this application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0038] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0039] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0040] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0042] It is understood that the method of the present application is applied to test equipment, such as Figure 1 As shown, the test equipment includes: a processor, a DDR controller, a DFI interface, a port physical layer for connecting to the DDR chip to be tested, and a detection module. The processor, DDR controller, DFI interface and port physical layer are connected in sequence, and the DFI interface is also connected to the detection module.

[0043] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0044] Please refer to Figure 2 , Figure 2 : is a flow chart of a first embodiment of a DDR test signal detection method provided by the present application, the method comprising:

[0045] Step S101: In the process of sending a test signal to the DDR chip to be tested, the test signal is input into the detection module from the DFI interface.

[0046] In this embodiment, after the test device is connected to the DDR chip to be tested, the processor of the test device will generate a corresponding test signal. The test signal will pass through the DDR controller, DFI interface and port physical layer in sequence to be input into the DDR chip to be tested. During this process, the test device also inputs the test signal from the DFI interface into the detection module so that the detection module can detect the test signal.

[0047] Step S102 : converting the test command in the test signal according to the type of the DDR chip to be tested to obtain a target test command.

[0048] In this embodiment, after the test device inputs a test signal from the DFI interface into the detection module, the test device converts the test command in the test signal based on the type of the DDR chip to be tested, obtaining a target test command. It will be appreciated that the target test command obtained by the test device through conversion of the test command in the test signal can be expressed using the same command format for test commands of different types of DDR chips, facilitating subsequent testing of test commands of test signals from different types of DDR chips using the same detection module.

[0049] For example, refer to Figure 3 The detection module includes a timing parameter measurement unit, which converts the test command in the received test signal to obtain a target test command.

[0050] Step S103 , determining a start test command and an end test command in the target test command based on the target timing parameter based on the detection module, determining a target measurement mode based on the start test command and the end test command, and measuring a measurement value of the target timing parameter according to the target measurement mode.

[0051] In this embodiment, the measuring device determines a start test command and an end test command in the target test command based on the target timing parameters, determines a target measurement mode based on the start test command and the end test command, and measures the target timing parameter value based on the target measurement mode. It should be noted that the target timing parameters may include timing parameters between the same test command and timing parameters between different test commands.

[0052] In one embodiment, after receiving the target test command, the test device uses a detection module to determine the starting test command type and the ending test command type corresponding to the target timing parameter within a preset timing parameter measurement standard. It is understood that the target timing parameter may be input into the test device by a tester, and the test device may determine the starting test command type and the ending test command type corresponding to the target timing parameter based on the preset timing parameter measurement standard.

[0053] In one embodiment, after determining the start test command type and end test command type corresponding to the target timing parameters, the test device determines a start test command within the target test command based on the start test command type, and determines an end test command within the target test command based on the end test command type. It will be appreciated that the start test command and end test command determined by the test device within the target test command are converted and formatted in a unified format. This helps standardize the test command formats for different DDR chips and simplifies timing parameter measurement solutions.

[0054] In one embodiment, the target test commands generally include: read command, write command, activate command, precharge command, refresh command, etc.; the target timing parameters include: tRCD, tRAS, tRPpb, tRPab, tWR, tRTP, tRFCpb, tRFCsb, tRFCab, tREFIpb, tREFIsb, tREFIab, tFAW, tRRD, etc.; wherein, tRCD refers to the time interval between issuing an activate command and issuing a read command or a write command, tRAS refers to the time interval between issuing an activate command and issuing a precharge command, tRP refers to the time interval between issuing a precharge command and issuing an activate or refresh command, tWR refers to the time interval between the end of issuing a write command and the ability to issue a precharge command for the same row, tRTP refers to the time interval from the completion of a read operation to the precharge command, and tRFC refers to the time interval from issuing a The time interval between a refresh command and the completion of the refresh operation, allowing the next command (such as an activate command or refresh command) to be accepted. tREFI refers to the average time interval between refresh commands. It is typically calculated by counting 1,000 to 10,000 refresh commands. tFAW defines the maximum time window within which up to four activate commands can be executed on different banks within the same memory channel. tRRD refers to the interval between two consecutive activate commands. In the timing parameter type, pb stands for perbank, meaning the test command applies to one bank. sb stands for samebank, meaning the test command applies to banks with the same bank number within each bank group. ab stands for allbank, meaning the test command applies to all banks in the DDR chip. For example, if the target timing parameter is tRFCab, the starting test command is a refresh command, and the ending test command is a new refresh or activate command.

[0055] For example, refer to Figure 3 The detection module includes a timing parameter measurement unit, which converts the test command in the received test signal to obtain a target test command, and then determines the start test command and the end test command in the target test command according to the target timing parameter, determines the target measurement method based on the start test command and the end test command, and measures the measurement value of the target timing parameter according to the target measurement method.

[0056] Step S104: detecting a command sequence of the test commands in the test signal based on the detection module.

[0057] In this embodiment, the test device detects the command sequence of the test commands in the test signal based on the detection module; it can be understood that the order of the test commands in the test signal is also an important factor affecting the DDR test, so the command sequence of the test commands needs to be detected.

[0058] The order between test commands is detected, primarily to determine whether the order between test commands meets the order requirements specified in the JEDEC standard. For example, the JEDEC standard stipulates that an activate command must precede a read / write command, and that a refresh command cannot be sent directly after a read / write command. A refresh command can only be sent after waiting for a precharge command and then placing the memory in an idle state. In a test signal segment, the commands included are, in order, an activate command, a write command, and a refresh command. Since a refresh command is sent after the write command, but not a precharge command, this does not conform to the order specified in the JEDEC standard. Therefore, it can be determined that the order between the read / write command and the refresh command in the DFI interface signal sequence does not meet the order requirements specified in the JEDEC standard.

[0059] Exemplary, reference Figure 3 The detection module also includes a command sequence detection unit. After the detection module converts the test command received in the test signal through the timing parameter measurement unit to obtain the target test command, the target test command is sent to the command sequence detection unit. The command sequence detection unit can detect the command sequence of the test commands in the test signal.

[0060] Step S105 : determining a detection result of the test signal according to the timing parameter measurement value and the command sequence.

[0061] In this embodiment, after obtaining the timing parameter measurement values ​​and command sequence corresponding to the test signal, the test equipment may compare the timing parameter measurement values ​​and command sequence with the corresponding timing parameter standard range and command standard sequence to thereby determine the test signal detection result. For example, if the timing parameter measurement values ​​do not fall within the timing parameter standard range, the test signal detection result is determined to be abnormal; if the command sequence differs from the command standard sequence, the test signal detection result is determined to be abnormal.

[0062] The test device of this embodiment converts test commands in test signals of different DDR chips to obtain target test commands in a unified format. A start test command and an end test command are then determined in the target test command based on target timing parameters. A target measurement method is then determined based on the start test command and the end test command. Timing parameter values ​​are then measured based on the target measurement method. This eliminates the need to switch between different detection modules when measuring test signals of different types of DDR chips. Instead, commands of different DDR types are converted to a unified command format, and corresponding measurement methods are determined for detection. This unifies the timing parameter measurement methods for different DDR chips and simplifies the timing parameter measurement solution.

[0063] Please refer to Figure 4 , Figure 4 : This is a flow chart of a second embodiment of the DDR test signal detection method provided by the present application. The difference between the second embodiment and the first embodiment is that the step of converting the test command in the test signal according to the type of the DDR chip to be tested to obtain the target test command includes:

[0064] Step S201: Determine whether a storage matrix group is divided in the internal structure of the DDR chip to be tested according to the type of the DDR chip to be tested.

[0065] In this embodiment, the test equipment determines whether the internal structure of the DDR chip to be tested is divided into storage matrix groups according to the type of the DDR chip to be tested. Specifically, the types of DDR chips include DDR1, DDR2, DDR3, DDR4, DDR5, LPDDR4, LPDDR5, etc. Among them, the internal structures of DDR4, DDR5, and LPDDR5 (BG mode) are divided into storage matrix groups, and the internal structures of DDR1, DDR2, DDR3, LPDDR4, and LPDDR5 (non-BG mode) are not divided into storage matrix groups. LPDDR5 has three structural modes: BG mode and bank group mode. There are two types of non-BG modes, namely 8B mode: there are 8 banks and no bank group and 16B mode: there are 16 banks and no bank group.

[0066] For example, refer to Figure 5 , Figure 5 This is a schematic diagram showing the internal structure of a DDR chip divided into memory matrix groups. A bank is a memory matrix of the DDR chip, and every four memory matrices form a memory matrix group, for a total of eight memory matrix groups numbered 0-7.

[0067] Step S202: If storage matrix groups are divided, the storage matrix group number, the storage matrix number within the group, and the storage matrix range to which the test command in the test signal applies are identified, and the storage matrix group number, the storage matrix number within the group, and the storage matrix range are converted to obtain a target test command in a unified format.

[0068] In this embodiment, if the test device determines that the internal structure of the type of DDR chip to be tested is divided into memory matrix groups, it identifies the memory matrix group number, the memory matrix number within the group, and the memory matrix range to which the test command in the test signal acts, and converts the memory matrix group number, the memory matrix number within the group, and the memory matrix range according to the preset conversion rules to obtain a target test command in a unified format. It should be noted that, with reference to Figure 5 The memory matrix group number is one of memory matrix groups 0 to 7, and the memory matrix numbers within a group are one of Bank 0 to Bank 3. Memory matrix ranges include perbank, samebank, and allbank. Perbank means the test command is scoped to a single memory matrix. Samebank means the test command is scoped to memory matrices with the same memory matrix number within each memory matrix group. For example, the test command is scoped to Bank 3 in each memory matrix group from 0 to 7. Allbank means the test command is scoped to all memory matrices of the DDR chip under test.

[0069] It can be understood that the test command is an activation command. When the storage matrix group on which the activation command acts is numbered storage matrix group 0, the storage matrix in the group is numbered Bank3, and the storage matrix range is perbank, that is, the activation command only acts on the storage matrix numbered Bank3 in storage matrix group 0.

[0070] It can be understood that the test command is an activation command, and the storage matrix group number it acts on is storage matrix group 0, the storage matrix number within the group is Bank3, and the storage matrix range is perbank. The corresponding conversion processing is performed according to the preset conversion rules so that this information is expressed in binary data. In the target activation command, storage matrix group 0 is represented as 000, the storage matrix number Bank3 within the group is represented as 11, and the storage matrix range perbank is represented as 01.

[0071] It should be noted that the target test command includes the following information:

[0072] 1. Command valid indication (command_valid) high level is valid

[0073] 2. Command type (commandtype, indicating the type of command, supports a total of 256 commands, which can be expanded)

[0074] 3. Rank number (can be simply understood as the number of different memory sticks)

[0075] 4. CID number (used for 3D stacked DDR chips to identify different layers of the chip)

[0076] 5. Bankscope (perbank, samebank or allbank)

[0077] 6. Equivalent bank number (combining the results of bankgroup number and bank number)

[0078] Specifically, the step of converting the storage matrix group number, the storage matrix number within the group, and the storage matrix range includes:

[0079] Step S2021: Obtain the number of storage matrices in each storage matrix group in the DDR chip to be tested.

[0080] In this embodiment, the test device obtains the number of memory matrices within each memory matrix group in the DDR chip under test. For example, the internal structures of DDR4, DDR5, and LPDDR5 are divided into memory matrix groups. DDR4 has four memory matrices within each memory matrix group, DDR5 has two to four memory matrices within each memory matrix group, and LPDDR5 has four memory matrices within each memory matrix group in BG mode (bank group).

[0081] Step S2022: Calculate the equivalent storage matrix number to which the test command acts according to the number of storage matrices, the storage matrix group number, and the storage matrix number within the group.

[0082] In this embodiment, the test device calculates the equivalent memory matrix number affected by the test command based on the number of memory matrices, the memory matrix group number, and the memory matrix number within the group. Specifically, the formula for calculating the equivalent memory matrix number is: equivalent memory matrix number = (memory matrix group number * number of memory matrices) + memory matrix number within the group. For example, if a test command affects a memory matrix group numbered as memory matrix group 3, with a memory matrix number within the group as Bank 3, and each memory matrix group in the DDR chip under test contains four memory matrices, the equivalent memory matrix number affected by the test command is 3 * 4 + 3 = 15.

[0083] Step S2023: Based on a preset rule, the storage matrix range is converted into a binary-based range parameter, and the equivalent storage matrix number is converted into a binary-based number parameter.

[0084] In this embodiment, after determining the equivalent storage matrix number, the test device converts the storage matrix range into a binary-based range parameter and the equivalent storage matrix number into a binary-based number parameter based on a preset rule. The binary-based range parameter refers to the conversion of the storage matrix range representation into a binary data form, and the binary-based number parameter refers to the conversion of the equivalent storage matrix number into a binary data form.

[0085] For example, the binary-based numbering parameter of the equivalent storage matrix number conversion is equivalent_bank, which is a binary number with a bit width of 5 bits, that is, equivalent_bank consists of 5 bits, equivalent_bank[4] to equivalent_bank[0], which is generated by the following method:

[0086] 1. If it is DDR4 or DDR5, because they both have storage matrix group numbers and storage matrix numbers within the group, then equivalent_bank is composed of the storage matrix group number and the storage matrix number within the group;

[0087] There are 2-4 memory matrix groups in DDR4. For DDR4: equivalent_bank = {1'b0, BG[1:0], BANK[1:0]}; where 1'b0 is a 1-bit binary number 0; BG[1:0] and BANK[1:0] are both two-bit binary numbers; when the memory matrix group affected by the test command is memory matrix group 3, and the memory matrix in the group is numbered Bank3, then equivalent_bank = 01111.

[0088] There are 4-8 memory matrix groups in DDR5. For DDR5: equivalent_bank[4:0] = {BG[2:0], BANK[1:0]}, where BG[2:0] is a three-digit binary number and BANK[1:0] is a two-digit binary number. When the memory matrix group affected by the test command is memory matrix group 7 and the memory matrix in the group is numbered Bank2, then equivalent_bank = 11110.

[0089] 2. If it is LPDDR5, LPDDR5 includes 4 storage matrix groups in BG mode (bankgroup), and each storage matrix group has 4 banks), then for LPDDR5: equivalent_bank = {1'b0, BG[1:0], BANK[1:0]}, when the storage matrix group numbered by the test command is storage matrix group 1, and the storage matrix number within the group is Bank1, then equivalent_bank = 00101.

[0090] Exemplarily, when the storage matrix range is converted into a binary-based range parameter, the binary-based range parameter of perbank is 01, the binary-based range parameter of samebank is 10, and the binary-based range parameter of allbank is 11.

[0091] Step S203: If no storage matrix group is divided, the storage matrix number and storage matrix range of the test command in the test signal are identified, and the storage matrix number and the storage matrix range are converted to obtain a target test command in a unified format.

[0092] In this embodiment, if the test device determines that the internal structure of the type of DDR chip to be tested does not have a memory matrix group, it identifies the memory matrix number and memory matrix range to which the test command in the test signal applies, and converts the memory matrix number and memory matrix range according to a preset conversion rule to obtain a target test command in a unified format. Figure 6 The memory matrix group number is one of Bank0 to Bank31. The memory matrix range includes perbank and allbank. Perbank means that the test command is scoped to a single memory matrix, while allbank means that the test command is scoped to all memory matrices of the DDR chip under test.

[0093] It should be noted that if it is DDR1 to DDR3, equivalent_bank is the binary expression of the storage matrix number; when the storage matrix number affected by the test command is Bank3, equivalent_bank = 00011; when the storage matrix number affected by the test command is Bank31, equivalent_bank = 11111.

[0094] In this way, after processing, unified equivalent BANK information is obtained, which greatly reduces the number of banks that need to be processed (from 128 to 32), thereby reducing the scale of the design and thus reducing the hardware cost.

[0095] The test device of this embodiment converts the test commands in the test signal of the DDR chip to be tested into a unified format of binary data according to the type of the DDR chip to be tested. This allows the detection module in the test device to identify the test signals of different types of DDR chips, avoids switching different detection devices to identify the test signals, and simplifies the design.

[0096] Please refer to Figure 7 , Figure 7 2 is a flow chart of a third embodiment of the DDR test signal detection method provided in the present application. The third embodiment differs from the first to second embodiments in that the step of determining a target measurement mode based on the start test command and the end test command, and measuring the measurement value of the target timing parameter according to the target measurement mode, includes:

[0097] Step S301 : If the start test command and the end test command are different, a first target measurement mode is determined according to a storage matrix range affected by the start test command, and a measurement value of the target timing parameter is measured according to the first target measurement mode.

[0098] In this embodiment, after the test device determines a start test command and its corresponding end test command based on the detection module, if the start test command and the end test command are different, a first target measurement mode is determined based on the memory matrix range affected by the start test command, and the target timing parameter measurement value is measured according to the first target measurement mode. Specifically, the memory matrix range affected by the test command can be one of perbank, samebank, and allbank. For each memory matrix range, there is a corresponding first target measurement mode for measuring the timing parameter measurement value between the start test command and the end test command. Specifically, since the test commands can be issued multiple times and the DDR chip to be tested contains a maximum of 32 banks, for the perbank test command, the detection module can simultaneously support the measurement of the timing parameter measurement values ​​between the test commands for up to 32 banks and the corresponding end test commands, that is, one counter is used for each bank, and up to 32 counters are activated at the same time; since the DDR5 chip to be tested usually contains a maximum of 4 banks in each storage matrix group (bankgroup), for the samebank test command, the detection module can simultaneously support the measurement of the timing parameter measurement values ​​between the test commands for up to 4 samebanks and the corresponding end test commands, that is, one counter is used for the banks with the same number in each storage matrix group, and up to 4 counters are activated at the same time; for the allbank test command, since these instructions are for all storage matrices, only one counter is required at this time.

[0099] For example, tRCD refers to the time interval between issuing an activate command and issuing a read or write command. The activate command affects the memory matrix range per bank, affecting bank 3 in the DDR chip under test. At this time, when the detection module receives the activate command, it activates the counter corresponding to bank 3. After receiving a subsequent read or write command for bank 3, the counter is stopped. The measured value of tRCD can be determined based on the counter's count value, the DFI phase when the activate command is received, and the DFI phase when the read or write command is received. If a read or write command other than bank 3 is received, the counter continues counting until a read or write command for bank 3 is received, at which point the counter stops.

[0100] For example, tRAS refers to the time interval between issuing an activate command and issuing a precharge command. The detection module receives four activate commands, which act on bank 3, bank 7, bank 10, and bank 20 in the DDR chip under test. At this time, the detection module activates the counters corresponding to bank 3, bank 7, bank 10, and bank 20 respectively. When the detection module receives a precharge command acting on all banks, it stops all counters. Based on the count value of each counter, the DFI phase when each activate command is received, and the DFI phase when the precharge command is received, the tRAS measurement value corresponding to the activate instruction acting on each bank can be determined. Furthermore, the maximum and minimum measurement values ​​are screened out from all tRAS measurement values.

[0101] As another example, tRFC refers to the time interval from the issuance of a refresh command to the completion of the refresh operation and the acceptance of the next command (such as an activation command, a refresh command). The detection module receives a refresh command acting on bank3, and the detection module activates the counter corresponding to bank3. When the detection module receives an activation command acting on bank3, a new refresh command acting on bank3, or a new refresh command acting on all storage matrix groups, the counter is stopped. The measured value of tRFCpb can be determined based on the count value of the counter, the DFI phase when the refresh command is received, and the DFI phase when the activation command or precharge command is received.

[0102] As another example, tRFC refers to the time interval from the issuance of a refresh command to the completion of the refresh operation and the acceptance of the next command (such as an activation command or a refresh command). The detection module receives a refresh command acting on all memory matrices in the DDR chip to be tested, and the detection module activates the corresponding counter. When the detection module receives a new refresh command acting on all memory matrix groups, an activation command acting on a certain memory matrix, or a refresh command acting on a certain memory matrix, the counter is stopped. The measured value of tRFCab can be determined based on the count value of the counter, the DFI phase when the refresh command is received, and the DFI phase when the activation command or pre-charge command is received.

[0103] Step S302 : If the start test command and the end test command are the same, a second target measurement mode is determined according to the storage matrix range affected by the start test command, and a measurement value of the target timing parameter is measured according to the second target measurement mode.

[0104] In this embodiment, after the testing device determines the start test command and its corresponding end test command based on the detection module, if the start test command and the end test command are the same, a second target measurement method is determined based on the storage matrix range on which the start test command acts, and the measurement value of the target timing parameter is measured according to the second target measurement method.

[0105] For example, tRRD refers to the interval between two consecutive Activate commands. The interval between two Activate commands in the same bank group is called tRRD-L, and the interval between two Activate commands in different bank groups is called tRRD-S. When the detection module receives an Activate command, it starts a counter and stops it when the next Activate command is detected. The measurement value is determined based on the counter value and the DFI phase between the two received Activate commands. The result is classified as tRRD-L or tRRD-S, depending on whether the two most recent Activate commands belong to the same bank group, to facilitate differentiation.

[0106] For example, tREFI refers to the average time interval between refresh commands. It is usually necessary to count 1000 to 10,000 refresh commands to calculate the average refresh interval. When the detection module receives 1000 refresh commands acting on the perbank, it determines the total duration of receiving 1000 refresh commands, sends the number 1000 and the total duration to the processor of the test equipment, and the processor calculates the measurement value of tREFIpb based on the total duration and number. For example: if the total duration of receiving 1000 refresh commands is 3 seconds, then the measurement value of tREFIpb = 3 / 1000. It should be noted that the measurement process of tREFIsb and tREFIab is the same as the measurement process of tREFIpb, and will not be repeated here.

[0107] The test device of this embodiment uses a detection module to determine the corresponding timing parameter type based on the command type of the start test command, and then determines the end test command. It then determines a measurement method based on the memory matrix range affected by the start test command, and then measures the timing parameter values ​​between the start test command and the end test command based on the measurement method. This allows the detection module in the test device to detect the timing parameters between test commands in the test signals of different types of DDR chips, avoiding the need to switch between different detection devices to detect the test signals, thereby improving the efficiency of testing the test signals of DDR chips.

[0108] Please refer to Figure 8 , Figure 8 This is a flow chart of a fourth embodiment of the DDR test signal detection method provided in the present application. The fourth embodiment differs from the first to third embodiments in that the step of measuring the timing parameter measurement value between the start test command and the end test command according to the first target measurement mode includes:

[0109] Step S401 : If the arrival time of the end test command and the arrival time of the start test command are located at the same DFI clock, determining the measured value of the target timing parameter according to the phase difference between the start test command and the end test command in the DFI interface.

[0110] In this embodiment, if the detection module in the test equipment determines that the arrival time of the end test command and the arrival time of the start test command are located in the same DFI clock, the measurement value of the target timing parameter is determined based on the phase difference between the start test command and the end test command in the DFI clock.

[0111] Specifically, the detection module starts a counter when a target test command arrives and stops the counter when an end test command arrives. The detection module then determines the target timing parameter measurement value based on the phase difference between the start and end test commands in the DFI interface. For example, if the start test command arrives at phase P0 of the DFI interface and the end test command arrives at phase P3 of the DFI interface, the phase difference between the start and end test commands in the DFI clock determines the timing parameter measurement value to be 3tck (tck is the DRAM clock).

[0112] Furthermore, if the detection module in the test equipment determines that the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, the phase of the start test command in its corresponding DFI clock, the phase of the end test command in its corresponding DFI clock, and the count value of the corresponding counter are recorded. Then, based on the phase of the start test command in its corresponding DFI clock, the phase of the end test command in its corresponding DFI clock, the count value of the corresponding counter, and the clock frequency ratio between the DFI interface and the DDR chip under test, the corresponding target timing parameter measurement value is calculated. Specifically, the calculation formula for the target timing parameter measurement value is: timing parameter measurement value = (counter value * clock frequency ratio) + phase of the end test command - phase of the start test command. Among them, the counter count value is increased by 1 every time a DFI clock passes, and the unit of the target timing parameter measurement value is tck (tck is the DRAM clock).

[0113] It should be noted that if Figure 9 As shown, P0 to P3 are the four phases of the DFI interface, and 1 to 8 are the eight test commands sent to the DDR chip under test. Four test commands are sent simultaneously on the DFI interface, while the test commands are sent serially to the DDR chip under test in the order of 1 to 8 at the port physical layer. The clock frequency ratio between the DFI interface and the DDR chip under test is 1:4, meaning the clock frequency of the DDR chip under test is four times that of the DFI interface. For example, if the DFI clock is 300 MHz, the clock of the DDR chip under test (DRAM clock) is 1200 MHz. Four commands are sent simultaneously on the four phases of the DFI interface, meaning each command on the DFI interface takes four times as long as on the DDR chip. Furthermore, the clock frequency ratio between the DFI interface and the DDR chip under test can also be 1:2 or 1:1.

[0114] Specifically, there are many situations in which the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks. The specific steps for different situations are described below:

[0115] Step S402: If the storage matrix range affected by the start test command is the first range, start the counter corresponding to the storage matrix affected by the start test command. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, determine the measurement value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0116] In this embodiment, if the detection module determines that the range of the storage matrix affected by the start test command is the first range, and the first range is perbank, then the detection module starts a counter corresponding to the storage matrix affected by the start test command. When the end test command is received, the counter is stopped and the count value of the counter is recorded. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0117] Exemplarily, the start test command and the end test command both act on bank 3 of the DDR chip under test. The start test command arrives at the P2 phase of the second DFI clock, at which time the counter corresponding to bank 3 is started. The end test command arrives at the P3 phase of the fifth DFI clock, at which time the counter corresponding to bank 3 is stopped and the count value of the counter is recorded. Since three DFI clocks have passed between the second DFI clock and the fifth DFI clock, the count value of the counter is 3. The clock frequency ratio between the DFI interface and the DDR chip under test is 1:4, that is, the clock frequency of the DDR chip under test is four times the DFI clock frequency. Substituting this into the formula, it can be calculated that: the measured value of the target timing parameter = 3*4 + P3-P2 = 3*4 + 1 = 13, the unit is tck (tck is the DRAM clock).

[0118] Step S403: If the storage matrix range affected by the start test command is the second range, start the counter corresponding to the storage matrix with the same number in the storage matrix group affected by the start test command. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, determine the measurement value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0119] In this embodiment, if the detection module determines that the storage matrix range affected by the start test command is the second range and the second range is samebank, then the counter corresponding to the storage matrix with the same number in the storage matrix group affected by the start test command is started. When the end test command is received, the counter is stopped and the count value of the counter is recorded. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0120] Exemplarily, the start test command and the end test command both act on the corresponding bank 1 in each storage matrix group. The start test command arrives at the P0 phase of the first DFI clock, at which time the counter corresponding to bank 1 is started. The end test command arrives at the P3 phase of the second DFI clock, at which time the counter corresponding to bank 1 is stopped and the count value of the counter is recorded. Since the first DFI clock and the second DFI clock are separated by one DFI clock, the count value of the counter is 1. The clock frequency ratio between the DFI interface and the DDR chip to be tested is 1:4, that is, the clock frequency of the DDR chip to be tested is 4 times the DFI clock frequency. Substituting this into the formula, it can be calculated that: the measured value of the target timing parameter = 1*4 + P3 - P0 = 1*4 + 3 = 7, the unit is tck (tck is the DRAM clock).

[0121] Step S404: If the storage matrix range affected by the start test command is the third range, start the counter corresponding to the storage matrix set affected by the start test command. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, determine the measurement value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0122] In this embodiment, if the detection module determines that the storage matrix range affected by the start test command is the third range, and the third range is allbank, then the counter corresponding to the storage matrix set affected by the start test command is started. When the end test command is received, the counter is stopped and the count value of the counter is recorded. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0123] Exemplarily, both the start test command and the end test command act on the storage matrix set. The start test command arrives at the P0 phase of the first DFI clock, at which time the counter corresponding to the storage matrix set is started. The end test command arrives at the P3 phase of the fifth DFI clock, at which time the counter corresponding to the storage matrix set is stopped and the count value of the counter is recorded. Since the first DFI clock and the fifth DFI clock have passed 4 DFI clocks, the count value of the counter is 4. The clock frequency ratio between the DFI interface and the DDR chip to be tested is 1:4, that is, the clock frequency of the DDR chip to be tested is 4 times the DFI clock frequency. Substituting into the formula, it can be calculated: the measured value of the target timing parameter = 4*4+P3-P0=4*4+3=19, the unit is tck (tck is the DRAM clock).

[0124] In particular, if the same command is sent repeatedly several times within the same DFI clock, such as in the following table:

[0125] P0 Same start command (same bank) P1 Same start command (same bank) P2 Same start command (same bank) P3 Same start command (same bank)

[0126] If all four phases are start commands for the same bank, the last P3 phase command is used as the starting point for measurement, and the commands of phases P0 to P2 are considered invalid. For example, if there are four consecutive identical activation commands within the same DFI clock, only the command of phase P3 is valid, and the commands of other phases are invalid.

[0127] Another example is the following table:

[0128] P0 Same end command (same bank) P1 Same end command (same bank) P2 Same end command (same bank) P3 Same end command (same bank)

[0129] If all four phases are end commands for the same bank, the first P0 phase command is used as the measurement endpoint, and the commands of phases P1 to P3 are considered invalid. For example, if there are four consecutive identical pre-charge commands in one beat, only the command of phase P0 is valid, and the commands of other phases are invalid.

[0130] When the test device in this embodiment determines that the command types of the start test command and the end test command are different based on the detection module, different measurement methods are adopted to measure the corresponding timing parameter measurement values ​​according to whether the arrival time of the start test command and the end test command are on the same DFI clock. This can improve the efficiency of the timing parameter measurement. At the same time, different measurement methods are adopted for different situations to avoid using the same measurement method, which can reduce the waste of computing resources.

[0131] Please refer to Figure 10 , Figure 10 This is a flow chart of a fifth embodiment of the DDR test signal detection method provided in the present application. The fifth embodiment differs from the first to fourth embodiments in that the step of measuring the timing parameter measurement value between the start test command and the end test command according to the second target measurement mode includes:

[0132] Step S501: If the arrival time of the end test command and the arrival time of the start test command are in the same DFI clock, the maximum phase difference and / or the minimum phase difference between the start test command and the end test command in the DFI interface are calculated, and the measured value of the target timing parameter is determined based on the maximum phase difference and / or the minimum phase difference.

[0133] In this embodiment, if the test device determines based on the detection module that the arrival time of the end test command and the arrival time of the start test command are located at the same DFI clock, the maximum phase difference and / or minimum phase difference between the start test command and the end test command in the DFI interface is calculated, and the timing parameter measurement value is determined based on the maximum phase difference and / or minimum phase difference.

[0134] Specifically, such as Figure 11 As shown in the table, the corresponding measurement results for 16 different combinations within the same DFI clock are listed. P0 to P3 on the left of the black vertical line represent the four phases, with 1 indicating a command and 0 indicating no command. The two columns to the right of the black vertical line represent the minimum and maximum values ​​of the ranging. Because the four phases of the same beat can have a 1011 case, meaning there are two distances of 1 tck and 2 tck, the maximum value recorded is 2 tck and the minimum value is 1 tck. If it is 1001, the maximum value recorded is 3 tck, and the minimum value is also 3 tck.

[0135] Furthermore, if the detection module in the test equipment determines that the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, the detection module records the phase of the start test command at the DFI interface, the phase of the end test command at the DFI interface, and the count value of the corresponding counter. While recording the count value of the corresponding counter, the counter is restarted for the next count. Then, based on the phase of the start test command at its corresponding DFI interface, the phase of the end test command at its corresponding DFI interface, the count value of the corresponding counter, and the clock frequency ratio between the DFI interface and the DDR chip under test, the corresponding target timing parameter measurement value is calculated. Specifically, the calculation formula for the timing parameter measurement value is: target timing parameter measurement value = (counter value * clock frequency ratio) + phase of the end test command - phase of the start test command. Among them, the counter count value is increased by 1 every time a DFI clock passes, and the unit of the timing parameter measurement value is tck (tck is the DRAM clock).

[0136] Specifically, there are many situations in which the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks. The specific steps for different situations are described below:

[0137] Step S502: If the storage matrix range affected by the start test command is the first range, start the counter corresponding to the storage matrix affected by the start test command; when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, count the count value of the counter and restart the counter; and determine the measured value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0138] In this embodiment, if the detection module determines that the memory matrix range affected by the start test command is the first range, and the first range is perbank, then the detection module starts a counter corresponding to the memory matrix affected by the start test command. When the end test command is received, the counter is stopped and the count value of the counter is recorded. The counter is then restarted for the next count. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0139] For example, both the start test command and the end test command act on bank 3 of the DDR chip under test. The start test command arrives at the P2 phase of the second DFI clock, at which time the counter corresponding to bank 3 is started. The end test command arrives at the P3 phase of the fifth DFI clock, at which time the count value of the counter is recorded and the counter corresponding to bank 3 is restarted for the next count. Since three DFI clocks have passed between the second and fifth DFI clocks, the count value of the counter is 3. The clock frequency ratio between the DFI interface and the DDR chip under test is 1:4, that is, the clock frequency of the DDR chip under test is four times the DFI clock frequency. Substituting this into the formula, it can be calculated that: the measured value of the target timing parameter = 3*4 + P3-P2 = 3*4 + 1 = 13, in units of tck (tck is the DRAM clock).

[0140] Step S503: If the storage matrix range affected by the start test command is the second range, start the counter corresponding to the storage matrix with the same number in the storage matrix group affected by the start test command; when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, record the count value of the counter and restart the counter; and determine the measured value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0141] In this embodiment, if the detection module determines that the memory matrix range affected by the start test command is the second range, and the second range is samebank, then the counter corresponding to the memory matrix with the same number in the affected memory matrix group is started. When the end test command is received, the count value of the counter is recorded, and the counter is restarted for the next count. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0142] Exemplarily, the start test command and the end test command both act on the corresponding bank 1 in each storage matrix group. The start test command arrives at the P0 phase of the first DFI clock, at which time the counter corresponding to bank 1 is started. The end test command arrives at the P3 phase of the second DFI clock, at which time the count value of the counter is recorded, and the counter corresponding to bank 1 is restarted for the next count. Since the first DFI clock and the second DFI clock have passed one DFI clock, the count value of the counter is 1. The clock frequency ratio between the DFI interface and the DDR chip to be tested is 1:4, that is, the clock frequency of the DDR chip to be tested is 4 times the DFI clock frequency. Substituting this into the formula, it can be calculated that: the measured value of the target timing parameter = 1*4 + P3 - P0 = 1*4 + 3 = 7, the unit is tck (tck is the DRAM clock).

[0143] Step S504: If the storage matrix range affected by the start test command is the third range, start the counter corresponding to the storage matrix set affected by the start test command. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, record the count value of the counter and restart the counter at the same time. Determine the measured value of the target timing parameter based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0144] In this embodiment, if the detection module determines that the storage matrix range affected by the start test command is the third range, and the third range is allbank, then the counter corresponding to the storage matrix set affected by the start test command is started. When the end test command is received, the count value of the counter is recorded, and the counter corresponding to the storage matrix set is restarted to perform the next count. The measurement value of the target timing parameter is determined based on the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

[0145] Exemplarily, both the start test command and the end test command act on the storage matrix set. The start test command arrives at the P0 phase of the first DFI clock, at which time the counter corresponding to the storage matrix set is started. The end test command arrives at the P3 phase of the fifth DFI clock, at which time the count value of the counter is recorded, and at the same time, the counter corresponding to the storage matrix set is restarted for the next count. Since the first DFI clock and the fifth DFI clock have passed 4 DFI clocks, the count value of the counter is 4. The clock frequency ratio between the DFI interface and the DDR chip to be tested is 1:4, that is, the clock frequency of the DDR chip to be tested is 4 times the DFI clock frequency. Substituting into the formula, it can be calculated: the measured value of the target timing parameter = 4*4+P3-P0=4*4+3=19, the unit is tck (tck is the DRAM clock).

[0146] In particular, for the timing parameter tFAW (minimum time for 4 activations), the second and third activation commands can be shielded in every four activation commands, and only the first and fourth activation commands are retained to be output to the detection module. The detection module measures the time interval between the first and fourth activation commands.

[0147] For example, the test signal contains eight consecutive activation commands, namely n, n+1, n+2, n+3, n+4, n+5, n+6, and n+7. During the measurement process, for the four commands n, n+1, n+2, and n+3, only the time interval between the two activation commands n and n+3 needs to be measured. For the four commands n+1, n+2, n+3, and n+4, only the time interval between the two activation commands n+1 and n+4 needs to be measured. For the four commands n+2, n+3, n+4, and n+5, only the time interval between the two activation commands n+2 and n+5 needs to be measured. For the four commands n+3, n+4, n+5, and n+6, only the time interval between the two activation commands n+3 and n+6 needs to be measured. For the four commands n+4, n+5, n+6, and n+7, only the time interval between the two activation commands n+4 and n+7 needs to be measured.

[0148] When the test device in this embodiment determines based on the detection module that the command types of the start test command and the end test command are the same, different measurement methods are used to measure the corresponding timing parameter measurement values ​​according to whether the arrival times of the start test command and the end test command are on the same DFI clock, thereby avoiding missed measurements.

[0149] Please refer to Figure 12 , Figure 12This is a flow chart of a sixth embodiment of the DDR test signal detection method provided in the present application. The sixth embodiment differs from the first to fifth embodiments in that the detection module further includes an embedded logic analyzer, and the step of determining the detection result of the test signal based on the timing parameter measurement value and the command sequence includes:

[0150] Step S601: If it is determined based on the analysis of the detection module that the timing parameter measurement value and / or the command sequence do not meet the preset test specification, the detection result of the test signal is determined to be abnormal.

[0151] In this embodiment, after measuring the timing parameter measurement value and / or command sequence, the detection module in the test device analyzes the timing parameter measurement value and / or command sequence. If it is determined that the timing parameter measurement value and / or command sequence does not meet the preset test specifications, the detection result of the test signal is determined to be abnormal.

[0152] Specifically, in the process of measuring timing parameters, the detection module will measure multiple different measurement values ​​for each type of timing parameters. According to preset standards, some timing parameters have corresponding standard value ranges, and some timing parameters have corresponding minimum standard values. For timing parameters with corresponding standard value ranges, it is necessary to select the maximum measurement value and the minimum measurement value from multiple measurement values. Only when the maximum measurement value and the minimum measurement value are both within the standard value range can the detection result of the test signal be determined to be normal, otherwise it is abnormal. For timing parameters with corresponding minimum standard values, the minimum measurement value is selected from multiple measurement values. If the minimum measurement value is greater than the standard minimum value, the detection result of the test signal is determined to be normal, otherwise it is abnormal.

[0153] Step S602 : intercepting a signal waveform corresponding to an abnormal test signal in the test signals, and displaying the waveform based on the embedded logic analyzer.

[0154] In this embodiment, reference Figure 13 The detection module also includes an embedded logic analyzer. The detection module analyzes the timing parameter measurement values ​​and / or command sequence. If it is determined that the timing parameter measurement values ​​and / or command sequence do not meet the preset test specifications, the detection result of the test signal is determined to be abnormal. The detection module triggers the embedded logic analyzer based on the abnormal test signal. The embedded logic analyzer can intercept the signal waveform corresponding to the abnormal test signal in the test signal and display and record it. It should be noted that the embedded logic analyzer will receive and store all waveforms of the test signal sent by the DFI interface.

[0155] It should be noted that the embedded logic analyzer is used to display and record the waveform of the test signal. It can use the signal on the DFI interface (including control signals, data or addresses) to trigger and observe the waveform. It can also use the abnormal signals of the timing parameter results and the abnormal signals of the command sequence to trigger and observe the waveform to locate DDR reading and writing faults.

[0156] It is understandable that for fault location of test signals, especially for locating sporadic faults, the existing method is to first save the waveforms of all test signals, then analyze the waveforms of all test signals by computer, and then determine the abnormal waveforms for fault location. The anomaly can only be found in the waveforms of all test signals. Although the speed of using a computer to analyze waveforms is fast, the large amount of waveform data leads to low efficiency in fault location. In this application, the test equipment first measures the timing parameters and detects the command sequence through the embedded detection module to obtain the measurement results. If the measurement result is an abnormal timing parameter or an abnormal command sequence, the test equipment triggers the embedded logic analyzer to display and record the waveform, which can effectively improve the efficiency of fault location of the test signal.

[0157] The test equipment in this embodiment can analyze the measured timing parameter values ​​and / or command sequences, and then determine the corresponding abnormal test signals, intercept the signal waveform corresponding to the abnormal test signal in the test signal, and display and record it based on it; it can eliminate the need for relevant test personnel to manually find the abnormal location, and can further improve the efficiency of detecting the test signals of the DDR chip.

[0158] It is understandable that Figure 14 As shown, the present application also provides a DDR test signal detection device, the DDR test signal detection device comprising:

[0159] An input module 10, configured to input the test signal into the detection module from the DFI interface during the process of sending the test signal to the DDR chip to be tested;

[0160] The conversion module 20 is used to convert the test command in the test signal according to the type of the DDR chip to be tested to obtain a target test command;

[0161] a measurement module 30 configured to determine a target measurement mode based on the storage matrix range affected by the target test command and the command type of the target test command, and measure timing parameter measurement values ​​between the test commands according to the target measurement mode;

[0162] a detection module 40, configured to detect a command sequence of the test commands in the test signal based on the detection module;

[0163] The determination module 50 is configured to determine a detection result of the test signal according to the timing parameter measurement value and the command sequence.

[0164] The device of this embodiment corresponds to the DDR test signal detection method of the above embodiment. The options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0165] The present application also provides a computer device. Exemplarily, the computer device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the computer device to execute the functions of each module in the above-mentioned DDR test signal detection method or the above-mentioned DDR test signal detection device.

[0166] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0167] The memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0168] The present application also provides a computer storage medium for storing the computer program used in the above-mentioned computer device. The computer storage medium may be a readable storage medium, a non-volatile storage medium, or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0170] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0171] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0172] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A DDR test signal detection method, characterized in that: The method is applied to a test device, which includes: a processor, a DDR controller, a DFI interface, a port physical layer for connecting to a DDR chip to be tested, and a detection module. The processor, the DDR controller, the DFI interface, and the port physical layer are connected in sequence, and the DFI interface is also connected to the detection module. The method includes: In the process of sending the test signal to the DDR chip to be tested, inputting the test signal into the detection module from the DFI interface; According to the type of the DDR chip to be tested, the test command in the test signal is converted to obtain a target test command; Determining a start test command and an end test command in the target test command according to the target timing parameter based on the detection module, determining a target measurement mode based on the start test command and the end test command, and measuring a measurement value of the target timing parameter according to the target measurement mode; Detecting a command sequence of the test commands in the test signal based on the detection module; A detection result of the test signal is determined according to the timing parameter measurement value and the command sequence.

2. The DDR test signal detection method according to claim 1, wherein: The step of converting the test command in the test signal according to the type of the DDR chip to be tested to obtain a target test command includes: Determining whether a storage matrix group is divided in the internal structure of the DDR chip to be tested according to the type of the DDR chip to be tested; If storage matrix groups are divided, identifying the storage matrix group number, the storage matrix number within the group, and the storage matrix range to which the test command in the test signal applies, and converting the storage matrix group number, the storage matrix number within the group, and the storage matrix range to obtain a target test command in a unified format; If no storage matrix group is divided, the storage matrix number and storage matrix range to which the test command in the test signal applies are identified, and the storage matrix number and the storage matrix range are converted to obtain a target test command in a unified format.

3. The DDR test signal detection method according to claim 2, wherein: The step of converting the storage matrix group number, the storage matrix number within the group, and the storage matrix range includes: Obtaining the number of memory matrices in each memory matrix group in the DDR chip to be tested; Calculating an equivalent storage matrix number to which the test command applies based on the number of storage matrices, the storage matrix group number, and the storage matrix number within the group; Based on a preset rule, the storage matrix range is converted into a binary-based range parameter, and the equivalent storage matrix number is converted into a binary-based number parameter.

4. The DDR test signal detection method according to claim 1, wherein: The step of determining a target measurement mode based on the start test command and the end test command, and measuring the measurement value of the target timing parameter according to the target measurement mode includes: If the start test command and the end test command are different, determining a first target measurement mode according to a storage matrix range affected by the start test command, and measuring a measurement value of the target timing parameter according to the first target measurement mode; If the start test command and the end test command are the same, a second target measurement mode is determined according to the storage matrix range affected by the start test command, and the measurement value of the target timing parameter is measured according to the second target measurement mode.

5. The DDR test signal detection method according to claim 4, wherein: The step of measuring the measurement value of the target timing parameter according to the first target measurement method includes: If the arrival time of the end test command and the arrival time of the start test command are located at the same DFI clock, determining the measured value of the target timing parameter according to the phase difference between the start test command and the end test command in the DFI interface; If the storage matrix range affected by the start test command is the first range, starting a counter corresponding to the storage matrix affected by the start test command, and when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, determining a measurement value of the target timing parameter according to a phase of the start test command, a phase of the end test command, a count value of the counter, and a clock frequency ratio between the DFI interface and the DDR chip to be tested; If the storage matrix range affected by the start test command is the second range, starting a counter corresponding to a storage matrix with the same number in the storage matrix group affected by the start test command, and when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, determining a measurement value of the target timing parameter according to a phase of the start test command, a phase of the end test command, a count value of the counter, and a clock frequency ratio between the DFI interface and the DDR chip to be tested; If the storage matrix range affected by the start test command is the third range, the counter corresponding to the storage matrix set affected by the start test command is started. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, the measurement value of the target timing parameter is determined according to the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

6. The DDR test signal detection method according to claim 4, wherein: The step of measuring the measurement value of the target timing parameter according to the second target measurement method includes: If the arrival time of the end test command and the arrival time of the start test command are located at the same DFI clock, calculating the maximum phase difference and / or the minimum phase difference between the start test command and the end test command in the DFI interface, and determining the measured value of the target timing parameter based on the maximum phase difference and / or the minimum phase difference; If the storage matrix range affected by the start test command is the first range, starting a counter corresponding to the storage matrix affected by the start test command; when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, counting the count value of the counter and restarting the counter; and determining the measured value of the target timing parameter according to the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested; If the storage matrix range affected by the start test command is the second range, starting a counter corresponding to a storage matrix with the same number in the storage matrix group affected by the start test command, and when the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, counting the count value of the counter and restarting the counter, and determining the measured value of the target timing parameter according to the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested; If the storage matrix range affected by the start test command is the third range, the counter corresponding to the storage matrix set affected by the start test command is started. When the arrival time of the end test command and the arrival time of the start test command are at different DFI clocks, the count value of the technology device is counted and the counter is restarted. The measurement value of the target timing parameter is determined according to the phase of the start test command, the phase of the end test command, the count value of the counter, and the clock frequency ratio between the DFI interface and the DDR chip to be tested.

7. The DDR test signal detection method according to any one of claims 1 to 6, wherein: The detection module further includes an embedded logic analyzer, and the step of determining the detection result of the test signal according to the timing parameter measurement value and the command sequence includes: If it is determined based on the analysis of the detection module that the timing parameter measurement value and / or the command sequence do not meet the preset test specification, then determining that the detection result of the test signal is abnormal; A signal waveform corresponding to an abnormal test signal in the test signals is intercepted and displayed based on the embedded logic analyzer.

8. A DDR test signal detection device, characterized in that: The DDR test signal detection device comprises: An input module, configured to input the test signal into the detection module from the DFI interface during the process of sending the test signal to the DDR chip to be tested; A conversion module, configured to convert the test command in the test signal according to the type of the DDR chip to be tested to obtain a target test command; a measurement module, configured to determine a target measurement mode based on a storage matrix range affected by the target test command and a command type of the target test command, and measure a timing parameter measurement value between the test commands according to the target measurement mode; a detection module, configured to detect a command sequence of the test commands in the test signal based on the detection module; A determination module is used to determine the detection result of the test signal according to the timing parameter measurement value and the command sequence.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the DDR test signal detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is run on a processor, the DDR test signal detection method according to any one of claims 1 to 7 is executed.

Images