High-reliability soft fully-encapsulated fan-out packaging method

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a high-reliability soft fully-encapsulated fan-out packaging method. Comprising the following steps: providing a slide glass and preparing a rewiring layer on the surface of the slide glass; providing a plurality of functional chips; mounting and interconnecting the plurality of functional chips to the re-wiring layer; coating the plurality of functional chips on the surface of the rewiring layer through a wafer reconstruction technology so as to form a soft reconstructed wafer; the soft reconstruction wafer is made of an epoxy resin or polyimide material; stripping the slide glass, and preparing a conductive bump on the surface of the exposed rewiring layer; cutting the reconstructed wafer to form a plurality of packaging chip structures; encapsulating layers are prepared on the front surfaces and the side surfaces of the plurality of packaging chip structures through a 3D printing technology so as to form a plurality of soft fully-encapsulated fan-out packaging structures; the reliability of the fan-out type packaging structure is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a highly reliable soft full-encapsulation fan-out packaging method. Background Art

[0002] In the post-Moore era, the path of continuously following Moore's Law by increasing chip size or reducing transistor feature size to improve chip performance has basically come to an end. Fan-out advanced packaging with heterogeneous heterogeneous integration has become a new development direction that goes beyond Moore's Law.

[0003] In conventional fan-out packaging structures, the chip surface is covered by redistribution layers such as copper wiring and polyimide dielectric layers, while the back and sides of the chip are encapsulated with plastic. During the chip's service life, water molecules can enter through the interface between different materials, affecting the reliability of the package structure. Furthermore, in conventional silicon-based side encapsulation solutions, trenches are created in the scribe area to fill the encapsulation material, resulting in the thickness of the side encapsulation layer being limited by the scribe width (typical scribe width is 5μm to 80μm). Therefore, to further improve the reliability of conventional fan-out packaging structures, new packaging solutions are needed. Summary of the Invention

[0004] The object of the present invention is to provide a highly reliable soft full-encapsulation fan-out packaging method for improving the reliability of the fan-out packaging.

[0005] To solve the above technical problems, the present invention provides a highly reliable soft full-encapsulation fan-out packaging method, comprising: Providing a carrier wafer and preparing a redistribution layer on the surface of the carrier wafer; Providing a plurality of functional chips; wherein the plurality of functional chips are the same chip or a plurality of different chips; Mounting and interconnecting the plurality of functional chips onto the redistribution layer; The functional chips are coated on the surface of the rewiring layer by wafer reconstruction technology to form a soft reconstruction wafer; the soft reconstruction wafer is made of epoxy resin or polyimide material; Peeling off the carrier sheet, and preparing conductive bumps on the exposed surface of the redistribution layer; cutting the reconstructed wafer to form a plurality of packaged chip structures; Encapsulation layers are prepared on the front and side surfaces of the several packaged chip structures by 3D printing technology to form several soft, fully encapsulated fan-out packaging structures.

[0006] Preferably, the thickness of the functional chips is 30 μm to 775 μm.

[0007] Preferably, when the carrier wafer is used to prepare the redistribution layer, or when the redistribution layer is used to prepare the conductive bump, sputtering, photolithography, physical vapor deposition, electroplating and chemical plating techniques are used for preparation.

[0008] Preferably, the number of layers of the redistribution layer is 1 to 15, and the thickness of each layer is 1 μm to 20 μm.

[0009] Preferably, when interconnecting the plurality of functional chips and the redistribution layer, the interconnection is achieved by adopting reflow soldering or bonding technology.

[0010] Preferably, the thickness of the conductive bump is 1 μm to 500 μm, and the shape of the conductive bump is spherical, cylindrical or pad-shaped.

[0011] Preferably, in the formed plurality of packaged chip structures, the back and side surfaces of the functional chip are encapsulated by the soft reconstruction wafer, and the front surface of the functional chip is covered by the redistribution layer and the conductive bumps.

[0012] Preferably, when the encapsulation layer is prepared by 3D printing technology, the encapsulation layer of different thicknesses is prepared by controlling the 3D printing glue amount, gluing speed process parameters and printing material viscosity, so that the thickness of the encapsulation layer can reach 200μm~1000μm.

[0013] Preferably, in the formed plurality of soft fully encapsulated fan-out packaging structures, the front and side surfaces of the redistribution layer are encapsulated by the encapsulation layer.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention encapsulates a number of heterogeneous and heterogeneous chips with different functions through wafer reconstruction technology to form a soft reconstructed wafer, cuts the reconstructed wafer to form a number of packaged chip structures, and prepares encapsulation layers on the front and side surfaces of the several packaged chip structures to form a number of soft and fully encapsulated fan-out packaging structures; by adopting the above-mentioned fan-out packaging process, the number of chips integrated inside the package body of a highly reliable soft reconstructed wafer is ≥1, thereby realizing heterogeneous heterogeneous integration; through the above-mentioned technical solution based on soft encapsulation, the thickness of the side encapsulation layer is not limited by the size of the silicon wafer dicing road, so that the thickness of the encapsulation layer can reach 200μm~1000μm, far exceeding the width of the cutting road, thereby improving the reliability of the fan-out packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the slide provided by the present invention.

[0016] Figure 2 It is a schematic diagram of preparing a redistribution layer on a carrier surface according to the present invention.

[0017] Figure 3 It is a schematic diagram of the present invention providing a functional chip.

[0018] Figure 4 It is a schematic diagram of mounting a functional chip on the surface of a redistribution layer according to the present invention.

[0019] Figure 5 It is a schematic diagram of forming a reconstructed wafer through wafer reconstruction technology of the present invention.

[0020] Figure 6 It is a schematic diagram of peeling off the carrier and preparing the conductive bump according to the present invention.

[0021] Figure 7 It is a schematic diagram of cutting a reconstructed wafer into a plurality of packaged chip structures according to the present invention.

[0022] Figure 8 It is a schematic diagram of the present invention forming a soft, fully encapsulated fan-out packaging structure by preparing an encapsulation layer.

[0023] Figure 9 This is a flow chart of a highly reliable soft full-encapsulation fan-out packaging method of the present invention.

[0024] In the figure: 1-carrier, 2-rewiring layer, 3-functional chip, 4-reconstructed wafer, 5-conductive bump, 6-encapsulation layer. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0026] like Figures 1 to 9 As shown, the embodiment of the present invention specifically provides a highly reliable soft full-encapsulation fan-out packaging method, including the following steps: Step 1: providing a slide 1; Step 2: Prepare a redistribution layer 2 on the front side of the carrier wafer 1 by sputtering, photolithography, physical vapor deposition, electroplating, chemical plating, or other techniques. The redistribution layer 2 has 1 to 15 layers, and each layer has a thickness of 1 μm to 20 μm. Step 3: providing a functional chip 3, which may include only one chip or multiple chips; the thickness of the functional chip is 30 μm to 775 μm; Step 4: Mount several functional chips 3 on the surface of the redistribution layer 2 and interconnect them through reflow soldering, bonding and other technologies; Step 5: Form a reconstructed wafer 4 on the front side of the carrier wafer 1 by wafer reconstructing technology. The reconstructed wafer 4 can be made of polymer materials, including resin and polyimide materials; Step 6: Peeling off the carrier film 1, and preparing conductive bumps 5 on the exposed surface of the redistribution layer 2 by using sputtering, photolithography, physical vapor deposition, electroplating, chemical plating, etc. The thickness of the conductive bumps 5 is 1 μm to 500 μm, and the shape of the conductive bumps is spherical, cylindrical, or pad-shaped; Step 7: Cutting the reconstructed wafer 4 into a plurality of packaged chip structures, wherein the back and side surfaces of the functional chip are encapsulated, and the front surface is covered with the redistribution layer 2 and the conductive bumps 5; Step 8: Prepare an encapsulation layer 6 on the surface and side surfaces of the packaged chip structure by 3D printing or other technologies, and the redistribution layer 2 on the front surface of the packaged chip structure and the side surfaces of the redistribution layer 2 are encapsulated.

[0027] The present invention adopts a fan-out packaging process, and the number of chips integrated inside a highly reliable soft package is ≥1, which can achieve heterogeneous heterogeneous integration. By adopting the technical solution based on soft encapsulation of the present invention, by controlling process parameters such as the amount of 3D printing glue and the gluing speed and the viscosity of the printing material, side encapsulation layers of different thicknesses can be achieved. Thicker encapsulation layers can provide better side encapsulation effects, so that the thickness of the side encapsulation layer is not limited by the size of the silicon wafer dicing road, so that the thickness of the encapsulation layer can reach 200μm~1000μm, far exceeding the cutting road width, thereby improving the reliability of the fan-out packaging structure.

[0028] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A highly reliable soft full-encapsulation fan-out packaging method, characterized in that: include: Providing a carrier wafer and preparing a redistribution layer on the surface of the carrier wafer; Providing a plurality of functional chips; wherein the plurality of functional chips are the same chip or a plurality of different chips; Mounting and interconnecting the plurality of functional chips onto the redistribution layer; The functional chips are coated on the surface of the rewiring layer by wafer reconstruction technology to form a soft reconstruction wafer; the soft reconstruction wafer is made of epoxy resin or polyimide material; Peeling off the carrier sheet, and preparing conductive bumps on the exposed surface of the redistribution layer; cutting the reconstructed wafer to form a plurality of packaged chip structures; Prepare encapsulation layers on the front and side surfaces of the plurality of packaged chip structures by 3D printing technology to form a plurality of soft, fully encapsulated fan-out packaging structures; In the formed plurality of packaged chip structures, the back and side surfaces of the functional chip are encapsulated by the soft reconstructed wafer, and the front surface of the functional chip is covered by the redistribution layer and the conductive bumps; When preparing the encapsulation layer by 3D printing technology, the encapsulation layer of different thicknesses is prepared by controlling the 3D printing glue amount, glue speed process parameters and printing material viscosity, so that the thickness of the encapsulation layer can reach 200μm~1000μm; In the formed plurality of soft fully encapsulated fan-out packaging structures, the front and side surfaces of the redistribution layer are encapsulated by the encapsulation layer.

2. A highly reliable soft full-encapsulation fan-out packaging method according to claim 1, characterized in that: The thickness of the functional chips is 30 μm to 775 μm.

3. A highly reliable soft full-encapsulation fan-out packaging method according to claim 1, characterized in that: When the carrier wafer is used to prepare the redistribution layer, or when the redistribution layer is used to prepare the conductive bump, sputtering, photolithography, physical vapor deposition, electroplating and chemical plating techniques are used for preparation.

4. A highly reliable soft full-encapsulation fan-out packaging method according to claim 1, characterized in that: The number of layers of the redistribution layer is 1 to 15, and the thickness of each layer is 1 μm to 20 μm.

5. A highly reliable soft full-encapsulation fan-out packaging method according to claim 1, characterized in that: When interconnecting the plurality of functional chips and the redistribution layer, the interconnection is achieved by adopting reflow soldering or bonding technology.

6. A highly reliable soft full-encapsulation fan-out packaging method according to claim 1, characterized in that: The thickness of the conductive bump is 1 μm to 500 μm, and the shape of the conductive bump is spherical, cylindrical or pad-shaped.

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