Switching step-down converter and method

Abstract

The invention relates to a switching step-down converter and a method. The first terminal receives a regulated voltage and is coupled to a reference potential through the resistor element. The major loop adjusts the adjustment voltage based on a comparison of a first voltage on the first terminal to a first threshold. When the first voltage is below a second threshold, the circuit enables a current source that delivers a first current on the first terminal. If the first voltage is above a third threshold, the current loop regulates the first voltage to a value of the third threshold by drawing a second current from the first terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. 24 / 02718, filed on March 19, 2024, entitled “Switched step-down converter,” which is hereby incorporated by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and methods, and more particularly to switched step-down converters ("buck switched-mode power supplies") and methods. Background Art

[0004] Figure 1 An example of an apparatus 1 comprising a switching step-down converter 2 is illustrated.

[0005] The converter 2 is configured to regulate the voltage Vout to a set value determined by the threshold Th1 .

[0006] The converter 2 comprises a terminal 200 configured to receive a regulated voltage Vout. The converter 2 comprises a resistor element R( Figure 1 2 ). The resistor element R couples the terminal 200 to a terminal 202 of the converter 2, which is configured to receive a reference potential GND, such as ground. For example, one terminal of the element R is connected to the terminal 200, and the other terminal of the element R is connected to the terminal 202.

[0007] The converter 2 includes a high-side switch HS. The HS switch is connected between a terminal 204 of the converter 2 and an output terminal 206 of the converter 2. The terminal 204 is configured to receive a power supply potential Vin, which is higher than the potential GND and higher than the regulation voltage setpoint Vout.

[0008] Terminals 200 and 206 of the converter 2 are configured to be coupled to each other. Preferably, as in the case of the device 1, the terminals 200 and 206 are coupled to each other via an inductor L. For example, one terminal of the inductor L is connected to the terminal 200, and the other terminal of the inductor L is connected to the terminal 206. Preferably, the inductor L does not form part of the converter 2.

[0009] The terminals 200 and 202 of the converter 2 are configured to be coupled to each other via a capacitive element C. The regulated voltage Vout is available across the element C. For example, one terminal of the element C is connected to the terminal 200 and the other terminal of the element C is connected to the terminal 202. Preferably, the element C does not form part of the converter 2. As an example, the element C corresponds to a smoothing capacitor and / or to a load ( Figure 1 A capacitor (not shown) is provided.

[0010] exist Figure 1 In the example of FIG. 2 , the converter 2 further includes a low-side switch LS. The LS switch is connected between the terminals 206 and 202 .

[0011] Converter 2 includes a main control loop 208 ( Figure 1 delimited by dotted lines).

[0012] The circuit 208 is configured to compare the voltage Vfb at the terminal 200 with a threshold value Th1 and, based on the result of the comparison, to control the HS and LS switches to adjust the voltage Vfb (and thus the voltage Vout) to its set value. For example, the value of the threshold value Th1 is equal to the set value of the voltage Vout.

[0013] As an example, the control loop 208 controls the HS and LS switches with pulse width modulation (PWM) and / or with pulse frequency modulation (PFM) and / or with pulse skipping modulation (PSM).

[0014] As an example, the control loop 208 includes an operational amplifier AMP1 configured to compare the voltage Vfb with a threshold Th1 and to deliver a signal sig1 resulting from the comparison.

[0015] For example, amplifier AMP1 has an input terminal that receives a voltage Vfb1 determined by voltage Vfb, another input terminal that receives a voltage Vth1 determined by threshold Th1, and an output terminal that delivers signal sig1. For example, resistor element R is a voltage divider bridge comprising two resistors R1 and R2 connected in series between terminals 200 and 202, and voltage Vfb1 is available at the node where resistors R1 and R2 are connected. The values ​​of resistors R1 and R2 and the value of voltage Vth1 are then determined so that a comparison of voltage Vth1 with voltage Vfb1 is equivalent to comparing voltage Vfb with threshold Th1.

[0016] As an example, the loop 208 includes a circuit CTRL configured to receive the signal sig1 and configured to control the HS and LS switches based on the signal sig1 .

[0017] More specifically, loop 208 is configured to control switching of the HS and LS switches in such a way as to increase the value of voltage Vout when voltage Vfb is below threshold Th1. In other words, loop 208 is configured to increase regulated voltage Vout when voltage Vfb is below threshold Th1.

[0018] Therefore, when voltage Vout drops below its set value and voltage Vfb becomes below threshold Th1, control loop 208 controls the HS and LS switches so that voltage Vout increases toward its set value. When voltage Vout increases and becomes greater than or equal to its set value again, this causes voltage Vfb to become greater than or equal to threshold Th1 again. Preferably, once voltage Vfb becomes greater than or equal to threshold Th1, loop 208 no longer controls the HS and LS switches to increase voltage Vout.

[0019] The operation described above is true as long as the terminal 200 effectively receives the voltage Vout, ie as long as the voltage Vfb effectively equals Vout.

[0020] In practice, if terminal 200 becomes disconnected from voltage Vout, i.e., terminal 200 no longer receives voltage Vout (e.g., because the solder joint of the wire or the solder joint of the conductive track at terminal 200 is broken or defective), then resistor element R pulls the potential of terminal 200 to the potential of terminal 202, so that voltage Vfb is zero.

[0021] Voltage Vfb then falls below threshold Th1, and loop 208 controls the HS and LS switches to increase voltage Vout. In the absence of a disconnection between voltage Vout and terminal 200, this would cause voltage Vfb to increase. However, while voltage Vout increases, voltage Vfb remains at zero due to the disconnection between voltage Vout and terminal 200. Voltage Vout then effectively rises well above its set value and could reach a value that could damage the load powered by voltage Vout, or even converter 2 itself, which is undesirable.

[0022] Although Figure 1Not shown in FIG, but present is a converter similar to converter 2, which further includes a circuit configured to detect an undervoltage of voltage Vout relative to its set value. The circuit is configured to compare voltage Vfb with a threshold value Th2 that is lower than threshold value Th1. The circuit is further configured to activate an alarm signal when voltage Vfb remains below threshold value Th2 for a period longer than a debounce period. When terminal 200 is properly connected to voltage Vout, activation of the alarm signal means that voltage Vout has fallen below a low value that is lower than its set value for a period longer than the debounce period, i.e., an undervoltage has been detected on voltage Vout.

[0023] This signal for detecting an undervoltage of voltage Vout is activated at the end of the debounce period due to the fact that voltage Vfb is zero in the event of a disconnection between terminal 200 and voltage Vout. It is thus possible to envisage using this alarm signal the disabling of the main control loop so that, in the event of a disconnection between terminal 200 and voltage Vout, voltage Vout does not rise to a value capable of damaging the converter or the load it supplies.

[0024] However, this would result in disabling the main control loop in the event of an undervoltage of the voltage Vout, even though the terminal 200 is effectively connected to the voltage Vout, which is undesirable.

[0025] Furthermore, in case of a disconnection between terminal 200 and voltage Vout, voltage Vout will still have time during the debounce period before activation of the alarm signal to reach a value that could damage the converter or the load it supplies, which is undesirable. Summary of the Invention

[0026] There is a need to overcome the known switching step-down converters (e.g. Figure 1 All or some of the disadvantages of a switching step-down converter of the type described.

[0027] For example, it is necessary to overcome all or some of these disadvantages when they are caused by or are associated with a disconnection between the voltage regulated by the converter and a terminal of the converter configured to receive this regulated voltage, i.e., when these disadvantages are caused by a disconnection between this terminal of the converter and a node external to the converter at which the voltage regulated by the converter is available.

[0028] Embodiments overcome all or part of the disadvantages of known switching step-down converters.

[0029] An embodiment provides a switching step-down converter, comprising:

[0030] - a first terminal configured to receive a voltage regulated by the converter;

[0031] - a resistor element coupling the first terminal and a second terminal configured to receive a reference potential;

[0032] - Main control loop, configured as:

[0033] * comparing a first voltage at the first terminal to a first threshold, and

[0034] * based on the comparison, regulating the regulation voltage at a set value determined by a first threshold by controlling the high-side switch of the converter or the high-side switch and the low-side switch of the converter,

[0035] - a selectively enabled current source configured to be in an active state to deliver a first current to the first terminal; - an enabling circuit configured to enable the current source during at least one first time period when the first voltage becomes lower than a second threshold value that is lower than the first threshold value; and

[0036] - Current control loop, configured as:

[0037] * comparing the first voltage to a third threshold value that is higher than the first threshold value,

[0038] * if the first voltage is above a third threshold, regulating the first voltage at a value of the third threshold by drawing a second current from the first terminal, and

[0039] *If the first voltage is below the third threshold, then do nothing.

[0040] According to an embodiment, the product of the value of the resistor element and the value of the first current is above the third threshold value.

[0041] According to an embodiment, the main control loop is configured to increase the regulated voltage when the first voltage is below a first threshold.

[0042] According to an embodiment, the current source is connected between the first terminal and a terminal of the converter configured to receive a supply potential.

[0043] According to an embodiment, the current control loop is configured such that when the first voltage is above a third threshold, the second current drawn from the first terminal has a value determined by a difference between the first voltage and the third threshold.

[0044] According to an embodiment, the current control loop includes a transimpedance amplifier having a first input terminal configured to receive a voltage determined by the first voltage, a second input terminal configured to receive a voltage determined by a third threshold, and an output terminal coupled (preferably connected) to the first terminal and configured to draw a second current from the first terminal when the first voltage is above the third threshold.

[0045] According to an embodiment, a transimpedance amplifier comprises:

[0046] - a differential pair receiving respective inputs of a transimpedance amplifier; and

[0047] a transistor coupling the output of the transimpedance amplifier to the second terminal, the gate of the transistor being controlled by the differential pair.

[0048] According to an embodiment, the current control loop comprises a detector circuit configured to detect that the second current is non-zero and to deliver a signal indicative of when the second current is non-zero, the detector circuit comprising:

[0049] a transistor connected between the node and the second terminal and having a gate connected to the gate of the transistor of the transimpedance amplifier, and

[0050] - another transistor configured to deliver a current to said node, said signal indicating when the second current is non-zero being determined as a function of the potential of said node.

[0051] According to an embodiment, the current control loop includes a detector circuit configured to detect that the second current is non-zero and to deliver a signal indicative of when the second current is non-zero.

[0052] According to an embodiment, the enabling circuit comprises:

[0053] a comparator configured to compare the first voltage with a second threshold value and configured to deliver a binary signal indicative of a result of the comparison; and

[0054] - a circuit receiving the binary signal and configured to enable the current source during at least a first time period when the binary signal switches to a state indicating that the first voltage is below a second threshold.

[0055] According to an embodiment, the value of the first current is configured such that when the first terminal receives the regulated voltage, fluctuations in the regulated voltage during a first time period during which the first terminal receives the first current are negligible, for example, such that an increase in the regulated voltage caused by the first current has a slope of less than 10 μV per microsecond.

[0056] According to an embodiment, the first time period is higher than the response time of the current control loop.

[0057] According to the embodiment:

[0058] - the converter comprises a third terminal;

[0059] - a high-side switch connected between the terminal configured to receive the supply potential and the third terminal; and

[0060] The converter is configured such that its first terminal and third terminal are coupled to each other, preferably via an inductor, and such that the capacitive element is connected between its second terminal and the first terminal.

[0061] According to an embodiment, the main control loop is configured to control switching of the high-side switch or switching of the high-side switch and the low-side switch such that the regulated voltage increases when the first voltage is below a first threshold.

[0062] Another embodiment provides an apparatus comprising a converter such as defined above, an inductor connected between a first terminal and a third terminal of the converter, and a capacitive element connected between the first terminal and a second terminal of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above features and advantages and other features and advantages will be described in detail in the remainder of the present disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0064] Figure 1 (described previously) shows an apparatus including an example of a switching step-down converter;

[0065] Figure 2 An example of an embodiment of a switching step-down converter is shown;

[0066] Figure 3 It shows the embodiment Figure 2 Examples of implementations of circuits of converters;

[0067] Figure 4 An example of the operation of a switching step-down converter including an undervoltage detection circuit such as previously described is illustrated in a timing diagram;

[0068] Figure 5 The timing diagram shows Figure 2 An example of the operation of the converter. DETAILED DESCRIPTION

[0069] In the various figures, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be deployed with the same structure, dimensions and material properties.

[0070] For the sake of clarity, only those steps and elements that are helpful for understanding the described embodiments are shown and described in detail. In particular, various circuits that can be powered by a voltage regulated by a switching step-down converter are not described in detail, as these circuits can also be powered by a voltage regulated by a switching step-down converter according to the described embodiments and variants.

[0071] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0072] In the following description, when absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as "top", "bottom", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc. are mentioned, unless otherwise specified, they refer to the orientation of the drawings.

[0073] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean plus or minus 10% or 10°, preferably plus or minus 5% or 5°.

[0074] Figure 2 An example of a switching step-down converter 3 is shown. Figure 2 Not shown, but converter 3 can be used Figure 1 The device 1 replaces the converter 2.

[0075] and Figure 1 Like converter 2 , converter 3 includes terminals 200 , 202 , 204 and 206 , an HS switch, an LS switch, a resistor element R and a main control loop 208 .

[0076] However, compared to converter 2 , converter 3 further comprises a secondary control loop or current control loop A2 , a selectively enabled current source CS and an enabling circuit C.

[0077] When the current source CS is controlled to be in an active state, it is configured to deliver a current I1 to the terminal 200. As an example, the current source CS is connected to the terminal 200, for example, between the terminal 204 and the terminal 200. The current I1 is a direct current (DC). When the current source CS is in an inactive state, it does not deliver current.

[0078] Therefore, when the terminal 200 is disconnected from the voltage Vout and the current source CS is enabled, the current source CS is connected in series with the resistor element R, and the current I1 flows through the resistor element R.

[0079] The circuit C is configured to enable the current source CS for at least the time period T1 when the voltage Vfb becomes lower than a threshold value Th2 . The threshold value Th2 is lower than the threshold value Th1 .

[0080] For example, circuit C is configured to compare voltage Vfb with threshold Th2 and, when the result of this comparison indicates that voltage Vfb has just fallen below threshold Th2, enable current source CS for at least time period T1. There is no delay other than the delay caused by signal propagation between the time voltage Vfb has just fallen below threshold Th2 and the time circuit C enables current source CS. Furthermore, due to the fact that current source CS is enabled for at least time period T1 when voltage Vfb has fallen below threshold Th2, source CS remains enabled for time period T1 even if voltage Vfb rises above threshold Th2 before the end of time period T1.

[0081] As an example, the circuit C includes a comparator COMP2 configured to compare the voltage Vfb with a threshold Th2 and to deliver a signal sig2 indicating the result of the comparison. As an example, the signal sig2 is a binary signal. As an example, the comparator COMP2 has a first input terminal receiving a voltage determined by the voltage Vfb, a second input terminal receiving a voltage Vth2 determined by the threshold Th2, and an output terminal delivering the signal sig2. Figure 2 In the example shown in , the first input terminal of the circuit COMP2 directly receives the voltage Vfb.

[0082] As an example, in addition to the comparator COMP2, the circuit C includes a circuit PG configured to receive a signal sig2 and to enable the current source CS for at least a time period T1 when the signal sig2 switches to a state indicating that the voltage Vfb is lower than the threshold Th2.

[0083] The current control loop A2 is configured to compare the voltage Vfb with a threshold value Th3 , which is higher than the threshold value Th1 .

[0084] The control loop A2 is further configured to adjust the voltage Vfb to a value of the threshold Th3 when the voltage Vfb is higher than the threshold Th3.

[0085] Therefore, if the voltage Vfb is higher than the threshold Th3, it is also higher than the threshold Th1, so the main control loop 208 does not control the HS and LS switches to increase the voltage Vout. Therefore, when the voltage Vfb is higher than the threshold Th3, the voltage Vout does not increase due to the behavior of the main control loop 208.

[0086] More specifically, when the voltage Vfb is higher than the threshold Th3, the control loop A2 is configured to adjust the voltage Vfb to the value of the threshold Th3 by drawing a current I2 from the terminal 200. Preferably, the value of the current I2 drawn from the terminal 200 when the voltage Vfb is higher than the threshold Th3 is determined by the difference between the voltage Vfb and the threshold Th3, for example, is proportional to the difference between the voltage Vfb and the threshold Th3.

[0087] Furthermore, when the voltage Vfb is lower than the threshold Th3, the current control loop A2 is configured not to regulate the voltage Vfb, i.e., not to supply any current to or draw any current from the terminal 200. In other words, when the voltage Vfb is lower than the threshold Th3, the loop A2 is configured to do nothing.

[0088] Therefore, when the terminal 200 is suddenly disconnected from the voltage Vout, the operation of the converter 3 is as follows.

[0089] First, the voltage Vfb is pulled to the potential GND through the resistor element R, and thus drops below the threshold value Th2 .

[0090] This results in the current source CS being enabled for at least the time period T1 .

[0091] Activation of current source CS causes current I1 to flow through resistor element R and causes voltage Vfb to stabilize at a value above threshold Th3. Therefore, the product of current I1 and the value of resistor element R is above threshold Th3. Preferably, the product of current I1 and resistor element R is below the maximum value of voltage Vfb, above which one or more circuits of converter 3 may be damaged.

[0092] Since voltage Vfb is higher than threshold Th3, current control loop A2 starts drawing current I2 from terminal 200. Therefore, the current flowing through resistor element R is equal to current I1 minus current I2, and voltage Vfb decreases to a value stable at threshold Th3.

[0093] Since threshold Th3 is higher than threshold Th1, primary control loop 208 does not increase the value of voltage Vout as long as voltage Vfb remains regulated by control loop A2 at threshold Th3. Therefore, as long as value Vfb is regulated by loop A2 at threshold Th3, voltage Vout does not increase to a value that could damage converter 3 or the load it supplies.

[0094] Furthermore, when the terminal 200 is effectively connected to the voltage Vout, the operation of the converter 3 is as follows.

[0095] If terminal 200 is actively receiving voltage Vout, and voltage Vout is above threshold Th2, primary control loop 208 regulates voltage Vout to its set value by comparing voltage Vfb (and therefore Vout) with threshold Th1 and controlling the HS and LS switches accordingly. Voltage Vfb is then below threshold Th3, and loop A2 does not draw current from terminal 200. The operation of converter 3 is then identical to that of converter 2, with circuits C, CS, and A2 having no effect on the operation.

[0096] If terminal 200 is actively receiving voltage Vout, and voltage Vout is below threshold Th2 (e.g., because converter 3 is in its startup phase, or because a load powered by converter 3 is drawing current (which causes voltage Vout to fall below threshold Th2)), circuit C activates current source CS for at least time period T1. Current I1 is then delivered to terminal 200, i.e., to the load powered by converter 3, capacitive element C, and resistor element R. The value of current I1 is configured such that, in this case, the change in voltage Vout caused by the delivery of current I1 to terminal 200 during time period T1 is negligible. Consequently, voltage Vout (and therefore voltage Vfb) remains below threshold Th3, and loop A2 does not draw current from terminal 200. Since loop A2 does not draw current from terminal 200, and activation of current source CS has only a negligible effect on the value of voltage Vout, the operation of converter 3 is identical to that of converter 2, where circuits C, CS, and A2 have no effect on the operation.

[0097] Preferably, the time period T1 is selected to be longer than the response time of loop A2, or in other words, determined by the bandwidth of loop A2. This allows the current source CS to still deliver the current I1 to the terminal 200 when the loop A2 starts to draw a non-zero current I2 from the terminal in the event of a disconnection between the terminal 200 and the voltage Vout.

[0098] As an example, the current I1 is configured such that the increase in the regulated voltage caused by the current I1 delivered to the terminal 200 has a slope of less than 10 μV per microsecond. For example, since the capacitive element C typically has a high value, such as greater than 10 μF, the current I1 is selected to be less than 100 μA, so that the increase in the voltage Vout caused by the current I1 delivered to the terminal 200 alone has a slope of less than 10 μV per microsecond.

[0099] As an example, circuit A2 includes an operational transimpedance amplifier (OTA). The OTA amplifier has a first input configured to receive a voltage determined by voltage Vfb, a second input configured to receive a voltage determined by threshold Th3, and an output coupled (preferably connected) to terminal 200. The output of the OTA amplifier is configured to draw current I2 from terminal 200 when voltage Vfb is higher than threshold Th3.

[0100] For example, the OTA amplifier receives a voltage Vfb3 at its first input and a voltage Vth3 at its second input. For example, the resistor element R is a voltage divider bridge comprising three resistors R3, R4, and R5 connected in series between terminals 200 and 202, with resistor R5 connected to terminal 202. Voltage Vfb3 is available at the node where resistors R5 and R4 are connected to each other. In this example, voltage Vfb1 can be available, for example, at the node where resistor R4 is connected to resistor R3. The values ​​of resistors R3, R4, and R5 are then determined such that a comparison of voltage Vth1 with voltage Vfb1 is equivalent to comparing voltage Vfb with threshold value Th1, and a comparison of voltage Vfb3 with voltage Vth3 is equivalent to comparing voltage Vfb with threshold value Th3. In this specific example, the values ​​of resistors R3 , R4 and R5 are preferably determined so that voltages Vth1 and Vth3 are equal, which enables a single voltage to be generated instead of two voltages, for example using a bandgap circuit.

[0101] An example of a mode of realization of the converter 3 has been described above that enables a load supplied by the regulated voltage Vout to be protected from a disconnection between the terminal 200 and the voltage Vout.

[0102] It may be desirable for the converter 3 to indicate when such a disconnection occurs.

[0103] Therefore, loop A2 is optionally configured to deliver a signal FBDIS indicating when such a disconnection occurs. For example, loop A2 is configured to indicate when a non-zero current I2 is drawn from terminal 200. In practice, when loop A2 draws a non-zero current I2 from terminal 200, this means that terminal 200 is disconnected from voltage Vout.

[0104] As an example, the current control loop includes a detection circuit DET, which is configured to detect that the current I2 is non-zero, for example, the current is above a non-zero current value, and is configured to deliver a signal FBDIS indicating when the current I2 is non-zero (or in other words, indicating that the terminal 200 is not connected to the voltage Vout).

[0105] As an example, when loop A2 comprises an OTA amplifier as described above, circuit DET is coupled to the output of the OTA amplifier.

[0106] As an example, when loop A2 is configured to deliver signal FBDIS, this signal may, for example, be present at the output terminal ( Figure 2 is delivered to the environment of the converter 3 ) to indicate to the environment of the converter 3 that the terminal 200 is disconnected from the voltage.

[0107] As an alternative or additional example, when loop A2 is configured to deliver signal FBDIS, the main control loop 208 can be controlled by the signal FBDIS, for example, to disable the control loop 208 when a disconnection from the terminal 200 is detected. Figure 2 In the example shown, the signal FBDIS is delivered to the circuit LOGIC, and the circuit LOGIC controls the loop 208 based on the signal FBDIS. In other examples not shown, the signal FBDIS is delivered directly to the loop 208 to control the loop.

[0108] Optionally, when loop A2 is configured to deliver signal FBDIS, converter 3 further comprises a circuit for detecting an undervoltage of voltage Vout. Figure 2 In the example shown in FIG1 , in the absence of a disconnection between the terminal 200 and the voltage Vout, if the voltage Vout is lower than a threshold value Th5 (which is lower than the threshold value Th1), then the voltage Vout is considered to exhibit an undervoltage. Then, the undervoltage detection circuit is configured to detect when the voltage Vfb is lower than the threshold value Th5 throughout the debounce period, and if the signal FBDIS indicates that there is no disconnection between the terminal 200 and the voltage Vout, then the circuit is configured to indicate that the voltage Vout exhibits an undervoltage using the alarm signal true-UV.

[0109] As an example, the brown-out detection circuit includes a comparator configured to compare the voltage Vfb with a threshold value Th5 to deliver a signal UV indicating a result of the comparison, the signal being, for example, binary. The brown-out detection circuit also includes a circuit configured to receive the signal UV and the signal FBDIS and to deliver a signal true-UV based on the signals UV and FBDIS.

[0110] More specifically, in Figure 2In the example, the threshold Th5 is considered to be equal to the threshold Th2. Therefore, when the circuit C includes the comparator COMP2, the comparator COMP2 can be shared between the circuit C and the undervoltage detection circuit, and the signal UV can then be obtained at the output of the comparator COMP2. The undervoltage detection circuit further includes a circuit LOGIC configured to receive the signals UV and FBDIS and configured to deliver a signal true-UV. As an example, the signal true-UV can be output at the output terminal ( Figure 2 ), for example to indicate to the environment of the converter 3 that the voltage Vout exhibits an undervoltage.

[0111] As an alternative example, when thresholds Th5 and Th2 are equal, the signal true-UV may be determined based solely on the signal UV, for example by the circuit LOGIC. In this case:

[0112] If terminal 200 is disconnected from voltage Vout, voltage Vfb will first be below threshold Th2 equal to Th5 before being regulated to the value of threshold Th3 and will therefore be above threshold Th2 at the end of the debounce period. Consequently, at the end of the debounce period, signal UV will no longer indicate that voltage Vfb is below threshold Th2 and signal true-UV will not be activated; and

[0113] If terminal 200 is connected to voltage Vout, then if voltage Vout effectively exhibits an undervoltage, voltage Vfb will still be below threshold Th2 at the end of the debounce period. Therefore, at the end of the debounce period, signal UV will indicate that voltage Vfb is below threshold Th2, and signal true-UV will be activated.

[0114] Optionally, the converter 3 further comprises a circuit for detecting an overvoltage of the voltage Vout. The overvoltage detection circuit is configured to detect when the voltage Vfb is above a threshold value Th4 throughout the debounce period and, if this occurs, is configured to indicate with an alarm signal true-OV that the voltage Vout exhibits an overvoltage. As an example, the signal true-OV may be delivered to the output terminal ( Figure 2 ), for example, to indicate to the environment of the converter 3 that the voltage Vout exhibits an overvoltage.

[0115] As an example, the overvoltage detection circuit includes a comparator COMP3 configured to compare the voltage Vfb with the threshold Th4 to deliver a signal OV indicating a result of the comparison, the signal being, for example, binary. The overvoltage detection circuit also includes a circuit configured to receive the signal OV and to deliver a signal true-OV based on the signal OV, for example, Figure 2As an example, the comparator COMP3 has a first input terminal receiving a voltage determined by the voltage Vfb, a second input terminal receiving a voltage Vth4 determined by the threshold Th4, and an output terminal delivering a signal OV. Figure 2 In the example shown in , the first input terminal of the circuit COMP3 directly receives the voltage Vfb.

[0116] As an example, threshold Th4 is higher than threshold Th3. Therefore, when terminal 200 is disconnected from the voltage, even if voltage Vfb rises above threshold Th4 when current source CS switches from the inactive state to the active state, voltage Vfb falls below threshold Th4 again before the end of the debounce period because loop A2 adjusts voltage Vfb to the value of threshold Th3.

[0117] As an alternative example, when threshold Th4 is lower than or equal to threshold Th3, the circuitry delivering signal true-OV then determines this signal based on signal OV and signal FBDIS when signal OV indicates that voltage Vfb is above threshold Th4 throughout the debounce period. In practice, at the end of the debounce period, signal true-OV will only indicate an undervoltage if signal FBDIS indicates that terminal 200 is not disconnected from voltage Vout.

[0118] Figure 3 It shows the embodiment Figure 2 An example of a converter circuit A2.

[0119] exist Figure 3 In an embodiment, circuit A2 includes an OTA amplifier.

[0120] The OTA amplifier includes a differential pair 300 that receives respective inputs of the OTA amplifier, namely, voltages Vfb3 and Vth3 in this example. The OTA amplifier also includes a transistor T1 that couples the output of the OTA amplifier to terminal 202. The output of the OTA amplifier is connected to terminal 200, and the gate of transistor T1 is controlled by the differential pair. More specifically, the transistors are controlled by differential pair 300 such that if voltage Vfb3 is lower than voltage Vth3 (voltage Vfb is lower than threshold Th3), transistor T1 is non-conductive, and if voltage Vfb3 is higher than voltage Vth3 (voltage Vfb is higher than threshold Th3), transistor T1 is conductive. When transistor T1 is conductive, current I2 is drawn from terminal 200 via the output of the OTA amplifier. Preferably, when voltage Vfb3 is higher than voltage Vth3, the value of current I2 drawn from terminal 200, i.e., the on-resistance of transistor T1, depends on the difference between the two voltages.

[0121] As an example, the transistor T1 is an NMOS transistor, and its source is coupled (preferably connected) to the terminal 202 , and its drain is coupled (preferably connected) to the terminal 200 .

[0122] As an example, the differential pair 300 includes two transistors T2 and T3, for example two PMOS transistors. Transistor T2 receives a voltage Vfb3 on its gate, and transistor T3 receives a voltage Vth3 on its gate. The gate of transistor T1 is then connected to a first conductive terminal of transistor T3.

[0123] The first conductive terminals (e.g., drains) of transistors T2 and T3 are coupled to terminal 202. For example, the first conductive terminals of transistors T2 and T3 are coupled to terminal 202 via transistors T4 and T5, respectively. Transistors T4 and T5 are, for example, NMOS transistors. Transistors T4 and T5 are assembled together in a current mirror configuration. For example, the sources of transistors T4 and T5 are connected to terminal 202, and their drains are connected to the first conductive terminals of transistors T2 and T3, respectively. The gates of transistors T4 and T5 are connected to each other and to the drain of transistor T4. Transistors T4 and T5 form, for example, an active load of differential pair 300.

[0124] The differential pair 300 is biased by a current source 302. The current source 302 is connected between the second conductive terminals (eg, sources) of the transistors T2 and T3 and a node 304 connected to a power supply potential VDD of the OTA amplifier. Preferably, the potential VDD is lower than the potential Vin ( Figure 2 ).

[0125] As an example, the current source 302 includes a transistor T6 (e.g., a PMOS) connected between the node 304 and the second conductive terminals of the transistors T2 and T3, and a transistor T7 (e.g., a PMOS). The transistor T7 is configured to allow the current I3 to flow through the transistor, and the transistors T6 and T7 are mirror images of each other, so that the current I3 determined by the current I3 is 偏置 Flows through transistor T6 and biases differential pair 300. For example, the source of each of transistors T6 and T7 is coupled (preferably connected) to node 304, the gates of transistors T6 and T7 are connected to each other and to the drain of transistor T7, and the drain of transistor T6 is coupled (preferably connected) to the second conduction terminals of transistors T3 and T2.

[0126] Preferably, the gate of transistor T1 is coupled to terminal 200 through a series association of resistor R6 and capacitor C6.

[0127] exist Figure 2 In the example, the control loop includes an optional circuit DET.

[0128] In this example of an OTA circuit including a differential pair 300 and a transistor T1, circuit DET includes a transistor T8 connected between node 308 and terminal 202, with the gate of transistor T8 connected to the gate of transistor T1. Therefore, current I4 flowing through transistor T8 is determined by current I2 in transistor T1, e.g., current I4 is equal to current I2. For example, transistor T8 is an NMOS transistor with its source connected to terminal 202 and its drain connected to node 308.

[0129] Circuit DET further includes a transistor T9, for example, a PMOS transistor, configured to deliver current I5 to node 308. Signal FBDIS is determined based on the potential at node 308. For example, current I5 is determined such that when current I4, determined by current I2 (e.g., equal to current I2), is higher than current I5, the potential at node 308 is lower than threshold Th6, and when current I4 is zero or lower than current I5, the potential at node 308 is higher than threshold Th6. In other words, in the example where current I4 is equal to current I2, when the value of current I2 is higher than the value of current I5, circuit DET indicates that current I2 is non-zero.

[0130] As an example, transistor T9 is assembled in a mirrored form with transistors T6 and T7 of current source 302. For example, the source of transistor T9 is connected to node 302, its drain is connected to node 308, and its gate is connected to the gates of transistors T6 and T7.

[0131] As an example, to determine signal FBDIS based on the potential of node 308, circuit DET includes a shaping circuit. For example, the shaping circuit includes a comparator 310 configured to compare the potential of node 308 with a threshold value Th6 and to deliver a binary signal sig resulting from the comparison. Comparator 310 is, for example, a Schmitt trigger. Signal FBDIS is determined based on signal sig. For example, signal sig is delivered to the input of inverter 312, and the output of inverter 312 delivers signal FBDIS. As an alternative example, signal FBDIS is signal sig.

[0132] Figure 4 and Figure 5 The difference in operation of converter 3 with respect to converter 2 is illustrated, in that a circuit UVDET for detecting an undervoltage of voltage Vout will be used to indicate a disconnection between terminal 200 and voltage Vout.

[0133] Figure 4The operation of the converter 2 is illustrated in a timing diagram, the converter 2 comprising a circuit for detecting an undervoltage of the voltage Vout, the circuit being configured to deliver the signal UVDET in a high state at the end of a debounce period TEMP during which the voltage Vfb has remained below the threshold Th2 . Figure 4 The variations (in volts) of the voltage Vout, the voltage Vfb and the signal UVDET are shown as a function of the time t (in milliseconds).

[0134] Before time t0, terminal 200 is connected to voltage Vout, and voltage Vout is regulated to its set value. In this example, the set value of voltage Vout is equal to 3.3 V. Then, in this example, voltage Vfb is equal to threshold Th1.

[0135] At time t0 , the connection between the terminal 200 and the voltage Vout is broken, and the terminal 200 no longer receives the voltage Vout.

[0136] Starting from time t0, voltage Vfb decreases. Specifically, at time t1, voltage Vfb becomes lower than threshold Th2. In this example, threshold Th2 is equal to 1.2V. Therefore, debounce period TEMP begins at time t1. In this example, the duration of period TEMP is approximately equal to 25μs.

[0137] At time t2 , which is equal to t1 +TEMP, signal UVDET switches to a high state because voltage Vfb has remained below threshold Th2 for the entire period TEMP.

[0138] However, it is not sufficient to disable the main control loop 208 by using this switching of the signal UVDET. In fact, during the time period TEMP, due to the fact that the voltage Vfb is lower than the threshold Th1, the loop 208 has already controlled the HS and LS switches to increase the voltage Vout. Therefore, the voltage Vout starts to increase from time t0 and quickly reaches a value during the time period TEMP that may damage the load powered by the voltage Vout. Figure 4 In the example shown in FIG. 5 , the voltage Vout increases to reach 9 V at the end of the period TEMP.

[0139] Figure 5 The operation of the converter 3 is illustrated in a timing diagram. Figure 5 The variations (in volts) of the voltage Vout, the voltage Vfb and the signal FBDIS are shown as a function of the time t (in milliseconds).

[0140] Before time t0, the situation is the same as Figure 4 The same as in .

[0141] At time t0 , the connection between the terminal 200 and the voltage Vout is interrupted, and the terminal 200 no longer receives the voltage Vout.

[0142] From time t0, the voltage Vfb decreases. In particular, at time t1, the voltage Vfb becomes lower than the threshold value Th2. In this example, Figure 4 As shown in , threshold Th2 is equal to 1.2 V. Therefore, for at least time period T1 , circuit C enables source CS, and voltage Vfb rises back to a value above threshold Th1 and above threshold Th3 .

[0143] Since voltage Vfb is above threshold Th3, control loop A2 begins to draw a non-zero current I2 from terminal 200 and regulates voltage Vfb to the value of threshold Th3 as long as source CS is active. In this example, threshold Th3 is equal to 4 V. Circuit DET detects that current I2 is non-zero and switches signal FBDIS to a state, here a high state, indicating that disconnection of terminal 200 from voltage Vout has been detected.

[0144] Furthermore, starting from time t1, since voltage Vfb is higher than threshold Th1, loop 208 does not control HS and LS switches to increase voltage Vout. Instead, starting from time t1, voltage Vout decreases at a slope determined by the power consumption of the load powered by voltage Vout and the capacitance value of capacitive element C.

[0145] In this example, when a disconnection between terminal 200 and voltage Vout is detected, signal FBDIS is used to disable converter 3. Thus, at time t3 after time t1 (e.g., where t3 is equal to t1+T1), converter 3 is disabled, voltage Vfb becomes zero, and signal FBDIS switches to its low state.

[0146] like Figure 5 As can be seen in FIG. 1 , in this example, the overvoltage on the voltage Vout caused by the disconnection between the terminal 200 and the voltage Vout is less than 200 mV, which makes it possible not to damage the load powered by the voltage Vout.

[0147] A variety of embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that further variations will occur to those skilled in the art. For example, the implementation of circuits A2 and C is not limited to the examples of the embodiments described above.

[0148] In particular, although the converter 3 including the HS switch and the LS switch and the control loop 208 for controlling both switches has been described above, in other embodiments not shown, the LS switch is replaced by a diode whose anode is connected to the terminal 202, and the loop 208 is configured to control only the HS switch.

[0149] Furthermore, although examples have been described where voltages Vth1 and Vth3 are equal and corresponding voltages Vfb1 and Vfb3 are different, those skilled in the art will be able to adapt these examples to situations where the two voltages Vth1 and Vth3 are different and the corresponding voltages Vfb1 and Vfb3 are different.

[0150] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, a person skilled in the art will be able to determine the value of the resistor element R, the value of the current I1, the duration T1, etc. to obtain the above-described operation.

Claims

1. A switching step-down converter, comprising: a first terminal configured to receive a voltage regulated by the converter; a resistor element coupling the first terminal and a second terminal of the converter configured to receive a reference potential; The main control loop is configured as follows: comparing a first voltage at the first terminal to a first threshold; as well as Based on the comparison, regulating the regulated voltage at a set value determined by a first threshold by controlling a high-side switch of the converter or a high-side switch and a low-side switch of the converter; a selectively enabled current source configured to deliver a first current to the first terminal in an active state; an enabling circuit configured to enable the selectively enableable current source during at least one first time period when the first voltage becomes lower than a second threshold value that is lower than the first threshold value; as well as The current control loop is configured as: comparing the first voltage to a third threshold value that is higher than the first threshold value; In response to the first voltage being above a third threshold, regulating the first voltage at a value of the third threshold by drawing a second current from the first terminal; and In response to the first voltage being lower than the third threshold, do nothing. 2 . The converter according to claim 1 , wherein a product of a value of the resistor element and a value of the first current is higher than a third threshold value. 3 . The converter of claim 1 , wherein the primary control loop is configured to increase the regulation voltage when the first voltage is below a first threshold. 4 . The converter of claim 1 , wherein the selectively enabled current source is connected between the first terminal and a terminal of the converter configured to receive a power supply potential. 5 . The converter of claim 1 , wherein the current control loop is configured such that when the first voltage is above a third threshold, the second current drawn from the first terminal has a value determined by a difference between the first voltage and the third threshold.

6. The converter of claim 1 , wherein the current control loop comprises a transimpedance amplifier having a first input configured to receive a voltage determined by the first voltage, a second input configured to receive a voltage determined by a third threshold, and an output coupled to the first terminal and configured to draw a second current from the first terminal when the first voltage is above the third threshold.

7. The converter of claim 6 , wherein the transimpedance amplifier comprises: a differential pair receiving corresponding inputs of a transimpedance amplifier; as well as A first transistor couples the output of the transimpedance amplifier to the second terminal, wherein a gate of the first transistor is controlled by the differential pair.

8. The converter of claim 7 , wherein the current control loop comprises a detector circuit configured to detect that the second current is non-zero and to deliver a signal indicative of when the second current is non-zero, the detector circuit comprising: a second transistor connected between the node and the second terminal and having a gate connected to the gate of the first transistor; as well as A third transistor is configured to deliver a current to the node, the signal indicating when the second current is non-zero being determined according to the potential of the node. 9 . The converter of claim 1 , wherein the current control loop comprises a detector circuit configured to detect that the second current is non-zero and to deliver a signal indicative of when the second current is non-zero.

10. The converter of claim 1 , wherein the enabling circuit comprises: a comparator configured to compare the first voltage to a second threshold value and configured to deliver a binary signal indicative of a result of the comparison; as well as A circuit receives the binary signal and is configured to enable the selectively enableable current source during at least a first time period when the binary signal switches to a state indicating that the first voltage is below a second threshold.

11. The converter of claim 1 , wherein the value of the first current is configured such that, when the first terminal receives the regulation voltage, fluctuations in the regulation voltage during a first time period during which the first terminal receives the first current are negligible, such that an increase in the regulation voltage caused by the first current has a slope lower than 10 μV per microsecond.

12. The converter of claim 1, wherein the first time period is higher than a response time of the current control loop.

13. The converter according to claim 1, wherein: The converter includes a third terminal; a high-side switch connected between a terminal of the converter configured to receive a power supply potential and a third terminal; as well as The converter is configured such that its first terminal and third terminal are coupled to each other, and such that its first terminal and second terminal are coupled to each other through a capacitive element.

14. The converter of claim 13, wherein the primary control loop is configured to control switching of the high-side switch or switching of the high-side and low-side switches such that the regulated voltage increases when the first voltage is below a first threshold.

15. An apparatus comprising: Switching step-down converter, including: a first terminal configured to receive a voltage regulated by the converter; a resistor element coupling the first terminal and a second terminal of the converter configured to receive a reference potential; The main control loop is configured as follows: comparing a first voltage at the first terminal to a first threshold; and Based on the comparison, regulating the regulated voltage at a set value determined by a first threshold by controlling a high-side switch of the converter or a high-side switch and a low-side switch of the converter; a third terminal, wherein the high-side switch is connected between a terminal of the converter configured to receive a power supply potential and the third terminal; a selectively enabled current source configured to deliver a first current to the first terminal in an active state; an enabling circuit configured to enable the selectively enabled current source during at least one first time period when the first voltage becomes lower than a second threshold value that is lower than the first threshold value; and The current control loop is configured as: comparing the first voltage to a third threshold value that is higher than the first threshold value; In response to the first voltage being above a third threshold, regulating the first voltage at a value of the third threshold by drawing a second current from the first terminal; and In response to the first voltage being lower than a third threshold, doing nothing; an inductor connected between the first terminal and the third terminal of the converter; and A capacitive element is connected between the first terminal and the second terminal of the converter.

16. A method of operating a switching step-down converter, the switching step-down converter comprising a first terminal and a second terminal coupled via a resistor element, the method comprising: receiving, at the first terminal, a voltage regulated by the converter; receiving a reference potential via the second terminal; comparing, by the main control loop, a first voltage at the first terminal with a first threshold; regulating the regulated voltage at a set value determined by a first threshold by controlling a high-side switch of the converter or a high-side switch and a low-side switch of the converter based on the comparison by the main control loop; delivering a first current to the first terminal by the selectively enabled current source in an active state; enabling, by the enabling circuit, the selectively enableable current source during at least one first time period in response to the first voltage becoming below a second threshold value that is lower than the first threshold value; comparing, by the current control loop, the first voltage with a third threshold value that is higher than the first threshold value; as well as The first voltage is regulated at a third threshold value by drawing a second current from the first terminal in response to the first voltage being greater than the third threshold value by the current control loop. The method of claim 16 , wherein a product of a value of the resistor element and a value of the first current is higher than a third threshold value.

18. The method according to claim 16, further comprising: The regulated voltage is increased by the main control loop in response to the first voltage being lower than the first threshold.

19. The method according to claim 16, further comprising: In response to the first voltage being greater than a third threshold, a value of a second current drawn from the first terminal is determined by the current control loop based on a difference between the first voltage and the third threshold.

20. The method of claim 16, further comprising: The detector circuit of the current control loop is: detecting that the second current is non-zero; as well as A signal is delivered indicating that the second current is non-zero.

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