Signal processing system and method based on LPTI controller

Abstract

The invention provides a signal processing system and method based on an LPTI controller. The system comprises an LPTI controller which comprises a channel controller, a link manager, a transmitting channel and a receiving channel; wherein the channel controller is connected with the link manager, and the transmitting channel is connected with the receiving channel; the link manager is connected with the channel controller, the transmitting channel and the receiving channel; the transmitting channel comprises a frame generator, an encoder, a transmitting cache and a transmitting low-voltage differential signal parallel-to-serial controller which are connected in sequence, and the frame generator is connected with the channel controller; the frame generator is connected with the link manager; the receiving channel comprises a frame parser, a decoder, a word alignment module, a receiving cache and a receiving low-voltage differential signal serial-to-parallel controller which are connected in sequence, and the frame parser is connected with the channel controller; the frame analyzer is connected with the link manager; the link manager further comprises a link manager state machine, and the link manager state machine is used for carrying out signal receiving and transmitting training on the controller.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a signal processing system and method based on an LPTI controller. Background Art

[0002] The Data Center-ready Secure Control Module (DC-SCM) is a key specification of the Open Compute Project (OCP) hardware management subproject. Version 2.0 of DC-SCM restructures the server management architecture through a modular design, significantly impacting server design and management. The OCP DC-SCM specification defines the LPTI (Low Pin Test Interface) channel protocol interface specification, which is used to connect SCM (Secure Control Module) card interfaces such as GPIO (General-Purpose Input / Output), I2C (Inter-Integrated Circuit), and UART (Universal Asynchronous Receiver / Transmitter) to the motherboard.

[0003] However, how to design LPTI control based on CPLD (Complex Programmable Logic Device) is a problem that all major server and SCM card design manufacturers must face. Summary of the Invention

[0004] The embodiments of the present application provide a signal processing system and method based on an LPTI controller, which can implement LPTI control.

[0005] In a first aspect, an embodiment of the present application provides a signal processing system based on an LPTI controller, wherein the LPTI controller includes: a channel controller, a link manager, a transmit channel, and a receive channel; wherein the channel controller is connected to the link manager, the transmit channel, and the receive channel;

[0006] The link manager is connected to the channel controller and the receiving channel;

[0007] The transmission channel includes: a frame generator, an encoder, a transmission buffer and a transmission low voltage differential signal parallel-to-serial controller connected in sequence, the frame generator is connected to the channel controller; the frame generator is connected to the link manager;

[0008] The receiving channel includes: a frame parser, a decoder, a word alignment module, a receiving buffer and a receiving low voltage differential signal serial to parallel controller connected in sequence, the frame parser is connected to the channel controller; the frame parser is connected to the link manager;

[0009] The link manager further includes a link manager state machine, and the link manager state machine is used to train the LPTI controller for signal transmission and reception.

[0010] In one embodiment, the link management state machine of the link manager includes a link training main state, a link configuration main state, and a link operation main state; wherein the link training main state is used to detect the link signal and set the link signal transmission speed; the link configuration main state is used to align the link signal; and the link operation main state operates the LPTI controller according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state.

[0011] In one embodiment, the link training main state includes: a link detection sub-state, a link speed sub-state, and a link training completion sub-state; wherein, the link detection sub-state is used to send and receive link detection type data frames; the link speed sub-state is used to send and receive link speed type data frames; and the link training completion sub-state is used to determine the configuration frequency range of the security control module.

[0012] In one embodiment, the link configuration main state includes: an idle substate, a link announcement alignment substate, a link announcement substate, a link configuration substate, a link reception substate and a link configuration completion substate; wherein, the idle substate is used to configure the rate of the transmitting channel and the rate of the receiving channel to the maximum frequency corresponding to the frequency interval, and to reconfigure the frequency of the clock enable signal; the link announcement alignment substate is used to send and receive link announcement type data frames; the link announcement substate is used to forward configuration type data frames from the serial management module to the host processor module, and to send low-speed interface information of the serial management module to the host processor module; the link configuration substate is used to send configuration type data frames; the link reception substate is used to forward received data frames sent by the host processor module to the serial management module; and the link configuration completion substate is used to enter the link operation main state.

[0013] In a second aspect, an embodiment of the present application provides a signal processing method based on an LPTI controller, which is applied to a signal processing system based on an LPTI controller provided in any embodiment of the present application, the method comprising:

[0014] In the startup state of the link management state machine of the link manager, configuring the system clock to a fixed frequency, and configuring the serial clock, the receiving clock, and the transmitting clock to non-fixed frequencies;

[0015] In the startup state of the link management state machine, the link manager determines the enable signals for the system clock, serial clock, receive clock and transmit clock according to the main state of the link management state machine, and the enable signals are used to make the system clock, serial clock, receive clock and transmit clock match the main state of the link management state machine.

[0016] In one embodiment, the link management state machine includes a link training main state, a link configuration main state, and a link operation main state; the method further includes:

[0017] In the link training main state, detecting link signals and setting the link signal transmission speed;

[0018] In the link configuration main state, aligning the link signals;

[0019] In the link operation main state, the LPTI controller operates according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state.

[0020] In one embodiment, detecting a link signal and setting a link signal transmission speed in the link training main state includes:

[0021] In the link detection substate of the link training main state, the link manager outputs a valid link detection signal, sends a first encapsulation notification to the frame generator, and sends a first detection notification to the frame parser, wherein the first encapsulation notification is used to notify the frame generator that the encapsulated data frame type is a link detection type, and the detection notification is used to notify the frame parser that the detection data frame type is a link detection type;

[0022] In the link speed substate of the link training main state, the link manager outputs a valid link speed signal, sends a second encapsulation notification to the frame generator, and sends a second detection notification to the frame parser, wherein the second encapsulation notification is used to notify the frame generator that the encapsulated data frame type is link speed, and the second detection notification is used to notify the frame parser to detect that the data frame type is link speed;

[0023] In the link training completion substate of the link training main state, the link manager determines the configuration frequency interval of the security control module by comparing the local link speed capability with the remote link speed capability. The configuration frequency interval is the frequency interval for the security control module to receive and / or send data.

[0024] In one embodiment, aligning the link signals in the link configuration master state includes:

[0025] In an idle substate of the link configuration main state, configuring the rate of the transmitting channel and the rate of the receiving channel to the maximum frequency corresponding to the frequency interval, and reconfiguring the frequency of the clock enable signal;

[0026] In the link advertisement alignment substate of the link configuration main state, sending a third encapsulation notification to the frame parser and sending a third detection notification to the frame parser, wherein the third encapsulation notification is used to notify the frame generator that the type of the encapsulated data frame is a link advertisement, and the third detection notification is used by the frame parser to detect that the type of the data frame is a link advertisement;

[0027] In the link advertisement substate of the link configuration main state, forwarding a data frame of a configuration type of the serial management module to the host processor module, and sending low-speed interface information of the serial management module to the host processor module;

[0028] forwarding a received data frame sent by the host processor module to the serial management module in a link receiving sub-state of the link configuration main state;

[0029] After the link configuration is completed sub-state of the link configuration main state, the link operation main state is entered.

[0030] In a third aspect, an embodiment of the present application provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method provided in any one of the embodiments of the present application is implemented.

[0031] According to another aspect of the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes the method provided in the relevant embodiment of the first aspect.

[0032] Through the system provided in the embodiment of the present application, communication between multiple interfaces and the mainboard can be achieved, and LPTI control can be implemented based on complex logic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1This is a schematic diagram of a system provided by an embodiment of the present application;

[0035] Figure 2 is a schematic diagram of a link manager according to an embodiment of the present application;

[0036] Figure 3 This is a schematic diagram of the main state of link training according to an embodiment of the present application;

[0037] Figure 4 This is a schematic diagram of the main state of link configuration according to an embodiment of the present application;

[0038] Figure 5 1 is a schematic diagram of a frame generator state machine according to an embodiment of the present application;

[0039] Figure 6 This is a schematic diagram of a clock signal according to an embodiment of the present application;

[0040] Figure 7 This is a schematic diagram of the TX FIFO interface according to an embodiment of the present application;

[0041] Figure 8 This is a schematic diagram of the interface of the RX FIFO according to an embodiment of the present application;

[0042] Figure 9 This is a functional block diagram of a word alignment module according to an embodiment of the present application;

[0043] Figure 10 This is a functional diagram of a word alignment module according to an embodiment of the present application;

[0044] Figure 11 This is the Low Latency GPIO Channel function of an embodiment of the present application;

[0045] Figure 12 This is a functional reference diagram of the Normal Latency GPIO Channel according to an embodiment of the present application;

[0046] Figure 13 This is a functional diagram of a UART Channel according to an embodiment of the present application;

[0047] Figure 14 This is a functional diagram of the Data Channel according to an embodiment of the present application;

[0048] Figure 15 is a schematic diagram of a method according to an embodiment of the present application;

[0049] Figure 16 Schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0051] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0052] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0053] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0054] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0055] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0056] The embodiments of the present application are exemplarily described below with reference to the accompanying drawings.

[0057] Figure 1In one embodiment of the present application, a signal processing system based on an LPTI controller includes: a channel controller, a link manager, a transmitting channel, and a receiving channel; wherein the channel controller is connected to the link manager, the transmitting channel is connected to the receiving channel; the link manager is connected to the channel controller, and the transmitting channel is connected to the receiving channel; the transmitting channel includes: a frame generator (Frame Generator), an encoder, a transmit buffer (TX FIFO, Transmit First-In-First-Out) and a transmit low-voltage differential signal (LVDS) parallel-to-serial controller connected in sequence, the frame generator is connected to the channel controller; the frame generator is connected to the link manager; the receiving channel includes: a frame parser (Frame Parser), a decoder, a word aligner module (word aligner), a receive buffer (RX FIFO, Receive The LPTI controller includes a first-in-first-out (FIFO) and a low-voltage differential signal serial-to-parallel controller, the frame parser is connected to the channel controller, the frame parser is connected to the link manager, and the link manager further includes a link manager state machine, which is used to train the LPTI controller for signal transmission and reception.

[0058] The signal processing system provided in the embodiment of the present application is used for an LPTI controller, and applies the LPTI interface specification defined in the OCP DC-SCM specification. DC-SCM implements modular server management and specifies all firmware states stored on a typical processor motherboard. DC-SCM typically transfers three key functions to a standard size module (CFM, Control Function Module, control function module). The three key functions include management function, security function, and control function, where the management function includes BMC function and LPTI interface. The DC-SCM architecture defines input / output ports that interoperate with the CPU (central processing unit) board. The DC-SCM server has only basic CPU, high-speed memory and IO connectors on the HPM (host processor module) board, and all other components are on the modular DC-SCM (security, control, management) board.

[0059] In the embodiments of the present application, the encoder may be an 8b / 10b encoder (8b_10b Encoder), which may refer to a line encoder that converts 8-bit data into 10-bit coded symbols. The decoder may be an 8b / 10b decoder (8b_10b Decoder), which may refer to a device that converts received 10-bit coded symbols into the original 8-bit data. The link manager state machine is a logical control module in the communication protocol used to manage link establishment, maintenance, and termination. The link manager state machine ensures that communicating parties (e.g., devices and nodes) can reliably establish and maintain connections through state transitions and event responses.

[0060] Through the system provided by the embodiment of the present application, interfaces such as the GPIO interface, UART interface, I2C interface, OEM (Original Equipment Manufacturer) interface, and DATA interface can transparently transmit data between the mainboard and the SCM, and have strong portability. During operation, the channel controller receives the target signal from the sending end, and the target signal is sent by at least one interface among the GPIO interface, UART interface, I2C interface, OEM interface, and DATA interface; the channel controller sends information to the link manager based on the received target signal, and the link manager generates a clock enable signal based on the interface corresponding to the target signal. The clock enable signal is used to dynamically enable or disable the transmission of the clock signal.

[0061] In the system of the embodiment of the present application, the clock signals include: system clock (sysclk), transceiver clock and receiver clock (TX Clk and RX Clk), Serdes (SERializer / DESerializer, serializer / deserializer)) serial clock (sclk). In addition, since the channel controller needs to support the rates corresponding to multiple Serdes serial clocks, including 25Mhz and the actual operating optional rate, the transmission of clock signals and clock enable signals is as follows: Figure 6As shown, the system clock is sent to the channel controller, frame generator, link manager, frame parser, encoder, decoder, word aligner, transmit buffer, and receive buffer. The LVDS TX sends the transmit clock signal from the transceiver clock, while the LVDS RX receives the receive clock signal from the transceiver clock. The LVDS TX also sends the transmit serial clock signal (TX sclk) to the transmit buffer, and the LVDS RX sends the receive serial clock signal (RX sclk) to the receive buffer. The system also sends clock enable signals to the channel controller, frame generator, link manager, frame parser, encoder, decoder, word aligner, transmit buffer, and receive buffer.

[0062] In a possible implementation, the structure of the link manager is as follows Figure 2 As shown, it includes a state machine controller, a CSR (Control & Status Register) controller, a clken (clock enable) controller, and a word aligner controller. The state machine controller includes a link management state machine.

[0063] In one embodiment, Figure 3 As shown, the link manager includes a link management state machine, which includes a link training (Link Training) main state, a link configuration (Link Configuration) main state and a link operation (Link Operational) main state; wherein the link training main state is used to detect the link signal and set the link signal transmission speed; the link configuration main state is used to align the link signal; the link operation main state runs the LPTI controller according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state. In an embodiment of the present application, when the signal processing system based on the LPTI controller is restarted, the link management state machine receives the restart signal (reset) and begins to enter the first main state (i.e., the link training main state). After the first main state is completed, it enters the second main state (i.e., the link configuration main state). After the second main state is completed, it enters the third main state (i.e., the link operation main state). When the link configuration main state is reset or times out, it returns to the link training main state. When the link operation main state is reset or times out, it returns to the link training main state. In the link detection main state and the link speed main state, link detection type data frames and link speed type data frames are respectively sent to the signal receiving end, and the number of sent data frames is a preset number. If the data frame type or the number of data frames sent in the main state is different from the preset number, it may cause the corresponding main state to be reset or timed out.

[0064] For example, according to pre-defined rules, in the Link Detect Master state, the SCM sends 255 Link Detect data frames and the HPM receives seven consecutive correct data frames. If, in the Link Detect Master state, 255 Link Detect data frames are sent to the signal receiving end but seven consecutive correct data frames are not received, a Master State reset or timeout occurs. For another example, according to pre-defined rules, in the Link Speed ​​Master state, the SCM sends seven Link Speed ​​data frames and the HPM receives three Link Speed ​​data frames. Otherwise, a Master State reset or timeout may occur due to link loss.

[0065] In one implementation, the channel controller can use a PLL (Phase-Locked Loop) reconfiguration scheme to support multiple SerDes serial clock rates. Specifically, in the Link Training master state, the TX and RX Clks are set to 25MHz, while the sysclk is set to 2.5MHz (25MHz / 10), and the sclk is set to 3.125MHz (25MHz / 8). After the Link Training master state is complete, the PLL is reconfigured to the rate agreed upon by the SCM and HPM (Host Processor Module), for example, TX and RX Clk to 100MHz, sysclk to 10MHz, and sclk to 12.5MHz. If the PLL is reconfigured, the PLL clock will be locked for a period of time, potentially creating unpredictable risks for downstream logic. Clock variations also pose a new challenge to speed constraints during layout and routing, requiring the matching of multiple clock speeds.

[0066] In another implementation, the channel controller can use a fixed system clock (corresponding to a 25 MHz rate) and reconfigurable sclk, TX clk, and RX clk (with a maximum rate of 25 MHz x 10, or 250 MHz). Clock enables are used to align the system clock, sysclk, with the sclk, TX clk, and RX clk. For example, during the link training phase, the cycle enable is valid for one out of every ten clock cycles. After link training is complete, the clock enable pulse period is modulated according to the selected frequency. The clock domains of sclk, TX clk, and RX clk contain only LVDS modules, without complex logic modules, minimizing the risk of unknowns during clock changes.

[0067] In one embodiment, the link training main state includes: a link detection (Link Detect) substate, a link speed (Link Speed) substate, and a link training completion (Link Training Done) substate; wherein, the link detection substate is used to send and receive link detection type data frames; the link speed substate is used to send and receive link speed type data frames; and the link training completion substate is used to determine the configuration frequency range of the security control module.

[0068] When in the Link Training main state, the LVDS rate is 25 MHz, and the clken clock signal is enabled for one out of every ten clock cycles. In the Link Detect substate, the Link_Detect signal is output as valid, notifying the Frame Generator module to encapsulate data frames into the Link Detect type and the Frame Parser to detect the data frame type as Link Detect. In the Link Speed ​​substate, the Link_Speed ​​signal is output as valid, notifying the Frame Generator module to encapsulate data frames into the Link Speed ​​type and the Frame Parser to detect the data frame type as Link Speed. In the Link Training Done substate, the main state machine is notified to enter the Link Configuration main state and determine the maximum configurable frequency of the SCM by comparing the local and remote link speed capabilities. In one possible example, this design supports only SDR mode, which can greatly simplify the LPTI controller logic and reduce module resource usage.

[0069] In one embodiment, reference Figure 4As shown, the link configuration main state includes: an idle (IDLE) substate, a link advertisement alignment (Link Advertise Align) substate, a link advertisement (Link Advertise) substate, a link configuration (Link Configure) substate, a link reception (Link Accept) substate and a link configuration completion (LinkConfiguration Done) substate; wherein, the idle substate is used to configure the rate of the transmitting channel and the rate of the receiving channel to the frequency interval corresponding to the most suitable for sending and receiving link advertisement type data frames; the link advertisement substate is used to forward the configuration type data frames from the serial management module to the host processor module, and to send the low-speed interface information of the serial management module to the host processor module; the link configuration substate is used to send the configuration type data frames; the link reception substate is used to forward the received data frames sent by the host processor module to the serial management module; and the link configuration completion substate is used to enter the link operation main state.

[0070] In the Link Configuration Main State, the Idle substate is first executed. After the Idle substate completes, the Link Advertisement Alignment substate is entered. After the Link Advertisement substate completes, the Link Advertisement substate is entered. Following the Link Advertisement substate, the Link Configuration substate and the Link Receive substate are entered. After the Link Configuration substate and the Link Receive substate complete, the Link Configuration Complete substate is entered. If the Link Advertisement Alignment substate is reset or times out for a set duration (e.g., 1 millisecond), the Idle substate is returned. If the Link Advertisement substate is reset or the link is lost, the Idle substate is returned. If the SCM sends 32 Link Configuration-type data frames in the Link Configuration substate, the Link Advertisement substate is returned. In the Link Advertisement Alignment substate, if the PLL is locked and three correct data frames are received, the Link Advertisement Alignment substate is completed. In the Link Advertisement substate, if the SCM times out for a set duration (e.g., 1 millisecond), the Link Advertisement substate is completed and the Link Configuration substate is entered. In the Link Advertisement Substate, if the HPM times out for a set duration (e.g., 1 millisecond) and receives a valid Link Configuration Type data frame, the Link Advertisement Substate is completed and the Link Receive Substate is entered. If a matching Link Receive Type data frame is received in the Link Configuration Substate, the Link Configuration Substate is completed. If a valid Link Operation Data frame is received in the Link Receive Substate, the Link Receive Substate is completed.

[0071] When in the Link Configuration main state, the sub-state machine jumps from the IDLE to the Link AdvertiserAlign sub-state. At this time, the LVDS TX and LVDS RX modules are configured to the highest rate determined in a), and the PLL in the LVDS module is reconfigured to output clken to 0 until the PLL is relocked. Then, clken is set to the latest matching rate (for example, the configurable LVDS rates are 250 MHz, 50 MHz, and 25 MHz, and clken is configured to be full high, 1 / 5 duty cycle, and 1 / 10 duty cycle, respectively). After the substate enters the Link Advertise Align substate, it notifies the Frame Generator module to encapsulate the data frame type as Link Advertise, and notifies the Frame Parser to detect the data frame type as LinkAdvertise; in the Link Advertise substate, it continues to send and receive Link Advertise data frames; in the LinkConfigurate substate, the SCM sends a configure type data frame to the HPM to inform the signal receiving end of the SCM's low-speed interface information (including at least one of the GPIO interface, I2C interface, UART interface, OEM interface, and DATA interface); in the LinkAccept substate, the HPM sends an Accept data frame to the SCM; when entering the Link Configuration Done substate, it notifies the main state machine to enter the Link Operational main state.

[0072] exist Figure 2 Based on the embodiment shown, the addresses and divisions of the registers in the CSR Controller are as shown in Table 1 for the general control and status register mapping, and in Table 2 for the LTPI control and status register. When the state machine changes, the LPTI status itself is updated in the Link Status register, and the peer status information received by the Frame Parser is updated in the register.

[0073]

[0074] Table 1

[0075]

[0076]

[0077]

[0078] The corresponding relationship between the status and encoding of the local LTPI link status in Table 2 is shown in Table 3 below.

[0079] state coding Link detection 0x0 Link speed 0x1 notice 0x2 Configuration 0x3 run 0x4 reserve 0x5-0xF

[0080] Table 3 The state and encoding correspondence of the remote LTPI link state is shown in Table 4.

[0081]

[0082]

[0083] Table 4 The correspondence between link speed and encoding of LTPI link speed is shown in Table 5.

[0084] state coding Basic frequency (based freq) x1 0x0 Basic frequency x2 0x1 Basic frequency x3 0x2 Basic frequency x4 0x3 Base frequency x6 0x4 Base frequency x8 0x5 Basic frequency x10 0x6 Basic frequency x12 0x7 Base frequency x16 0x8 Basic frequency x24 0x9 Base frequency x32 0xA Basic frequency x40 0xB reserve 0xC-0xF

[0085] Table 5

[0086] exist Figure 2 Based on the Link Manager module, the WordAlign controller interacts with the Word Aligner module. When the Frame Parser module is in the IDLE state, the WordAlign controller sends an en_rxdata_slip (Enable Received Data Slip) valid signal to the WordAligner module every 16 clken signals until the CommaSymbol detected by the Frame Parser module matches the current Link state. The frame counter in the WordAlign controller increments by 1 for each matching signal (the initial value of the frame counter is 0 and returns to 0 when the Link state jumps). The WordAlign controller outputs the frame counter value to the StateMachine controller (providing a reference for state machine jumps such as Link Training and Link Configuration).

[0087] Figure 1 The Frame Generator shown is mainly used to encapsulate data frames, which are divided into multiple types. The length of each data frame is fixed to 16 bits. For example, in the LinkDetect data frame, there is a Framesubtype code after the Comma Symbol. In the Frame Generator module, set the state machine, such as Figure 5As shown, the MCU includes states S0 through S15. These states correspond to bytes at offsets 0 through 15 in the transmitted data frame. In states S0 through S15, the CLKEN flag is asserted. Link status and other frame information are input by the LinkManager and ChannelController modules. In state S15, if the PLL is locked, the MCU enters the Idle Master state. In the Idle Master state, if CLKEN is asserted, the MCU enters the Main State S0.

[0088] Table 6 shows a summary of the data frame types that the frame generator can encapsulate.

[0089]

[0090] Table 6

[0091] Table 7 shows the subframe field values ​​corresponding to the frame type.

[0092]

[0093]

[0094] Table 7

[0095] Table 8 shows the detailed information of the link detection type data frame.

[0096]

[0097] Table 8

[0098] The Frame Parser primarily parses data frames. Its state machine, in contrast to the Frame Generator, consists of Main States S0 through S15. Main States S0 through S15 correspond to bytes at offsets 0 through 15 in the data frame and output the corresponding fields to the Link Manager or Channel Controller. Furthermore, the Frame Parser collaborates with the Link Manager during link training and configuration phases to count input data and frames, enabling the Link Manager to determine link status and word alignment.

[0099] In the embodiment of the present application, the encoder and decoder can respectively perform 8b / 10b encoding and decryption, and the encoding and decoding are completed using a table lookup.

[0100] The interfaces of TX FIFO and RX FIFO are as follows: Figure 7 and Figure 8 As shown, in Figure 7In the example shown, the interfaces of TXFIFO include: reset (rst) interface, sysclk interface, write data (wrdata) interface, write enable signal (wren) interface, almost full signal (almost full) interface, full signal (full) interface, sclk interface, read data (rddata) interface, read enable signal (rden) interface, almost empty (almost empty) interface, empty (empty) interface. Figure 8 In the example shown, the RX FIFO interface is the same as the TX FIFO interface. The data width of the wrdata and rddata interfaces is 10, the depth can be set to 8x16, the almost full interface threshold can be set to 7x16, and the almost empty interface threshold can be set to 16.

[0101] exist Figure 1 Based on the embodiment shown, the word alignment module functional block diagram and functional schematic are as follows Figure 9 As shown, it includes slip_counter (offset counter), shifter (shift) module and data_sel (data strobe) module. When en_rxdata_slip (enable receive data offset, from Link Manager module) is valid, slip_counter is incremented by 1 (assuming that the counting range of the offset counter is 0-N, N can be an integer greater than 0, for example, N is 10). Figure 9 and Figure 10 As shown, the shifter module connects the two i_rxdata (receive data input) before and after into a data variable data with a width of 2N. When i_rxdata_vld is valid, data is shifted left by N bits and the new i_rxdata is placed at bits N-1 to 0 of data. In the data_sel module, a segment of data with a width of N is intercepted from data based on the value of slip_counter and output. For example, when slip_counter == 0, the output o_rxdata (receive data output) is filled with bits N-1 to 0 of data. When slip_counter == 1, the output o_rxdata is filled with bits N-1+1 to 1 of data. When slip_counter == 2, the output o_rxdata is filled with bits N-1+2 to 2 of data, and so on.

[0102] exist Figure 1 Based on the above, the functional block diagram of Channel Controller is as follows: Figure 11As shown in the figure, the main function of the channel controller is to convert low-speed interfaces such as GPIO, I2C, and UART into the data frame content format for transmission during the Link Operational phase, or convert the content of received data frames into low-speed interface signals. The channel controller includes low latency GPIO channel 0 (low latency GPIO channel 0), low latency GPIO channel 1 (low latency GPIO channel 1), normal latency GPIO channel 0 (normal latency GPIO channel 0), normal latency GPIO channel 1 (normal latency GPIO channel 1), UART channel, I2C0 / 1 channel, I2C2 / 3 channel, I2C4 / 5 channel, and data channel. The channel controller can transmit information between the interface and the data frame multiplexer. The data frame multiplexer transmits information from the general-delay GPIO channel 0, general-delay GPIO channel 1, UART channel, I2C0 / 1 channel, I2C2 / 3 channel, I2C4 / 5 channel, and data channel to the frame generator and frame parser. Alternatively, the data frame selector transmits information from the frame generator and frame parser to the general-delay GPIO channel 0, general-delay GPIO channel 1, UART channel, I2C0 / 1 channel, I2C2 / 3 channel, I2C4 / 5 channel, and data channel. Data frames are divided into IO (input / output) frames and Data (data type) frames. Data frames are burst data frames. Under normal circumstances, the data frame mux (multiplexer) connects to interfaces such as UART and I2C, meaning that data frames are generally IO frames. When the data channel transmission signal is valid, the mux switches to the data channel. Similarly, when the received data frame is a data frame, the mux switches to the data channel.

[0103] For example, the format of the IO frame is shown in Table 9 below.

[0104]

[0105] Table 9

[0106] Figure 10 The Low Latency GPIO Channel function is as follows Figure 11As shown in the figure, the Low Latency GPIO Channel is used to sample GPIO in real time and convert it into data frame content, or to convert data frames into real-time IO signals. At each clken clock enable, the GPIO is latched into a register and output to the Frame Generator. Similarly, the byte corresponding to the Low Latency GPIO in the data frame received from the Frame Parser is latched into the reg register when clken is asserted and output to the GPIO.

[0107] Normal Latency GPIO Channel Function Reference Figure 12 As shown, the GPIO interface corresponding to the Normal Latency GPIOChannel channel does not have such high real-time requirements, but it supports a large number of interfaces. GPIO values ​​are passed to the Frame Generator through multi-frame time-division multiplexing. The transmit counter frame_counter is set. The maximum value of the counter depends on the number of GPIOs supported. When the number of GPIO channels to be supported is 8, the maximum value of the counter is 8-1=7. When the frame_offset is 15, the counter is increased by 1, and the corresponding GPIO channel is selected in the mux for the next frame of data transmission. Whenever the clock signal "clken" arrives, the data of the GPIO channel is latched into the register and output to the Frame Generator. Similarly, when a data frame is received, the corresponding byte of the data frame is latched into the register when the clock signal "clken" is received. The mux is then switched using the receive counter frame_counter, thereby allocating the data to the corresponding GPIO channel.

[0108] UART Channel functions are as follows Figure 13 As shown in the figure, the UART interface is sampled three times per data frame. The UART interface TX value is sampled and latched into reg1 when frame_offset is 0, 5, and 10. When frame_offset is 15, the data in reg1 is latched into reg2 and output to the FrameGenerator module. Similarly, the received data frame content is latched into reg4 when clken is valid. When offset is 15, the content of reg4 is latched into reg3. At offsets of 0, 5, and 10, the content of reg3 is converted into the UART RX signal.

[0109] Data Channel functions such as Figure 14As shown, it is used to convert the local bus to the data frame format. The format is as follows: Local bus conversion and the corresponding payload of the data frame are converted to each other. The payload is fixed at 10x8 bits.

[0110] The embodiment of the present application further provides a signal processing method based on an LPTI controller, which is applied to a signal processing system based on an LPTI controller provided in any embodiment of the present application, such as Figure 15 As shown, the signal processing method based on the LPTI controller includes the following steps S151 to S152.

[0111] Step S151: in the startup state of the link management state machine, the system clock is configured to have a fixed frequency, and the serial clock, the receiving clock and the transmitting clock are configured to have non-fixed frequencies.

[0112] Step S152: In the startup state of the link management state machine, the link manager determines the enable signal of the system clock, serial clock, receive clock and transmit clock according to the main state of the state machine, and the enable signal is used to make the system clock, serial clock, receive clock and transmit clock match the main state of the state machine.

[0113] In one embodiment, the link management state machine includes a link training main state, a link configuration main state, and a link operation main state; and the signal processing method based on the LPTI controller further includes:

[0114] In the link training main state, detecting link signals and setting the link signal transmission speed;

[0115] In the link configuration main state, aligning the link signals;

[0116] In the link operation main state, the LPTI controller operates according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state.

[0117] In one embodiment, detecting a link signal and setting a link signal transmission speed in the link training main state includes:

[0118] In the link detection substate of the link training main state, the link manager outputs a valid link detection signal, sends a first encapsulation notification to the frame generator, and sends a first detection notification to the frame parser, wherein the first encapsulation notification is used to notify the frame generator that the encapsulated data frame type is a link detection type, and the detection notification is used to notify the frame parser that the detection data frame type is a link detection type;

[0119] In the link speed substate of the link training main state, the link manager outputs a valid link speed signal, sends a second encapsulation notification to the frame generator, and sends a second detection notification to the frame parser, wherein the second encapsulation notification is used to notify the frame generator to encapsulate the data frame type as the link speed, and the second detection notification detects that the data frame type is the link speed;

[0120] In the link training completion substate of the link training main state, the link manager determines the configuration frequency interval of the security control module by comparing the local link speed capability with the remote link speed capability. The configuration frequency interval is the frequency interval for the security control module to receive and / or send data.

[0121] In one embodiment, aligning the link signals in the link configuration master state includes:

[0122] In an idle substate of the link configuration main state, configuring the rate of the transmitting channel and the rate of the receiving channel to the maximum frequency corresponding to the frequency interval, and reconfiguring the frequency of the clock enable signal;

[0123] In the link advertisement alignment substate of the link configuration main state, sending a third encapsulation notification to the frame parser and sending a third detection notification to the frame parser, wherein the third encapsulation notification is used to notify the frame generator that the type of the encapsulated data frame is a link advertisement, and the third detection notification is used by the frame parser to detect that the type of the data frame is a link advertisement;

[0124] In the link advertisement substate of the link configuration main state, forwarding a data frame of a configuration type of the serial management module to the host processor module, and sending low-speed interface information of the serial management module to the host processor module;

[0125] forwarding a received data frame sent by the host processor module to the serial management module in a link receiving sub-state of the link configuration main state;

[0126] After the link configuration is completed sub-state of the link configuration main state, the link operation main state is entered.

[0127] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0128] Figure 16 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present application. Figure 16As shown, the electronic device 6 of this embodiment includes: a processor 60, a memory 61, and a computer program 62 stored in the memory 61 and executable on the at least one processor 60. The processor 60 includes the processor and each core of the server in any of the above-mentioned system embodiments.

[0129] The electronic device 6 can be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device can include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will understand that Figure 3 This is merely an example of the electronic device 6 and does not constitute a limitation on the electronic device 6 . The electronic device 6 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device 6 may also include input and output devices, network access devices, etc.

[0130] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0131] In some embodiments, the memory 61 may be an internal storage unit of the electronic device 6, such as a hard disk or memory of the electronic device 6. In other embodiments, the memory 61 may also be an external storage device of the electronic device 6, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 6. Furthermore, the memory 61 may also include both an internal storage unit of the electronic device 6 and an external storage device. The memory 61 is used to store an operating system, an application program, a boot loader, data, and other programs, such as the program code of the computer program. The memory 61 may also be used to temporarily store data that has been output or is about to be output.

[0132] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps performed by the server or any one of the cores in the above-mentioned various method embodiments are implemented.

[0133] An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device implements the steps performed by the server or any core in the above-mentioned various method embodiments.

[0134] The present application also provides a chip comprising a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit may execute computer instructions to cause a computer device to perform the steps performed by the server or any core in any of the method embodiments provided above.

[0135] Optionally, the computer instructions are stored in a storage unit.

[0136] Optionally, the storage unit is a storage unit within the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip within the terminal, such as a ROM or other type of static storage device that can store static information and instructions, random access RAM, etc. The processor mentioned in any of the above may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above method. The processing unit and the storage unit may be decoupled and respectively provided on different physical devices, and connected by wired or wireless means to implement the respective functions of the processing unit and the storage unit, so as to support the system chip to implement the various functions in the above embodiments. Alternatively, the processing unit and the memory may also be coupled on the same device.

[0137] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0138] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] In the embodiments provided in this application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0140] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0141] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0142] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can at least include: any entity or device capable of carrying computer program code to the electronic archive generation device / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, mobile hard drive, magnetic disk, or optical disk. In some jurisdictions, based on legislation and patent practice, computer-readable media cannot be electric carrier signals or telecommunication signals.

[0143] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A signal processing system based on an LPTI controller, characterized in that: The LPTI controller includes: a channel controller, a link manager, a transmitting channel, and a receiving channel; wherein the channel controller is connected to the link manager, the transmitting channel, and the receiving channel; The link manager is connected to the transmitting channel and the receiving channel; The transmission channel includes: a frame generator, an encoder, a transmission buffer and a transmission low voltage differential signal parallel-to-serial controller connected in sequence, the frame generator is connected to the channel controller; the frame generator is connected to the link manager; The receiving channel includes: a frame parser, a decoder, a word alignment module, a receiving buffer and a receiving low voltage differential signal serial to parallel controller connected in sequence, the frame parser is connected to the channel controller; the frame parser is connected to the link manager; The link manager further includes a link manager state machine, and the link manager state machine is used to train the LPTI controller for signal transmission and reception.

2. The system according to claim 1, wherein: The link management state machine of the link manager includes a link training main state, a link configuration main state, and a link operation main state; wherein the link training main state is used to detect link signals and set the link signal transmission speed; the link configuration main state is used to align link signals; and the link operation main state operates the LPTI controller according to the signal transmission speed set in the link training main state and the data parameters aligned in the link configuration main state.

3. The system according to claim 2, characterized in that The link training main state includes: a link detection sub-state, a link speed sub-state and a link training completion sub-state; wherein, the link detection sub-state is used to send and receive link detection type data frames; the link speed sub-state is used to send and receive link speed type data frames; and the link training completion sub-state is used to determine the configuration frequency interval of the security control module.

4. The system according to claim 3, characterized in that The link configuration main state includes: an idle substate, a link announcement alignment substate, a link announcement substate, a link configuration substate, a link reception substate and a link configuration completion substate; wherein, the idle substate is used to configure the rate of the transmitting channel and the rate of the receiving channel to the maximum frequency corresponding to the frequency interval, and to reconfigure the frequency of the clock enable signal; the link announcement alignment substate is used to send and receive link announcement type data frames; the link announcement substate is used to forward configuration type data frames from the serial management module to the host processor module, and to send low-speed interface information of the serial management module to the host processor module; the link configuration substate is used to send configuration type data frames; the link reception substate is used to forward received data frames sent by the host processor module to the serial management module; the link configuration completion substate is used to enter the link operation main state.

5. A signal processing method based on an LPTI controller, applied to the signal processing system based on an LPTI controller according to any one of claims 1 to 4, characterized in that: The method comprises: In the startup state of the link management state machine of the link manager, configuring the system clock to a fixed frequency, and configuring the serial clock, the receiving clock, and the transmitting clock to non-fixed frequencies; In the startup state of the link management state machine, the link manager determines the enable signals for the system clock, serial clock, receive clock and transmit clock according to the main state of the link management state machine, and the enable signals are used to make the system clock, serial clock, receive clock and transmit clock match the main state of the link management state machine.

6. The method according to claim 5, characterized in that The link management state machine includes a link training main state, a link configuration main state, and a link operation main state; the method further includes: In the link training main state, detecting link signals and setting the link signal transmission speed; In the link configuration main state, aligning the link signals; The LPTI controller is operated in the link operation main state according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state.

7. The method according to claim 6, characterized in that In the link training main state, detecting the link signal and setting the link signal transmission speed includes: In the link detection substate of the link training main state, the link manager outputs a valid link detection signal, sends a first encapsulation notification to the frame generator, and sends a first detection notification to the frame parser, wherein the first encapsulation notification is used to notify the frame generator that the encapsulated data frame type is a link detection type, and the detection notification is used to notify the frame parser that the detection data frame type is a link detection type; In the link speed substate of the link training main state, the link manager outputs a valid link speed signal, sends a second encapsulation notification to the frame generator, and sends a second detection notification to the frame parser, wherein the second encapsulation notification is used to notify the frame generator that the encapsulated data frame type is link speed, and the second detection notification is used to notify the frame parser to detect that the data frame type is link speed; In the link training completion substate of the link training main state, the link manager determines the configuration frequency interval of the security control module by comparing the local link speed capability with the remote link speed capability. The configuration frequency interval is the frequency interval for the security control module to receive and / or send data.

8. The method according to claim 7, characterized in that The aligning of the link signals in the link configuration main state includes: In an idle substate of the link configuration main state, configuring the rate of the transmitting channel and the rate of the receiving channel to the maximum frequency corresponding to the frequency interval, and reconfiguring the frequency of the clock enable signal; In the link advertisement alignment substate of the link configuration main state, sending a third encapsulation notification to the frame parser and sending a third detection notification to the frame parser, wherein the third encapsulation notification is used to notify the frame generator that the type of the encapsulated data frame is a link advertisement, and the third detection notification is used by the frame parser to detect that the type of the data frame is a link advertisement; In the link advertisement substate of the link configuration main state, forwarding a data frame of a configuration type of the serial management module to the host processor module, and sending low-speed interface information of the serial management module to the host processor module; forwarding a received data frame sent by the host processor module to the serial management module in a link receiving sub-state of the link configuration main state; After the link configuration is completed sub-state of the link configuration main state, the link operation main state is entered.

9. An electronic device, characterized in that: include: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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