Low-power-consumption SPI communication system and communication method
By introducing the chip select module and clock control module, precise selection of the slave module and dynamic control of the clock path in the CMOS image sensor are achieved, solving the high power consumption and low efficiency problems of the traditional SPI communication mode, improving the system communication efficiency and reducing invalid power consumption.
Patent Information
- Application Number
- CN202510714740.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-19
AI Technical Summary
The traditional SPI communication method has the problems of high power consumption and low communication efficiency in CMOS image sensors. Especially when there are many slave modules, the system efficiency is significantly reduced and the invalid power consumption is increased.
The chip select module and clock control module are introduced. The chip select module responds to the chip select parameters to control the gating and interruption of the slave module. The clock control module dynamically opens or closes the clock path between the slave module and the master module to achieve precise slave module gating and communication control.
It improves communication efficiency, reduces invalid power consumption, supports simultaneous selection of multiple slave modules, and ensures the reliability and integrity of data transmission.
Smart Images
Figure CN120676264A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a low-power SPI communication system and a communication method. Background Art
[0002] CMOS image sensors consist of pixel circuits, readout circuits, digital timing control circuits, and several slave modules. Slave modules typically use SPI communication to respond to the master module, setting the operating mode and transmitting data. However, with the development of CMOS image sensors, the internal integration density has increased, and the number of slave modules has increased. This trend has gradually exposed numerous problems with the traditional SPI communication method in terms of communication efficiency and dynamic power consumption, becoming a key bottleneck limiting the further improvement of the integration density of CMOS image sensors.
[0003] In traditional SPI communication, the master module must select the target slave module individually using the chip select signal each time it communicates with a slave module. Furthermore, the clock signal remains on during communication, even if the slave modules do not need to transmit data simultaneously. This communication method significantly reduces system communication efficiency and increases inefficient power consumption when there are many slave modules. Summary of the Invention
[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a low-power SPI communication system and communication method that can reduce power consumption when a master module communicates with multiple slave modules and improve communication efficiency.
[0005] To solve the above technical problems, the present invention adopts a technical solution: providing a low-power SPI communication system, comprising: a master module, a chip select module, a clock control module, a plurality of slave modules, and an SPI communication bus for connecting the master module, the chip select module, the clock control module, and the slave modules; the master module is used to enable and / or interrupt the entire communication system and send chip select parameters and / or reset parameters to the chip select module during communication; the chip select module is used to control a chip select signal in response to the chip select parameters and / or reset parameters; and the clock control module is used to open and / or close a clock path between a corresponding slave module and the master module in response to the chip select signal, thereby realizing communication between the master module and the slave modules.
[0006] Furthermore, the SPI communication bus includes an SCLK signal line, a MOSI signal line, a MISO signal line, and a CS signal line; the CS port of the master module is connected to the CS port of the chip select module via the CS signal line, and the chip select signal output ends of the chip select module are connected to the CSn ports of the slave modules in a one-to-one correspondence via the CSn signal line, and the chip select signal output ends of the chip select module are also connected to the CSn ports of the clock control module in a one-to-one correspondence via the CSn signal line; the MOSI port of the master module is also connected to the MOSI port of each slave module via the MOSI signal line. The MOSI port of the master module is connected to the MOSI port of the chip select module through a MOSI signal line; the SCLK port of the master module is connected to the SCLK input end of the clock control module through an SCLK signal line, and the several SCLK output ends of the clock control module are respectively connected to the SCLK ports of several slave modules through SCLK signal lines in a one-to-one correspondence; the MISO ports of the slave modules are respectively connected to the MISO signal input ends of the chip select module in a one-to-one correspondence through MISO signal lines, and the MISO signal output end of the chip select module is connected to the MISO port of the master module through a MISO signal line.
[0007] Furthermore, the chip select module includes a chip select register, and the chip select module sets the chip select register according to the chip select parameters and / or reset parameters. The several CSn ports of the chip select register serve as the several chip select signal output ends of the chip select module and are connected one-to-one with the CSn ports of the several slave modules through the CSn signal lines. The several CSn ports of the chip select register are also connected one-to-one with the several CSn ports of the clock control module through the CSn signal lines.
[0008] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a low-power SPI communication method, which is applied to the low-power SPI communication system, comprising the following steps:
[0009] When communication starts, the master module sends a system selection signal to the chip selection module to select the entire system;
[0010] The master module sends a chip select parameter to the chip select module. In response to the chip select parameter, the chip select module enables a chip select signal of a slave module corresponding to the chip select parameter, and the slave module enters a working state.
[0011] In response to the chip select signal, the clock control module opens a clock path between the slave module and the master module corresponding to the chip select signal;
[0012] The master module communicates with the slave module whose clock path is opened;
[0013] After the communication is completed, the master module sends a reset parameter to the chip selection module, and in response to the reset parameter, the chip selection module interrupts the chip selection signal of the slave module corresponding to the reset parameter;
[0014] After the chip select signal is interrupted, the clock control module turns off the clock path between the slave module and the master module corresponding to the chip select signal.
[0015] Furthermore, the master module sends a request code and a chip select parameter to the chip select module, and in response to the request code and the chip select parameter, the chip select module enables a chip select signal of the slave module corresponding to the chip select parameter. The step of the slave module entering a working state includes the following sub-steps:
[0016] The main module sends the request code and chip select parameters to the chip select module;
[0017] If the request code received by the chip selection module is correct, the chip selection module enters the response state from the standby state; otherwise, the chip selection module remains in the standby state;
[0018] The chip selection module that has entered the response state sets the chip selection register according to the received chip selection parameter, enables the chip selection signal of the corresponding slave module, and the slave module enters the working state.
[0019] Furthermore, in the step of the master module communicating with the slave module whose clock path is opened, when the master module writes data to the slave module, the following sub-steps are included:
[0020] The master module sends a write address code to the slave module, and after receiving the write address code, the slave module enters a data writing state from a standby state;
[0021] The master module sends data to the slave module, and the slave module writes the data into the internal register corresponding to the write address after receiving the data.
[0022] Furthermore, in the step of the master module communicating with the slave module whose clock path is opened, when the master module reads data from the slave module, the following sub-steps are included:
[0023] The master module sends a read address code to the slave module, and after receiving the read address code, the slave module enters a data reading state from a standby state;
[0024] The slave module sends the data of the register corresponding to the read address to the chip selection module, and the chip selection module forwards the data to the master module after receiving the data.
[0025] Furthermore, when data from at least two slave modules are read simultaneously, after the chip select module receives data from at least two slave modules, the chip select register determines the priority of the received data and then forwards it to the master module in order of priority.
[0026] Furthermore, after the communication is completed, the master module sends a reset parameter to the chip select module, and in response to the reset parameter, the chip select module interrupts the chip select signal of the slave module corresponding to the reset parameter, including the following sub-steps:
[0027] The main module sends the request code and reset parameters to the chip select module;
[0028] If the request code received by the chip selection module is correct, the chip selection module enters the response state from the standby state; otherwise, the chip selection module remains in the standby state;
[0029] The chip select module that enters the response state sets the chip select register according to the received reset parameter, and the chip select register interrupts the chip select signal of the corresponding slave module, and the slave module resumes the standby state.
[0030] Furthermore, the chip select module enters a standby state after completing the setting of the chip select register;
[0031] When the chip selection module receives the chip selection parameter, if it is in a standby state, it remains in the standby state and does not take any action.
[0032] The low-power SPI communication system and communication method of the present invention have at least the following beneficial effects: the present invention realizes precise gating of slave modules and dynamic control of clock paths by introducing a chip select module and a clock control module. During the communication process, only the selected slave module will be activated, and it also supports gating multiple slave modules at the same time, thereby improving the communication efficiency of the system; the clock control module can dynamically open and close the clock path between the slave module and the master module according to the chip select signal. When the slave module does not need to transmit data, the clock path is closed, thereby reducing ineffective power consumption; the master module can flexibly control the gating and interruption of the slave module by sending chip select parameters and reset parameters. This flexibility enables the system to adapt to different working modes and data transmission requirements; when it is necessary to read data from at least two slave modules at the same time, the chip select module can determine the priority of the received data and forward it to the master module in priority order, thereby ensuring communication reliability and data integrity. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0034] Figure 1 This is a structural principle diagram of an embodiment of a low-power SPI communication system of the present invention.
[0035] Figure 2 This is a flow chart of an embodiment of a low-power SPI communication method of the present invention.
[0036] Figure 3 This is a structural principle diagram of an implementation scheme of a low-power SPI communication system for a CMOS image sensor. DETAILED DESCRIPTION
[0037] The present invention will be further described below with reference to the accompanying drawings.
[0038] See also Figure 1 The low-power SPI communication system of the present invention includes a master module, a chip select module, a clock control module, several slave modules, and an SPI communication bus for connecting the master module, chip select module, clock control module, and slave modules. The master module is used to enable and / or disable the entire communication system and transmit chip select parameters and / or reset parameters to the chip select module during communication. The chip select module is used to control the chip select signal in response to the chip select parameters and / or reset parameters. The clock control module is used to enable and / or disable the clock path between the corresponding slave module and the master module in response to the chip select signal, thereby enabling communication between the master module and the slave modules.
[0039] The SPI communication bus includes SCLK, MOSI, MISO, and CS signal lines. The CS port of the master module is connected to the CS port of the chip select module via the CS signal lines. The chip select module's multiple chip select signal outputs are connected to the CSn ports of multiple slave modules via CSn signal lines in a one-to-one correspondence. The chip select signal outputs of the chip select module are also connected to the CSn ports of the clock control module via CSn signal lines in a one-to-one correspondence. In this embodiment, eight slave modules are provided, so n = 1, 2, ... 8. The MOSI port of the master module is also connected to the MOSI ports of each slave module via MOSI signal lines. The MOSI port of the master module is also connected to the MOSI port of the chip select module via MOSI signal lines. The SCLK port of the master module is connected to the SCLK input of the clock control module via the SCLK signal lines. The SCLK outputs of the clock control module are connected to the SCLK ports of multiple slave modules via SCLK signal lines in a one-to-one correspondence. The MISO ports of the slave modules are connected to the MISO signal input terminals of the chip select modules in a one-to-one correspondence via MISO signal lines, and the MISO signal output terminals of the chip select modules are connected to the MISO ports of the master modules via MISO signal lines.
[0040] The chip select module includes a chip select register, and the module sets the chip select register according to the chip select parameter and / or reset parameter. The multiple CSn ports of the chip select register serve as the multiple chip select signal output ends of the chip select module and are connected to the CSn ports of the multiple slave modules via CSn signal lines in a one-to-one correspondence. The multiple CSn ports of the chip select register are also connected to the multiple CSn ports of the clock control module in a one-to-one correspondence via CSn signal lines.
[0041] The present invention also discloses a low-power SPI communication method, which is implemented based on the low-power SPI communication system of the above embodiment. Figure 2 , is a flow chart of an embodiment of a low-power SPI communication method of the present invention. This embodiment specifically includes the following steps:
[0042] S100, gating system.
[0043] Specifically, when communication starts, the main module sends a system selection signal to the chip selection module to select the entire system. In this embodiment, the system selection signal is a high level.
[0044] S200, select the slave module.
[0045] Specifically, the master module sends chip select parameters to the chip select module. In response to the chip select parameters, the chip select module enables the chip select signal of the slave module corresponding to the chip select parameters, and the slave module enters the working state. The specific process includes: the master module sends a request code and chip select parameters to the chip select module; if the request code received by the chip select module is correct, it enters the response state from the standby state; otherwise, the chip select module remains in the standby state; the chip select module that enters the response state sets the chip select register according to the received chip select parameters, enables the chip select signal of the corresponding slave module, and the slave module enters the working state. It should be noted that after the chip select module completes the setting of the chip select register according to the received chip select parameters, it will enter the standby state. And if the chip select module is in the standby state when it receives the chip select parameters, it will remain in the standby state and do nothing.
[0046] S300, open the clock path.
[0047] Specifically, in response to the chip select signal, the clock control module opens a clock path between the slave module corresponding to the chip select signal and the master module.
[0048] S400: Perform communication.
[0049] Specifically, the master module communicates with a slave module whose clock path is enabled. Communication between the master module and the slave module includes data writing and data reading. The master module writes data to the slave module by: sending a write address code to the slave module, and upon receiving the write address code, the slave module switches from a standby state to a write data state; sending data to the slave module, and upon receiving the data, the slave module writes the data into an internal register corresponding to the write address. The master module reads data from the slave module by: sending a read address code to the slave module, and upon receiving the read address code, the slave module switches from a standby state to a read data state; and sending data from the register corresponding to the read address to a chip select module, and upon receiving the data, the chip select module forwards the data to the master module. It should be noted that when simultaneously reading data from at least two slave modules, after receiving data from the at least two slave modules, the chip select module prioritizes the data in the chip select register and then forwards the data to the master module in that order.
[0050] S500, interrupt communication.
[0051] Specifically, after communication is complete, the master module sends a reset parameter to the chip select module. In response to the reset parameter, the chip select module interrupts the chip select signal of the slave module corresponding to the reset parameter. The specific process includes: the master module sends a request code and reset parameter to the chip select module; if the request code received by the chip select module is correct, it enters the response state from the standby state; otherwise, the chip select module remains in the standby state; the chip select module in the response state sets the chip select register according to the received reset parameter, the chip select register interrupts the chip select signal of the corresponding slave module, and the slave module resumes the standby state.
[0052] S600: Close the clock path.
[0053] Specifically, after the chip select signal is interrupted, the clock control module closes the clock path between the slave module and the master module corresponding to the chip select signal. It should be understood that after all communications are completed, the system selection signal needs to be set to a low level and the entire system exits the communication state.
[0054] Below, we will take the COMS image sensor as an example to specifically explain the application of the low-power SPI communication system and communication method of the present invention. Figure 3In this implementation, the off-chip FPGA serves as the master module, while the on-chip interfaces 1, 2, and slave module 0 serve as the three slave modules. Interfaces 1 and 2 are responsible for the CMOS image sensor's data output, while slave module 0 is an internal module with data compression capabilities. In this implementation, the CMOS image sensor defaults to full-scale output mode, and slave module 0 enables data compression. In this default mode, the FPGA does not need to send commands to the CMOS image sensor.When the CMOS image sensor needs to turn off the data compression function of slave module 0 and the output rates of interface 1 and interface 2 are adjusted to twice the default rate, the specific communication method is as follows: (1) FPGA sends the request code 0x7a and the chip select parameter 0x01 to the chip select module through the MOSI signal line; (2) The chip select module receives the correct request code and enters the response state from the standby state; (3) The chip select module in the response state converts the received chip select parameter 0x01 into the corresponding binary code 0000_0001 and stores it in the chip select register; (4) The bit [0] of the chip select register corresponds to the chip select signal of slave module 0, and slave module 0 is selected. At the same time, the clock control module opens the clock path between the FPGA and slave module 0; (5) After the chip select parameters are stored in the chip select register, the chip select module re-enters the standby state; (6) The FPGA is now in a connected state with slave module 0, and the FPGA sends the write address code and data to slave module 0 via the MISO signal line. After the slave module 0 responds, it writes the corresponding address register and turns off the data compression function of slave module 0; (7) After the communication between the FPGA and slave module 0 ends, the FPGA sends the request code 0x7a and the reset parameter 0x00 to the chip select module via the MOSI signal line. After the chip select module receives the request code 0x7a and the reset parameter 0x00, the chip select module interrupts the chip select signal of slave module 0, and the clock control module The control module closes the clock path between the FPGA and slave module 0; (8) The FPGA sends a request code 0x7a and a chip select parameter 0x06 to the chip select module; (9) The chip select module receives the correct request code 0x7a, enters the response state from the standby state, and then converts the received chip select parameter 0x06 into the corresponding binary code 0000_0110 and stores it in the chip select register; (10) Bits [2] and [1] of the chip select register are pulled high to enable the chip select signals of interface 2 and interface 1, and at the same time the clock control module opens the clock path between the two slave modules and the FPGA; (11) After the chip select parameters are stored in the chip select register, the chip select module restarts. Enter the standby state; (12) FPGA is now connected to interface 2 and interface 1. FPGA sends write address code and data to interface 2 and interface 1 through the MOSI signal line. Interface 2 and interface 1 have the same structure and can respond to the address and data on the bus at the same time, adjusting the output rate to twice the default rate; (13) FPGA ends the communication with interface 2 and interface 1. FPGA sends the request code 0x7a and reset parameter 0x00 to the chip select module through the MOSI signal line. After receiving the request code, the chip select module interrupts the chip select signal of interface 2 and interface 1, and the clock control module closes the clock path between FPGA and interface 1 and interface 2.
[0055] When the FPGA needs to query the control parameters of the slave module 0 in the CMOS image sensor chip, the specific communication method is as follows: (1) The FPGA sends the request code 0x7a and the chip select parameter 0x01 to the chip select module through the MOSI signal line; (2) After receiving the correct request code, the chip select module enters the response state from the standby state; (3) The chip select module in the response state converts the received chip select parameter 0x01 into the corresponding binary code 0000_0001 and stores it in the chip select register; (4) The [0]th bit of the chip select register corresponds to the chip select signal of the slave module 0, so the chip select signal CS0 of the slave module 0 is set high, the slave module 0 is selected, and at the same time the clock control module opens the clock path between the FPGA and the slave module 0; (5) After the chip select parameters are stored in the chip select register, the chip select module enters the standby state; (6) The FPGA is now connected to slave module 0. The FPGA sends a read address to slave module 0 via the MOSI signal line. After slave module 0 responds, it outputs the register value corresponding to the read address to the chip select module via the MISO signal line; (7) After the chip select module receives the data from slave module 0, it transfers it to the FPGA via the MISO signal line; (8) The FPGA receives the data and the communication ends. The FPGA sends the request code 0x7a and the reset parameter 0x00 to the chip select module via the MOSI signal line. After receiving the data, the chip select module interrupts the chip select signal of slave module 0, and the clock control module turns off the clock path between the FPGA and slave module 0. It should be noted that when the chip select module receives data from multiple slave modules, it will prioritize the received data according to the value of the chip select register and then transfer it to the FPGA via the MISO signal line, thereby ensuring that only one slave module sends data at a time.
[0056] The present invention realizes precise gating of slave modules and dynamic control of clock paths by introducing a chip selection module and a clock control module. During the communication process, only the selected slave module will be activated, and it also supports gating multiple slave modules at the same time, thereby improving the communication efficiency of the system; the clock control module can dynamically open and close the clock path between the slave module and the master module according to the chip selection signal. When the slave module does not need to transmit data, the clock path is closed, thereby reducing invalid power consumption; the master module can flexibly control the gating and interruption of the slave module by sending chip selection parameters and reset parameters. This flexibility enables the system to adapt to different working modes and data transmission requirements; when it is necessary to read data from at least two slave modules at the same time, the chip selection module can determine the priority of the received data and forward it to the master module in priority order, thereby ensuring communication reliability and data integrity.
[0057] The above description merely expresses the preferred embodiments of the present invention, and its description is relatively specific and detailed, but it should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art may make a number of variations and improvements without departing from the concept of the present invention, and these variations and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent of the present invention shall be based on the appended claims.
Claims
1. A low-power SPI communication system, characterized in that: include: A master module, a chip select module, a clock control module, several slave modules, and an SPI communication bus for connecting the master module, chip select module, clock control module, and slave modules; the master module is used to enable and / or interrupt the entire communication system and send chip select parameters and / or reset parameters to the chip select module during communication; the chip select module is used to control the chip select signal in response to the chip select parameters and / or reset parameters; the clock control module is used to open and / or close the clock path between the corresponding slave module and the master module in response to the chip select signal, thereby realizing communication between the master module and the slave modules.
2. The low-power SPI communication system according to claim 1, wherein: The SPI communication bus includes an SCLK signal line, a MOSI signal line, a MISO signal line, and a CS signal line; the CS port of the master module is connected to the CS port of the chip select module via the CS signal line, and the chip select signal output ends of the chip select module are connected to the CSn ports of the slave modules in a one-to-one correspondence via the CSn signal line, and the chip select signal output ends of the chip select module are also connected to the CSn ports of the clock control module in a one-to-one correspondence via the CSn signal line; the MOSI port of the master module is also connected to the MOSI port of each slave module via the MOSI signal line. The MOSI port of the block is connected to the MOSI port of the chip select module through a MOSI signal line; the SCLK port of the master module is connected to the SCLK input end of the clock control module through an SCLK signal line, and several SCLK output ends of the clock control module are respectively connected to the SCLK ports of several slave modules through SCLK signal lines in a one-to-one correspondence; the MISO ports of the slave modules are respectively connected to the MISO signal input ends of the chip select module through MISO signal lines in a one-to-one correspondence, and the MISO signal output end of the chip select module is connected to the MISO port of the master module through a MISO signal line.
3. The low-power SPI communication system according to claim 2, wherein: The chip select module includes a chip select register, which is set according to chip select parameters and / or reset parameters. Several CSn ports of the chip select register serve as several chip select signal output ends of the chip select module and are connected to the CSn ports of several slave modules via CSn signal lines in a one-to-one correspondence. The several CSn ports of the chip select register are also connected to the CSn ports of the clock control module in a one-to-one correspondence via CSn signal lines.
4. A low-power SPI communication method, characterized in that: The low-power SPI communication system according to any one of claims 1 to 3 comprises the following steps: When communication starts, the master module sends a system selection signal to the chip selection module to select the entire system; The master module sends a chip select parameter to the chip select module. In response to the chip select parameter, the chip select module enables a chip select signal of a slave module corresponding to the chip select parameter, and the slave module enters a working state. In response to the chip select signal, the clock control module opens a clock path between the slave module and the master module corresponding to the chip select signal; The master module communicates with the slave module whose clock path is opened; After the communication is completed, the master module sends a reset parameter to the chip selection module, and in response to the reset parameter, the chip selection module interrupts the chip selection signal of the slave module corresponding to the reset parameter; After the chip select signal is interrupted, the clock control module turns off the clock path between the slave module and the master module corresponding to the chip select signal.
5. The low-power SPI communication method according to claim 4, wherein: The master module sends a request code and a chip select parameter to the chip select module, and in response to the request code and the chip select parameter, the chip select module enables a chip select signal of the slave module corresponding to the chip select parameter, and the step of the slave module entering a working state includes the following sub-steps: The main module sends the request code and chip select parameters to the chip select module; If the request code received by the chip selection module is correct, the chip selection module enters the response state from the standby state; otherwise, the chip selection module remains in the standby state; The chip selection module that has entered the response state sets the chip selection register according to the received chip selection parameter, enables the chip selection signal of the corresponding slave module, and the slave module enters the working state.
6. The low-power SPI communication method according to claim 4, wherein: In the step of communicating between the master module and the slave module whose clock path is opened, when the master module writes data into the slave module, the following sub-steps are included: The master module sends a write address code to the slave module, and after receiving the write address code, the slave module enters a data writing state from a standby state; The master module sends data to the slave module, and the slave module writes the data into the internal register corresponding to the write address after receiving the data.
7. The low-power SPI communication method according to claim 4, wherein: In the step of the master module communicating with the slave module whose clock path is opened, when the master module reads data from the slave module, the following sub-steps are included: The master module sends a read address code to the slave module, and after receiving the read address code, the slave module enters a data reading state from a standby state; The slave module sends the data of the register corresponding to the read address to the chip selection module, and the chip selection module forwards the data to the master module after receiving the data.
8. The low-power SPI communication method according to claim 7, wherein: When data from at least two slave modules are read simultaneously, after the chip select module receives data sent by at least two slave modules, the chip select register determines the priority of the received data and then forwards it to the master module in order of priority.
9. The low-power SPI communication method according to claim 4, wherein: After the communication is completed, the master module sends a reset parameter to the chip select module, and in response to the reset parameter, the chip select module interrupts the chip select signal of the slave module corresponding to the reset parameter, including the following sub-steps: The main module sends the request code and reset parameters to the chip select module; If the request code received by the chip selection module is correct, the chip selection module enters the response state from the standby state; otherwise, the chip selection module remains in the standby state; The chip select module that enters the response state sets the chip select register according to the received reset parameter, and the chip select register interrupts the chip select signal of the corresponding slave module, and the slave module resumes the standby state.
10. The low-power SPI communication method according to claim 5 or claim 9, wherein: After completing the setting of the chip select register, the chip select module enters the standby state; When the chip selection module receives the chip selection parameter, if it is in a standby state, it remains in the standby state and does not take any action.