Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a memory system, the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a plurality of supporting layers which are arranged at intervals in a first direction; the capacitor structure is located in the supporting layer and comprises a first energy storage structure and a first electrode layer; the first energy storage structure comprises a first energy storage layer and a second electrode layer, the supporting layers are arranged around the first electrode layer and connected with the first electrode layer, the first energy storage layer is located on the side, away from the supporting layers, of the first electrode layer, and the second electrode layer is located on the side, away from the first electrode layer, of the first energy storage layer; on the cross section perpendicular to the first direction Z, one part of the first electrode layer is located in the supporting layer, and the other part of the first electrode layer protrudes out of the supporting layer; the first energy storage layer is connected with the part, protruding out of the supporting layer, of the first electrode layer. According to the semiconductor device, the preparation method thereof and the memory system provided by the invention, the preparation process is simple, and the capacitance value of the capacitor structure can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a semiconductor device, a manufacturing method thereof, and a memory system. Background Art

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in integrated circuits. For example, a memory cell in a dynamic random access memory (DRAM) may include a transistor and a capacitor structure, with the transistor controlling the writing or reading of data into or from the capacitor structure.

[0003] However, in the preparation of three-dimensional integrated DRAM, the energy storage cavity used to accommodate the capacitor structure needs to be formed through multiple etching processes. The etching process is complex. During the etching process, the first electrode of the capacitor structure is lost, and the capacitance value of the capacitor structure is reduced. Summary of the Invention

[0004] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system, which have a simple manufacturing process and can improve the capacitance value of a capacitor structure.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a semiconductor device, including a first semiconductor structure, which includes: multiple support layers, which are arranged at intervals in a first direction; and a capacitor structure, which is located in a stack formed by the support layers and includes a first energy storage structure and a first electrode layer extending along the first direction; wherein the first energy storage structure includes a first energy storage layer and a second electrode layer, which respectively extend along the first direction, and the support layers are respectively arranged around the first electrode layer and respectively connected to the first electrode layer, the first energy storage layer is located on a side of the first electrode layer away from the support layer, and the second electrode layer is located on a side of the first energy storage layer away from the first electrode layer; wherein, in a cross section perpendicular to the first direction, a portion of the first electrode layer is located in the stack formed by the support layers, and another portion protrudes from the stack formed by the support layers; the first energy storage layer is connected to the portion of the first electrode layer that protrudes from the support layer.

[0007] In some embodiments, the portion of the first electrode layer protruding from the support layer is arc-shaped, the first energy storage layer has at least one first arc-shaped surface and at least one second arc-shaped surface, the first arc-shaped surface is concave toward the center of the circle where the second arc-shaped surface is located, and the first arc-shaped surface is connected to the second arc-shaped surface; in a second direction perpendicular to the first direction, the portion of the first electrode layer protruding from the support layer is connected to the first arc-shaped surface of the first energy storage layer, and the second arc-shaped surface of the first energy storage layer is connected to the support layer between two adjacent first electrode layers.

[0008] In some embodiments, the semiconductor device also includes a second semiconductor structure, and the support layer is located on the second semiconductor structure; the second semiconductor structure includes a transistor, the transistor includes a semiconductor column, the first electrode layer includes a first end connected to the semiconductor column and a second end away from the semiconductor column, and the first end of the first electrode layer is connected to the semiconductor column.

[0009] In some embodiments, the stack formed by the supporting layer includes a first supporting surface and a second supporting surface, the first supporting surface is away from the second semiconductor structure, and the second supporting surface is connected to the second semiconductor structure; the first end of the first electrode layer is connected to the semiconductor column, and the second end of the first electrode layer protrudes from the first supporting surface.

[0010] In some embodiments, the first electrode layer includes a first sub-electrode layer and a second sub-electrode layer extending along the first direction, respectively; at least a portion of the first sub-electrode layer is connected to the support layer, and another portion of the first sub-electrode layer away from the support layer is connected to the first energy storage layer; the second sub-electrode layer is located on a side of the first sub-electrode layer away from the support layer and the first energy storage layer and is connected to the first sub-electrode layer; wherein the second ends of the second sub-electrode layer and the first sub-electrode layer both protrude from the first support surface.

[0011] In some embodiments, the capacitor structure further includes a second energy storage structure and a third energy storage structure. The second energy storage structure is located between two adjacent support layers and connected to the first electrode layer. The third energy storage structure is located on the first support surface and connected to the first electrode layer.

[0012] In some embodiments, the second energy storage structure includes a second energy storage layer and a third electrode layer, the second energy storage layer is connected to the support layer and the first sub-electrode layer, and the third electrode layer is located on the side of the second energy storage layer away from the support layer and the first sub-electrode layer; the third energy storage structure includes a third energy storage layer and a fourth electrode layer, the third energy storage layer is connected to the support layer and the first sub-electrode layer, and the fourth electrode layer is located on the side of the third energy storage layer away from the support layer and the first sub-electrode layer.

[0013] In some embodiments, the second ends of the first electrode layers are independent of each other.

[0014] In some embodiments, the first energy storage structure further includes a first filling layer, which is located on a side of the second electrode layer away from the first energy storage layer and extends along a first direction, and an end of the first filling layer away from the second semiconductor structure protrudes from the second end of the first electrode layer; the second energy storage structure further includes a second filling layer, the third electrode layer surrounds the second filling layer, and the second energy storage layer surrounds the third electrode layer; the third energy storage structure further includes a third filling layer, the third filling layer is located on a side of the fourth electrode layer away from the third energy storage layer, and the fourth electrode layer surrounds the third filling layer.

[0015] In some embodiments, the cross-section of the first sub-electrode layer along the first direction is U-shaped, and the end of the first sub-electrode layer away from the first support surface is connected to the semiconductor column; the cross-sections of the first energy storage layer and the second electrode layer along the first direction are both U-shaped, and the end of the first energy storage layer away from the first support surface is connected to the support layer connected to the second semiconductor structure.

[0016] In some embodiments, the first energy storage layer of a first energy storage structure is respectively connected to a plurality of first electrode layers distributed around the first energy storage structure.

[0017] In some embodiments, the number of support layers is greater than or equal to three.

[0018] The present application also provides a method for preparing a semiconductor device, comprising: forming a stacked structure, the stacked structure comprising a first sacrificial layer and a supporting layer alternately stacked in a first direction; the stacked structure further comprising a first supporting surface and a second supporting surface opposite to the first supporting surface in the first direction; forming a plurality of blind holes extending from the first supporting surface to the second supporting surface on the stacked structure, the blind holes penetrating at least a portion of the supporting layer and at least a portion of the first sacrificial layer; filling the blind holes with a sacrificial layer material to obtain a second sacrificial layer connected to the first sacrificial layer; forming a plurality of electrode holes on the stacked structure penetrating the first sacrificial layer and the supporting layer of the stacked structure along the first direction, the electrode holes being arranged adjacent to the blind holes; filling the electrode holes with a first electrode material to obtain a first electrode layer, the first electrode layer being connected to the first sacrificial layer, the second sacrificial layer and the supporting layer; and removing the second sacrificial layer to obtain a first energy storage cavity and forming a first energy storage structure in the first energy storage cavity.

[0019] In some embodiments, the process of removing the second sacrificial layer to obtain the first energy storage cavity and forming the first energy storage structure in the first energy storage cavity further includes: removing the first sacrificial layer to obtain the second energy storage cavity and forming the second energy storage structure in the second energy storage cavity.

[0020] In some embodiments, after the step of filling the blind hole with a sacrificial layer material to obtain a second sacrificial layer, the step further includes: forming a third sacrificial layer on the first supporting surface of the stacked structure, the third sacrificial layer covering the second sacrificial layer and the supporting layer; the loss ratio of the third sacrificial layer in dry etching is less than the loss ratio of the supporting layer in dry etching; in the process of forming a plurality of electrode holes on the stacked structure that penetrate the remaining first sacrificial layer and the supporting layer of the stacked structure along the first direction, the electrode holes also penetrate the third sacrificial layer; in the process of filling the electrode holes with a first electrode material to obtain a first electrode layer, the first electrode layer is also connected to the third sacrificial layer; in the process of removing the second sacrificial layer to obtain a first energy storage cavity and forming a first energy storage structure in the first energy storage cavity, the step further includes: removing the third sacrificial layer to obtain a third energy storage cavity and forming a third energy storage structure in the third energy storage cavity.

[0021] In some embodiments, the semiconductor device includes a first semiconductor structure, the first semiconductor structure includes a support layer, a first electrode layer, a first energy storage structure, a second energy storage structure and a third energy storage structure; before the step of forming a stacked structure, the step also includes: providing a second semiconductor structure, the second semiconductor structure includes a plurality of semiconductor pillars; the stacked structure is located on the second semiconductor structure; the first energy storage cavity is located between a plurality of adjacent first electrode layers, and in the process of forming a plurality of electrode holes on the stacked structure that penetrate the first sacrificial layer and the support layer of the stacked structure along the first direction, the positions of the electrode holes are arranged one by one relative to the positions of the semiconductor pillars, and the first electrode layer is connected to the semiconductor pillars.

[0022] In some embodiments, during the process of removing the second sacrificial layer to obtain the first energy storage cavity, multiple first electrode layers are distributed around a first energy storage cavity, a portion of the first electrode layer is connected to the support layer, and the other portion is located in the first energy storage cavity.

[0023] In some embodiments, the steps of forming a first energy storage structure, forming a second energy storage structure, and forming a third energy storage structure include: forming a first energy storage layer in a first energy storage cavity, forming a second energy storage layer in a second energy storage cavity, and forming a third energy storage layer in a third energy storage cavity, the first electrode layer being connected to the first energy storage layer, the second energy storage layer, and the third energy storage layer, respectively; forming a second electrode layer on a side of the first energy storage layer away from the first electrode layer, forming a third electrode layer on a side of the second energy storage layer away from the first electrode layer, and forming a fourth electrode layer on a side of the third energy storage layer away from the first electrode layer; and forming a first filling layer, a second filling layer, and a third filling layer, respectively, on the sides of the second electrode layer, the third electrode layer, and the fourth electrode layer away from the first electrode layer.

[0024] In some embodiments, during the process of forming a first energy storage layer in a first energy storage cavity, forming a second energy storage layer in a second energy storage cavity, and forming a third energy storage layer in a third energy storage cavity, in a second direction and a third direction perpendicular to the first direction, a portion of the first electrode layer is connected to the support layer, another portion of the first electrode layer is connected to the first energy storage layer, and the first energy storage layer is also connected to the support layer between two adjacent first electrode layers.

[0025] The present application also provides a memory system, comprising: at least one semiconductor device as described above; and a controller coupled to the semiconductor device and configured to control the semiconductor device.

[0026] The present application provides a semiconductor device, a preparation method thereof, and a memory system, wherein the semiconductor device is formed by the following steps, specifically: forming a stacked structure, the stacked structure including a first sacrificial layer and a supporting layer alternately stacked in a first direction; the stacked structure also including a first supporting surface and a second supporting surface opposite to the first supporting surface in the first direction; forming a plurality of blind holes extending from the first supporting surface to the second supporting surface on the stacked structure, the blind holes penetrating at least a portion of the supporting layer and the first sacrificial layer; filling the blind holes with a sacrificial layer material to obtain a second sacrificial layer connected to the first sacrificial layer; forming a plurality of electrode holes on the stacked structure penetrating the first sacrificial layer and the supporting layer of the stacked structure along the first direction, the electrode holes being arranged adjacent to the blind holes; filling the electrode holes with a first electrode material to obtain a first electrode layer, the first electrode layer being connected to the first sacrificial layer, the second sacrificial layer, and the supporting layer; and removing the second sacrificial layer to obtain a first energy storage cavity and forming a first energy storage structure in the first energy storage cavity. In the preparation method of a semiconductor device, the present application forms a blind hole penetrating the first sacrificial layer and the support layer between two adjacent electrode holes before the step of forming the electrode hole, and forms a second sacrificial layer connected to the first sacrificial layer in the blind hole. In this way, since there is no gap of the support layer, the remaining first sacrificial layer and the second sacrificial layer in the stacked structure can be removed at one time through a single etching process. That is to say, the formation of the electrode hole of the present application only requires one etching without multiple etchings. The preparation method of the semiconductor device provided by the present application not only has a simple preparation process, but also reduces the loss of the first electrode layer during the preparation process, thereby improving the capacitance value of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application.

[0029] Figure 2 A cross-sectional view of the initial semiconductor structure provided for this application.

[0030] Figure 3 For Figure 2 A cross-sectional view of the initial semiconductor structure after an initial electrode layer is formed in the electrode hole shown.

[0031] Figure 4 For patterning Figure 3The initial electrode layer and the support layer on the surface of the stacked structure of the initial semiconductor structure are shown, and a cross-sectional view after the first electrode layer is obtained.

[0032] Figure 5 To remove Figure 4 A cross-sectional view showing the first sacrificial layer exposed from within the first sub-storage cavity is shown.

[0033] Figure 6 To remove Figure 5 A cross-sectional view showing the supporting layer exposed from the second sub-storage cavity is shown.

[0034] Figure 7 To remove Figure 6 The first sacrificial layer exposed from the third sub-storage cavity is shown as a cross-sectional view after obtaining the first intermediate semiconductor structure.

[0035] Figure 8 for Figure 7 A partial top view of the first intermediate semiconductor structure is shown.

[0036] Figure 9 For Figure 8 The cross-sectional view of the semiconductor device is shown after the first energy storage structure is formed in the first energy storage cavity.

[0037] Figure 10 A schematic flow chart of a method for preparing a semiconductor device provided in some other embodiments of the present application.

[0038] Figure 11 Cross-sectional views of initial semiconductor structures provided for some other embodiments of the present application.

[0039] Figure 12 For Figure 11 The cross-sectional view of the stacked structure of the initial semiconductor structure after a first hard mask layer is formed on the surface thereof is shown.

[0040] Figure 13 For Figure 12 A cross-sectional view of a laminate structure after blind vias are formed therein is shown.

[0041] Figure 14 For Figure 13 The cross-sectional view is shown after the blind hole is filled with sacrificial layer material to obtain a second sacrificial layer.

[0042] Figure 15 For Figure 14 A cross-sectional view of the stacked structure after a third sacrificial layer is formed on the first supporting surface is shown.

[0043] Figure 16 For Figure 15 The cross-sectional view is shown after a second hard mask layer and electrode holes are formed on the stacked structure.

[0044] Figure 17 To remove Figure 16 A cross-sectional view after the second hard mask layer is shown.

[0045] Figure 18 For Figure 17 A cross-sectional view of the electrode hole after the initial electrode layer is formed.

[0046] Figure 19 To remove Figure 18 A cross-sectional view of a portion of the initial electrode layer after obtaining the first electrode layer is shown.

[0047] Figure 20 To remove Figure 19 The first sacrificial layer, the second sacrificial layer and the third sacrificial layer are shown as a cross-sectional view after obtaining the second intermediate semiconductor structure.

[0048] Figure 21 for Figure 20 A partial top view of the second intermediate semiconductor structure is shown.

[0049] Figure 22 For Figure 20 The energy storage structure is formed in the energy storage cavity of the second intermediate semiconductor structure, and a cross-sectional view of the semiconductor device is obtained.

[0050] Figure 23 for Figure 22 A partial top view of the semiconductor device shown.

[0051] Figure 24 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings of some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0053] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0054] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0055] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0056] The present application addresses the technical problem of difficulty in etching electrode holes in DRAMs, and provides a method for preparing a semiconductor device, comprising: forming a stacked structure, the stacked structure comprising a first sacrificial layer and a supporting layer alternately stacked in a first direction; the stacked structure further comprising a first supporting surface and a second supporting surface opposite to the first supporting surface in the first direction; forming a plurality of blind holes extending from the first supporting surface to the second supporting surface on the stacked structure, the blind holes penetrating at least a portion of the supporting layer; filling the blind holes with a sacrificial layer material to obtain a second sacrificial layer connected to the first sacrificial layer; forming a plurality of electrode holes on the stacked structure penetrating the first sacrificial layer and the supporting layer of the stacked structure along the first direction, the electrode holes being arranged adjacent to the blind holes; filling the electrode holes with a first electrode material to obtain a first electrode layer, the first electrode layer being connected to the first sacrificial layer, the second sacrificial layer and the supporting layer; and removing the second sacrificial layer to obtain a first energy storage cavity and forming a first energy storage structure in the first energy storage cavity. In the preparation method of a semiconductor device, the present application forms a blind hole penetrating the first sacrificial layer and the support layer between two adjacent electrode holes before the step of forming the electrode hole, and forms a second sacrificial layer connected to the first sacrificial layer in the blind hole. In this way, since there is no gap of the support layer, the remaining first sacrificial layer and the second sacrificial layer in the stacked structure can be removed at one time through a single etching process. That is to say, the formation of the electrode hole of the present application only requires one etching without multiple etchings. The preparation method of the semiconductor device provided by the present application not only has a simple preparation process, but also reduces the loss of the first electrode layer during the preparation process, thereby improving the capacitance value of the capacitor structure.

[0057] The following will be combined Figures 1 to 22 , specifically describe the specific structure and preparation method of the semiconductor device.

[0058] See also Figures 1 to 8 , the present application provides a method for preparing a semiconductor device 100, comprising:

[0059] Step S11, please refer to Figure 1 and Figure 2 , providing an initial semiconductor structure 110 including a stacked structure 10 and forming an electrode hole 11 penetrating the stacked structure 10 in the stacked structure 10 .

[0060] In some embodiments, the stacked structure 10 includes first sacrificial layers 12 and support layers 13 alternately stacked in a first direction Z. The stacked structure 10 further includes a first support surface 141 and a second support surface 142 , which are oppositely disposed in the first direction Z.

[0061] In some embodiments, the initial semiconductor structure 110 further includes a second semiconductor structure 20 , and the stacked structure 10 is located on the second semiconductor structure 20 . The second supporting surface 142 is in contact with the second semiconductor structure 20 .

[0062] In some embodiments, the second semiconductor structure 20 includes a transistor 21 and a dielectric layer 22. The transistor 21 is located within the dielectric layer 22. The transistor 21 includes a semiconductor pillar 211, an ohmic contact layer 212, and a connection contact 213. The semiconductor pillar 211 extends along a first direction Z. The ohmic contact layer 212 is located at one end of the semiconductor pillar 211 in the first direction Z. The connection contact 213 is located at one end of the ohmic contact layer 212 in the first direction Z. A support layer 13 is connected to the second semiconductor structure 20.

[0063] Step S12, see Figure 1 、 Figure 3 and Figure 4 An initial electrode layer 14 is formed in the electrode hole 11 of the initial semiconductor structure 110 and on the second support surface 142 of the stacked structure 10 , and the initial electrode layer 14 on the second support surface 142 is patterned to obtain a first electrode layer 15 .

[0064] In step S12, the support layer 13 connected to the initial electrode layer 14 located on the second support surface 142 is also patterned, that is, the portion of the support layer 13 located between and connected to two adjacent electrode holes 11 is removed to form a first sub-energy storage cavity 1511 connected to the electrode hole 11. The first electrode layer 15 includes an electrode portion 151 located in two adjacent electrode holes 11 and a connecting portion 152 connecting any two adjacent electrode portions 151.

[0065] In step S12 , due to the characteristics of etching, when the initial electrode layer 14 on the second supporting surface 142 is patterned, a portion of the electrode portion 151 will also be etched.

[0066] Step S13, please refer to Figure 1 and Figure 5 , removing the first sacrificial layer 12 exposed from the first sub-energy storage cavity 1511 to obtain a second sub-energy storage cavity 1512 communicating with the first sub-energy storage cavity 1511 .

[0067] In step S13 , the other supporting layers 13 on the same layer as the first sacrificial layer 12 exposed from the first sub-energy storage cavity 1511 are also removed to obtain the second energy storage cavity 161 .

[0068] Step S14, please refer to Figure 1 and Figure 6 , removing the support layer 13 exposed from the second sub-energy storage cavity 1512 to obtain a third sub-energy storage cavity 1513 communicating with the second sub-energy storage cavity 1512 .

[0069] In step S14 , the support layer 13 covered by the connection portion 152 is not removed.

[0070] Step S15, please refer to Figure 1 、 Figure 7 and Figure 8 The first sacrificial layer 12 exposed from the third sub-energy storage cavity 1513 is removed to obtain a fourth sub-energy storage cavity 1514 connected to the third sub-energy storage cavity 1513 and the first intermediate semiconductor structure 120. The first sub-energy storage cavity 1511, the second sub-energy storage cavity 1512, the third sub-energy storage cavity 1513 and the fourth sub-energy storage cavity 1514 constitute the first energy storage cavity 162.

[0071] The first intermediate semiconductor structure 120 includes a first electrode layer 15 and a patterned support layer 13 .

[0072] In step S15 , other support layers 13 on the same layer as the first sacrificial layer 12 exposed from the first sub-energy storage cavity 1511 are also removed. That is, the energy storage cavity between two adjacent support layers 13 covered by the connecting portion 152 is the second energy storage cavity 161 .

[0073] In some embodiments, a first sub-energy storage chamber 1511 is connected to multiple electrode holes 11 , and a connecting portion 152 is connected to multiple electrode portions 151 .

[0074] Step S16, see Figure 1 and Figure 9 A first energy storage layer 171 and a second electrode layer 172 are formed in the first energy storage cavity 162 to obtain a first energy storage structure 17, and a second energy storage layer (not shown) and a third electrode layer (not shown) are formed in the second energy storage cavity 161 to obtain a second energy storage structure (not shown), and finally a semiconductor device 100 is obtained.

[0075] The first energy storage structure 17 includes a first energy storage layer 171 and a second electrode layer 172. The first energy storage layer 171 is located between the electrode portion 151 of the first electrode layer 15 and the second electrode layer 172. The second energy storage structure includes a second energy storage layer and a third electrode layer. The second energy storage layer is located between the electrode portion 151 of the first electrode layer 15 and the third electrode layer. One first energy storage layer 171 is connected to multiple electrode portions of the first electrode layer 15. In the first direction Z, one electrode portion 151 of the first electrode layer 15 is connected to multiple second energy storage layers.

[0076] In some embodiments, the first energy storage structure 17 further includes a first filling layer 173 , and the second electrode layer 172 is located between the first energy storage layer 171 and the first filling layer 173 ; the second energy storage structure further includes a second filling layer, and the third electrode layer is located between the second energy storage layer and the second filling layer.

[0077] Because the formation of the electrode holes requires multiple etching steps, the first electrode layer 15 of the semiconductor device 100 provided herein suffers from a loss of the electrode portion 151 away from the second semiconductor structure 20, reducing the capacitance of the capacitor structure and making the etching process more complex. Furthermore, as the density of the capacitor structure increases, the number of electrode holes and energy storage cavities required to accommodate the first electrode layer and energy storage structure increases. After removing the first sacrificial layer 12, the support function of the support layer 13 is weakened, making the first electrode layer 15 susceptible to bending.

[0078] In order to improve these problems, the present application provides a method for preparing a semiconductor device 200 . Please refer to the following embodiments for details.

[0079] See also Figures 10 to 23 , the present application provides a method for preparing a semiconductor device 200, comprising:

[0080] Step S21, please refer to Figures 10 and 11 , providing a second semiconductor structure 30 , the second semiconductor structure 30 includes a plurality of semiconductor pillars 31 .

[0081] In some embodiments, the second semiconductor structure 30 includes a transistor 301 and a dielectric layer 302. The transistor 301 is located within the dielectric layer 302. The transistor 301 includes a semiconductor pillar 31, an ohmic contact layer 32, and a connection contact 33. The semiconductor pillar 31 extends along a first direction Z. The ohmic contact layer 32 is located at one end of the semiconductor pillar 31 in the first direction Z. The connection contact 33 is located at one end of the ohmic contact layer 32 in the first direction Z. Of course, the transistor 301 also includes a gate layer (not shown) disposed on at least one side of the semiconductor pillar 31.

[0082] In some embodiments, the dielectric layer 302 is made of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In this embodiment, the dielectric layer 302 is made of silicon oxide.

[0083] Step S22, please refer again Figure 10 and Figure 11 , forming a stacked structure 40, the stacked structure 40 includes a first sacrificial layer 41 and a support layer 42 alternately stacked in the first direction Z; the stacked structure 40 also includes a first support surface 421 and a second support surface 422 opposite to the first support surface 421 in the first direction Z.

[0084] In step S22 , the stacked structure 40 is located on one side of the second semiconductor structure 30 .

[0085] In some embodiments, the first supporting layer 42 is connected to the second semiconductor structure 30 .

[0086] In step S22 , the number of the support layers 42 is greater than or equal to 3, so as to enhance the supporting function of the support layer 13 and prevent bending of the first electrode layer that may occur after the first sacrificial layer 41 is completely removed.

[0087] In some embodiments, the first supporting surface 421 is connected to the second semiconductor structure 30 .

[0088] In some embodiments, the first sacrificial layer 41 is made of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In this embodiment, the first sacrificial layer 41 is made of silicon oxide.

[0089] In some embodiments, the support layer 42 is made of at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), etc. In this embodiment, the support layer 42 is made of silicon nitride.

[0090] Step S23, please refer to Figure 10 、 Figure 12 and Figure 13 A plurality of blind holes 43 extending from the first supporting surface 421 to the second supporting surface 422 are formed on the stacked structure 40 . The blind holes 43 penetrate at least a portion of the supporting layer 42 and at least a portion of the first sacrificial layer 41 .

[0091] The orthographic projection of the blind hole 43 on the second semiconductor structure 30 at least falls between two adjacent transistors 301 .

[0092] See also Figure 12 In some embodiments, a hard mask layer 401, an anti-reflective layer 402, and a photoresist 403 may be sequentially formed on the surface of the stacked structure 40, and the stacked structure 40 may be patterned through an image transfer process to obtain a blind hole 43.

[0093] In step S23 , the blind via 43 penetrates at least a portion of the first sacrificial layer 41 closest to the second semiconductor structure 30 , penetrates the remaining first sacrificial layer 41 , and penetrates the supporting layer 42 except the supporting layer 42 connected to the second semiconductor structure 30 .

[0094] Step S24, please refer to Figure 10 and Figure 14 , a sacrificial layer material is filled in the blind hole 43 to obtain a second sacrificial layer 44 connected to the first sacrificial layer 41 .

[0095] In step S24 , the second sacrificial layer 44 is located in the blind hole 43 , and one end of the second sacrificial layer 44 close to the second semiconductor structure 30 is connected to the remaining first sacrificial layer 41 .

[0096] In some embodiments, the second sacrificial layer 44 is made of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In this embodiment, the second sacrificial layer 44 is made of silicon oxide.

[0097] Before forming the electrode hole 46 (see below), the present application first forms a blind hole 43 whose orthographic projection falls between two adjacent semiconductor pillars 31 and fills the blind hole 43 with a second sacrificial layer 44. In the process of forming the blind hole 43, the first sacrificial layer 41 and the support layer 42 corresponding to the blind hole 43 are removed together, and the second sacrificial layer 44 replaces part of the first sacrificial layer 41 and the support layer 42. That is, when the first energy storage cavity 48, the second energy storage cavity 49 and the third energy storage cavity 50 are subsequently formed, the remaining first sacrificial layer 41 in the stacked structure 40 is not separated by the support layer 42. 41 and the second sacrificial layer 44 can be removed at one time through a one-time etching process, that is, the formation of the electrode hole 46 of the present application only requires one etching without multiple etchings. Compared with the preparation method of the semiconductor device in the above embodiment that uses multiple etchings to remove the first sacrificial layer 12 and the support layer 13 respectively to form the first energy storage cavity 162 and the second energy storage cavity 161, the preparation method of the semiconductor device of the present application not only has a simple preparation process, but also reduces the cost and the loss of the first electrode layer 47 during the preparation process, thereby improving the capacitance value of the capacitor structure.

[0098] Step S25, please refer to Figure 10 and Figure 15 A third sacrificial layer 45 is formed on the first supporting surface 421 of the stacked structure 40 , and the third sacrificial layer 45 covers the second sacrificial layer 44 and the supporting layer 42 .

[0099] In the dry etching, the loss ratio of the third sacrificial layer 45 is smaller than the loss ratio of the supporting layer 42 .

[0100] In some embodiments, the third sacrificial layer 45 is made of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In this embodiment, the third sacrificial layer 45 is made of silicon oxide.

[0101] Step S26, see Figure 10 、 Figure 16 and Figure 17 A plurality of electrode holes 46 are formed on the stacked structure 40 along the first direction Z and penetrate the first sacrificial layer 41 and the support layer 42 of the stacked structure 40 . The electrode holes 46 are arranged adjacent to the blind holes 43 .

[0102] The orthographic projection of the electrode hole 46 on the second semiconductor structure 30 at least covers a portion of the semiconductor pillar 31 of the transistor 301 .

[0103] See also Figure 16 , by forming a second hard mask layer 417 on the side of the third sacrificial layer 45 away from the stacked structure 40 and forming the electrode hole 46 through an image transfer process. Figure 17 After forming the electrode hole 46 , the second hard mask layer 417 is removed by a dry etching process.

[0104] Since the loss ratio of the third sacrificial layer 45 (for example: SiO) is smaller than the loss ratio of the support layer 42 (for example: SiN) during dry etching, the loss of the support layer of pure silicon nitride material in the dry etching process is higher than the loss of the stack composed of the third sacrificial layer 45 of silicon oxide material and the support layer 42 of silicon nitride material of the same thickness during dry etching. Therefore, the depth of the electrode hole obtained in the present application in the first direction Z is greater than the depth of the electrode hole formed in the support layer of pure silicon nitride material. As a result, the effective height of the capacitor structure obtained in the present application is increased, and the capacitance value of the capacitor structure is increased.

[0105] In step S26 , the electrode hole 46 also penetrates the third sacrificial layer 45 .

[0106] Step S27, see Figure 10 、 Figure 18 and Figure 19 The electrode hole 46 is filled with a first electrode material to obtain a first electrode layer 47 , which is connected to the first sacrificial layer 41 , the second sacrificial layer 44 and the support layer 42 . One end of the first electrode layer 47 is connected to the semiconductor pillar 31 .

[0107] In step S27 , the first electrode layer 47 is further connected to the third sacrificial layer 45 .

[0108] In some embodiments, the first electrode layer 47 is connected to the semiconductor pillar 31 through the connection contact 33 and the ohmic contact layer 32 .

[0109] In some embodiments, the first electrode layer 47 includes a first end 471 connected to the semiconductor pillar 31 and a second end 472 away from the semiconductor pillar 31 . The first end 471 of the first electrode layer 47 is connected to the semiconductor pillar 31 .

[0110] In some embodiments, the first electrode layer 47 includes a first sub-electrode layer 473 and a second sub-electrode layer 474, each extending along the first direction Z. At least a portion of the first sub-electrode layer 473 is connected to at least three support layers 42, and another portion of the first sub-electrode layer 473 not connected to the support layers 42 is respectively connected to the first sacrificial layer 41, the second sacrificial layer 44, and the third sacrificial layer 45. The second ends 472 of the second sub-electrode layer 474 and the first sub-electrode layer 473 both protrude from the first support surface 421.

[0111] In some embodiments, a cross-section of the first sub-electrode layer 473 along the first direction Z is U-shaped, and one end of the first sub-electrode layer 473 away from the first supporting surface 421 is connected to the semiconductor pillar 31 .

[0112] Step S27 includes: first, refer to Figure 18 , an initial first electrode layer 407 is formed in the electrode hole 46 and on the side of the third sacrificial layer 45 away from the stacked structure 40; secondly, refer to Figure 19 , a portion of the initial first electrode layer 407 located on a side of the third sacrificial layer 45 away from the stacked structure 40 is removed to obtain a first electrode layer 47 .

[0113] Step S28, see Figure 10 and Figures 20 to 23 , the second sacrificial layer 44 is removed to obtain a first energy storage cavity 48 and a first energy storage structure 51 is formed in the first energy storage cavity 48 to obtain a semiconductor device 200 .

[0114] The first energy storage structure 51 and the first electrode layer 47 form a capacitor structure.

[0115] Step S28 further includes: removing the first sacrificial layer 41 to obtain a second energy storage cavity 49 and forming a second energy storage structure 52 in the second energy storage cavity 49 .

[0116] Step S28 further includes: removing the third sacrificial layer 45 to obtain a third energy storage cavity 50 and forming a third energy storage structure 53 in the third energy storage cavity 50 .

[0117] Please refer again Figure 20 and Figure 21 In step S28, a first energy storage cavity 48 is located between multiple adjacent first electrode layers 47. In this embodiment, a first energy storage cavity 48 is located between four adjacent first electrode layers 47. That is, multiple first electrode layers 47 are distributed around a first energy storage cavity 48, with a portion of the first electrode layer 47 connected to the support layer 42 and the other portion located within the first energy storage cavity 48.

[0118] Please refer again Figure 20 and Figure 21In some embodiments, after removing the first sacrificial layer 41, the second sacrificial layer 44, and the third sacrificial layer 45, a second intermediate semiconductor structure 420 is obtained. The second intermediate semiconductor structure 420 includes a support layer 42, a first electrode layer 47, and a second semiconductor structure 30. A second energy storage cavity 49 is defined between adjacent support layers 42, and a first energy storage cavity 48 is defined between adjacent first electrode layers 47. The support layer 42 farthest from the second semiconductor structure 30 and the first electrode layer 47 protruding from the support layer 42 form a third energy storage cavity 50. The second energy storage cavity 49 and the third energy storage cavity 50 are respectively connected to the first energy storage cavity 48.

[0119] In some embodiments, the transistor 301 further includes an ohmic contact layer 32 and a connecting contact 33 . The semiconductor pillar 31 extends along a first direction Z. The ohmic contact layer 32 is located at one end of the semiconductor pillar 31 in the first direction Z. The connecting contact 33 is located at one end of the ohmic contact layer 32 in the first direction Z. Of course, the transistor 301 further includes a gate layer (not shown) disposed on at least one side of the semiconductor pillar 31 .

[0120] See also Figure 22 and Figure 23 In some embodiments, the first energy storage structure 51 includes a first energy storage layer 511 and a second electrode layer 512 extending along the first direction Z, respectively. The support layers 42 are respectively arranged around the first electrode layer 47 and are respectively connected to the first electrode layer 47. The first energy storage layer 511 is located on the side of the first electrode layer 47 away from the support layer 42, and the second electrode layer 512 is located on the side of the first energy storage layer 511 away from the first electrode layer 47.

[0121] In some embodiments, the second sub-electrode layer 474 is located on a side of the first sub-electrode layer 473 away from the support layer 42 and the first energy storage layer 511 and is connected to the first sub-electrode layer 473 .

[0122] In some embodiments, the cross-sections of the first energy storage layer 511 and the second electrode layer 512 along the first direction Z are both U-shaped, and one end of the first energy storage layer 511 away from the first supporting surface 421 is connected to the supporting layer 42 connected to the second semiconductor structure 30 .

[0123] In some embodiments, the first energy storage layer 511 of a first energy storage structure 51 is respectively connected to a plurality of first electrode layers 47 distributed around the first energy storage structure 51 .

[0124] See also Figure 22 and Figure 23In some embodiments, the second energy storage structure 52 includes a second energy storage layer 521 and a third electrode layer 522. The second energy storage layer 521 is connected to the support layer 42 and the first sub-electrode layer 473. The third electrode layer 522 is located on a side of the second energy storage layer 521 away from the support layer 42 and the first sub-electrode layer 473. The second energy storage structure 52 also includes a second filling layer 523. The second filling layer 523 is located on a side of the third electrode layer 522 away from the second energy storage layer 521. The third electrode layer 522 surrounds at least a portion of the second filling layer 523.

[0125] The third energy storage structure 53 includes a third energy storage layer 531 and a fourth electrode layer 532. The third energy storage layer 531 is connected to the support layer 42 and the first sub-electrode layer 473. The fourth electrode layer 532 is located on a side of the third energy storage layer 531 away from the support layer 42 and the first sub-electrode layer 473. The third energy storage structure 53 also includes a third filling layer 533. The third filling layer 533 is located on a side of the fourth electrode layer 532 away from the third energy storage layer 531. The fourth electrode layer 532 surrounds at least a portion of the third filling layer 533.

[0126] In some embodiments, the cross-sections of the second energy storage layer 521 , the third electrode layer 522 , the third energy storage layer 531 and the fourth electrode layer 532 along the first direction Z are all U-shaped, and the second energy storage layer 521 and the third energy storage layer 531 are connected to the support layer 42 and the first sub-electrode layer 473 .

[0127] See also Figure 22 and Figure 23 In some embodiments, the steps of forming the first energy storage structure 51, forming the second energy storage structure 52, and forming the third energy storage structure 53 include: first, forming a first energy storage layer 511 in the first energy storage cavity 48, forming a second energy storage layer 521 in the second energy storage cavity 49, and forming a third energy storage layer 531 in the third energy storage cavity 50, and the first electrode layer 47 is connected to the first energy storage layer 511, the second energy storage layer 521, and the third energy storage layer 531 respectively; second, forming a second electrode layer 512 on a side of the first energy storage layer 511 away from the first electrode layer 47, forming a third electrode layer 522 on a side of the second energy storage layer 521 away from the first electrode layer 47, and forming a fourth electrode layer 532 on a side of the third energy storage layer 531 away from the first electrode layer 47; third, forming a first filling layer 513, a second filling layer 523, and a third filling layer 533 on the sides of the second electrode layer 512, the third electrode layer 522, and the fourth electrode layer 532 away from the first electrode layer 47 respectively.

[0128] In some embodiments, in the steps of forming the first energy storage layer 511 in the first energy storage cavity 48, forming the second energy storage layer 521 in the second energy storage cavity 49, and forming the third energy storage layer 531 in the third energy storage cavity 50, in the second direction X and the third direction Y perpendicular to the first direction Z, a portion of the first electrode layer 47 is connected to the support layer 42, another portion of the first electrode layer 47 is connected to the first energy storage layer 511, and the first energy storage layer 511 is also connected to the support layer 42, the second energy storage layer 521, and the third energy storage layer 531 between two adjacent first electrode layers 47.

[0129] Please refer again Figure 22 and Figure 23 The present application also provides a semiconductor device 200, comprising a first semiconductor structure 70. The first semiconductor structure 70 includes a plurality of support layers 42 spaced apart in a first direction Z and a capacitor structure 60. The capacitor structure 60 is located within a stack formed by the support layers 42 and includes a first energy storage structure 51 and a first electrode layer 47 extending along the first direction Z. The first energy storage structure 51 includes a first energy storage layer 511 and a second electrode layer 512, each extending along the first direction Z. The support layers 42 are disposed around and connected to the first electrode layer 47. The first energy storage layer 511 is located on a side of the first electrode layer 47 away from the support layers 42, and the second electrode layer 512 is located on a side of the first energy storage layer 511 away from the first electrode layer 47. In a cross section perpendicular to the first direction Z, a portion of the first electrode layer 47 is located within the stack formed by the support layers 42, while another portion protrudes from the stack formed by the support layers 42. The first energy storage layer 511 is connected to the portion of the first electrode layer 47 protruding from the support layer 42.

[0130] A first energy storage cavity 48 extending along the first direction Z is defined between adjacent first electrode layers 47 . The first energy storage structure 51 is located in the first energy storage cavity 48 and connected to the first electrode layer 47 .

[0131] Since the manufacturing process of the semiconductor device 200 provided in the present application is simple, on the cross section perpendicular to the first direction Z, a portion of the first electrode layer 47 is located in the stack formed by the support layer 42, and the other portion protrudes from the stack formed by the support layer 42. The first energy storage layer 511 is connected to the portion of the first electrode layer 47 protruding from the support layer 42. In this way, the first electrode layer 47 is less lost in the etching process, and the capacitance value of the capacitor structure is less affected, thereby improving the capacitance value of the capacitor structure to a certain extent.

[0132] In some embodiments, the portion of the first electrode layer 47 protruding from the support layer 42 is arc-shaped. The first energy storage layer 511 has at least one first arcuate surface 501 and at least one second arcuate surface 502. The first arcuate surface 501 is recessed toward the center of the circle containing the second arcuate surface 502, and the first arcuate surface 501 and the second arcuate surface 502 are connected. That is, the center of the first arcuate surface 501 and the center of the second arcuate surface 502 are not on the same side of the first electrode layer 47. In a second direction X and a third direction Y, which are perpendicular to the first direction Z, the portion of the first electrode layer 47 protruding from the support layer 42 is connected to the first arcuate surface 501 of the first energy storage layer 511, and the second arcuate surface 502 of the first energy storage layer 511 is connected to the support layer 42 between two adjacent first electrode layers 47. Since the first electrode layer 47 protrudes from the support layer 42 in a direction perpendicular to the first direction Z, and the first electrode layer 47 protruding from the support layer 42 is arc-shaped, the overlapping area between the first electrode layer 47 and the first energy storage layer 511 and the second electrode layer 512 is increased, thereby further increasing the capacitance value of the capacitor structure 60.

[0133] In some embodiments, the first energy storage layer 511 of a first energy storage structure 51 is respectively connected to a plurality of first electrode layers 47 distributed around the first energy storage structure 51 .

[0134] In some embodiments, the number of the support layers 42 is greater than or equal to 3. In this way, the support capability of the support layer 42 can be improved, thereby reducing the bending risk of the first electrode layer 47 during the formation of the capacitor structure.

[0135] In some embodiments, the semiconductor device 200 further includes a second semiconductor structure 30, and the support layer 42 is located on the second semiconductor structure 30. The second semiconductor structure 30 includes a transistor 301, and the transistor 301 includes a semiconductor pillar 31. The first electrode layer 47 includes a first end 471 connected to the semiconductor pillar 31 and a second end 472 away from the semiconductor pillar 31. The first end 471 of the first electrode layer 47 is connected to the semiconductor pillar 31. A capacitor structure 60 includes a first electrode layer 47 and a first energy storage structure 51, a second energy storage structure 52, and a third energy storage structure 53 connected to the first electrode layer 47. A capacitor structure 60 includes multiple capacitors. The transistor 301 is connected to the capacitor structure 60 and is configured to control the charging and discharging of the capacitor structure. The transistor 301 and the capacitor structure 60 connected thereto constitute a 1TnC storage unit, where T represents a transistor, C represents a capacitor, and n represents a positive integer greater than or equal to 1.

[0136] In some embodiments, the stack formed by the support layer 42 includes a first support surface 421 and a second support surface 422. The first support surface 421 is away from the second semiconductor structure 30, and the second support surface 422 is connected to the second semiconductor structure 30. The first end 471 of the first electrode layer 47 is connected to the semiconductor pillar 31, and the second end 472 of the first electrode layer 47 protrudes from the first support surface 421. Because the second end 472 of the first electrode layer 47 protrudes from the first support surface 421, the effective capacitor height of the capacitor structure is increased, and the capacitance value of the capacitor structure 60 of the semiconductor device 200 is further increased.

[0137] In some embodiments, the first electrode layer 47 includes a first sub-electrode layer 473 and a second sub-electrode layer 474 extending along the first direction Z, respectively. At least a portion of the first sub-electrode layer 473 is connected to the support layer 42, and another portion of the first sub-electrode layer 473 away from the support layer 42 is connected to the first energy storage layer 511. The second sub-electrode layer 474 is located on a side of the first sub-electrode layer 473 away from the support layer 42 and the first energy storage layer 511 and is connected to the first sub-electrode layer 473. The second end 472 of the second sub-electrode layer 474 and the first sub-electrode layer 473 both protrude from the first support surface 421.

[0138] In some embodiments, the first energy storage structure 51 further includes a first filling layer 513 , which is located on a side of the second electrode layer 512 away from the first energy storage layer 511 and extends along the first direction Z. An end of the first filling layer 513 away from the second semiconductor structure 30 protrudes from the second end 472 of the first electrode layer 47 .

[0139] In some embodiments, the second ends 472 of the first electrode layers 47 are independent of each other. In other words, the second ends 472 of the first electrode layers 47 are not connected to each other. In this way, the sub-capacitor structures formed by each transistor 301, the first electrode layer 47 connected to the transistor 301, and the energy storage structure corresponding to the first electrode layer 47 can input the same or different signals, reducing the risk of mutual interference between adjacent sub-capacitor structures.

[0140] In some embodiments, the cross-section of the first sub-electrode layer 473 along the first direction Z is U-shaped, and the end of the first sub-electrode layer 473 away from the first support surface 421 is connected to the semiconductor column 31. The cross-sections of the first energy storage layer 511 and the second electrode layer 512 along the first direction Z are both U-shaped, and the end of the first energy storage layer 511 away from the first support surface 421 is connected to the support layer 42 connected to the second semiconductor structure 30.

[0141] In some embodiments, the capacitor structure 60 also includes a second energy storage structure 52 and a third energy storage structure 53. The second energy storage structure 52 is located in a second energy storage cavity 49 formed by two adjacent support layers 42 and the first electrode layer 47 and is connected to the first electrode layer 47. The third energy storage structure 53 is located in a third energy storage cavity 50 formed by the first support surface 421 and the first electrode layer 47 protruding from the first support surface 421 and is connected to the first electrode layer 47.

[0142] In some embodiments, the second energy storage structure 52 includes a second energy storage layer 521 and a third electrode layer 522. The second energy storage layer 521 is connected to the support layer 42 and the first sub-electrode layer 473, and the third electrode layer 522 is located on a side of the second energy storage layer 521 away from the support layer 42 and the first sub-electrode layer 473. The third energy storage structure 53 includes a third energy storage layer 531 and a fourth electrode layer 532. The third energy storage layer 531 is connected to the support layer 42 and the first sub-electrode layer 473, and the fourth electrode layer 532 is located on a side of the third energy storage layer 531 away from the support layer 42 and the first sub-electrode layer 473.

[0143] In some embodiments, the second energy storage structure 52 further includes a second filling layer 523. The second filling layer 523 is located on a side of the third electrode layer 522 away from the second energy storage layer 521. The third electrode layer 522 surrounds the second filling layer 523, and the second energy storage layer 521 surrounds the third electrode layer 522. Both the second energy storage layer 521 and the third electrode layer 522 are in a "mouth" shape.

[0144] In some embodiments, the third energy storage structure 53 further includes a third filling layer 533 , which is located on a side of the fourth electrode layer 532 away from the third energy storage layer 531 . The third energy storage layer 531 and the fourth electrode layer 532 are both U-shaped, and the fourth electrode layer 532 surrounds the third filling layer 533 .

[0145] In some embodiments, the constituent materials of the first energy storage layer 511, the second energy storage layer 521 and the third energy storage layer 531 are selected from ferroelectric materials or antiferroelectric materials. Among them, ferroelectric materials have two or more possible orientations of spontaneous polarization phenomena at a finite temperature, and the orientation of this spontaneous polarization can be changed under the action of an electric field. The ions inside the lattice of the antiferroelectric material will undergo spontaneous polarization similar to that of the ferroelectric material, but unlike the ferroelectric material, the adjacent lattices inside the antiferroelectric material have spontaneous polarizations in opposite directions. For example, the constituent materials of the first energy storage layer 511, the second energy storage layer 521 and the third energy storage layer 531 can be selected from hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Sia(HfO2) b ), aluminum-doped hafnium dioxide (Ala(HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b) or zirconium oxide (ZrO), etc. Here, a and b are positive numbers. The hafnium can be formed by a thin film deposition process, etc. In other embodiments, the material of the hafnium is not limited to ferroelectric materials or antiferroelectric materials, and can be set and adjusted according to actual needs.

[0146] In some embodiments, the first electrode layer 47, the second electrode layer 512, the third electrode layer 522, and the fourth electrode layer 532 are formed of a material selected from a conductive material such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium. The first electrode layer 47, the second electrode layer 512, the third electrode layer 522, and the fourth electrode layer 532 can be formed by a thin film deposition process, for example.

[0147] In some embodiments, the material of the support layer 42 is selected from at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), etc., but the present application is not limited thereto.

[0148] See also Figure 24 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 200 as described above and a controller 300 , wherein the controller 300 is connected to the semiconductor device 200 and is configured to control the semiconductor device 200 .

[0149] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0150] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0151] In some embodiments, the controller 300 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0152] Before forming the electrode hole 46, the present application first forms a blind hole 43 whose orthographic projection falls between two adjacent semiconductor pillars 31 and fills the blind hole 43 with a second sacrificial layer 44. In the process of forming the blind hole 43, the first sacrificial layer 41 and the support layer 42 corresponding to the blind hole 43 are removed together, and the second sacrificial layer 44 replaces part of the first sacrificial layer 41 and the support layer 42. That is, when the first energy storage cavity 48, the second energy storage cavity 49 and the third energy storage cavity 50 are subsequently formed, the remaining first sacrificial layer 41 in the stacked structure 40 is not separated by the support layer 42. And the second sacrificial layer 44 can be removed at one time through a one-time etching process, that is to say, the formation of the electrode hole 46 of the present application only requires one etching without multiple etchings. Compared with the semiconductor device preparation method in the above embodiment that uses multiple etchings to remove the first sacrificial layer 12 and the support layer 13 respectively to form the first energy storage cavity 162 and the second energy storage cavity 161, the semiconductor device preparation method of the present application not only has a simple preparation process, but also reduces the cost and the loss of the first electrode layer 47 during the preparation process, thereby improving the capacitance value of the capacitor structure.

[0153] In addition, in the preparation method of the semiconductor device of the present application, before forming the electrode hole 46, a third sacrificial layer 45 is first formed on the first supporting surface 421 of the supporting layer 42 and the second sacrificial layer 44. Since the loss ratio of the third sacrificial layer 45 (for example: SiO) is less than the loss ratio of the supporting layer 42 (for example: SiN) during dry etching, the support layer of pure silicon nitride material and the stack composed of the third sacrificial layer 45 of silicon oxide material and the support layer 42 of silicon nitride material of the same thickness have a higher loss in the dry etching process than the stack composed of the third sacrificial layer 45 of silicon oxide material and the support layer 42 of silicon nitride material. Therefore, the depth of the electrode hole obtained in the present application in the first direction Z is greater than the depth of the electrode hole formed in the support layer of pure silicon nitride material. As a result, the effective height of the capacitor structure 60 obtained in the present application is increased, thereby increasing the capacitance value of the capacitor structure 60.

[0154] Structurally, since the manufacturing process of the semiconductor device 200 provided in the present application is simple, in a cross section perpendicular to the first direction Z, a portion of the first electrode layer 47 is located within the stack formed by the support layer 42, and the other portion protrudes from the stack formed by the support layer 42. The first energy storage layer 511 is connected to the portion of the first electrode layer 47 protruding from the support layer 42. In this way, the first electrode layer 47 is less lost during the etching process, and the capacitance value of the capacitor structure 60 is less affected, thereby improving the capacitance value of the capacitor structure to a certain extent. In addition, since the first electrode layer 47 protrudes from the support layer 42 in a direction perpendicular to the first direction Z, and the first electrode layer 47 protruding from the support layer 42 is arc-shaped, the overlapping area between the first electrode layer 47 and the first energy storage layer 511 and the second electrode layer 512 is increased, thereby further increasing the capacitance value of the capacitor structure 60.

[0155] Structurally speaking, since the second end 472 of the first electrode layer 47 of the semiconductor device 200 provided in the present application protrudes from the first support surface 421, the device 200 of the semiconductor device of the present application includes a third energy storage structure 53, which, to a certain extent, increases the effective height of the capacitor structure 60, thereby increasing the capacitance value of the capacitor structure 60.

[0156] From a structural perspective, the number of the support layers 42 is greater than or equal to 3. This can improve the support capability of the support layer 42 and thereby reduce the risk of bending of the first electrode layer 47 during the formation of the capacitor structure.

[0157] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: A plurality of support layers are spaced apart in a first direction; and a capacitor structure located in the stack formed by the support layer and comprising a first energy storage structure and a first electrode layer extending along a first direction; The first energy storage structure includes a first energy storage layer and a second electrode layer respectively extending along a first direction, the support layers are respectively arranged around the first electrode layers and respectively connected to the first electrode layers, the first energy storage layer is located on a side of the first electrode layer away from the support layer, and the second electrode layer is located on a side of the first energy storage layer away from the first electrode layer; In which, on a cross section perpendicular to the first direction, a portion of the first electrode layer is located within the stack formed by the support layer, and another portion protrudes from the stack formed by the support layer; the first energy storage layer is connected to the portion of the first electrode layer protruding from the support layer.

2. The semiconductor device according to claim 1, wherein The portion of the first electrode layer protruding from the support layer is arc-shaped, the first energy storage layer has at least one first arc-shaped surface and at least one second arc-shaped surface, the first arc-shaped surface is recessed toward the center of the circle where the second arc-shaped surface is located, and the first arc-shaped surface is connected to the second arc-shaped surface; In a second direction perpendicular to the first direction, the portion of the first electrode layer protruding from the support layer is connected to the first curved surface of the first energy storage layer, and the second curved surface of the first energy storage layer is connected to the support layer between two adjacent first electrode layers.

3. The semiconductor device according to claim 1, wherein The semiconductor device further includes a second semiconductor structure, and the support layer is located on the second semiconductor structure; The second semiconductor structure includes a transistor, the transistor includes a semiconductor column, the first electrode layer includes a first end connected to the semiconductor column and a second end away from the semiconductor column, and the first end of the first electrode layer is connected to the semiconductor column.

4. The semiconductor device according to claim 3, wherein The stack formed by the supporting layer includes a first supporting surface and a second supporting surface, the first supporting surface is away from the second semiconductor structure, and the second supporting surface is connected to the second semiconductor structure; The first end of the first electrode layer is connected to the semiconductor pillar, and the second end of the first electrode layer protrudes from the first supporting surface.

5. The semiconductor device according to claim 4, wherein The first electrode layer includes a first sub-electrode layer and a second sub-electrode layer respectively extending along the first direction; At least a portion of the first sub-electrode layer is connected to the support layer, and another portion of the first sub-electrode layer away from the support layer is connected to the first energy storage layer; The second sub-electrode layer is located on a side of the first sub-electrode layer away from the support layer and the first energy storage layer and is connected to the first sub-electrode layer; The second ends of the second sub-electrode layer and the first sub-electrode layer both protrude from the first supporting surface.

6. The semiconductor device according to claim 5, wherein The capacitor structure further includes a second energy storage structure and a third energy storage structure. The second energy storage structure is located between two adjacent support layers and connected to the first electrode layer. The third energy storage structure is located on the first support surface and connected to the first electrode layer.

7. The semiconductor device according to claim 6, wherein The second energy storage structure includes a second energy storage layer and a third electrode layer, the second energy storage layer is connected to the support layer and the first sub-electrode layer, and the third electrode layer is located on a side of the second energy storage layer away from the support layer and the first sub-electrode layer; The third energy storage structure includes a third energy storage layer and a fourth electrode layer. The third energy storage layer is connected to the support layer and the first sub-electrode layer. The fourth electrode layer is located on a side of the third energy storage layer away from the support layer and the first sub-electrode layer.

8. The semiconductor device according to claim 3, wherein The second ends of the first electrode layers are independent of each other.

9. The semiconductor device according to claim 7, wherein The first energy storage structure further includes a first filling layer, the first filling layer is located on a side of the second electrode layer away from the first energy storage layer and extends along the first direction, and an end of the first filling layer away from the second semiconductor structure protrudes from the second end of the first electrode layer; The second energy storage structure further includes a second filling layer, the third electrode layer surrounds the second filling layer, and the second energy storage layer surrounds the third electrode layer; The third energy storage structure further includes a third filling layer. The third filling layer is located on a side of the fourth electrode layer away from the third energy storage layer. The fourth electrode layer surrounds the third filling layer.

10. The semiconductor device according to claim 5, wherein The cross section of the first sub-electrode layer along the first direction is U-shaped, and one end of the first sub-electrode layer away from the first supporting surface is connected to the semiconductor pillar; The cross-sections of the first energy storage layer and the second electrode layer along the first direction are both U-shaped, and one end of the first energy storage layer away from the first supporting surface is connected to the supporting layer connected to the second semiconductor structure.

11. The semiconductor device according to any one of claims 1 to 10, wherein: A first energy storage layer of the first energy storage structure is respectively connected to a plurality of first electrode layers distributed around the first energy storage structure.

12. The semiconductor device according to any one of claims 1 to 10, wherein: The number of the supporting layers is greater than or equal to 3.

13. A method for preparing a semiconductor device, characterized in that: include: forming a stacked structure, the stacked structure comprising first sacrificial layers and supporting layers alternately stacked in a first direction; the stacked structure further comprising a first supporting surface and a second supporting surface opposite to the first supporting surface in the first direction; forming a plurality of blind holes on the stacked structure, extending from the first supporting surface to the second supporting surface, wherein the blind holes penetrate at least a portion of the supporting layer and at least a portion of the first sacrificial layer; Filling the blind hole with a sacrificial layer material to obtain a second sacrificial layer connected to the first sacrificial layer; forming a plurality of electrode holes on the stacked structure that penetrate the first sacrificial layer and the support layer of the stacked structure along the first direction, wherein the electrode holes are arranged adjacent to the blind holes; Filling the electrode hole with a first electrode material to obtain a first electrode layer, wherein the first electrode layer is connected to the first sacrificial layer, the second sacrificial layer and the support layer; and The second sacrificial layer is removed to obtain a first energy storage cavity and a first energy storage structure is formed in the first energy storage cavity.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The process of removing the second sacrificial layer to obtain the first energy storage cavity and forming the first energy storage structure in the first energy storage cavity also includes: removing the first sacrificial layer to obtain the second energy storage cavity and forming the second energy storage structure in the second energy storage cavity.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: After the step of filling the blind hole with a sacrificial layer material to obtain a second sacrificial layer, the method further includes: forming a third sacrificial layer on the first supporting surface of the stacked structure, the third sacrificial layer covering the second sacrificial layer and the supporting layer; wherein a loss ratio of the third sacrificial layer during dry etching is smaller than a loss ratio of the supporting layer during dry etching; In the process of forming a plurality of electrode holes on the stacked structure that penetrate the remaining first sacrificial layer and the supporting layer of the stacked structure along the first direction, the electrode holes also penetrate the third sacrificial layer; In the process of filling the electrode hole with the first electrode material to obtain the first electrode layer, the first electrode layer is also connected to the third sacrificial layer; The process of removing the second sacrificial layer to obtain the first energy storage cavity and forming the first energy storage structure in the first energy storage cavity also includes the steps of: removing the third sacrificial layer to obtain the third energy storage cavity and forming the third energy storage structure in the third energy storage cavity.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The semiconductor device includes a first semiconductor structure, wherein the first semiconductor structure includes the support layer, the first electrode layer, the first energy storage structure, the second energy storage structure and the third energy storage structure; Before the step of forming the stacked structure, the method further includes the steps of: providing a second semiconductor structure, wherein the second semiconductor structure includes a plurality of semiconductor pillars; and the stacked structure is located on the second semiconductor structure; The first energy storage cavity is located between multiple adjacent first electrode layers. In the process of forming multiple electrode holes on the stacked structure that penetrate the first sacrificial layer and the support layer of the stacked structure along the first direction, the positions of the electrode holes are arranged one by one relative to the positions of the semiconductor columns, and the first electrode layer is connected to the semiconductor columns.

17. The method for manufacturing a semiconductor device according to claim 13, wherein: In the process of removing the second sacrificial layer to obtain the first energy storage cavity, a plurality of first electrode layers are distributed around one first energy storage cavity, a portion of the first electrode layer is connected to the support layer, and the other portion is located in the first energy storage cavity.

18. The method for manufacturing a semiconductor device according to claim 15, wherein: The steps of forming a first energy storage structure, forming a second energy storage structure, and forming a third energy storage structure include: forming a first energy storage layer in the first energy storage cavity, forming a second energy storage layer in the second energy storage cavity, and forming a third energy storage layer in the third energy storage cavity, wherein the first electrode layer is connected to the first energy storage layer, the second energy storage layer, and the third energy storage layer, respectively; forming a second electrode layer on a side of the first energy storage layer away from the first electrode layer, forming a third electrode layer on a side of the second energy storage layer away from the first electrode layer, and forming a fourth electrode layer on a side of the third energy storage layer away from the first electrode layer; and A first filling layer, a second filling layer and a third filling layer are respectively formed on the sides of the second electrode layer, the third electrode layer and the fourth electrode layer away from the first electrode layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: In the process of forming a first energy storage layer in the first energy storage cavity, forming a second energy storage layer in the second energy storage cavity, and forming a third energy storage layer in the third energy storage cavity, in a second direction and a third direction perpendicular to the first direction, a portion of the first electrode layer is connected to the support layer, another portion of the first electrode layer is connected to the first energy storage layer, and the first energy storage layer is also connected to the support layer between two adjacent first electrode layers.

20. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 12; and The controller is coupled to the semiconductor device and configured to control the semiconductor device.

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