Silicon-based capacitor structure and preparation method thereof
By forming slits and barrier layers in the silicon-based capacitor structure, the problem of substrate warping caused by stress concentration is solved, the manufacturing yield and reliability are improved, and the feasibility of high aspect ratio trench applications is expanded.
Patent Information
- Application Number
- CN202510825791.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-09-19
AI Technical Summary
In the prior art, when filling the last layer of D-Poly in silicon-based capacitors, the compressive stress caused by the difference in thermal expansion coefficients between the conductive layer and the insulating layer causes the substrate wafer to warp, affecting the alignment accuracy and manufacturing yield of subsequent process steps.
A trench is formed on a silicon substrate, and an insulating layer, an n-periodic stacked conductive layer/dielectric layer, and a top conductive layer are stacked in sequence. The top conductive layer does not fill the trench to form a slit. A barrier layer is formed in combination with a PECVD process to cover the upper port of the slit and form a gap within the slit to reduce stress concentration.
It effectively reduces stress concentration, lowers the risk of silicon substrate warping, improves manufacturing yield and reliability, and expands the feasibility of high aspect ratio trench applications.
Smart Images
Figure CN120676648A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a silicon-based capacitor structure and a preparation method thereof. Background Art
[0002] In the field of semiconductor manufacturing, silicon-based capacitors are more suitable for use in ultra-small, ultra-thin products with extremely high reliability requirements because they can significantly improve capacitance density under the same voltage resistance conditions. Silicon-based capacitor structures usually form an insulating layer, a periodic conductive layer and a dielectric layer on the substrate wafer and in the trench, as well as a final layer of phosphorus-doped polysilicon (D-Poly) that fills the trench and is led out through contact vias.
[0003] The presence of the trenches, after filling the final D-Poly layer, creates compressive stress due to the difference in thermal expansion coefficients between the conductive and insulating layers, leading to significant tensile stress on the substrate wafer, which in turn causes the substrate wafer to warp. This warping can alter the flatness of the substrate wafer surface, further impacting subsequent photolithography, etching, and other precision processing steps. The warping can also lead to alignment issues in subsequent process steps, potentially increasing chip defects and reducing overall manufacturing yield. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a silicon-based capacitor structure and a preparation method thereof, which is used to solve the problem in the prior art of stress concentration causing substrate wafer warping when filling the last layer of D-Poly in the trench.
[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a silicon-based capacitor structure, the method comprising:
[0006] Providing a silicon-based substrate, wherein a groove is formed on the silicon-based substrate;
[0007] An insulating layer, an n-periodic stacked conductive layer / dielectric layer and a top conductive layer are sequentially formed on the bottom wall and sidewall of the trench and the silicon-based substrate; wherein n≥1, and the top conductive layer does not completely fill the trench to form a slit in the trench.
[0008] Optionally, n=3, and the n-periodic stacked conductive layers / dielectric layers include, in stacking order, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a third conductive layer, and a third dielectric layer.
[0009] Optionally, the materials of the conductive layer in the n-periodic stack of conductive layers / dielectric layers and the top conductive layer both include phosphorus-doped polysilicon, and the material of the dielectric layer in the n-periodic stack of conductive layers / dielectric layers includes silicon nitride.
[0010] Optionally, the maximum cross-sectional dimension of the slit is
[0011] Optionally, after forming the slit, the method further includes forming a barrier layer, wherein the barrier layer covers the upper end of the slit and the top conductive layer outside the slit, and forms a gap in the slit.
[0012] Furthermore, the barrier layer is formed by a PECVD process.
[0013] Furthermore, the thickness of the barrier layer on the top conductive layer outside the slit is
[0014] Optionally, the warping deformation of the silicon-based substrate is less than 150 μm.
[0015] The present invention also provides a silicon-based capacitor structure, comprising:
[0016] A silicon-based substrate having a groove formed thereon;
[0017] an insulating layer formed on the bottom wall and sidewalls of the trench and on the silicon-based substrate;
[0018] n-periodic stacked conductive layers / dielectric layers are formed on the insulating layer; wherein n≥1;
[0019] A top conductive layer is formed on the n-periodic stack of conductive layers / dielectric layers, and the top conductive layer does not completely fill the trench to form a slit in the trench.
[0020] Optionally, a barrier layer is further included, wherein the barrier layer covers the upper end of the slit and the top conductive layer outside the slit and forms a gap in the slit.
[0021] As described above, the silicon-based capacitor structure and preparation method thereof of the present invention have the following beneficial effects: by providing a silicon-based substrate and forming a groove thereon, and then sequentially forming an insulating layer, an n-periodic stacked conductive layer / dielectric layer and a top conductive layer on the groove and the substrate, and the top conductive layer does not fill the entire groove to form a slit in the groove, the internal structure of the silicon-based capacitor is effectively optimized. While this method significantly improves the capacitance density of the silicon-based capacitor under the same withstand voltage conditions, it reduces stress concentration when filling the top conductive layer by forming a slit between the top conductive layers in the groove, thereby reducing or even avoiding the risk of warping of the silicon-based substrate due to stress, thereby improving the manufacturing yield and reliability of the silicon-based capacitor and expanding its feasibility in high aspect ratio trench applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a schematic flow chart of the method for preparing the silicon-based capacitor structure of the present invention.
[0023] Figures 2 to 4 Shown are schematic cross-sectional structures of various steps in the method for preparing a silicon-based capacitor structure according to the present invention.
[0024] Figure 5 It is a schematic diagram showing that the silicon-based substrate of the silicon-based capacitor structure prepared by the method for preparing the silicon-based capacitor structure of the present invention is not warped or deformed.
[0025] Component number description
[0026] 10 Silicon-based substrate
[0027] 11 Grooves
[0028] 12 Insulation layer
[0029] 13. First conductive layer
[0030] 14. First dielectric layer
[0031] 15. Second conductive layer
[0032] 16. Second dielectric layer
[0033] 17 Third conductive layer
[0034] 18. Third dielectric layer
[0035] 19 Top conductive layer
[0036] 20 n Periodically stacked conductive layers / dielectric layers
[0037] 21 Slit
[0038] 22 barrier layer
[0039] Steps S1-S2 DETAILED DESCRIPTION
[0040] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0041] See also Figures 1 to 5 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0042] This embodiment provides a method for preparing a silicon-based capacitor structure. Figure 1 As shown, the preparation method includes:
[0043] S1, providing a silicon-based substrate, wherein a groove is formed on the silicon-based substrate;
[0044] S2, forming an insulating layer, an n-periodic stacked conductive layer / dielectric layer and a top conductive layer in sequence on the bottom wall and sidewall of the trench and the silicon-based substrate; wherein n≥1, and the top conductive layer does not fill the trench to form a slit in the trench.
[0045] The method for preparing a silicon-based capacitor structure of this embodiment provides a silicon-based substrate and forms a trench thereon, and then sequentially forms an insulating layer, an n-periodic stacked conductive layer / dielectric layer, and a top conductive layer on the trench and the substrate. The top conductive layer does not completely fill the trench to form a slit within the trench, effectively optimizing the internal structure of the silicon-based capacitor. While significantly improving the capacitance density of the silicon-based capacitor under the same withstand voltage conditions, this method reduces stress concentration during filling of the top conductive layer by forming slits between the top conductive layers within the trench, thereby reducing or even avoiding the risk of warping of the silicon-based substrate due to stress. This improves the manufacturing yield and reliability of silicon-based capacitors and expands their feasibility in high-aspect-ratio trench applications.
[0046] The method for preparing the silicon-based capacitor structure of this embodiment will be described in detail below with reference to the specific drawings.
[0047] like Figure 2 As shown, step S1 is first performed to provide a silicon-based substrate 10 , on which a trench 11 is formed.
[0048] As an example, the material of the silicon-based substrate 10 includes one of silicon, sapphire, silicon carbide and gallium nitride, etc., which can be selected according to needs and is not overly restricted here. The size of the silicon-based substrate 10 is preferably wafer-level.
[0049] like Figure 3 As shown, step S2 is then performed to sequentially form an insulating layer 12, an n-periodic stacked conductive layer / dielectric layer 20 and a top conductive layer 19 on the bottom wall and side wall of the trench 11 and the silicon-based substrate 10; wherein n≥1, and the top conductive layer 19 does not completely fill the trench 11 to form a slit 21 in the trench 11.
[0050] As an example, the value of n can be adjusted according to the required capacitance density. Preferably, n can be 1, 2 or 3 to reduce the risk of warping of the silicon-based substrate 10. This embodiment is illustrated by taking n=3 as an example. Figure 3 As shown, the n-periodic stacked conductive layer / dielectric layer 20 includes, in stacking order, a first conductive layer 13, a first dielectric layer 14, a second conductive layer 15, a second dielectric layer 16, a third conductive layer 17 and a third dielectric layer 18.
[0051] As an example, the n-periodic stacked conductive layer / dielectric layer 20 includes n conductive layers and n dielectric layers. The conductive layers (eg, Figure 3 The materials of the first conductive layer 13, the second conductive layer 15 and the third conductive layer 17 and the top conductive layer 19 are all composed of phosphorus-doped polysilicon, and the dielectric layer in the n-periodic stack of conductive layer / dielectric layer 20 (such as Figure 3 The material of the first dielectric layer 14, the second dielectric layer 16 and the third dielectric layer 18 shown in FIG. 1 comprises silicon nitride.
[0052] As an example, the material of the insulating layer 12 includes silicon oxide. The insulating layer 12 can inhibit the diffusion of doped ions in, for example, a phosphorus-doped polysilicon conductive layer, and maintain the conductivity of the phosphorus-doped polysilicon conductive layer. In some embodiments, when the silicon-based capacitor is integrated into a substrate containing a through silicon via (TSV) structure, the insulating layer 12 can block metal ions from the substrate to ensure that the conductive layer is not damaged.
[0053] As an example, the maximum cross-sectional dimension of the slit 21 is In order to reduce stress concentration when forming the top conductive layer 19, for example, the maximum cross-sectional dimension of the groove 11 is After forming the insulating layer 12, the n-periodic stacked conductive layer / dielectric layer 20, and the top conductive layer 19, the slit 21 is wide at the top and narrow at the bottom, and the maximum cross-sectional dimension of the slit 21 is
[0054] As an example, the preparation method also includes a step of forming a conductive layer electrical lead-out structure (not shown), which conductive layer lead-out structure includes a contact hole structure to achieve electrical lead-out of the conductive layer in the n-periodic stacked conductive layer / dielectric layer 20.
[0055] As an example, in order to avoid the photoresist from flowing into the slit 21 when forming the contact hole structure by using a photolithography process, as shown in FIG. Figure 4 As shown, after the slit 21 is formed, a step of forming a barrier layer 22 by, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is also included. The barrier layer 22 covers the upper port of the slit 21 and the top conductive layer 19 outside the slit 21, and forms a gap (not shown) in the slit 21 to be compatible with the existing contact hole structure preparation process. By covering the upper port of the slit 21 and forming a gap in the slit 21, stress concentration during the formation of the barrier layer 22 is reduced or even avoided.
[0056] As an example, the material of the barrier layer 22 is silicon oxide, which has a smaller thermal expansion coefficient than that of polysilicon material to achieve smaller stress changes, thereby further improving the warping problem of the silicon-based substrate 10.
[0057] As an example, the thickness of the barrier layer 22 on the top conductive layer 19 outside the slit 21 is This can reduce stress concentration while improving the overall flatness of the silicon wafer and ensure the smooth progress of subsequent processes.
[0058] As an example, the warpage deformation of the silicon-based substrate 10 of the silicon-based capacitor structure prepared by the method for preparing the silicon-based capacitor structure of this embodiment is less than 150 μm. Figure 5 As shown, the warping deformation of the silicon-based substrate 10 is 0, that is, when the silicon-based capacitor structure is formed, the silicon-based substrate 10 is not warped or deformed.
[0059] This embodiment also provides a silicon-based capacitor structure, such as Figure 3 As shown, the silicon-based capacitor structure includes:
[0060] A silicon-based substrate 10 having a groove 11 formed thereon;
[0061] an insulating layer 12 formed on the bottom wall and sidewalls of the trench 11 and on the silicon-based substrate 10;
[0062] An n-periodic stack of conductive layers / dielectric layers 20 is formed on the insulating layer 12; wherein n≥1;
[0063] A top conductive layer 19 is formed on the n-periodic stack of conductive layer / dielectric layer 20 , and the top conductive layer 19 does not completely fill the trench 11 to form a slit 21 in the trench 11 .
[0064] As a good example, Figure 4 As shown, the silicon-based capacitor structure further includes a barrier layer 22 , which covers the upper end of the slot 21 and the top conductive layer 19 outside the slot 21 and forms a gap (not shown) in the slot 21 .
[0065] The silicon-based capacitor structure can be prepared using the above-mentioned method for preparing the silicon-based capacitor structure, but is not limited thereto. Other suitable preparation methods are also acceptable. The beneficial effects that can be achieved can be found in the specific description of the preparation method, which will not be repeated here.
[0066] In summary, the present invention provides a silicon-based capacitor structure and a method for preparing the same. By providing a silicon-based substrate and forming a trench thereon, an insulating layer, an n-periodic stacked conductive layer / dielectric layer, and a top conductive layer are sequentially formed on the trench and the substrate, and the top conductive layer does not completely fill the trench to form a slit in the trench, effectively optimizing the internal structure of the silicon-based capacitor. While significantly improving the capacitance density of the silicon-based capacitor under the same withstand voltage conditions, the method reduces stress concentration when filling the top conductive layer by forming a slit between the top conductive layers in the trench, thereby reducing or even avoiding the risk of warping of the silicon-based substrate due to stress, thereby improving the manufacturing yield and reliability of the silicon-based capacitor and expanding its feasibility in high aspect ratio trench applications. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.
[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for preparing a silicon-based capacitor structure, characterized in that: The preparation method comprises: Providing a silicon-based substrate, wherein a groove is formed on the silicon-based substrate; An insulating layer, an n-periodic stacked conductive layer / dielectric layer and a top conductive layer are sequentially formed on the bottom wall and sidewall of the trench and the silicon-based substrate; wherein n≥1, and the top conductive layer does not completely fill the trench to form a slit in the trench.
2. The method for preparing a silicon-based capacitor structure according to claim 1, wherein: n=3, and the n-periodic stack of conductive layers / dielectric layers includes, in stacking order, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a third conductive layer, and a third dielectric layer.
3. The method for preparing a silicon-based capacitor structure according to claim 1, wherein: The materials of the conductive layer and the top conductive layer in the n-periodic stack of conductive layers / dielectric layers both include phosphorus-doped polysilicon, and the material of the dielectric layer in the n-periodic stack of conductive layers / dielectric layers includes silicon nitride.
4. The method for preparing a silicon-based capacitor structure according to claim 1, wherein: The maximum cross-sectional dimension of the slit is 5. The method for preparing a silicon-based capacitor structure according to claim 1, wherein: After forming the slit, the method further includes forming a barrier layer, wherein the barrier layer covers the upper end of the slit and the top conductive layer outside the slit, and forms a gap in the slit.
6. The method for preparing a silicon-based capacitor structure according to claim 5, wherein: The barrier layer is formed by a PECVD process.
7. The method for preparing a silicon-based capacitor structure according to claim 5, wherein: The thickness of the barrier layer on the top conductive layer outside the slit is 8. The method for preparing a silicon-based capacitor structure according to claim 1, wherein: The warping deformation of the silicon-based substrate is less than 150 μm.
9. A silicon-based capacitor structure, characterized in that: include: A silicon-based substrate having a groove formed thereon; an insulating layer formed on the bottom wall and sidewalls of the trench and on the silicon-based substrate; n-periodic stacked conductive layers / dielectric layers are formed on the insulating layer; wherein n≥1; A top conductive layer is formed on the n-periodic stack of conductive layers / dielectric layers, and the top conductive layer does not completely fill the trench to form a slit in the trench.
10. The silicon-based capacitor structure according to claim 9, wherein: The invention also includes a barrier layer, which covers the upper end of the slot and the top conductive layer outside the slot and forms a gap in the slot.