Negative quantum capacitance transistor based on Weel semimetal and preparation method thereof

Abstract

The invention discloses a negative quantum capacitance transistor based on Weel semimetal and a preparation method thereof, the negative quantum capacitance transistor comprises a substrate, a source electrode and a drain electrode, and the source electrode and the drain electrode are formed on the surface of the substrate at a certain interval; two sides of the channel layer are respectively contacted with and partially overlapped with the source electrode and the drain electrode; a lower insulating medium layer, a Weel semimetal layer and an upper insulating medium layer are sequentially arranged above the source electrode, the drain electrode and the channel layer; the lower insulating medium layer and the upper insulating medium layer completely cover the Weel semimetal layer; and the top of the upper insulating dielectric layer is a top gate. The gate voltage amplification effect is realized, the total capacitance of the device is increased, the SS is reduced, the switching rate of the device is improved, and the power consumption of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic component design and manufacturing, and particularly relates to a negative quantum capacitance transistor based on Weyl semimetal and a preparation method thereof. Background Art

[0002] The rapid development of the modern information industry has placed higher demands on memory and data storage technologies, such as miniaturization, high speed, low power consumption, and high storage density. However, as integrated circuit process nodes continue to advance toward the nanometer scale, the miniaturization of CMOS technology is facing severe power consumption challenges. At the device physics level, the continued reduction of operating voltage is limited by the von Neumann bottleneck—the subthreshold swing (SS) of traditional field-effect transistors at room temperature has a theoretical limit of no less than 60mV / dec (the Boltzmann limit). This fundamentally restricts the optimization space for device static power consumption.

[0003] In recent years, 2D layered materials and van der Waals (vdW) heterostructures have attracted widespread attention due to their atomically thin thickness and potential for fabricating a variety of functional devices. The vdW structure, with its dangling bond-free surface, stable polarization, tunable band structure, and compatibility with silicon-based processes, holds broad application prospects in ferroelectric memory, neuromorphic computing, nanogenerators, photovoltaic devices, and spintronic devices. By leveraging the dangling bond-free nature of 2D materials, it is possible to overcome the scaling limitations of traditional transistors and achieve transistor structures with improved performance. Therefore, the use of 2D materials to fabricate transistors can help improve their performance.

[0004] Furthermore, to overcome the von Neumann bottleneck, researchers have recently focused on developing negative capacitance transistors (NCFETs) based on ferroelectric gate dielectrics. These transistors, with their low-voltage drive and small cell size, are considered an attractive architecture. Furthermore, these transistors can achieve gate voltage amplification and device capacitance redistribution through polarization control, thereby optimizing the device's SS. However, current NCFETs often suffer from lattice mismatch and severe charge trapping at the ferroelectric semiconductor interface during the epitaxial growth of ferroelectric materials on the silicon channel, as described in the literature (DOI: 10.7498 / aps.69.20200354). Lattice mismatch and structural defects prevent perfect bonding between silicon and ferroelectric surface atoms, resulting in unsaturated chemical bonds (dangling bonds). These dangling bonds are potent charge traps. Furthermore, ferroelectric materials themselves (especially perovskite oxides) often contain high concentrations of point defects such as oxygen vacancies, which accumulate near the interface and contribute to charge trapping. Therefore, it greatly affects the performance of the device, resulting in mobility degradation, subthreshold characteristic degradation or reliability issues, and the ferroelectric domain switching speed also limits the switching speed of the device. Summary of the Invention

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a negative quantum capacitance transistor based on Weyl semimetal and a preparation method thereof, introducing a Weyl semimetal as the device gate. The Weyl semimetal surface is conductive and the interior is insulating, and has quantum capacitance, which is affected by the carrier density in the system. When its Fermi level is near the Dirac point, the carrier density in the system is low, the quantum capacitance will decrease, and may even become negative, thereby achieving an amplification effect of the gate voltage, increasing the total capacitance of the device, reducing SS, improving the switching rate of the device and reducing the power consumption of the device.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A negative quantum capacitance transistor based on a Weyl semimetal comprises a substrate, a channel layer, a lower insulating dielectric layer, a Weyl semimetal layer, an upper insulating dielectric layer, and a gate, which are arranged in sequence. A source electrode and a drain electrode are arranged on the substrate and isolated by the channel layer.

[0008] Two sides of the channel layer are in contact with the source electrode and the drain electrode respectively and partially overlap with each other;

[0009] The lower insulating dielectric layer and the upper insulating dielectric layer completely cover the Weyl semi-metal layer.

[0010] The Weyl semimetal layer provides negative quantum capacitance and has a linear band structure of a Dirac cone, with a conductive surface and an insulating interior, which redistributes the voltage inside the device, increases the total capacitance, reduces the subthreshold swing, and realizes fast switching of the device.

[0011] Since the top gate typically covers both the Weyl semi-metal layer and the channel layer, the capacitance generated by the Weyl semi-metal layer and the capacitance generated by the channel layer are dominated by their respective areas. The area of ​​the Weyl semi-metal layer is close to that of the channel layer to achieve more appropriate capacitance matching. The channel layer is generally narrow and long, with the distance between the two ends in contact with the source and drain electrodes defined as the length, and the length perpendicular to the direction of the side cross-sectional structural diagram defined as the width. The Weyl semi-metal layer is shorter than the channel layer to prevent it from exceeding the coverage of the insulating dielectric layer and contacting the source or drain electrode. The substrate is Si / SiO2.

[0012] The channel layer is a two-dimensional material with high mobility, preferably MoS2.

[0013] The insulating dielectric layer is made of a material that is stable at room temperature and can be obtained in a relatively thin form, preferably h-BN.

[0014] The Weyl semimetal layer is a Weyl semimetal with easily adjustable energy band position, preferably MoTe2 or WTe2.

[0015] The Weyl semimetal layer is an indirect bandgap semiconductor with a very small bandgap, typically ranging from a few millielectronvolts to tens of millielectronvolts, and can even be considered zero in some cases. Its conduction band and valence band contact at discrete points (called Weyl points) that appear in pairs in momentum space. These Weyl points are degenerate points in momentum space, also known as Weyl fermions, which have a definite chirality (left-handed or right-handed) and are connected only by peculiar non-closed surface states (i.e., Fermi arcs) at the crystal boundaries.

[0016] The channel layer, the lower insulating dielectric layer, the upper insulating dielectric layer and the Weyl semimetal layer are all two-dimensional materials. It is well known that 2D materials usually have an atomic-level thickness, and thin layers of materials can be obtained by peeling; the length of the channel layer is controlled to be 8 to 10 μm so that it can contact the source electrode and the drain electrode, and the thickness is controlled within 30 nm; the lower insulating dielectric layer and the upper insulating dielectric layer generally need to be thinner to reduce their impact on the overall capacitance, and are controlled within 10 nm; and the Weyl semimetal layer generally needs to be very thin, and the thickness is controlled within 10 nm. This is because only when it is thin enough will its capacitance be affected by quantum mechanical effects, generating quantum capacitance, thereby optimizing device performance through the negative quantum capacitance effect.

[0017] A method for preparing a negative quantum capacitance device based on Weyl semimetal comprises the following steps:

[0018] Step 1: AR-P5350 photoresist is spin-coated on a clean, flat silicon wafer and baked. The pre-drawn electrode pattern is imported into a laser direct writing system and exposed. After development, a silicon wafer with the photoresist dissolved at the electrode pattern is obtained. Thin metal electrodes are deposited on the silicon wafer by magnetron sputtering and lift-off is performed. The resulting electrodes are the source and drain electrodes, where the source and drain electrodes are relatively short. This can reduce the channel length. The smaller the channel length, the stronger the gate's ability to control the channel current, which helps optimize the device's subthreshold swing.

[0019] Step 2: Prepare a long strip of channel material slightly longer than the distance between the source electrode and the drain electrode, and then transfer it to the middle of the source electrode and the drain electrode grown on the substrate to form a channel layer, so that both ends of the channel layer are in contact with and partially cover the source electrode and the drain electrode;

[0020] Step 3: Prepare a thin lower insulating dielectric layer on the channel layer by transfer or sputtering growth and try to cover the channel layer to prevent the Weyl semi-metal layer from contacting it;

[0021] Step 4: peeling off a thin Weyl semi-metal layer by mechanical peeling, and transferring the Weyl semi-metal layer to the upper surface of the lower insulating dielectric layer in step 3 by dry transfer, and overlapping the position of the channel layer as much as possible;

[0022] Step 5: Prepare a second upper insulating dielectric layer on the upper surface of the Weyl semi-metal layer in step 1 by transfer or sputtering growth and completely cover it to prevent oxidation;

[0023] Step 6: Determine the material positions in the above steps and draw the corresponding top electrode layout, and use the same spin coating, resin baking, exposure, development, photolithography and lift-off steps as in step 1 to prepare the top gate.

[0024] The substrate is preferably Si / SiO2.

[0025] The channel layer is a two-dimensional material with high mobility, preferably MoS2.

[0026] The insulating dielectric layer is made of a material that is stable at room temperature and can be obtained as a thin layer, preferably h-BN, wherein the insulating dielectric layer under the Weyl semi-metal should be thinner.

[0027] The Weyl semimetal layer is a Weyl semimetal with easily adjustable energy band positions, preferably a thin layer of MoTe2 or WTe2. A Weyl semimetal layer is generally an indirect bandgap semiconductor with a very small bandgap, and its conduction band and valence band contact at discrete points (called Weyl points) that appear in pairs in momentum space. These Weyl points are degenerate points in momentum space, also known as Weyl fermions, which have a definite chiral characteristic (left-handed or right-handed) and are connected only by peculiar non-closed surface states (i.e., Fermi arcs) at the crystal boundaries.

[0028] Beneficial effects of the present invention:

[0029] (1) Compared with traditional MOSFETs, this device is often fabricated using two-dimensional materials. Two-dimensional materials have atomic-level thickness, can form a VDW interface without dangling bonds, have ultra-high carrier mobility, and have a tunable band gap. Therefore, the device interfaces in this invention are all VDW interfaces, which are smooth and uniform with few defects and exhibit excellent performance.

[0030] (2) The Weyl semimetal MoTe2 used in the present invention has a unique linear band structure. When its Fermi level is near the Weyl point, the density of states and carrier density in the system are low, and the quantum capacitance decreases or even becomes negative, which produces the NQC effect. This effect amplifies the gate voltage, increasing the total capacitance of the device, thereby breaking the Boltzmann theoretical limit of traditional MOSFETs, reducing SS, increasing the switching rate of the device, and reducing the power consumption of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Flowchart of the preparation method of negative quantum capacitance transistor based on Weyl semimetal.

[0032] Figure 2 Schematic diagram of the device structure after the source and drain electrodes are formed.

[0033] Figure 3 Schematic diagram of the device structure after the channel layer is formed.

[0034] Figure 4 Schematic diagram of the device structure after forming a gate stack consisting of an insulating dielectric layer / Weyl semi-metal layer / insulating dielectric layer.

[0035] Figure 5 Schematic diagram of the negative quantum capacitance transistor structure based on Weyl semimetal.

[0036] Figure 6 This is the equivalent circuit of a negative quantum capacitance transistor based on Weyl semimetal.

[0037] Figure 7 The electrical properties of the negative quantum capacitance transistor based on Weyl semimetal are shown. Description of the drawings:

[0039] 1. Substrate, 2. Source electrode, 3. Drain electrode, 4. Channel layer, 5. Lower insulating dielectric layer, 6. Weyl semi-metal layer, 7. Upper insulating dielectric layer, 8. Top gate. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below with reference to the accompanying drawings.

[0041] Example 1:

[0042] Figure 1 This is a flow chart of the preparation method of negative quantum capacitor devices based on Weyl semimetals. Figure 1 As shown, first prepare a clean Si / SiO2 substrate 1, where the SiO2 layer is 300nm thick. Use a laser direct writing system to import the pre-designed source and drain electrode pattern and perform photolithography. Then deposit Ti / Au metal as the source 2 and drain 3, as shown in step 1, where the thickness of the Ti layer is 5nm and the thickness of the Au layer is 30nm. The resulting structure is shown in the figure below. Figure 2 shown.

[0043] In step 2, a long strip channel layer 4 with a length of about 8 to 10 μm is peeled off by mechanical stripping. The selected channel material is MoS2 with a thickness of about 20 nm. Then, it is transferred to the middle of the source and drain electrodes grown on the substrate by dry transfer, so that the two ends of the channel layer 4 are in contact with the source 2 and drain 3 and partially cover the obtained structure. Figure 3 However, the present invention is not limited thereto, and WSe2, WS2, etc. may also be used as the channel layer 4.

[0044] In step 3, the insulating dielectric layer 5 with a thickness of about 10 nm is peeled off by mechanical stripping, and the insulating dielectric layer 5 is transferred to the position above the channel layer 4 by dry transfer and covered as much as possible to prevent the Weyl semi-metal layer 6 from contacting it.

[0045] In step 4, a Weyl semi-metal layer 6 having a thickness of approximately 8 nm is removed by mechanical stripping, and then the Weyl semi-metal layer 6 is transferred to the upper surface of the insulating dielectric layer 5 by dry transfer, overlapping as closely as possible with the channel layer 4. However, the present invention is not limited thereto, and WTe2 or the like may also be used as the Weyl semi-metal layer 6.

[0046] In step 5, the second insulating dielectric layer 7 is peeled off by mechanical stripping, and the insulating dielectric layer 7 is transferred to the upper surface of the Weyl semi-metal layer 6 by dry transfer and completely covers it to prevent oxidation. After steps 3 to 5, the device structure is shown in FIG. Figure 4 shown.

[0047] In step 6, the pattern of the top gate electrode 8 is drawn using AutoCAD, and a laser direct writing system is used to align and photolithography the structure where the first 7 layers have been transferred. Then, Ti / Au metal is deposited as the top gate electrode 8, where the thickness of the Ti layer is 5nm and the thickness of the Au layer is 60nm. The structure of the negative quantum capacitor device based on Weyl semimetal is finally prepared as shown in the figure below. Figure 5 shown.

[0048] In order to more clearly illustrate the principle and effect of the present invention, Figure 6 The equivalent circuit of the negative quantum capacitor device is shown in FIG. Q 、C 2D are MoTe2 quantum capacitance and two-dimensional (2D) channel semiconductor capacitance respectively; C BN1 and C BN2 The upper and lower insulating dielectric layers are the capacitances, respectively. The upper insulating dielectric 7, Weyl semimetal 6, and lower insulating dielectric 5 form a complete gate stack, and the overall capacitance is C Gate .

[0049] The entire device can be viewed as a series of transistors connected in series, with a total capacitance C total It can be expressed as:

[0050]

[0051] Weyl semimetal MoTe2 has a unique linear band structure. When its Fermi level is near the Dirac point, the state density and carrier density in the system are low, and the quantum capacitance C Q will decrease or even become negative, which will produce the NQC effect. Q When it decreases to a negative value, the total capacitance C total will increase accordingly, so a very small SS can be achieved.

[0052] like Figure 7 The following figures show the electrical characteristics test results of an embodiment of the present invention, with the left figure showing the transfer characteristic curve and the right figure showing the variation of SS with current. The figure shows that the minimum SS is only 55.3 mV / dec, demonstrating the optimization effect of Weyl semimetals on SS. This also indicates that the application of Weyl semimetals in transistor gate stacks can break the Boltzmann theoretical limit of traditional MOSFETs, increasing device switching speeds and reducing power consumption.

[0053] Example 2:

[0054] like Figure 1 As shown, first prepare a clean Si / SiO2 substrate 1, where the SiO2 layer is 300nm thick. Use a laser direct writing system to import the pre-designed source and drain electrode pattern and perform photolithography. Then deposit Ti / Au metal as the source 2 and drain 3, as shown in step 1, where the thickness of the Ti layer is 5nm and the thickness of the Au layer is 30nm. The resulting structure is shown in the figure below. Figure 2 shown.

[0055] In step 2, a long strip channel layer 4 with a length of about 10 μm is peeled off by mechanical stripping. The selected channel material is MoS2 with a thickness of 11.5 nm. Then, it is transferred to the middle of the source and drain grown on the substrate by dry transfer, so that the two ends of the channel layer 4 are in contact with the source 2 and drain 3 and partially cover the obtained structure as shown in the figure. Figure 3 shown.

[0056] In step 3, an insulating dielectric layer 5 with a thickness of about 10 nm is peeled off by mechanical stripping. The insulating material used is h-BN. The insulating dielectric layer 5 is transferred to the position above the channel layer 4 by a dry transfer method and is covered as much as possible to prevent the Weyl semi-metal layer 6 from contacting it.

[0057] In step 4, a Weyl semi-metal layer 6 with a thickness of about 2.8 nm is peeled off by mechanical stripping. The selected Weyl semi-metal material is WTe2. The Weyl semi-metal layer 6 is transferred to the upper surface of the insulating dielectric layer 5 by dry transfer and overlaps with the position of the channel layer 4 as much as possible.

[0058] In step 5, the second insulating dielectric layer 7 is removed by mechanical stripping, again made of h-BN, and the insulating dielectric layer 7 is transferred to the upper surface of the Weyl semi-metal layer 6 and completely covers it to prevent oxidation. The device structure is the same as that of Example 1.

[0059] In step 6, the pattern of the top gate electrode 8 was drawn using AutoCAD. A laser direct writing system was used to align and photolithography the structure where the first seven layers had been transferred. Subsequently, Ti / Au metal was deposited as the top gate electrode 8, where the thickness of the Ti layer was 5 nm and the thickness of the Au layer was 60 nm. The structure of the negative quantum capacitor device based on the Weyl semimetal finally prepared was consistent with that of Example 1.

[0060] like Figure 7 (b) shows the electrical characteristics test results of an embodiment of the present invention, with the left figure showing the transfer characteristic curve and the right figure showing the variation of SS with current. The figure shows that the minimum SS is only 51.5 mV / dec, demonstrating the optimization effect of Weyl semimetals on SS. This indicates that the application of Weyl semimetals in transistor gate stacks can break the Boltzmann theoretical limit of traditional MOSFETs, increasing device switching speeds and reducing power consumption.

[0061] Example 3:

[0062] like Figure 1 As shown, first prepare a clean Si / SiO2 substrate 1, where the SiO2 layer is 300nm thick. Use a laser direct writing system to import the pre-designed source and drain electrode pattern and perform photolithography. Then deposit Ti / Au metal as the source 2 and drain 3, as shown in step 1, where the thickness of the Ti layer is 5nm and the thickness of the Au layer is 30nm. The resulting structure is shown in the figure below. Figure 2 shown.

[0063] In step 2, a strip channel layer 4 with a length of about 10 μm is peeled off by mechanical stripping. The selected channel material is MoS2 with a thickness of about 15 nm. Then, it is transferred to the middle of the source and drain electrodes grown on the substrate by dry transfer, so that both ends of the channel layer 4 are in contact with and partially cover the source 2 and drain 3. The resulting structure is shown in FIG. Figure 3 shown.

[0064] In step 3, an insulating dielectric layer 5 with a thickness of about 10 nm is peeled off by mechanical stripping. The insulating material used is h-BN. The insulating dielectric layer 5 is transferred to the position above the channel layer 4 by a dry transfer method and is covered as much as possible to prevent the Weyl semi-metal layer 6 from contacting it.

[0065] In step 4, a Weyl semi-metal layer 6 with a thickness of about 6 nm is peeled off by mechanical stripping. The selected Weyl semi-metal material is WTe2. The Weyl semi-metal layer 6 is transferred to the upper surface of the insulating dielectric layer 5 by dry transfer and overlaps with the position of the channel layer 4 as much as possible.

[0066] In step 5, the second insulating dielectric layer 7 is removed by mechanical stripping, again made of h-BN, and is transferred to the upper surface of the Weyl semi-metal layer 6 and completely covers it to prevent oxidation. The device structure is the same as that of Examples 1 and 2.

[0067] In step 6, the pattern of the top gate electrode 8 was drawn using AutoCAD. A laser direct writing system was used to align and photolithography the structure where the first seven layers had been transferred. Subsequently, Ti / Au metal was deposited as the top gate electrode 8, where the thickness of the Ti layer was 5 nm and the thickness of the Au layer was 60 nm. The structure of the negative quantum capacitor device based on the Weyl semimetal finally prepared was consistent with that of Examples 1 and 2.

[0068] like Figure 7 (c) shows the electrical characteristics test results of an embodiment of the present invention, with the left figure showing the transfer characteristic curve and the right figure showing the variation of SS with current. The figure shows that the minimum SS is only 20.3 mV / dec, demonstrating the optimization effect of Weyl semimetals on SS. This indicates that the application of Weyl semimetals in transistor gate stacks can break the Boltzmann theoretical limit of traditional MOSFETs, increasing device switching speeds and reducing power consumption.

[0069] It should be emphasized that although the above three embodiments illustrate the technical solution of integrating MoTe2 and WTe2 into the gate stack structure and using MoS2 as the channel layer, the material system of the present invention is not limited to this specific combination. In specific implementations, the layer structure parameters and heterojunction integration scheme can be adaptively optimized based on device performance indicators. At the same time, thanks to the universal transfer process of two-dimensional materials, the substrate material can be flexibly selected to realize device preparation.

Claims

1. A negative quantum capacitance transistor based on Weyl semimetal, characterized in that: The invention comprises a substrate (1), a channel layer (4), a lower insulating dielectric layer (5), a Weyl semi-metal layer (6), an upper insulating dielectric layer (7), and a gate (8) which are arranged in sequence; a source electrode (2) and a drain electrode (3) are arranged on the substrate (1) and isolated by the channel layer (4); Both sides of the channel layer (4) are in contact with and partially overlap with the source electrode (2) and the drain electrode (3); The lower insulating dielectric layer (5) and the upper insulating dielectric layer (7) completely cover the Weyl semi-metal layer (6).

2. The negative quantum capacitance transistor based on Weyl semimetal according to claim 1, characterized in that: The Weyl semimetal layer (6) is an indirect bandgap semiconductor with a bandgap between several millielectronvolts and tens of millielectronvolts, and its conduction band and valence band are in contact at discrete points that appear in pairs in momentum space, and the discrete points are connected only through peculiar non-closed surface states at the crystal boundaries.

3. The negative quantum capacitance transistor based on Weyl semimetal according to claim 2, characterized in that: The Weyl semimetal layer (6) provides negative quantum capacitance, the surface of which is conductive but the interior is insulating, so that the voltage inside the device is redistributed, the total capacitance is increased, the subthreshold swing is reduced, and the fast switching of the device is achieved.

4. The negative quantum capacitance transistor based on Weyl semimetal according to claim 2, characterized in that: The capacitance generated by the Weyl semi-metal layer (6) and the capacitance generated by the channel layer (4) are respectively dominated by the areas of the two. The area of ​​the Weyl semi-metal layer (6) is close to that of the channel layer (4). The channel layer (4) is narrower and longer than the Weyl semi-metal layer (6). The distance between the two ends in contact with the source electrode (2) and the drain electrode (3) is long, and the length perpendicular to the side profile structure is wide. The Weyl semi-metal layer (6) is shorter than the channel layer (4).

5. The negative quantum capacitance transistor based on Weyl semimetal according to claim 2, characterized in that: The Weyl semimetal layer (6) is MoTe2 or WTe2.

6. The negative quantum capacitance transistor based on Weyl semimetal according to claim 1, characterized in that: The cross-sectional dimensions of the Weyl semi-metal layer (6) are smaller than those of the lower insulating dielectric layer (5) and the upper insulating dielectric layer (7).

7. The negative quantum capacitance transistor based on Weyl semimetal according to claim 1, characterized in that: The channel layer (4) is a two-dimensional material with high mobility, namely MoS2.

8. The negative quantum capacitance transistor based on Weyl semimetal according to claim 1, characterized in that: The insulating dielectric layer is made of a material that is stable at room temperature and can be obtained in a relatively thin form, and is h-BN.

9. The negative quantum capacitance transistor based on Weyl semimetal according to claim 1, characterized in that: The channel layer (4), the lower insulating dielectric layer (5), the upper insulating dielectric layer (7) and the Weyl semi-metal layer (6) are all two-dimensional materials, wherein the length of the channel layer (4) is controlled to be 8 to 10 μm, and the thickness is controlled to be within 30 nm; the lower insulating dielectric layer (5) and the upper insulating dielectric layer (7) are controlled to be 10 nm; and the thickness of the Weyl semi-metal layer (6) is controlled to be within 10 nm.

10. A method for preparing a negative quantum capacitance device based on a Weyl semimetal according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1: spin-coating AR-P5350 photoresist on a clean and flat silicon wafer and baking the photoresist, importing the electrode pattern drawn in advance into a laser direct writing system and exposing it, and after development, obtaining a silicon wafer with the photoresist dissolved at the electrode pattern, depositing a thin metal electrode on the silicon wafer by magnetron sputtering and performing lift-off, thereby obtaining a source electrode (2) and a drain electrode (3), wherein the source electrode (2) and the drain electrode (3) are relatively short; Step 2: preparing a long strip of channel material having a length slightly greater than the distance between the source electrode (2) and the drain electrode (3), and then transferring the strip to the middle of the source electrode (2) and the drain electrode (3) grown on the substrate (1) to form a channel layer (4), so that both ends of the channel layer (4) are in contact with and partially cover the source electrode (2) and the drain electrode (3); Step 3: preparing a thin lower insulating dielectric layer (5) on the channel layer (4) by a transfer or sputtering growth method and covering the channel layer (4) to prevent the Weyl semi-metal layer (6) from contacting it; Step 4: peeling off the thin Weyl semi-metal layer (6) by mechanical peeling, and transferring the Weyl semi-metal layer (6) to the upper surface of the lower insulating dielectric layer (5) in step 3 by dry transfer, and overlapping the position of the channel layer (4) as much as possible; Step 5: Prepare a second upper insulating dielectric layer (7) on the upper surface of the Weyl semi-metal layer (6) in step 4 by transfer or sputtering growth and completely cover it to prevent oxidation; Step 6: Determine the material positions in the above steps and draw the corresponding top electrode layout, and prepare the top gate (8) by spin coating, baking, exposure, development, photolithography and lift-off steps.

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