Power switch device containing floating field plate

Abstract

The invention belongs to the technical field of semiconductors, and particularly discloses a floating field plate-containing power switch device, which comprises a floating field plate, a second field plate, a floating field plate vertical extension region and a second field plate vertical extension region, and is characterized in that the floating field plate is positioned in a second dielectric layer, the second field plate is positioned in a third dielectric layer, and the second field plate is positioned in a third dielectric layer; the floating field plate is located on the side, away from the drain electrode, of the second field plate, the orthographic projection of the floating field plate and the orthographic projection of the second field plate on the horizontal plane are partially overlapped, and the vertical extension area of the floating field plate, the vertical extension area of the second field plate and the orthographic projection of the second field plate on the vertical plane are partially overlapped. A gap is formed between the vertical extension area of the floating field plate and the vertical extension area of the second field plate; a first connection structure is arranged between the second field plate vertical extension region and the gate structure, or a second connection structure is arranged between the second field plate vertical extension region and the source electrode. According to the power switch device, the floating field plate can generate extra electric field gradient when the device is turned off and bears high voltage, and the reliability of the device under high voltage can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a power switch device containing a floating field plate. Background Art

[0002] For lateral devices such as GaN HEMT, due to chip size limitations, the distance between the drain electrode and the source electrode needs to be shortened. This will cause a large electric field spike between the gate electrode and the drain electrode. Currently, multiple field plates are used to weaken the electric field spike.

[0003] In the existing technology, there are mainly multiple gate field plates connected to the gate, multiple source field plates connected to the source, and field plates with inclined structures that can also achieve electric field modulation. There are also continuously spaced floating field plates suitable for microwave devices, which use the coupling between multiple floating field plates to modulate the electric field.

[0004] However, the multi-field plate process often requires a photomask to implement each layer of field plates due to the different heights of each layer, which complicates the production process. Furthermore, since each field plate has a fixed height and a fixed potential difference, it can only withstand a relatively low voltage. The remaining high voltage will be distributed between the end of the field plate and the drain electrode, which is not conducive to the reliability of the device under high voltage. The slanted field plate process is difficult to implement and it is difficult to form a stable structure. It also has the above problems and is not conducive to the reliability of the device under high voltage. The electric field distribution formed by multiple floating field plates arranged in a continuous interval is affected by many factors, which can lead to deviations in device consistency. Summary of the Invention

[0005] In view of this, in order to overcome the defects of the prior art, an object of the present invention is to provide a power switching device containing a floating field plate, which can increase the reliability of the device under high voltage and simplify the process.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions: A power switching device containing a floating field plate comprises a substrate, a stacked structure, a first dielectric layer, a second dielectric layer, and a third dielectric layer, arranged in sequence from bottom to top. A source electrode, a drain electrode, and a gate structure are arranged on a side of the stacked structure away from the substrate. A two-dimensional electron gas is present in the stacked structure. The gate structure comprises a gate electrode and a first field plate. The power switching device further comprises a floating field plate, a second field plate, a floating field plate vertical extension region located above the floating field plate, and a second field plate vertical extension region located above the second field plate. The floating field plate Located in the second dielectric layer, the second field plate is located in the third dielectric layer, the floating field plate is located on a side of the second field plate away from the drain electrode, the top of the floating field plate vertical extension region and the top of the second field plate vertical extension region both pass through the top of the third dielectric layer, the floating field plate and the second field plate are partially overlapped in their orthographic projections on the horizontal plane, the floating field plate vertical extension region overlaps with the second field plate vertical extension region and the orthographic projections of the second field plate on the vertical plane, and a gap is formed between the floating field plate vertical extension region and the second field plate vertical extension region; A first connection structure is provided between the second field plate vertical extension region and the gate structure for connecting the second field plate to the gate electrode, or a second connection structure is provided between the second field plate vertical extension region and the source electrode for connecting the second field plate to the source electrode; wherein, when the second field plate is connected to the gate electrode, the second field plate is equivalent to a gate field plate; when the second field plate is connected to the source electrode, the second field plate is equivalent to a source field plate.

[0007] By providing a floating field plate, a floating field plate vertical extension region, a second field plate, and the second field plate vertical extension region, and utilizing a first connection structure or a second connection structure to connect the second field plate to the gate electrode or source electrode, a floating field plate is inserted between the source field plate and the two-dimensional electron gas below it, or between the gate field plate and the two-dimensional electron gas below it. The orthographic projections of the floating field plate and the second field plate on a horizontal plane partially overlap, and the floating field plate is located on the side of the second field plate away from the drain electrode. The potential below the floating field plate can be adjusted by adjusting the spacing and overlapping area between the fixed potential field plate (the second field plate) and the floating field plate. When the device is turned off and subjected to high voltage, the floating field plate generates an additional electric field gradient, which helps improve the reliability of the device under high voltage. Furthermore, because the floating field plate is implemented under the same photomask as the other field plates, the device fabrication process can be effectively simplified.

[0008] According to some preferred embodiments of the present invention, the floating field plate vertical extension region is parallel to the second field plate vertical extension region, and the floating field plate vertical extension region is located between the second field plate vertical extension region and the gate structure.

[0009] According to some preferred embodiments of the present invention, let the bottom area of ​​the floating field plate be S1, let the overlapping area of ​​the orthographic projection of the floating field plate and the second field plate on the horizontal plane be S2, let the overlapping area of ​​the vertical extension region of the floating field plate, the vertical extension region of the second field plate, and the orthographic projection of the second field plate on the vertical plane be S3, let the distance from the top surface of the first dielectric layer to the top surface of the two-dimensional electron gas be d1, let the thickness of the second dielectric layer be d2, and let the spacing between the vertical extension region of the floating field plate and the vertical extension region of the second field plate be d3, then (S2×d3+S3×d2)>S1×d3.

[0010] According to some preferred embodiments of the present invention, the second field plate includes an independent portion and a coupling portion, the independent portion is located on a side of the floating field plate close to the drain electrode and there is a gap between the independent portion and the end portions of the floating field plate close to each other, the coupling portion is located above the independent portion, and the bottom of the coupling portion at one end close to the drain electrode is connected to the top of the independent portion at one end away from the drain electrode.

[0011] According to some preferred embodiments of the present invention, the independent portion does not overlap with the orthographic projection of the floating field plate on the horizontal plane, the coupling portion partially overlaps with the orthographic projection of the floating field plate on the horizontal plane, and the overlapping area is S2, and S3 is the overlapping area of ​​the orthographic projection of the vertical extension region of the floating field plate, the vertical extension region of the second field plate, and the coupling portion on the vertical plane.

[0012] According to some preferred implementation aspects of the present invention, along the horizontal direction, a side of the floating field plate close to the gate structure is located between a side of the gate structure close to the floating field plate and an end of the coupling portion away from the drain electrode.

[0013] In the present invention, the design of the second field plate and the floating field plate, and their interaction, creates a structure equivalent to two capacitors connected in series: the lower capacitor is formed by the floating field plate and the two-dimensional electron gas directly below it, while the upper capacitor is formed by the floating field plate and the coupling portion of the second field plate above it (the portion that overlaps with the horizontal projection of the floating field plate). Furthermore, a capacitor is formed between the vertical extension of the floating field plate and the vertical extension of the second field plate, thereby increasing the capacitance of the upper capacitor formed by the floating field plate and the coupling portion above it.

[0014] Specifically, in some embodiments of the present invention, let the non-overlapping area of ​​the orthographic projection of the independent portion of the second field plate and the floating field plate on the horizontal plane be S4, let the potential of the floating field plate at high voltage equilibrium be V1, let the potential of the second field plate at high voltage equilibrium be V2, let the potential of the two-dimensional electron gas below the floating field plate at high voltage equilibrium be V3, let the potential of the two-dimensional electron gas below the second field plate at high voltage equilibrium be V4, then the potential balance formula of the floating field plate is: V3-V1=Q1 / C1=(n×q×S1) / (ε×ε0×S1 / d1)=n×q×d1 / (ε×ε0), the potential balance formula of the second field plate is: V4-V2=Q2 / C2=(n×q×S4) / [ε×ε0×S4 / (d1+d2)]=n×q×( d1+d2) / (ε×ε0), where Q1 is the charge stored in the capacitor formed by the floating field plate and the two-dimensional electron gas directly below it, C1 is the capacitance formed by the floating field plate and the two-dimensional electron gas directly below it, Q2 is the charge stored in the capacitor formed by the independent portion of the second field plate and the two-dimensional electron gas directly below it, C2 is the capacitance formed by the independent portion of the second field plate and the two-dimensional electron gas directly below it, n is the number of free electrons per unit volume, q is the charge of a single electron, ε0 is the vacuum dielectric constant, and ε is the relative dielectric constant of the medium used in the first dielectric layer. In the present invention, to simplify the calculation process, the relative dielectric constant of the medium used in the first dielectric layer is equal to the relative dielectric constant of the medium used in the second dielectric layer, and both are represented by ε.

[0015] The voltage divider formula of the upper and lower capacitances formed by the floating field plate is further derived as follows: (V1-V2) / (V3-V1)=C1 / C3=(S1×d2×d3) / [(S2×d3+S3×d2)×d1], where C3 is the capacitance formed between the floating field plate and the coupling portion of the second field plate, and between the vertical extension region of the floating field plate and the vertical extension region and coupling portion of the second field plate. From this, the potential of the floating field plate at high voltage equilibrium can be derived as V1=V2+n×q / (ε×ε0)×(S1×d2×d3) / The potential of the two-dimensional electron gas below the floating field plate at high-voltage equilibrium is V3 = V2 + n × q / (ε × ε0) × [(S1 × d2 × d3) / (S2 × d3 + S3 × d2) + d1]. The potential of the two-dimensional electron gas below the second field plate at high-voltage equilibrium is V4 = V2 + n × q / (ε × ε0) × (d1 + d2). Therefore, it can be seen that the potential below the floating field plate can be adjusted by regulating S1, S2, and S3 and / or d1, d2, and d3. Furthermore, since V4 is required to be greater than V3, (S2 × d3 + S3 × d2) is designed to be greater than S1 × d3, and the value of S1 × d3 / (S2 × d3 + S3 × d2) is 10% to 90%, preferably 40% to 50%.

[0016] According to some preferred embodiments of the present invention, the bottom surface of the floating field plate is aligned with the top surface of the first dielectric layer, the bottom surface of the second field plate is aligned with the top surface of the second dielectric layer, the vertical extension region of the floating field plate is located on the side of the floating field plate close to the gate structure and the bottom surface of the vertical extension region of the floating field plate is connected to the top surface of the floating field plate, and the vertical extension region of the second field plate is located at an end of the coupling portion away from the drain electrode and the bottom surface of the vertical extension region of the second field plate is connected to the top surface of the coupling portion.

[0017] According to some preferred embodiments of the present invention, the first field plate is located on a side of the gate electrode close to the drain electrode, and the first field plate and the floating field plate have the same thickness and are located on the same plane.

[0018] According to some preferred embodiments of the present invention, the first connection structure includes a first vertical connection portion and a first horizontal connection portion that are perpendicular to each other, the first vertical connection portion is parallel to the vertical extension region of the second field plate, the first vertical connection portion passes through the thickness direction of the second dielectric layer and the third dielectric layer, the first horizontal connection portion is located on the side of the third dielectric layer away from the second dielectric layer and the bottom surface of the first horizontal connection portion is in contact with the top surface of the third dielectric layer.

[0019] According to some preferred embodiments of the present invention, the bottom surface of the first vertical connection portion is connected to the top surface of the gate electrode, the top of the first vertical connection portion is connected to an end of the first horizontal connection portion away from the vertical extension region of the second field plate, and the end of the first horizontal connection portion away from the first vertical connection portion is connected to the top of the vertical extension region of the second field plate.

[0020] According to some preferred embodiments of the present invention, the second connection structure includes a second vertical connection portion and a second horizontal connection portion perpendicular to each other, the second vertical connection portion is parallel to the second field plate vertical extension region, the second vertical connection portion passes through the thickness direction of the second dielectric layer and the third dielectric layer, the second horizontal connection portion is located on the side of the third dielectric layer away from the second dielectric layer and the bottom surface of the second horizontal connection portion is in contact with the top surface of the third dielectric layer.

[0021] According to some preferred embodiments of the present invention, the bottom surface of the second vertical connection portion is connected to the top surface of the source electrode, the top of the second vertical connection portion is connected to an end of the second horizontal connection portion away from the vertical extension region of the second field plate, and the end of the second horizontal connection portion away from the second vertical connection portion is connected to the top of the vertical extension region of the second field plate.

[0022] In some embodiments of the present invention, the materials of the first connection structure and the second connection structure are both metal, and the gate electrode and the second field plate are short-circuited through the first connection structure, so that the second field plate is equivalent to the gate field plate; the source electrode and the second field plate are short-circuited through the second connection structure, so that the second field plate is equivalent to the source field plate.

[0023] Due to the adoption of the above technical solution, the present invention offers advantages over existing technologies in that: a power switching device containing a floating field plate is constructed in such a way that a floating field plate is inserted between the source field plate and the two-dimensional electron gas below it, or between the gate field plate and the two-dimensional electron gas below it. By adjusting the spacing and overlapping area between the second field plate and the floating field plate, the potential below the floating field plate can be adjusted. This results in the floating field plate generating an additional electric field gradient when the device is turned off and subjected to high voltage, thereby improving the device's reliability under high voltage. Furthermore, because the floating field plate is implemented under the same photomask as the other field plates, the device fabrication process can be effectively simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 Schematic diagram of the top view of the power switch device in Example 1 of the present invention; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the dotted line A; Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the dotted line B; Figure 4 Schematic diagram of the top view of the power switch device in Example 2 of the present invention; Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the dotted line C; Figure 6 for Figure 4 Schematic diagram of the cross-sectional structure along the dotted line D; Wherein, the accompanying drawings are marked as follows: Substrate-1, nucleation layer-21, buffer layer-22, channel layer-23, barrier layer-24, cap layer-25, first dielectric layer-3, second dielectric layer-4, third dielectric layer-5, source electrode-6, drain electrode-7, gate structure-8, gate electrode-81, first field plate-82, floating field plate-9, second field plate-10, independent part-101, coupling part-102, floating field plate vertical extension region-11, second field plate vertical extension region-12, first connection structure-13, first vertical connection part-131, first horizontal connection part-132, second connection structure-14, second vertical connection part-141, second horizontal connection part-142. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0027] Embodiment 1: This embodiment provides a power switch device, such as Figures 1 to 3 As shown, it includes a source electrode 6, a drain electrode 7, a gate structure 8, a floating field plate 9, a second field plate 10, a floating field plate vertical extension region 11 located above the floating field plate 9, a second field plate vertical extension region 12 located above the second field plate 10, and a substrate 1, a stacked structure, a first dielectric layer 3, a second dielectric layer 4 and a third dielectric layer 5 arranged in sequence from bottom to top. The source electrode 6, the drain electrode 7 and the gate structure 8 are located on the side of the stacked structure away from the substrate 1, and the second dielectric layer 4 covers the source electrode 6, the drain electrode 7 and the gate structure 8.

[0028] Specifically, the stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24 and a cap layer 25 arranged in sequence from bottom to top, and the heterojunction interface between the channel layer 23 and the barrier layer 24 has a two-dimensional electron gas, wherein the source electrode 6 and the drain electrode 7 are both located in the barrier layer 24, the cap layer 25, the first dielectric layer 3 and the second dielectric layer 4, the gate structure 8 includes a gate electrode 81 and a first field plate 82, the first field plate 82 is located on the side of the gate electrode 81 close to the drain electrode 7, the gate electrode 81 is located in the first dielectric layer 3 and the second dielectric layer 4, and the first field plate 82 is located in the second dielectric layer 4; the floating field plate 9 is located in the second dielectric layer 4, the second field plate 10 is located in the third dielectric layer 5, the first field plate 82 is equal to the thickness of the floating field plate 9, and the first field plate 82 and the floating field plate 9 are located on the same plane.

[0029] Further, if Figure 2As shown, the floating field plate 9 is located on the side of the second field plate 10 away from the drain electrode 7. The second field plate 10 includes an independent portion 101 and a coupling portion 102. The independent portion 101 is located on the side of the floating field plate 9 near the drain electrode 7, with a gap between the adjacent ends of the independent portion 101 and the floating field plate 9. The coupling portion 102 is located above the independent portion 101, with the bottom of the coupling portion 102 near the drain electrode 7 connected to the top of the independent portion 101 away from the drain electrode 7. Horizontally, the side of the floating field plate 9 near the gate structure 8 is located between the side of the gate structure 8 near the floating field plate 9 and the end of the coupling portion 102 away from the drain electrode 7. The orthographic projections of the independent portion 101 and the floating field plate 9 on the horizontal plane do not overlap, while the orthographic projections of the coupling portion 102 and the floating field plate 9 on the horizontal plane partially overlap.

[0030] The bottom surface of the floating field plate 9 is adhered to the top surface of the first dielectric layer 3, the bottom surface of the second field plate 10 is adhered to the top surface of the second dielectric layer 4, the floating field plate vertical extension region 11 is located on the side of the floating field plate 9 close to the gate structure 8, and the bottom surface of the floating field plate vertical extension region 11 is connected to the top surface of the floating field plate 9; the second field plate vertical extension region 12 is located at the end of the coupling portion 102 away from the drain electrode 7, and the bottom surface of the second field plate vertical extension region 12 is connected to the top surface of the coupling portion 102, and the top of the floating field plate vertical extension region 11 and the top of the second field plate vertical extension region 12 both pass through the top of the third dielectric layer 5. The floating field plate vertical extension region 11 is parallel to the second field plate vertical extension region 12. The floating field plate vertical extension region 11 is located between the second field plate vertical extension region 12 and the gate structure 8. There is a distance between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12. The floating field plate vertical extension region 11 partially overlaps with the second field plate vertical extension region 12 and the coupling portion 102 in the vertical plane.

[0031] Furthermore, let the bottom area of ​​the floating field plate 9 be S1, let the overlapping area of ​​the orthographic projections of the floating field plate 9 and the coupling portion 102 on the horizontal plane be S2, let the overlapping area of ​​the orthographic projections of the floating field plate vertical extension region 11, the second field plate vertical extension region 12, and the coupling portion 102 on the vertical plane be S3, let the distance from the top surface of the first dielectric layer 3 to the top surface of the two-dimensional electron gas be d1, let the thickness of the second dielectric layer 4 be d2, and let the spacing between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12 be d3. In this embodiment, because the potential of the two-dimensional electrons below the second field plate 10 at high-voltage equilibrium is greater than the potential of the two-dimensional electrons below the floating field plate 9 at high-voltage equilibrium, (S2×d3+S3×d2)>S1×d3, and the value of S1×d3 / (S2×d3+S3×d2) is preferably 40%-50%.

[0032] Further, if Figure 3As shown, in this embodiment, a first connection structure 13 is provided between the second field plate vertical extension region 12 and the gate structure 8. The first connection structure 13 includes a first vertical connection portion 131 and a first horizontal connection portion 132, which are perpendicular to each other. The first vertical connection portion 131 is parallel to the second field plate vertical extension region 12 and extends through the thickness of the second dielectric layer 4 and the third dielectric layer 5. The first horizontal connection portion 132 is located on the side of the third dielectric layer 5 away from the second dielectric layer 4, and the bottom surface of the first horizontal connection portion 132 is aligned with the top surface of the third dielectric layer 5. The bottom surface of the first vertical connection portion 131 is connected to the top surface of the gate electrode 81, the top of the first vertical connection portion 131 is connected to the end of the first horizontal connection portion 132 away from the second field plate vertical extension region 12, and the end of the first horizontal connection portion 132 away from the first vertical connection portion 131 is connected to the top of the second field plate vertical extension region 12. The first connection structure 13 is used to connect the second field plate 10 to the gate electrode 81, so that the second field plate 10 is equivalent to a gate field plate, and further makes the floating field plate 9 in this embodiment equivalent to being inserted between the gate field plate and the two-dimensional electron gas below it. When the device is turned off and subjected to high voltage, the floating field plate 9 generates an additional electric field gradient, which is beneficial to increasing the reliability of the device under high voltage.

[0033] In this embodiment, by disposing a floating field plate 9 between the gate field plate and the two-dimensional electron gas, and by reasonably controlling the overlapping area of ​​the orthographic projection of the floating field plate 9 and the coupling portion 102 in the second field plate 10 above on the horizontal plane, the overlapping area of ​​the floating field plate 9 and the two-dimensional electron gas below (equivalent to the bottom area of ​​the floating field plate 9 itself), the overlapping area of ​​the orthographic projection of the floating field plate vertical extension region 11, the second field plate vertical extension region 12, and the coupling portion 102 on the vertical plane, the distance from the top surface of the first dielectric layer 3 to the top surface of the two-dimensional electron gas, the thickness of the second dielectric layer 4, and the spacing between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12, the electric potential below the floating field plate 9 can be regulated.

[0034] This embodiment also provides a method for preparing the above-mentioned power switch device, which specifically includes the following steps: Step 1: Nitride epitaxial growth is performed on substrate 1, sequentially forming a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25. Materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 21, buffer layer 22, channel layer 23, barrier layer 24, and cap layer 25 form a stacked structure, thus forming a complete semiconductor epitaxial layer structure. This layer can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 23 and the barrier layer 24, generating a conductive channel. Substrate 1 is composed of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing Group III nitride materials.

[0035] Step 2: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 on the cap layer 25 to form a first dielectric layer 3, and etch out source electrode through holes and drain electrode through holes that pass through the first dielectric layer 3, the cap layer 25, and the barrier layer 24, respectively; and again use yellow light to etch out a gate groove that passes through the first dielectric layer 3.

[0036] Step 3: Fill the source electrode through hole and the drain electrode through hole with metal to form the source electrode 6 and the drain electrode 7 respectively, and perform annealing treatment so that the source electrode 6 and the drain electrode 7 form ohmic contacts with the epitaxial material thereunder.

[0037] Step 4: Fill metal above the first dielectric layer 3 and etch to form a gate structure 8 and a floating field plate 9. Since the depth of the gate trench etching is shallow, the gate structure 8 will not form an ohmic contact with the epitaxial material below, and the gate structure 8 is divided into a gate electrode 81 in the gate trench and a first field plate 82 outside the gate trench close to the drain electrode 7.

[0038] Step 5: deposit one or more combinations of SiN, SiO 2 , SiON, and Al 2 O 3 on the gate structure 8 and the floating field plate 9 to form a second dielectric layer 4 .

[0039] Step 6: Fill metal above the second dielectric layer 4 and etch to form a second field plate 10, wherein the second field plate 10 includes an independent portion 101 and a coupling portion 102 (longitudinal capacitive coupling region), the coupling portion 102 is located above the independent portion 101, the portion close to the drain electrode 7 and not overlapping with the orthographic projection of the floating field plate 9 on the horizontal plane is the independent portion 101, and the coupling portion 102 partially overlaps with the orthographic projection of the floating field plate 9 on the horizontal plane.

[0040] Step 7: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate 10 to form a third dielectric layer 5, and etch a first through hole, a first through groove, and a second through groove downward from the top surface of the third dielectric layer 5 corresponding to the gate electrode 81, the side of the floating field plate 9 close to the gate structure 8, and the side of the coupling portion 102 close to the gate structure 8, respectively. The first through hole and the first through groove both penetrate the second dielectric layer 4 and the third dielectric layer 5, and the second through groove penetrates the third dielectric layer 5.

[0041] Step 8: Fill metal above the third dielectric layer 5 and in the first through hole, the first through groove and the second through groove and etch to form a first connecting structure 13, a floating field plate vertical extension region 11 and a second field plate vertical extension region 12. The second field plate 10 and the gate electrode 81 are electrically connected through the second field plate vertical extension region 12 and the first connecting structure 13, so that the second field plate 10 is equivalent to the gate field plate, and the power switching device containing the floating field plate 9 in this embodiment is obtained, and the floating field plate 9 in this embodiment is equivalent to being inserted between the gate field plate and the two-dimensional electron gas.

[0042] Embodiment 2: The power switch device in this embodiment includes: Figures 4 to 6 As shown, it includes a source electrode 6, a drain electrode 7, a gate structure 8, a floating field plate 9, a second field plate 10, a floating field plate vertical extension region 11 located above the floating field plate 9, a second field plate vertical extension region 12 located above the second field plate 10, and a substrate 1, a stacked structure, a first dielectric layer 3, a second dielectric layer 4 and a third dielectric layer 5 arranged in sequence from bottom to top. The source electrode 6, the drain electrode 7 and the gate structure 8 are located on the side of the stacked structure away from the substrate 1, and the second dielectric layer 4 covers the source electrode 6, the drain electrode 7 and the gate structure 8.

[0043] Specifically, the stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24 and a cap layer 25 arranged in sequence from bottom to top, and the heterojunction interface between the channel layer 23 and the barrier layer 24 has a two-dimensional electron gas, wherein the source electrode 6 and the drain electrode 7 are both located in the barrier layer 24, the cap layer 25, the first dielectric layer 3 and the second dielectric layer 4, the gate structure 8 includes a gate electrode 81 and a first field plate 82, the first field plate 82 is located on the side of the gate electrode 81 close to the drain electrode 7, the gate electrode 81 is located in the first dielectric layer 3 and the second dielectric layer 4, and the first field plate 82 is located in the second dielectric layer 4; the floating field plate 9 is located in the second dielectric layer 4, the second field plate 10 is located in the third dielectric layer 5, the first field plate 82 is equal to the thickness of the floating field plate 9, and the first field plate 82 and the floating field plate 9 are located on the same plane.

[0044] Further, if Figure 5As shown, the floating field plate 9 is located on the side of the second field plate 10 away from the drain electrode 7. The second field plate 10 includes an independent portion 101 and a coupling portion 102. The independent portion 101 is located on the side of the floating field plate 9 near the drain electrode 7, with a gap between the adjacent ends of the independent portion 101 and the floating field plate 9. The coupling portion 102 is located above the independent portion 101, with the bottom of the coupling portion 102 near the drain electrode 7 connected to the top of the independent portion 101 away from the drain electrode 7. Horizontally, the side of the floating field plate 9 near the gate structure 8 is located between the side of the gate structure 8 near the floating field plate 9 and the end of the coupling portion 102 away from the drain electrode 7. The orthographic projections of the independent portion 101 and the floating field plate 9 on the horizontal plane do not overlap, while the orthographic projections of the coupling portion 102 and the floating field plate 9 on the horizontal plane partially overlap.

[0045] The bottom surface of the floating field plate 9 is adhered to the top surface of the first dielectric layer 3, the bottom surface of the second field plate 10 is adhered to the top surface of the second dielectric layer 4, the floating field plate vertical extension region 11 is located on the side of the floating field plate 9 close to the gate structure 8, and the bottom surface of the floating field plate vertical extension region 11 is connected to the top surface of the floating field plate 9; the second field plate vertical extension region 12 is located at the end of the coupling portion 102 away from the drain electrode 7, and the bottom surface of the second field plate vertical extension region 12 is connected to the top surface of the coupling portion 102, and the top of the floating field plate vertical extension region 11 and the top of the second field plate vertical extension region 12 both pass through the top of the third dielectric layer 5. The floating field plate vertical extension region 11 is parallel to the second field plate vertical extension region 12. The floating field plate vertical extension region 11 is located between the second field plate vertical extension region 12 and the gate structure 8. There is a distance between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12. The floating field plate vertical extension region 11 partially overlaps with the second field plate vertical extension region 12 and the coupling portion 102 in the vertical plane.

[0046] Furthermore, let the bottom area of ​​the floating field plate 9 be S1, let the overlapping area of ​​the orthographic projections of the floating field plate 9 and the coupling portion 102 on the horizontal plane be S2, let the overlapping area of ​​the orthographic projections of the floating field plate vertical extension region 11, the second field plate vertical extension region 12, and the coupling portion 102 on the vertical plane be S3, let the distance from the top surface of the first dielectric layer 3 to the top surface of the two-dimensional electron gas be d1, let the thickness of the second dielectric layer 4 be d2, and let the spacing between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12 be d3. In this embodiment, because the potential of the two-dimensional electrons below the second field plate 10 at high-voltage equilibrium is greater than the potential of the two-dimensional electrons below the floating field plate 9 at high-voltage equilibrium, (S2×d3+S3×d2)>S1×d3, and the value of S1×d3 / (S2×d3+S3×d2) is preferably 40%-50%.

[0047] Further, if Figure 6As shown, in this embodiment, a second connection structure 14 is provided between the second field plate vertical extension region 12 and the source electrode 6. The second connection structure 14 includes a second vertical connection portion 141 and a second horizontal connection portion 142, which are perpendicular to each other. The second vertical connection portion 141 is parallel to the second field plate vertical extension region 12 and extends through the thickness of the second dielectric layer 4 and the third dielectric layer 5. The second horizontal connection portion 142 is located on the side of the third dielectric layer 5 away from the second dielectric layer 4, and the bottom surface of the second horizontal connection portion 142 is aligned with the top surface of the third dielectric layer 5. The bottom surface of the second vertical connection portion 141 is connected to the top surface of the source electrode 6, the top of the second vertical connection portion 141 is connected to the end of the second horizontal connection portion 142 away from the second field plate vertical extension region 12, and the end of the second horizontal connection portion 142 away from the second vertical connection portion 141 is connected to the top of the second field plate vertical extension region 12. The second connection structure 14 is used to connect the second field plate 10 to the source electrode 6, so that the second field plate 10 is equivalent to the source field plate, and further makes the floating field plate 9 in this embodiment equivalent to being inserted between the source field plate and the two-dimensional electron gas below it. When the device is turned off and subjected to high voltage, the floating field plate 9 generates an additional electric field gradient, which is beneficial to increasing the reliability of the device under high voltage.

[0048] In this embodiment, by disposing a floating field plate 9 between the source field plate and the two-dimensional electron gas, and by reasonably controlling the overlapping area of ​​the orthographic projection of the floating field plate 9 and the coupling portion 102 in the second field plate 10 above on the horizontal plane, the overlapping area of ​​the floating field plate 9 and the two-dimensional electron gas below (equivalent to the bottom area of ​​the floating field plate 9 itself), the overlapping area of ​​the orthographic projection of the floating field plate vertical extension region 11, the second field plate vertical extension region 12, and the coupling portion 102 on the vertical plane, the distance from the top surface of the first dielectric layer 3 to the top surface of the two-dimensional electron gas, the thickness of the second dielectric layer 4, and the spacing between the floating field plate vertical extension region 11 and the second field plate vertical extension region 12, the electric potential below the floating field plate 9 can be regulated.

[0049] This embodiment also provides a method for preparing the above-mentioned power switch device, which specifically includes the following steps: Step 1: Nitride epitaxial growth is performed on substrate 1, sequentially forming a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25. Materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 21, buffer layer 22, channel layer 23, barrier layer 24, and cap layer 25 form a stacked structure, thus forming a complete semiconductor epitaxial layer structure. This layer can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 23 and the barrier layer 24, generating a conductive channel. Substrate 1 is composed of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing Group III nitride materials.

[0050] Step 2: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 on the cap layer 25 to form a first dielectric layer 3, and etch out source electrode through holes and drain electrode through holes that pass through the first dielectric layer 3, the cap layer 25, and the barrier layer 24, respectively; and again use yellow light to etch out a gate groove that passes through the first dielectric layer 3.

[0051] Step 3: Fill the source electrode through hole and the drain electrode through hole with metal to form the source electrode 6 and the drain electrode 7 respectively, and perform annealing treatment so that the source electrode 6 and the drain electrode 7 form ohmic contacts with the epitaxial material thereunder.

[0052] Step 4: Fill metal above the first dielectric layer 3 and etch to form a gate structure 8 and a floating field plate 9. Since the depth of the gate trench etching is shallow, the gate structure 8 will not form an ohmic contact with the epitaxial material below, and the gate structure 8 is divided into a gate electrode 81 in the gate trench and a first field plate 82 outside the gate trench close to the drain electrode 7.

[0053] Step 5: deposit one or more combinations of SiN, SiO 2 , SiON, and Al 2 O 3 on the gate structure 8 and the floating field plate 9 to form a second dielectric layer 4 .

[0054] Step 6: Fill metal above the second dielectric layer 4 and etch to form a second field plate 10, wherein the second field plate 10 includes an independent portion 101 and a coupling portion 102 (longitudinal capacitive coupling region), the coupling portion 102 is located above the independent portion 101, the portion close to the drain electrode 7 and not overlapping with the orthographic projection of the floating field plate 9 on the horizontal plane is the independent portion 101, and the coupling portion 102 partially overlaps with the orthographic projection of the floating field plate 9 on the horizontal plane.

[0055] Step 7: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate 10 to form a third dielectric layer 5, and etch a second through hole, a first through groove, and a second through groove downward from the top surface of the third dielectric layer 5 corresponding to the source electrode 6, the side of the floating field plate 9 close to the gate structure 8, and the side of the coupling part 102 close to the gate structure 8, respectively. The second through hole and the first through groove both penetrate the second dielectric layer 4 and the third dielectric layer 5, and the second through groove penetrates the third dielectric layer 5.

[0056] Step 8: Fill metal above the third dielectric layer 5 and in the second through hole, the first through groove and the second through groove and etch to form a second connection structure 14, a floating field plate vertical extension area 11 and a second field plate vertical extension area 12. The second field plate 10 and the source electrode 6 are electrically connected through the second field plate vertical extension area 12 and the second connection structure 14, so that the second field plate 10 is equivalent to the source field plate, and the power switching device containing the floating field plate 9 in this embodiment is obtained, and the floating field plate 9 in this embodiment is equivalent to being inserted between the source field plate and the two-dimensional electron gas.

[0057] In the power switching device of the present invention, a floating field plate 9 is inserted between the source field plate or the gate field plate and the two-dimensional electron gas. By adjusting the spacing and overlapping area between the second field plate 10 and the floating field plate 9, the electric potential below the floating field plate 9 can be adjusted, so that when the device is turned off and subjected to high voltage, the floating field plate 9 will generate an additional electric field gradient, which is beneficial to increasing the reliability of the device under high voltage; in addition, through the preparation methods in the above-mentioned Examples 1 and 2, it can be seen that the floating field plate 9 is obtained under the same layer of mask as other field plates, which is beneficial to simplifying the preparation process of the device.

[0058] The above embodiments of the present invention are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made in accordance with the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. A power switching device with a floating field plate, comprising a substrate, a stacked structure, a first dielectric layer, a second dielectric layer, and a third dielectric layer arranged in sequence from bottom to top, wherein a source electrode, a drain electrode, and a gate structure are arranged on a side of the stacked structure away from the substrate, a two-dimensional electron gas is present in the stacked structure, and the gate structure includes a gate electrode and a first field plate, characterized in that: The power switching device further includes a floating field plate, a second field plate, a floating field plate vertical extension region located above the floating field plate, and a second field plate vertical extension region located above the second field plate, wherein the floating field plate is located in the second dielectric layer, the second field plate is located in the third dielectric layer, the floating field plate is located on a side of the second field plate away from the drain electrode, the top of the floating field plate vertical extension region and the top of the second field plate vertical extension region both pass through the top of the third dielectric layer, the orthographic projections of the floating field plate and the second field plate on a horizontal plane partially overlap, the floating field plate vertical extension region overlaps with the second field plate vertical extension region and the orthographic projections of the second field plate on a vertical plane, and a gap is provided between the floating field plate vertical extension region and the second field plate vertical extension region; A first connection structure is provided between the second field plate vertical extension region and the gate structure for connecting the second field plate to the gate electrode, or a second connection structure is provided between the second field plate vertical extension region and the source electrode for connecting the second field plate to the source electrode.

2. The power switch device with a floating field plate according to claim 1, characterized in that: The floating field plate vertical extension region is parallel to the second field plate vertical extension region, and the floating field plate vertical extension region is located between the second field plate vertical extension region and the gate structure.

3. The power switch device with a floating field plate according to claim 2, characterized in that: Let the bottom area of ​​the floating field plate be S1, let the overlapping area of ​​the orthographic projections of the floating field plate and the second field plate on the horizontal plane be S2, let the overlapping area of ​​the vertical extension region of the floating field plate, the vertical extension region of the second field plate, and the orthographic projections of the second field plate on the vertical plane be S3, let the distance from the top surface of the first dielectric layer to the top surface of the two-dimensional electron gas be d1, let the thickness of the second dielectric layer be d2, and let the spacing between the vertical extension region of the floating field plate and the vertical extension region of the second field plate be d3, then (S2×d3+S3×d2)>S1×d3.

4. The power switch device with a floating field plate according to claim 3, characterized in that: The second field plate includes an independent part and a coupling part. The independent part is located on the side of the floating field plate close to the drain electrode and there is a gap between the ends of the independent part and the floating field plate close to each other. The coupling part is located above the independent part, and the bottom of the coupling part close to the drain electrode is connected to the top of the independent part away from the drain electrode.

5. The power switch device with a floating field plate according to claim 4, characterized in that: The independent portion does not overlap with the orthographic projection of the floating field plate on the horizontal plane, the coupling portion partially overlaps with the orthographic projection of the floating field plate on the horizontal plane, and the overlapping area is S2, and S3 is the overlapping area of ​​the orthographic projection of the vertical extension area of ​​the floating field plate, the vertical extension area of ​​the second field plate, and the coupling portion on the vertical plane.

6. The power switch device with a floating field plate according to claim 5, characterized in that: Along the horizontal direction, a side of the floating field plate close to the gate structure is located between a side of the gate structure close to the floating field plate and an end of the coupling portion away from the drain electrode.

7. The power switch device with a floating field plate according to claim 5, characterized in that: The bottom surface of the floating field plate is aligned with the top surface of the first dielectric layer, the bottom surface of the second field plate is aligned with the top surface of the second dielectric layer, the vertical extension region of the floating field plate is located on the side of the floating field plate close to the gate structure and the bottom surface of the vertical extension region of the floating field plate is connected to the top surface of the floating field plate, the vertical extension region of the second field plate is located at the end of the coupling portion away from the drain electrode and the bottom surface of the vertical extension region of the second field plate is connected to the top surface of the coupling portion.

8. The power switch device with a floating field plate according to claim 1, wherein: The first field plate is located on a side of the gate electrode close to the drain electrode. The first field plate and the floating field plate have the same thickness and are located on the same plane.

9. The power switch device with a floating field plate according to claim 1, wherein: The first connection structure includes a first vertical connection portion and a first horizontal connection portion that are perpendicular to each other, the first vertical connection portion is parallel to the vertical extension area of ​​the second field plate, the first vertical connection portion passes through the thickness direction of the second dielectric layer and the third dielectric layer, the first horizontal connection portion is located on the side of the third dielectric layer away from the second dielectric layer and the bottom surface of the first horizontal connection portion is in contact with the top surface of the third dielectric layer.

10. The power switch device containing a floating field plate according to claim 9, characterized in that: The bottom surface of the first vertical connection portion is connected to the top surface of the gate electrode, the top of the first vertical connection portion is connected to an end of the first horizontal connection portion away from the second field plate vertical extension region, and the end of the first horizontal connection portion away from the first vertical connection portion is connected to the top of the second field plate vertical extension region.

11. The power switch device with a floating field plate according to claim 1, wherein: The second connection structure includes a second vertical connection portion and a second horizontal connection portion perpendicular to each other, the second vertical connection portion is parallel to the second field plate vertical extension area, the second vertical connection portion passes through the thickness direction of the second dielectric layer and the third dielectric layer, the second horizontal connection portion is located on the side of the third dielectric layer away from the second dielectric layer and the bottom surface of the second horizontal connection portion is in contact with the top surface of the third dielectric layer.

12. The power switch device with a floating field plate according to claim 11, characterized in that: The bottom surface of the second vertical connection portion is connected to the top surface of the source electrode, the top of the second vertical connection portion is connected to an end of the second horizontal connection portion away from the second field plate vertical extension region, and the end of the second horizontal connection portion away from the second vertical connection portion is connected to the top of the second field plate vertical extension region.

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