Semiconductor device cellular structure and preparation method thereof, and semiconductor device

Abstract

The invention relates to a semiconductor device cellular structure, a preparation method thereof and a semiconductor device. The semiconductor device cellular structure comprises a substrate; the top surface of the substrate comprises a dielectric layer; the substrate comprises a plurality of unit regions which are arranged at intervals along a first direction and a second direction, and strip-shaped trench gates which are positioned between the adjacent unit regions; each unit region internally comprises a source region, a base region and a strip-shaped well region with a cross-shaped cross section which pass through the first surface of the substrate and are sequentially arranged along a third direction towards the substrate; the section is perpendicular to the third direction; the strip-shaped well region penetrates through the source region and the base region along a third direction; the adjacent strip-shaped well regions are aligned; the dielectric layer comprises a plurality of contact holes, and the contact holes and the unit areas are arranged in a one-to-one mode. Aiming at the inherent reliability problem of the grid groove, by optimizing the injection layout of the strip-shaped well region, a similar grid-shaped P + shielding injection layout is formed, so that the balance between the performance and the reliability is achieved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device cell structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a widely used and high-performance power device with advantages such as fast switching speed, low loss, and simple drive circuits. The trench silicon carbide (SiC) MOSFET device structure has rapidly developed in the new energy industry due to its excellent high-voltage and high-temperature resistance.

[0003] Among related technologies, grid-shaped trench-type SiC MOSFETs are widely used because they optimize on-resistance by increasing channel density. However, with the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of device physical dimensions has led to a continuous decrease in the step size of its cell structure, resulting in electric field concentration at the corners or bottom of the device trench, and a significant increase in the breakdown risk faced by the gate oxide layer.

[0004] Therefore, how to ensure the reliability of the gate oxide layer of the grid-shaped trench SIC MOSFET has become one of the problems that need to be solved urgently by those skilled in the art. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor device cell structure and its preparation method, and a semiconductor device to address the technical problems in the prior art, which can at least ensure the reliability of the grid-shaped trench SIC MOSFET gate oxide layer.

[0006] In a first aspect, the present application provides a semiconductor device cell structure, comprising: a substrate; a dielectric layer on the top surface of the substrate;

[0007] The substrate includes a plurality of cell regions spaced apart along a first direction and a second direction, and strip-shaped trench gates located between adjacent cell regions; each cell region includes a source region, a base region, and a strip-shaped well region having a "cross"-shaped cross section, which are arranged in sequence along a third direction toward the substrate through the first surface of the substrate; the cross section is perpendicular to the third direction;

[0008] The strip-shaped well region penetrates the source region and the base region along a third direction; adjacent strip-shaped well regions are aligned;

[0009] The dielectric layer includes a plurality of contact holes, and the contact holes are arranged one to one with the cell areas.

[0010] In the cell structure described in the above embodiment, the cell area is separated by strip trench gates to form a grid-like distribution structure. By optimizing the injection layout of the strip well region, a strip well region is introduced as a shielding region within the cell area of ​​the grid-like trench structure. Compared to a dispersed block structure, the depletion layer formed by the shielding region increases the protection range of the bottom gate oxide during reverse cutoff of the device. Compared to a single strip distribution, the grid-like trench device provided in the embodiment of the present application has a higher channel density and better on-resistance performance.

[0011] In some embodiments, the stripe-shaped well region penetrates the cell region along the first direction and along the second direction.

[0012] In some embodiments, the strip trench gate penetrates the source region and the base region along a third direction;

[0013] The depth of the strip trench gate is not greater than the depth of the strip well region;

[0014] The width of the strip trench gate is not less than the spacing between adjacent cell areas;

[0015] The width is used to characterize the size along the first direction, and the depth is used to characterize the size along the third direction.

[0016] In some embodiments, the contact holes are arranged one-to-one with the cell regions, including:

[0017] The contact hole penetrates the dielectric layer along a third direction;

[0018] The orthographic projection of the contact hole on the top surface of the cell region is located within the top surface of the cell region.

[0019] In some embodiments, the geometric center of the stripe-shaped well region is located within the orthographic projection of the contact hole on the top surface of the cell region.

[0020] In some embodiments, the gate conductive layer is located in the strip-shaped trench gate, and its top surface is flush with the top surface of the substrate;

[0021] a gate oxide layer, located between the dielectric layer and the substrate, and between the gate conductive layer and the substrate;

[0022] The front metal layer is located on the top surface of the dielectric layer and in the contact hole, and extends to the top surface of the substrate along the third direction.

[0023] In a second aspect, the present application provides a method for preparing a semiconductor device cell structure, comprising: providing a substrate; the substrate comprising a plurality of unit regions spaced apart along a first direction and a second direction; each unit region comprising a source region and a base region sequentially arranged along a third direction away from the substrate and extending through a first surface of the substrate;

[0024] A strip well region with a "cross"-shaped cross section is formed between the unit regions, and a strip trench gate is formed between adjacent unit regions; the strip well region penetrates the source region and the base region along a third direction; and the cross section is perpendicular to the third direction;

[0025] A dielectric layer covering the top surface of the substrate is formed; the dielectric layer includes a plurality of contact holes, and the contact holes are arranged one-to-one with the cell areas.

[0026] In the fabrication method described in the aforementioned embodiment, compared to the cellular structure that adds a shielding region at the bottom of the trench gate, the method provided in the embodiment of the present application is compatible with the existing mesh shielding region implantation method. Without requiring additional process steps, it avoids the increase in on-resistance caused by the introduction of an additional JFET region at the bottom shielding region of the trench gate, thus achieving a balance between device performance and gate oxide reliability. Furthermore, the shielding region (strip well region) can be grounded within the existing structure, avoiding the etching and metal backfilling steps of the polysilicon gate at the bottom shielding region in the related art, thus reducing the difficulty of process implementation.

[0027] In some embodiments, forming a stripe-shaped well region includes:

[0028] Performing an ion implantation process on the substrate to form a plurality of first ion implantation regions spaced apart along a first direction and extending along a second direction, and a plurality of second ion implantation regions spaced apart along the second direction and extending along the first direction;

[0029] A strip trench is formed between adjacent cell regions and passes through the source region and the base region along a third direction; the remaining first ion implantation region and the second ion implantation region constitute a strip well region, and the depth of the strip trench is no greater than the depth of the strip well region;

[0030] Depth is used to characterize the size along the third direction.

[0031] In some embodiments, forming a dielectric layer includes:

[0032] After forming a gate oxide layer covering the top surface of the substrate and the inner surface of the strip-shaped trench, a gate conductive layer is formed in the strip-shaped trench;

[0033] After forming a dielectric material layer on the top surface of the gate conductive layer and the top surface of the gate oxide layer, a portion of the dielectric material layer is removed to form a contact hole, and the remaining dielectric material layer is used to form a dielectric layer; the contact hole penetrates the dielectric layer and the gate oxide layer along a third direction, and the geometric center of the strip well region is located within the orthographic projection of the contact hole on the top surface of the cell area.

[0034] In a third aspect, the present application further provides a semiconductor device, comprising a cellular structure as described in any one of the above embodiments; or a cellular structure prepared by the preparation method as described in any one of the above embodiments.

[0035] In the semiconductor device in the above embodiment, the device improves electrical performance (low-resistance conduction, high-voltage tolerance) while simplifying the manufacturing process through collaborative innovation of structure and process, thereby achieving dual optimization of device reliability and process feasibility.

[0036] The semiconductor device cell structure and its preparation method, as well as the semiconductor device provided by this application, have the following unexpected technical effects:

[0037] The fabrication method provided in this application is highly compatible with existing mesh shielding implantation processes, maintaining the original block P+ shielding implantation sequence. The novel structure can be fabricated using only conventional process steps, including mask deposition, photolithography, dry etching, and ion implantation. Compared to conventional methods that implant a shielding region at the bottom of a trench gate, this method eliminates the need for additional process steps, significantly simplifying the process flow. Furthermore, grounding is achieved through electrical connection to the existing block P+ shielding implantation structure, eliminating complex process steps such as polysilicon gate etching and metal backfill. This significantly reduces the complexity of process implementation and effectively improves production line compatibility and fabrication efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 A top view schematic diagram of a mesh trench SIC MOSFET cell structure provided for related technologies;

[0040] Figure 2a This is one of the structural schematic diagrams of a cellular structure provided in one embodiment;

[0041] Figure 2b This is a second structural diagram of a cellular structure provided in one embodiment;

[0042] Figure 3 is a flow chart of a preparation method provided in one embodiment;

[0043] Figure 4 Schematic diagram of the structure obtained after forming the source region and the base region in step S102 of the preparation method provided in one embodiment;

[0044] Figure 5 Schematic diagram of the structure obtained after forming the first ion implantation region and the second ion implantation region in step S202 of the preparation method provided in one embodiment;

[0045] Figure 6Schematic diagram of the structure obtained after forming the gate oxide layer and the gate conductive layer in step S206 of the preparation method provided in one embodiment;

[0046] Figure 7 Schematic diagram of the structure obtained after forming the contact hole in step S106 of the preparation method provided in one embodiment;

[0047] Figure 8 Schematic diagram of the structure obtained after forming the front metal layer in step S302 of the preparation method provided in one embodiment;

[0048] Figure 9 Schematic diagram of the structure obtained after the back surface process is completed in step S304 of the preparation method provided in one embodiment.

[0049] Description of reference numerals:

[0050] 1. Substrate; 10. Cell region; 11. Base region; 12. Source region; 201. First ion implantation region; 202. Second ion implantation region; 20. Stripe well region; 30. Stripe trench gate; 31. Gate oxide layer; 32. Gate conductive layer; 13. Dielectric layer; 40. Contact hole; 14. Front metal layer; 15. Passivation layer; 16. Protective layer; 17. Back metal layer. DETAILED DESCRIPTION

[0051] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0054] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0057] As mentioned above, the grid trench device has a better on-resistance. Figure 1 As shown, the shielding area in the grid-shaped trench device adopts a block distribution design, which makes it difficult to achieve effective protection of the gate oxide under the reverse cutoff and high reverse voltage conditions of the device, resulting in device reliability failure.

[0058] In existing technologies, a shielding area is added to the bottom of the trench to protect it. Specifically, in order to achieve grounding of the bottom shielding area, the polysilicon used as the gate electrode must be etched again and then backfilled with metal. While this solution effectively ensures reliability, its process is complex and difficult to implement. These two issues lead to high costs and low production efficiency. Furthermore, the shielding injection at the bottom of the trench also increases the on-resistance, which is not conducive to improving device performance.

[0059] Based on this, see Figure 2a , Figure 2a Figures a and b in the middle respectively show a partial perspective view and a partial top view of an exemplary semiconductor device cell structure; Figure 2b Shown along Figure 2a Figure a shows an exemplary cross section taken along lines AA' and BB'. For ease of understanding, the substrate may include a first surface located on the front side and a second surface located opposite the front side. In the embodiments of the present application, the first direction is defined as the Y-axis direction, the second direction is defined as the X-axis direction, and the third direction is defined as the Z-axis direction.

[0060] The present application provides a semiconductor device cell structure, comprising: a substrate 1; a dielectric layer 13 on the top surface of the substrate 1;

[0061] The substrate 1 includes a plurality of cell regions 10 spaced apart along the OY direction and the OX direction, and a strip trench gate 30 located between adjacent cell regions 10; each cell region 10 includes a source region 12, a base region 11, and a strip well region 20 having a "cross"-shaped cross section, which extends through the first surface of the substrate 1 and is sequentially arranged along the OZ direction; the cross section is perpendicular to the OZ direction;

[0062] The strip-shaped well region 20 penetrates the source region 12 and the base region 11 along the OZ direction;

[0063] The dielectric layer 13 includes a plurality of contact holes 40 , and the contact holes 40 are arranged one-to-one with the cell regions 10 .

[0064] The width is used to represent the size along the OY direction, and the depth is used to represent the size along the OZ direction.

[0065] Among them, when the conductivity type of the substrate 1 is N-type, the base region 11 is P-type, the source region 12 is N-type, and the strip well region is P-type. Conversely, if the substrate 1 is P-type, the conductivity types of each region are correspondingly reversed.

[0066] The strip trench gate 30 extends through the source region 12 and the base region 11 along the OZ direction. The depth of the strip trench gate 30 is no greater than the depth of the strip well region 20, and its width is no less than the spacing between adjacent cell regions 10. The strip well region 20 is deeper than the strip trench gate 30, ensuring that the shielding region can provide space for the lateral depletion layer to expand.

[0067] The contact hole 40 is used for metal filling to form an electrical connection (such as a source contact) to connect to an external circuit.

[0068] In the above embodiment, multiple cell regions 10 are separated by strip trench gates 30, and two adjacent rows of cell regions and strip well regions are aligned. The cell regions are arranged in an array along the OX and OY directions to form a grid-type cellular structure. Within each cell region 10, an active region 12 and a base region 11 are arranged sequentially along the OZ direction from the first surface into the substrate 1. The strip well region extends along the OZ direction through the source region 12 and the base region 11 into the substrate 1, serving as a shielding region for the semiconductor device. It forms a depletion layer with the substrate 1 of opposite conductivity type, optimizes the electric field lines at the bottom of the strip trench gates 30, and alleviates the problem of electric field concentration at corners.

[0069] In addition, the cross section of the stripe-shaped well region 20 in the cell region 10 in the XY plane is a cross.

[0070] For example, in some embodiments, the strip well region 20 penetrates the cell region 10 along the OY direction and the OX direction, with the center of the cross at the center of the cell, and extends in two directions to the strip trench gate 30, effectively strengthening the protection of the bottom gate oxide disposed in the strip trench gate 30 when the device is reversely cut off, and ensuring the uniformity of device performance.

[0071] Specifically, the contact hole 40 is arranged one-to-one with the cell area 10 , including: the contact hole 40 penetrates the dielectric layer 13 along the OZ direction, and its orthographic projection on the top surface of the cell area 10 is located within the top surface of the cell area 10 .

[0072] Furthermore, in some embodiments, the geometric center of the strip-shaped well region 20 is located within the orthographic projection of the contact hole 40 on the top surface of the cell region 10 .

[0073] In the above embodiment, the contact hole 40 is defined on the geometric center of the stripe-shaped well region 20 to ensure uniformity of the distance from the adjacent stripe-shaped trench gate 30 .

[0074] For example, the cell structure further includes: a gate conductive layer 32 (not shown), located in the strip trench gate 30, with its top surface flush with the top surface of the substrate; a gate oxide layer 31, located between the dielectric layer 13 and the substrate 1, and between the gate conductive layer 32 and the substrate 1; a front metal layer 14, located on the top surface of the dielectric layer 13 and in the contact hole 40, and extending along the third direction to the top surface of the gate oxide layer 31.

[0075] The following describes an embodiment of forming the above-mentioned cell structure. Figure 3 , the present application provides a method for preparing a cellular structure, which can be used to prepare Figure 2a The semiconductor cell structure shown in the figure includes steps S102 to S112.

[0076] Step S102 : providing a substrate 1 ; the substrate 1 comprises a plurality of unit regions 10 spaced apart along the OX direction and the OY direction; each unit region 10 comprises a source region 12 and a base region 11 arranged in sequence along the OZ direction through the first surface of the substrate 1 .

[0077] Step S104: forming a strip well region 20 with a "cross" shaped cross section between the cell regions 10 and a strip trench gate 30 between adjacent cell regions 10; the strip well region 20 penetrates the source region 12 and the base region 11 along the OZ direction; and the cross section is perpendicular to the OZ direction.

[0078] Step S106 : forming a dielectric layer 13 covering the top surface of the substrate 1 ; the dielectric layer 13 includes a plurality of contact holes 40 , and the contact holes 40 are arranged one-to-one with the cell regions 10 .

[0079] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 3At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0080] Next, combine Figures 4 to 9 Describe an exemplary method for preparing a cellular structure according to the present application, Figures 4 to 9 The present invention shows a step-by-step stereoscopic view and a cross-sectional view of a cellular structure prepared according to the preparation method of the present application.

[0081] See also Figure 4 , Figure 4 Figure a is a partial stereoscopic view of the cell structure obtained in step S102, Figure b is a side view of the partial structure, and Figure c is a top view of the partial structure. In the extension step of step S102, conventional process steps such as growth masking, photolithography, dry etching, and implantation are performed on substrate 1. P-type ions are sequentially used to implant base region 11, and N-type ions are used to implant source region 12.

[0082] The depth of the base region 11 can be designed to be 0.5 μm to 0.8 μm, for example, 0.5 μm, 0.6 μm, 0.7 μm, or 0.8 μm; the depth of the source region 12 can be designed to be 0.1 μm to 0.4 μm, for example, 0.1 μm, 0.2 μm, 0.3 μm, or 0.4 μm. Of course, the specific implantation depth can be determined according to the channel length and design.

[0083] In the embodiment mentioned in this application, the substrate 1 material includes silicon carbide (SiC).

[0084] See also Figure 5-Figure 6 In some embodiments, step S104 further includes:

[0085] See also Figure 5 Step S202: performing an ion implantation process on the substrate 1 to form a plurality of first ion implantation regions 201 spaced apart along the OY direction and extending along the OX direction, and a plurality of second ion implantation regions 202 spaced apart along the OX direction and extending along the OY direction.

[0086] For example, the mask is grown, and the lithography, etching and implantation steps are performed to complete the first ion implantation area 201 and the second ion implantation area 202, and the structure is obtained as shown below. Figure 5 As shown. Among them, Figure 5 (1) is a three-dimensional schematic diagram of the cell structure. Figure 5 (2) Figures a-c show the Figure 5(1) The exemplary cross section taken along lines A-A', B-B' and CC' is shown in Figure d. Figure 5 (1) Top view of the structure shown.

[0087] For example, P-type ion implantation is used to form the first ion implantation region 201 and the second ion implantation region 202. The doping concentration is greater than the implantation concentration of the base region 11 and the depth is deeper, greater than 0.8 μm. The widths of the first ion implantation region 201 and the second ion implantation region 202 can be optimized based on simulation or actual wafer reliability results to achieve a balance between performance and reliability.

[0088] Step S204 (not shown): After the above implantation is completed, a strip trench is formed between adjacent cell regions 10 and passes through the source region 12 and the base region 11 along the OZ direction; the remaining first ion implantation region 201 and the second ion implantation region 202 constitute a strip well region 20, and the depth of the strip trench is no greater than the depth of the strip well region 20.

[0089] See also Figure 6 Step S206: After forming a gate oxide layer 31 covering the top surface of the substrate 1 and the inner surface of the strip trench, a gate conductive layer 32 is formed in the strip trench.

[0090] The gate oxide layer 31 may be formed by using either an oxidation process or a deposition process; the material of the gate conductive layer 32 includes doped polysilicon.

[0091] For example, in this embodiment, after the strip trench is formed, the gate oxide growth process is continued, and polysilicon filling and back etching are performed on the gate oxide to obtain the following Figure 6 The structure shown, Figure 6 (2) Figures a and b show the Figure 6 (1) An exemplary cross section taken along line AA' and line BB', Figure c is Figure 6 (1) Top view of the structure shown.

[0092] See also Figure 7 In the extension step of step S106, the following steps are included: after forming a dielectric material layer on the top surface of the gate conductive layer 32 and the top surface of the gate oxide layer 31, a portion of the dielectric material layer is removed to form a contact hole 40, and the remaining dielectric material layer is used to form the dielectric layer 13; the contact hole 40 penetrates the dielectric layer 13 along the OZ direction, and the geometric center of the strip well region 20 is located within the orthographic projection of the contact hole 40 on the top surface of the cell region 10.

[0093] For example, any deposition method can be used to deposit the dielectric layer, and at the same time, the source and gate contact holes 40 can be opened by dry etching respectively; nickel sputtering is then performed, and two annealings are performed continuously to convert the nickel silicide in the contact hole 40 into a low-resistance nickel silicide, so as to obtain the following: Figure 7 The structure shown, Figure 7 (2) Figures a and b show the Figure 7 (1) An exemplary cross section taken along line AA' and line BB', Figure c is Figure 7 (1) Top view of the structure shown.

[0094] In the above embodiment, the preparation method provided by the present application does not change the original process sequence of preparing block P+ shielding injection, is compatible with traditional processes, and simultaneously performs mask deposition, photolithography, dry etching, ion implantation and other process steps, which greatly simplifies the process flow compared to the related scheme of injecting the shielding area into the bottom; grounding can be achieved through connection with the original block P+ shielding injection, avoiding the etching and metal backfilling steps of the polysilicon gate in the related scheme, and reducing the difficulty of process implementation.

[0095] In some embodiments, the preparation method further comprises:

[0096] See also Figure 8 Step S302: forming a front metal layer 14 on the top surface of the dielectric layer 13 and in the contact hole 40. The front metal layer 14 extends along the OZ direction to the top surface of the substrate 1 and contacts the low-resistance nickel silicide. Figure 8 (2) Figures a and b show the Figure 8 (1) An exemplary cross section taken along line AA' and line BB', Figure c is Figure 8 (1) is a top view of the transparent top front metal layer of the structure shown in Figure d. Figure 8 (1) Top view of the non-transparent top front metal layer of the structure shown.

[0097] For example, the material of the front metal layer 14 includes, but is not limited to, aluminum (Al), copper (Au), or a combination thereof.

[0098] See also Figure 9 Step S304: Deposit a passivation layer 15 and a protective layer 16. Apply and bake polyimide, completing the front-side process. Then, perform back-side thinning, sputter nickel to form an ohmic contact, and finally perform back-side metal evaporation to form a back-side metal layer 17 and a drain electrode, completing the back-side process.

[0099] By way of example, the material of the passivation layer 15 includes, but is not limited to, silicon nitride (SiN).

[0100] For example, the protection layer 16 is formed by coating and baking, and the material includes: polyimide.

[0101] As an example, the material of the back metal layer 17 includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag).

[0102] In some embodiments, the present application further provides a semiconductor device comprising a cellular structure as described in any of the above embodiments, or a cellular structure prepared using the preparation method described in any of the above embodiments. Since the semiconductor devices of the above embodiments and the cellular structure provided by the present invention are based on the same inventive concept, the semiconductor device using this cellular structure has all the advantages of the cellular structure and preparation method provided by the present invention, and no further description is given here.

[0103] In the above embodiments, the unexpected technical effects of the present application are:

[0104] By designing the cell area into a grid distribution and introducing a cross-shaped strip well area as a shielding area, compared with the traditional block shielding area, the protection range of the depletion layer to the bottom gate oxide during reverse cutoff is optimized, and the gate oxide protection effect is significantly enhanced; compared with a single strip distribution structure, the grid trench design effectively improves the channel density and greatly improves the conduction performance.

[0105] In terms of preparation technology, the method of forming the cross-shaped strip well region is seamlessly connected with the original mesh shielding area injection process, avoiding the problem of increased on-resistance caused by the JFET effect introduced by the addition of a shielding area at the bottom of the trench gate. At the same time, it eliminates complex processes such as polysilicon gate etching and metal backfilling, effectively reducing process complexity while improving device performance, achieving a dual breakthrough in performance optimization and process simplification.

[0106] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device cell structure, characterized in that: include: Substrate; the top surface of the substrate includes a dielectric layer; The substrate includes a plurality of cell regions spaced apart along a first direction and a second direction, and strip-shaped trench gates located between adjacent cell regions; each cell region includes a base region, a source region, and a strip-shaped well region having a "cross"-shaped cross section, which are sequentially arranged along a third direction toward the substrate and through the first surface of the substrate; the cross section is perpendicular to the third direction; The strip-shaped well regions penetrate the base region and the source region along the third direction; adjacent strip-shaped well regions are aligned; The dielectric layer includes a plurality of contact holes, and the contact holes are arranged one-to-one with the cell areas.

2. The cellular structure according to claim 1, characterized in that The strip-shaped well region penetrates the cell region along the first direction and along the second direction.

3. The cellular structure according to claim 2, characterized in that The strip trench gate penetrates the source region and the base region along the third direction; The depth of the strip-shaped trench gate is not greater than the depth of the strip-shaped well region; The width of the strip-shaped trench gate is not less than the distance between adjacent unit areas; The width is used to characterize the size along the first direction, and the depth is used to characterize the size along the third direction.

4. The cellular structure according to claim 1, wherein: The contact holes are arranged one-to-one with the cell areas, including: The contact hole penetrates the dielectric layer along the third direction; The orthographic projection of the contact hole on the top surface of the cell region is located within the top surface of the cell region.

5. The cellular structure according to claim 4, characterized in that The geometric center of the strip-shaped well region is located within the orthographic projection of the contact hole on the top surface of the cell region.

6. The cellular structure according to any one of claims 1 to 5, characterized in that Also includes: a gate conductive layer, located in the strip-shaped trench gate, with a top surface flush with a top surface of the substrate; a gate oxide layer, located between the dielectric layer and the substrate, and between the gate conductive layer and the substrate; The front metal layer is located on the top surface of the dielectric layer and in the contact hole, and extends along the third direction to the top surface of the substrate.

7. A method for preparing a semiconductor device cell structure, characterized in that: For preparing the cellular structure according to any one of claims 1 to 6, comprising: Providing a substrate; the substrate comprising a plurality of unit regions spaced apart along a first direction and a second direction; each unit region comprising a source region and a base region sequentially arranged along a third direction away from the substrate and passing through the first surface of the substrate; forming a strip-shaped well region with a "cross"-shaped cross section between the unit regions, and a strip-shaped trench gate located between adjacent unit regions; the strip-shaped well region penetrates the source region and the base region along the third direction; and the cross section is perpendicular to the third direction; A dielectric layer covering the top surface of the substrate is formed; the dielectric layer includes a plurality of contact holes, and the contact holes are arranged one-to-one with the cell areas.

8. The preparation method according to claim 7, characterized in that Forming the strip-shaped well region includes: Performing an ion implantation process on the substrate to form a plurality of first ion implantation regions spaced apart along the first direction and extending along the second direction, and a plurality of second ion implantation regions spaced apart along the second direction and extending along the first direction; forming the strip-shaped trench located between adjacent cell regions and penetrating the source region and the base region along the third direction; the remaining first ion implantation region and the second ion implantation region constitute the strip-shaped well region, and the depth of the strip-shaped trench is no greater than the depth of the strip-shaped well region; The depth is used to represent the size along the third direction.

9. The preparation method according to claim 8, characterized in that Forming the dielectric layer includes: After forming a gate oxide layer covering the top surface of the substrate and the inner surface of the strip-shaped trench, forming a gate conductive layer in the strip-shaped trench; After forming a dielectric material layer on the top surface of the gate conductive layer and the top surface of the gate oxide layer, part of the dielectric material layer is removed to form a contact hole, and the remaining dielectric material layer is used to constitute the dielectric layer; the contact hole penetrates the dielectric layer along the third direction, and the geometric center of the strip-shaped well region is located within the orthographic projection of the contact hole on the top surface of the cell area.

10. A semiconductor device, characterized in that: include: The cellular structure according to any one of claims 1 to 6; or A cellular structure prepared by the preparation method according to any one of claims 7 to 9.

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