Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device capable of reducing gate resistance and a method for manufacturing the same. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first and second electrodes and includes first to third semiconductor regions. A plurality of third electrodes are provided side by side in the cell region where the second electrodes are provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on top of the semiconductor layer. The wiring is provided in the cell region within the first insulating layer, extends above and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor device including a transistor such as a power MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor), by reducing the gate resistance of the transistor, for example, the switching speed can be improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of reducing gate resistance and a method for manufacturing the same.

Means for Solving the Problems

[0005] According to embodiments of the present invention, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer, a plurality of third electrodes, a fourth electrode, a first insulating layer, and wiring. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of a first conductivity type provided on the second semiconductor region and electrically connected to the second electrode. The plurality of third electrodes are provided side by side in a cell region where the second electrode is provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating portion. The first insulating layer is provided on the semiconductor layer. The wiring is provided within the first insulating layer in the cell region, extends over and along the fourth electrode, is thinner than the fourth electrode, and is electrically connected to the fourth electrode. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 4] Figure 4 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 5] Figure 5 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 6] Figure 6 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 7] Figure 7 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 8] Figure 8 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 9]FIG. 9 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 10] FIGS. 10(a) and 10(b) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. [Figure 11] FIGS. 11(a) and 11(b) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. [Figure 12] FIGS. 12(a) and 12(b) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. [Figure 13] FIG. 13 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 14] FIG. 14 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 15] FIG. 15 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 16] FIG. 16 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 17] FIG. 17 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 18] FIG. 18 is a schematic diagram illustrating a semiconductor device according to a modified example of the embodiment. [Figure 19] FIGS. 19(a) and 19(b) are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to a modified example. [Figure 20] FIG. 20 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 22] FIG. 22 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 23] FIG. 23 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 25]FIG. 25 is a schematic diagram illustrating another semiconductor device according to an embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same reference numerals are assigned to the same elements as those described above with respect to the previously shown figures, and the detailed description will be omitted as appropriate. In the following description, n

[0009] , , , ,

[0008] , , n - notation represents the relative level of each impurity concentration. That is, the notation with “+” has a relatively higher impurity concentration than the notation without either “+” or “-”, and the notation with “-” has a relatively lower impurity concentration than the notation without either. These notations represent the relative level of the net impurity concentration after the impurities compensate each other when both p-type impurities and n-type impurities are included in each region. In the following examples, the first conductivity type is n-type and the second conductivity type is p-type. However, for each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. In the description of the embodiment, the X direction, Y direction, and Z direction that are perpendicular to each other are used. For example, as shown in FIG. 1, when viewed from above (when viewed along the Z direction), the semiconductor device 100 according to the embodiment is rectangular with sides extending in the X direction and Y direction.

[0009] The semiconductor device 100 is, for example, a MOSFET. A source electrode 12, a gate pad 13, and gate wiring 14 are provided on the upper surface of the semiconductor device 100. The source electrode 12, gate pad 13, and gate wiring 14 are arranged, for example, in the same XY plane.

[0010] The semiconductor device 100 has a cell region RC where the source electrode 12 is located, and a peripheral region RE located around the cell region RC in the XY plane. As will be described later, the cell region RC is the region in the semiconductor layer where the transistor is formed. The source electrode 12 extends in the XY plane and covers the entire cell region RC. The gate pad 13 and gate wiring 14 are not located in the cell region RC. The source electrode 12 is insulated from the gate pad 13 and gate wiring 14.

[0011] The peripheral region RE aligns with the cell region RC in the XY plane. The peripheral region RE may include, for example, the termination region of the semiconductor device 100. The termination region includes the outer edge of the semiconductor layer in a plan view and is the region along that outer edge. The gate wiring 14 and gate pad 13 are located in the peripheral region RE and may surround, for example, the source electrode 12. The gate wiring 14 extends in the X or Y direction and is electrically connected to the gate pad 13. In this example, the gate pad 13 is located at the rectangular corner of the semiconductor device 100. The source electrode 12 is not located in the peripheral region RE.

[0012] Figures 2 to 5 are schematic diagrams illustrating semiconductor devices according to the embodiment. Figures 2 to 5 show the structure within cell region RC (region R1 shown in Figure 1). Figures 2 and 3 show the planar layout. The hatching in Figure 2 corresponds to the cross-section along line A1-A1' shown in Figure 4, and the hatching in Figure 3 corresponds to the cross-section along line A2-A2' shown in Figure 4. Figure 4 shows the cross-section along line A3-A3' shown in Figures 2 and 3. Figure 5 shows the cross-section along line A4-A4' shown in Figures 2 and 3.

[0013] For example, as shown in Figure 4, the semiconductor device 100 has a drain electrode 11 (first electrode), a source electrode 12 (second electrode), and a semiconductor layer 20. The semiconductor layer 20 is located between the drain electrode 11 and the source electrode 12.

[0014] In the description of the embodiment, the direction from the drain electrode 11 to the source electrode 12 is referred to as the Z direction (first direction). The upper and lower surfaces of the semiconductor layer 20 (semiconductor substrate) are aligned with the XY plane perpendicular to the Z direction. For convenience, the direction from the drain electrode 11 to the source electrode 12 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the drain electrode 11 and the source electrode 12 and are independent of the direction of gravity.

[0015] The semiconductor layer 20 includes a drain region 24, a drift region 21 (first semiconductor region), a base region 22 (second semiconductor region), and a source region 23 (third semiconductor region). The drain region 24 is the first conductivity type (n + This is a semiconductor region of the shape ( ). The drain region 24 is provided on the drain electrode 11 and is electrically connected to the drain electrode 11. The drift region 21 is provided above the drain region 24 and has a first conductivity type (n - This is the semiconductor region of the n-type impurity. The concentration of n-type impurity in the drift region 21 is (atoms / cm³). 3 ) is the concentration of n-type impurities in the drain region 24 (atoms / cm³). 3 It is lower than ). The base region 22 is a second conductivity type (p-type) semiconductor region located on a portion of the drift region 21. The source region 23 is provided on a part of the base region 22 and has a first conductive type (n + This is a semiconductor region of n-type impurities. The upper end of the source region 23 is located on the upper surface 20U of the semiconductor layer 20 (the surface on the source electrode 12 side). The concentration of n-type impurities in the source region 23 is (atoms / cm³). 3 ) is higher than the concentration of n-type impurities in the drift region 21. For example, the drift region 21 and the drain region 24 are provided across the cell region RC and the peripheral region RE, while the base region 22 and the source region 23 are provided in the cell region RC.

[0016] For example, as shown in Figure 4, the upper surface 20U of the semiconductor layer 20 is provided with a plurality of FP trenches TR1 (first trenches) and gate trenches TR2 (second trenches).

[0017] The FP trench TR1 extends in the Z direction from the upper surface 20U to the drift region 21. An FP insulating portion 41 (first insulating portion) and an FP electrode 31 (third electrode) are provided inside the FP trench TR1. The FP insulating portion 41 covers the inner wall (side and bottom surface) of the FP trench TR1. The FP insulating portion 41 is in contact with the drift region 21 and the base region 22.

[0018] The FP electrode 31 is a field plate. The FP electrode 31 is located inside the FP insulating portion 41 within the FP trench TR1. In other words, the FP insulating portion 41 is provided between the FP electrode 31 and the semiconductor layer 20. The lower surface and side surfaces of the FP electrode 31 are in contact with the FP insulating portion 41. The FP electrode 31 is insulated from the semiconductor layer 20 by the FP insulating portion 41. The FP electrode 31 has a portion that aligns with a part of the drift region 21 in the direction of the XY plane. That is, the FP electrode 31 faces a part of the drift region 21 via the FP insulating portion 41.

[0019] The gate trench TR2 includes a portion located between two adjacent FP trenches TR1 (the closest FP trenches TR1 to each other among multiple FP trenches TR1). In the Z direction, the gate trench TR2 extends from the upper surface 20U of the semiconductor layer 20 to the drift region 21. The gate trench TR2 is shallower than the FP trenches TR1.

[0020] A gate insulator 42 (second insulator) and a gate electrode 32 (fourth electrode) are provided inside the gate trench TR2. The gate insulator 42 covers the inner wall (side and bottom) of the gate trench TR2. The gate insulator 42 is in contact with the drift region 21, the base region 22, and the source region 23.

[0021] The gate electrode 32 is located inside the gate insulator 42 within the gate trench TR2. In other words, the gate insulator 42 is provided between the gate electrode 32 and the semiconductor layer 20. The lower and side surfaces of the gate electrode 32 are in contact with the gate insulator 42. The gate electrode 32 is insulated from the semiconductor layer 20 by the gate insulator 42. In the direction of the XY plane, the gate electrode 32 has portions that align with a part of the drift region 21, a base region 22, and a part of the source region 23. That is, the gate electrode 32 faces the drift region 21, the base region 22, and the source region 23 via the gate insulator 42. The FP electrode 31 extends to a deeper position than the gate electrode 32.

[0022] Furthermore, as shown in Figure 4, for example, an insulating layer 51 (first insulating layer) extending along the XY plane is provided on the upper surface 20U of the semiconductor layer 20. The insulating layer 51 is provided in contact with the upper surface 20U, the upper surface of the FP insulating portion 41, and the upper surface of the gate insulating portion 42. In this example, the insulating layer 51 has a first layer 51a and a second layer 51b laminated on the first layer 51a. However, the insulating layer 51 may consist of three or more layers laminated together, or it may consist of a single layer.

[0023] Within the cell region RC, a gate wiring 70 electrically connected to the gate electrode 32 is provided within the insulating layer 51. The gate wiring 70 is located directly above the gate trench TR2 and the gate electrode 32. The gate wiring 70 extends in the Z direction and penetrates the insulating layer 51. In other words, the gate wiring 70 is embedded in a slit (trench) that penetrates the insulating layer 51 in the Z direction. The lower end of the gate wiring 70 is in contact with the upper surface of the gate electrode 32.

[0024] An insulating layer 80 (second insulating layer) is provided on top of the gate wiring 70, covering the upper end of the gate wiring 70. In this example, the insulating layer 80 is positioned to be in contact with the upper end of the gate wiring 70 and the upper surface of the insulating layer 51. That is, the insulating layer 80 is formed to protrude upward from the upper surface of the insulating layer 51. The source electrode 12 is provided to be in contact with the insulating layer 51 and the insulating layer 80. The source electrode 12 is in contact with the side and top surfaces of the insulating layer 80. The source electrode 12 is insulated from the gate wiring 70 by the insulating layer 80. The thickness (length in the Z direction) of the insulating layer 80 may be less than the thickness of the insulating layer 51. A thinner insulating layer 80 can improve the flatness of the source electrode 12.

[0025] A source contact 38 (second contact) is provided above the base region 22 and the FP insulating portion 41. The source contact 38 extends in the Z direction and penetrates the insulating layer 51. In other words, the source contact 38 is provided within a slit that penetrates the insulating layer 51. The source contact 38 is in contact with the lower surface of the source electrode 12 and the source region 23 (and base region 22). As a result, the source contact 38 electrically connects the source electrode 12 and the source region 23. The source contact 38 may be separated from the FP electrode 31. In this example, a portion of the source contact 38 is above the FP insulating portion 41. This ensures that the width of the source contact 38 can be secured even when the trenches are densely arranged.

[0026] An FP contact 36 (first contact) is provided above the center of the FP electrode 31. The FP contact 36 extends in the Z direction and penetrates the insulating layer 51. In other words, the FP contact 36 is provided within a contact hole that penetrates the insulating layer 51. The FP contact 36 is in contact with the lower surface of the source electrode 12 and the FP electrode 31. As a result, the FP contact 36 electrically connects the source electrode 12 and the FP electrode 31.

[0027] In this example, the height of the upper end of the gate wiring 70 (position in the Z direction) is the same as the height of the upper end of the FP contact 36 and the same as the height of the upper end of the source contact 38. The height of the upper end of the gate wiring 70 may also be the same as the height of the upper surface of the insulating layer 51. That is, for example, the upper end of the gate wiring 70, the upper end of the FP contact 36, the upper end of the source contact 38, and the upper surface of the insulating layer 51 are all on the same plane. Also, the height of the lower end of the gate wiring 70 may be the same as the height of the lower end of the FP contact 36 and the same as the height of the lower end of the source contact 38.

[0028] Furthermore, as shown in Figure 3, the source region 23 (and a part of the base region 22) surrounds the outer circumference of the lower end portion 38a of the source contact 38 in the XY plane and is in contact with the outer surface of the lower end portion 38a. The lower end portion 38a of the source contact 38 surrounds the outer circumference of the upper end portion 41a of the FP insulating portion 41 in the XY plane and is in contact with the outer surface of the upper end portion 41a. The upper end portion 41a surrounds the outer circumference of the FP electrode 31.

[0029] In Figure 2, the positions of the FP contact 36, FP electrode 31, FP insulating portion 41, FP trench TR1, source contact 38, gate trench TR2, and gate wiring 70 are shown by dotted lines in a plan view from above. For example, as shown in Figure 2, in the cell region RC, multiple FP trenches TR1 are arranged in the XY plane. More specifically, the multiple FP trenches TR1 are arranged in a first alignment direction D1 and a second alignment direction D2. The first alignment direction D1 is the direction that connects one FP trench TR1 to the FP trench TR1 closest to it by the shortest distance. In a plan view, the multiple FP electrodes 31 (FP trenches TR1) are located at the grid-like or mesh-like intersections where lines extending in the first alignment direction D1 and lines extending in the second alignment direction D2 intersect. In this example, the first alignment direction D1 is the X direction, and the second alignment direction D2 is the Y direction. Therefore, in a plan view, the multiple FP electrodes 31 are located at the vertices of a square. In this embodiment, the first array direction D1 and the second array direction D2 do not necessarily have to be orthogonal.

[0030] For example, the planar shape of the FP electrode 31 and the FP insulating part 41 is circular. The planar shape of the FP electrode 31 and the FP insulating part 41 may also be a regular polygon such as a square or a regular hexagon. Note that a regular polygon includes a regular polygon with rounded corners. An FP electrode 31 is provided in the center of each FP trench TR1. The FP contact 36 is cylindrical and located in the center of the FP electrode 31.

[0031] As shown in Figure 3, in the cell region RC, the gate trench TR2 has a first extension portion 61, a second extension portion 62, and an intersection portion 65. The first extension portion 61 is located between two adjacent FP trenches TR1 in the first array direction D1 and extends in a direction perpendicular to the first array direction D1. The first extension portion 61 has, for example, a constant width W61 (length in the direction perpendicular to the first array direction D1). The second extension portion 62 is located between two adjacent FP trenches TR1 in the second array direction D2 and extends in a direction perpendicular to the second array direction D2. The second extension portion 62 has, for example, a constant width W62 (length in the direction perpendicular to the second array direction D2). The width W62 may be the same as the width W61.

[0032] The intersection 65 is the point where the first extending portion 61 and the second extending portion 62 intersect. In other words, the intersection 65 connects the end of the first extending portion 61 and the end of the second extending portion 62. For example, the planar shape of the gate trench TR2 is mesh-like. In this example, the gate trench TR2 is a grid where a portion extending in the first alignment direction D1 and a portion extending in the second alignment direction D2 intersect at the intersection 65. That is, an intersection 65 is located at each vertex of the square, and two first extending portions 61 and two second extending portions 62 are located on the four sides of the square. Inside the square, one FP trench TR1 is arranged, and the FP electrode 31 is located at the center of the square.

[0033] For example, the width W65 of the intersection 65 (length in the direction perpendicular to the first arrangement direction D1) is wider than the width W61 of the first extension 61. The width W65 of the intersection 65 is wider than the width W62 of the second extension 62. The width of the intersection 65 in the second arrangement direction D2 may be the same as the width W65 in the first arrangement direction D1.

[0034] For example, the width of the intersection 65 gradually widens continuously from the first extension 61 or the second extension 62. Therefore, the planar shape of the region enclosed by the first extension 61, the second extension 62, and the intersection 65 is a polygon with rounded corners (a square in this example). However, in this embodiment, the width W65 of the intersection 65 may be the same as the width W61 of the first extension 61.

[0035] In a plan view, the thickness of the gate insulating portion 42 within the gate trench TR2 may be substantially constant. The gate electrode 32 includes an extending portion (first extending portion) provided within the first extending portion 61 and extending similarly to the first extending portion 61, an extending portion (second extending portion) provided within the second extending portion 62 and extending similarly to the second extending portion 62, and a portion provided within the intersection portion 65. The gate electrode 32, like the gate trench TR2, is mesh-like or grid-like. The width of the gate electrode 32 within the intersection portion 65 may be wider than the width of the gate electrode 32 within the first extending portion 61 or the second extending portion 62. By making the gate trench TR2 and the gate electrode 32 inside it mesh-like or grid-like, a large area for operation as a transistor can be secured.

[0036] The gate wiring 70 extends over and along the gate electrode 32. For example, the planar shape of the gate wiring 70 (the planar shape of the contact surface between the gate wiring 70 and the gate electrode 32) is mesh-like or grid-like, similar to the planar shape of the gate electrode 32. In plan view, the entire gate wiring 70 may overlap with the gate trench TR2 or the gate electrode 32.

[0037] More specifically, in this example, the gate wiring 70 includes a plurality of first wiring sections 71 and a plurality of second wiring sections 72. The gate wiring 70 is a grid in which the first wiring sections 71 and the second wiring sections 72 intersect each other. The first wiring section 71 extends above the first extension section 61 and along the first extension section 61. That is, the first wiring section 71 is located above the gate electrode 32 within the first extension section 61 and extends in the second arrangement direction D2. The second wiring section 72 extends above the second extension section 62 and along the second extension section 62. That is, the second wiring section 72 is located above the gate electrode 32 within the second extension section 62 and extends in the first arrangement direction D1.

[0038] In a plan view, one FP electrode 31 is surrounded by a square formed by two adjacent first wiring sections 71 and two adjacent second wiring sections 72, with the FP contact 36 positioned at the center of the square.

[0039] The gate wiring 70 is narrower than the gate trench TR2. For example, as shown in Figure 3, the width W71 of the first wiring section 71 (length in the direction perpendicular to the first arrangement direction D1) is narrower than the width W61 of the first extension section 61. For example, the width W72 of the second wiring section 72 (length in the direction perpendicular to the second arrangement direction D2) is narrower than the width W62 of the second extension section 62. The width W62 may be the same as the width W61.

[0040] For example, the width of the gate wiring 70 is narrower than the width of the gate electrode 32. However, the width of the gate wiring 70 may be the same as the width of the gate electrode 32, or wider than the width of the gate electrode 32. Also, the width of the gate trench TR2 (width W61 of the first extension 61, width W62 of the second extension 62) may be narrower than the width of the FP trench TR1 (length in the first or second arrangement direction D1). Furthermore, the width of the gate electrode 32 within the first or second extension 61 may be narrower than the width of the FP electrode 31.

[0041] As shown in Figure 3, the planar shape of the region enclosed by the gate trench TR2 is a square with rounded corners, and the planar shape of the outer edge of the source contact 38 is also a square with rounded corners. That is, in a plan view, the outer edge of the source contact 38 extends along the gate trench TR2 such that the distance from the gate trench TR2 is constant. In other words, the width of the source region 23 is approximately constant. This suppresses, for example, bias in the transistor characteristics within the plane. Each source contact 38 is cylindrical, and each FP contact 36 is arranged inside the cylinder.

[0042] As shown in Figure 2, the insulating layer 80 extends along the gate wiring 70. For example, the planar shape of the insulating layer 80 is mesh-like or grid-like, similar to the planar shape of the gate wiring 70.

[0043] More specifically, in this example, the insulating layer 80 includes a plurality of first portions 81 and a plurality of second portions 82. The insulating layer 80 is arranged in a grid pattern in which the first portions 81 and the second portions 82 intersect each other. The first portion 81 extends above the first wiring portion 71 and along the first wiring portion 71, for example, in the second arrangement direction D2. The second portion 82 extends above the second wiring portion 72 and along the second wiring portion 72, for example, in the first arrangement direction D1.

[0044] The width of the insulating layer 80 is wider than the width of the gate wiring 70 and wider than the width of the gate trench TR2. For example, the width W81 (length in the direction perpendicular to the first arrangement direction D1) of the first portion 81 of the insulating layer 80 is wider than the width W71 (see Figure 3) of the first wiring portion 71 and wider than the width W61 (see Figure 3) of the first extension portion 61. The width W82 (length in the direction perpendicular to the second arrangement direction D2) of the second portion 82 of the insulating layer 80 may be the same as the width W81. In this way, the insulating layer 80 overlaps with the entire gate trench TR2 and the entire gate wiring 70 in the Z direction. This allows for more reliable insulation between the gate wiring 70 and the source electrode 12. In the plan view of Figure 2, the source contact 38 and the FP trench TR1 are arranged inside each of the square openings provided in the insulating layer 80.

[0045] Figures 6 to 9 are schematic diagrams illustrating semiconductor devices according to the embodiment. Figures 6 to 9 show the structure of the end portion (region R2 shown in Figure 1) within the cell region RC. Figures 6 and 7 show the planar layout. The hatching in Figure 6 corresponds to the cross section along the line A5-A5' shown in Figures 8 and 9, and the hatching in Figure 7 corresponds to the cross section along the line A6-A6' shown in Figures 8 and 9. Figure 8 shows the cross section along the line A7-A7' shown in Figures 6 and 7. Figure 9 shows the cross section along the line A8-A8' shown in Figures 6 and 7.

[0046] For example, the entire gate trench TR2 is located within the cell region RC and not outside the cell region RC. As shown in Figures 6 and 7, the end e1 of the gate trench TR2 and the end 70p of the gate wiring 70 are located within the cell region RC.

[0047] The semiconductor device 100 has a lead wire 85 that is electrically connected to the gate wiring 70. In the cell region RC, the end 85p of the lead wire 85 is connected to the end 70p of the gate wiring 70. The lead wire 85 extends from the end 85p that is in contact with the gate wiring 70 to the outside of the cell region RC, i.e., the peripheral region RE (see Figure 1).

[0048] Thus, a portion of the lead wiring 85 is located in the cell region RC on the peripheral region RE side of the gate trench TR2 and gate wiring 70, and extends toward the peripheral region RE. In the peripheral region RE, the lead wiring 85 is electrically connected to the gate wiring 14 (see Figure 1) located above the lead wiring 85. In other words, the lead wiring 85 electrically connects the gate wiring 70 and the gate wiring 14. The lead wiring 85 allows the gate wiring 70 to be led out into the peripheral region RE.

[0049] In the examples shown in Figures 6 and 7, end 70p is the end in the X direction of the gate wiring 70 (second wiring section 72) extending in the X direction, and end 85p is the end in the X direction of the lead wiring 85 extending in the X direction. Multiple lead wirings 85 are connected to multiple second wiring sections 72. Although not shown, lead wirings 85 extending in the Y direction may be provided from the end in the Y direction of the gate wiring 70 (first wiring section 71).

[0050] For example, as shown in Figure 6, the width W85 of the lead wire 85 may be wider than the width of the gate wire 70 (width W72 of the second wiring section 72). A wider width W85 of the lead wire 85 can reduce gate resistance.

[0051] In a plan view, within the cell region RC, FP electrodes 31 are provided even between two adjacent lead wires 85. Between two adjacent lead wires 85, no source contacts 38 are provided, and as shown in Figure 6, an insulating layer 80 is positioned above a portion of the FP insulating portion 41.

[0052] As shown in Figure 9, the lead wire 85 is provided on top of the insulating layer 51. The end 85p of the lead wire 85 is provided on top of the end 70p of the gate wire 70. In other words, in this example, the lead wire 85 is located above the entire gate wire 70. For example, the length (thickness) of the gate wire 70 in the Z direction is longer than the length of the lead wire 85 in the Z direction.

[0053] An insulating layer 80 is provided on top of the lead wiring 85. The insulating layer 80 is in contact with the top and sides of the lead wiring 85, covering them. The insulating layer 80 is located between the source electrode 12 and the lead wiring 85. As a result, the source electrode 12 and the lead wiring 85 are insulated from each other.

[0054] Furthermore, the lead wire 85 may be made of the same material as the gate wire 70 and formed integrally with the gate wire 70. In other words, the gate wire 70 may be a part of one conductive part, and the lead wire 85 may be another part of that conductive part.

[0055] An example of the materials used for each element of the semiconductor device 100 will be described below. Each semiconductor region of the semiconductor layer 20 contains silicon (Si), silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The semiconductor layer 20 is a semiconductor substrate, such as a silicon substrate. The FP electrode 31 and the gate electrode 32 include a conductive material such as polysilicon or metal. The FP insulating portion 41, the gate insulating portion 42, the insulating layer 51, and the insulating layer 80 each contain an insulating material such as silicon oxide or silicon nitride. The drain electrode 11, source electrode 12, gate wiring 14, and gate pad 13 contain a metal such as Al (aluminum). The gate wiring 70, source contact 38, and FP contact 36 each contain at least one of silicide and a metallic material. The silicide contains at least one selected from the group consisting of Co (cobalt), W (tungsten), Ti (titanium), and Ni (nickel). As the silicide, metallic silicides such as CoSi, WSi, TiSi, and NiSi are used. The metallic material contains at least one selected from the group consisting of Ti, TiN (titanium nitride), W, Cu (copper), and Al. By using a metallic material, a conductive part with lower resistance can be obtained. For example, the electrical resistivity of the gate wiring 70, source contact 38, or FP contact 36 may be lower than the electrical resistivity of the gate electrode 32 or FP electrode 31. By using silicide, the formation of the conductive part becomes easier. The material of the source contact 38 and the material of the FP contact 36 may be the same as the material of the gate wiring 70.

[0056] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the source electrode 12 and the drain electrode 11, a positive voltage is applied to the gate pad 13. This causes the gate wiring 14 to run from the gate pad 13. A voltage is applied to the gate electrode 32 via the lead wiring 85 and the gate wiring 70. When a voltage greater than the threshold is applied to the gate electrode 32, an inversion layer is formed in the base region 22, and the transistor turns on. That is, an on-current flows from the drain electrode 11 to the source electrode 12 through the drift region 21, the base region 22, the source region 23, and the source contact 38. When the voltage at the gate pad 13 becomes low and the voltage at the gate electrode 32 falls below the threshold, the transistor turns off and no on-current flows.

[0057] As described above, in the semiconductor device 100 according to this embodiment, gate wiring 70 is provided within the insulating layer 51 in the cell region RC. The gate wiring 70 extends along the gate electrode 32 and is electrically connected to the gate electrode 32. By providing the gate wiring 70, the gate resistance in the semiconductor device 100 can be reduced.

[0058] For example, in the reference example semiconductor device, a configuration is conceivable in which the gate wiring 70 is not provided within the cell region RC, and the gate wiring 14 and the gate electrode 32 are connected in the peripheral region RE. In contrast, in the embodiment, by providing the gate wiring 70, for example, the current within the cell region RC flows through a path in which the gate wiring 70 and the gate electrode 32 are connected in parallel. Therefore, according to the embodiment, the gate resistance can be reduced compared to the reference example.

[0059] Furthermore, in the example, one possible method to reduce gate resistance is to improve the chip layout design and increase the number of gate traces 14. However, increasing the number of gate traces 14 reduces the effective device area for the same chip size, thus worsening area efficiency. Another possible method to reduce gate resistance is to use a metal gate, where the gate electrode is formed from a metal material. However, in the case of a metal gate, there is a risk that characteristics such as withstand voltage, leakage current, and defect density may deteriorate due to damage to the gate insulating film during the manufacturing process. In addition, the manufacturing process for metal gates can be complex.

[0060] In contrast, in this embodiment, the gate resistance can be reduced by providing the gate wiring 70, as described above. For example, by using polysilicon as the material for the gate electrode 32 and providing the gate wiring 70, the gate resistance can be reduced while avoiding the degradation of characteristics and the complexity of the manufacturing process caused by a metal gate. However, in this embodiment, it is also possible to use a metal material for the gate electrode 32.

[0061] Furthermore, widening the gate electrode 32 reduces the gate resistance. However, widening the gate electrode 32 can increase capacitance between the gate electrode 32 and the drain electrode 11, which can increase the feedback capacitance of the transistor. For example, in a structure where the gate electrode 32 and the FP electrode 31 are located in separate trenches, the feedback capacitance tends to increase more easily when the gate electrode 32 is widened compared to a configuration where the gate electrode 32 and the FP electrode 31 are located in the same trench. In contrast, in a configuration where the gate electrode 32 and the FP electrode 31 are located in separate trenches, providing gate wiring 70 can reduce the gate resistance while suppressing the increase in feedback capacitance.

[0062] Furthermore, the gate wiring 70 is thinner than the gate trench TR2. The thinness of the gate wiring 70 allows for a sufficient distance between the gate wiring 70 and the source region 23. Therefore, for example, providing the gate wiring 70 can suppress the occurrence of defects in the insulating layer or semiconductor layer, which would otherwise degrade the transistor's characteristics.

[0063] For example, the length (thickness) of the gate wiring 70 in the Z direction is longer than the width of the gate wiring 70 (width W71 or width W72 as explained in Figure 3) and longer than the length of the insulating layer 80 in the Z direction. By making the gate wiring 70 thicker, the gate resistance can be further reduced while making the gate wiring 70 thinner. Also, as shown in Figure 4, for example, the width of the gate wiring 70 may be narrower than the width W36 (diameter) of the FP contact 36 or the width W38 of the source contact 38.

[0064] An insulating layer 80 is provided on top of the gate wiring 70, and the source electrode 12 is provided on top of the insulating layer 80. By providing the gate wiring 70 and the source electrode 12 on separate layers in this way, the gate wiring 70 can be arranged to extend more widely within the cell region RC. For example, as described above, the gate wiring 70 is in a grid shape in which a first wiring section 71 and a second wiring section 72 intersect along the gate trench TR2 and the gate electrode 32. This further reduces the gate resistance and allows the gate wiring 70 to be drawn out in two directions.

[0065] Figures 10(a) to 12(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. As shown in Figure 10(a), for example, an FP trench TR1 and a gate trench TR2 are formed on the upper surface 20U of the semiconductor layer 20 by RIE (reactive ion etching). An FP insulating portion 41 is formed in the FP trench TR1, and an FP electrode 31 is formed inside it. A gate insulating portion 42 is formed in the gate trench TR2, and a gate electrode 32 is formed inside it. Before (or after) the formation of the FP trench TR1 and gate trench TR2, a base region 22 and a source region 23 are formed by ion implantation.

[0066] Subsequently, as shown in Figure 10(b), an insulating layer 51 is formed on the semiconductor layer 20, the FP electrode 31, and the gate electrode 32. For example, a SiN layer is deposited as the first layer 51a, and then an SiO2 layer is deposited on top of it as the second layer 51b. After that, the upper surface of the insulating layer 51 is flattened by CMP (chemical mechanical polishing).

[0067] A resist is applied to the insulating layer 51 and patterned by photolithography. Using this resist as a mask, through-holes are formed in the insulating layer 51 by RIE. That is, as shown in Figure 11(a), a first through-hole 70s (slit), a second through-hole 38s, and a third through-hole 36s are simultaneously formed in the insulating layer 51.

[0068] The first through-hole 70s extends along the gate electrode 32, is narrower than the gate trench TR2, and reaches the gate electrode 32 from the upper surface 51U of the insulating layer 51. The second through-hole 38s is above the base region 22 and reaches the base region 22 from the upper surface 51U of the insulating layer 51. The third through-hole 36s is above the FP electrode 31 and reaches the FP electrode 31 from the upper surface 51U of the insulating layer 51.

[0069] Subsequently, the conductive film 33, which will become the gate wiring 70, source contact 38, and FP contact 36 as shown in Figure 11(b), is deposited on the insulating layer 51 (on the upper surface 51U, inside the first through hole 70s, inside the second through hole 38s, and inside the third through hole 36s). The conductive film 33 is, for example, a laminated film of TiN and W. Then, a portion of the conductive film 33 formed on the upper surface 51U of the insulating layer 51 is removed, for example, by RIE, to expose the upper surface 51U. As a result, as shown in Figure 11(b), a portion of the conductive film 33 remains as the gate wiring 70 inside the first through hole 70s. A portion of the conductive film 33 remains as the source contact 38 inside the second through hole 38s. A portion of the conductive film 33 remains as the FP contact 36 inside the third through hole 36s.

[0070] Although not shown in the diagram, a mask (a resist patterned by photolithography) is formed on a portion of the conductive film 33 before the RIE of the conductive film 33. As a result, the conductive film 33 remaining on the upper surface 51U of the insulating layer 51 becomes the lead wiring 85.

[0071] Subsequently, a silicon oxide layer, which will become the insulating layer 80 as shown in Figure 12(a), is deposited on top of the insulating layer 51. A portion of the silicon oxide layer on the source contact 38 and FP contact 36 is removed by photolithography and RIE. This forms the insulating layer 80 on top of the insulating layer 51 and the gate wiring 70 (and lead wiring 85).

[0072] As shown in Figure 12(b), the source electrode 12 is formed on the insulating layer 51 and the insulating layer 80, for example, by sputtering.

[0073] In this way, the first through-hole 70s (slit), the second through-hole 38s, and the third through-hole 36s can be formed simultaneously. Furthermore, by embedding the conductive film 33 in these through-holes, the gate wiring 70, source contact 38, FP contact 36, and lead wiring 85 can be formed simultaneously from the same conductive film 33. This reduces the number of steps and allows for the manufacture of semiconductor devices in a simpler manner. When using this manufacturing method, as described above, for example, the height of the upper end of the gate wiring 70 will be the same as the height of the upper end of the source contact 38 or FP contact 36.

[0074] Figures 13 to 15 are schematic diagrams illustrating a semiconductor device according to a modified embodiment. Figure 13 shows a planar layout of a modified semiconductor device, similar to Figure 3. The hatching in Figure 13 corresponds to the cross-section along line A11-A11' shown in Figures 14 and 15. Figure 14 shows the cross-section along line A9-A9' shown in Figure 13. Figure 15 shows the cross-section along line A10-A10' shown in Figure 13.

[0075] This modified example is a semiconductor device 100 described with reference to Figures 1 to 9, in which the insulating layer 80 above the gate wiring 70 is embedded within the slit of the insulating layer 51. That is, as shown in Figure 14 or 15, for example, the insulating layer 51 is located to the side of the gate wiring 70 and the insulating layer 80. In other words, the insulating layer 51 is aligned with the gate wiring 70 and the insulating layer 80 in the lateral direction (perpendicular to the Z direction). The width of the insulating layer 80 may be the same as the width of the gate wiring 70.

[0076] The height of the upper surface of the insulating layer 51 (position in the Z direction) is the same as the height of the upper surface of the insulating layer 80. The upper surfaces of the insulating layer 51 and the insulating layer 80 are flush and extend along the XY plane. The height of the upper end of the source contact 38 and the upper end of the FP contact 36 may be the same as the height of the upper surface of the insulating layer 51. The source electrode 12 is provided in contact with the insulating layer 51 and the insulating layer 80. The height of the upper end of the gate wiring 70 is lower than the height of the upper end of the source contact 38 and the upper end of the FP contact 36.

[0077] Although insulating layer 51 and insulating layer 80 are described as separate layers for convenience, this includes cases where the boundary between insulating layer 51 and insulating layer 80 is not necessarily clearly observable. In other words, insulating layer 80 may be formed as part of insulating layer 51.

[0078] Figures 16 to 18 are schematic diagrams illustrating a semiconductor device according to a modified embodiment. Figure 16 shows a planar layout of a modified semiconductor device, similar to Figure 7. The hatching in Figure 16 corresponds to the cross-section along line A14-A14' shown in Figures 17 and 18. Figure 17 shows the cross-section along line A12-A12' shown in Figure 16. Figure 18 shows the cross-section along line A13-A13' shown in Figure 16.

[0079] As shown in Figure 18, in this example, the height of the upper surface of the lead wiring 85 (position in the Z direction) is the same as the height of the upper surface of the gate wiring 70. The upper surfaces of the lead wiring 85 and the gate wiring 70 are flush and extend along the XY plane. Therefore, the upper surface of the insulating layer 80 is substantially flat.

[0080] Figures 19(a) and 19(b) are schematic cross-sectional views illustrating a modified method for manufacturing a semiconductor device. In the manufacturing of the modified semiconductor device, as in Figures 10(a) and 10(b), the semiconductor region, FP trench TR1, gate trench TR2, FP insulating portion 41, FP electrode, gate insulating portion 42, gate electrode 32, and insulating layer 51 are formed on the semiconductor layer 20.

[0081] Subsequently, as shown in Figures 11(a) and 11(b), the first through-hole 70s, the second through-hole 38s, and the third through-hole 36s are formed, and the conductive film 33 is embedded. Although not shown in the illustration, before embedding the conductive film 33, grooves (referred to as wiring grooves) that communicate with the first through-hole 70s and into which the lead wiring 85 is embedded are formed in the insulating layer 51 by photolithography or RIE. The conductive film 33 is deposited in the wiring grooves at the same time as in the first through-hole 70s, etc.

[0082] Subsequently, as shown in Figure 19(a), a resist 88 is formed on the insulating layer 51. That is, the resist 88 is patterned by photolithography so as to cover the conductive film 33 in the second through-hole 38s and the third through-hole 36s, and expose the conductive film 33 in the first through-hole 70s (and the wiring groove). Using the patterned resist 88 as a mask, a portion of the conductive film 33 in the upper part of the first through-hole 70s (and the upper part of the wiring groove) is removed by RIE. As shown in Figure 19(a), the portion of the conductive film 33 remaining in the lower part of the first through-hole 70s becomes the gate wiring 70. The portion of the conductive film 33 remaining in the lower part of the wiring groove becomes the lead wiring 85.

[0083] After removing the resist 88, an insulating layer 80 is deposited in the upper part of the first through-hole 70s (and the upper part of the wiring groove) from which the conductive film 33 was removed, and on top of the insulating layer 51. Then, the insulating layer 80 is polished by CMP to expose the FP contact 36, the source contact 38, and the upper surface 51U of the insulating layer 51. In this way, the insulating layer 80 is embedded in the upper part of the first through-hole 70s (and the upper part of the wiring groove), as shown in Figure 19(b). Subsequently, the source electrode 12 is formed on top of the insulating layer 51, the insulating layer 80, the FP contact 36, and the source contact 38 by sputtering.

[0084] As described above, in the modified examples shown in Figures 13 to 19(b), the gate resistance can be reduced by providing gate wiring 70, similar to the semiconductor layer described in Figures 1 to 12. Furthermore, in the modified examples, the insulating layer 80 is embedded in the insulating layer 51, which suppresses surface steps. This improves, for example, the uniformity of the thickness of the source electrode 12.

[0085] Figures 20 to 25 are schematic diagrams illustrating another semiconductor device according to the embodiment. Although not shown in the diagram, this semiconductor device also has a cell region RC where the source electrode 12 is provided, and a peripheral region RE where the gate wiring 14 and gate pad 13 are provided, similar to Figure 1 described above.

[0086] Figures 20 and 22 show the structure of the central part of the RC cell region. Figure 20 shows the planar layout. The hatching in Figure 20 corresponds to the cross-section along line A17-A17' shown in Figures 21 and 22. Figure 21 shows the cross-section along line A15-A15' shown in Figure 20. Figure 22 shows the cross-section along line A16-A16' shown in Figure 20.

[0087] Figures 23 to 25 show the structure of the end portion within the RC cell region. Figure 23 shows the planar layout. The hatching in Figure 23 corresponds to the cross-section along the A20-A20' line shown in Figures 24 and 25. Figure 24 shows the cross-section along the A18-A18' line shown in Figure 23. Figure 25 shows the cross-section along the A19-A19' line shown in Figure 23.

[0088] As shown in Figure 20 or Figure 23, in the cell region RC, multiple FP trenches TR1 are aligned in a first alignment direction D1 and a second alignment direction D2 in the XY plane. In this example, the first alignment direction D1 is the X direction. The second alignment direction D2 is inclined relative to the first alignment direction D1. For example, the angle between the first alignment direction D1 and the second alignment direction D2 is 60°. In this example, in a plan view, the multiple FP electrodes 31 are arranged to be located at the vertices of a triangle (e.g., an equilateral triangle).

[0089] The gate trench TR2 has a first extending portion 61, a second extending portion 62, and a third extending portion 63. The first extending portion 61 extends in the Y direction (a direction perpendicular to the first arrangement direction D1). The second extending portion 62 extends in a direction perpendicular to the second arrangement direction D2. The third extending portion 63 extends in a direction different from that of the first extending portion 61 and the second extending portion 62.

[0090] The planar shape of the gate trench TR2 is a mesh made up of hexagons (e.g., regular hexagons). That is, two first extensions 61, two second extensions 62, and two third extensions 63 are located on the six sides of the hexagon. At each vertex of the hexagon, the first extensions 61, the second extensions 62, and the third extensions 63 are connected. One FP trench TR1 is placed inside the hexagon, and the FP electrode 31 is located at the center of the hexagon. Note that the hexagon formed by the gate trench TR2 may be a hexagon with rounded corners (vertices). For example, the planar shape of the region enclosed by the first extensions 61, the second extensions 62, the third extensions 63, and their connections may be a regular hexagon with rounded corners. The gate electrode 32 is a mesh made up of repeating hexagons, similar to the gate trench TR2.

[0091] The gate wiring 70 includes a first wiring section 71, a second wiring section 72, and a third wiring section 73. The first wiring section 71 extends above and along the first extension section 61 of the gate trench TR2. The second wiring section 72 extends above and along the second extension section 62 of the gate trench TR2. The third wiring section 73 extends above and along the third extension section 63 of the gate trench TR2. In other words, the planar shape of the gate wiring 70 is a mesh of hexagons. Two first wiring sections 71, two second wiring sections 72, and two third wiring sections 73 are located along the six sides of the hexagon.

[0092] The insulating layer 80 extends over the first wiring section 71, the second wiring section 72, and the third wiring section 73, and along the first wiring section 71, the second wiring section 72, and the third wiring section 73. That is, in a plan view, the insulating layer 80 has a mesh-like portion in which hexagons are arranged, similar to the gate wiring 70.

[0093] In this way, multiple FP electrodes 31 may be arranged in a triangular shape. In this example as well, the gate resistance can be reduced by providing gate wiring 70, similar to the semiconductor device described above.

[0094] According to the embodiment, a semiconductor device capable of reducing gate resistance and a method for manufacturing the same can be provided.

[0095] In this specification, "electrically connected" includes not only cases where the connection is made by direct contact, but also cases where the connection is made via other conductive members or the like.

[0096] The relative levels of impurity concentrations between semiconductor regions can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0097] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0098] 11: Drain electrode 12: Source electrode 13: Gate Pad 14: Gate wiring 20: Semiconductor layer 20U:Top surface 21: Drift Region 22: Base area 23: Source area 24: Drain area 31:FP electrode 32: Grid gate 33: Conductive film 36: FP Contact 36s: 3rd through hole 38: Source Contact 38a: Bottom end 38s: 2nd through hole 41: FP insulation section 41a: Upper end 42: Gate insulation 51: Insulating layer 51U:Top surface 51a: 1st layer 51b: 2nd layer 61~63: 1st~3rd extension part 65: Intersection 70: Gate wiring 70p: Edge 70s: 1st through hole 71~73: 1st~3rd wiring section 80: Insulating layer 81, 82: 1st and 2nd parts 85: Output wiring 85p: Edge 88: Resist 100: Semiconductor Devices RC: Cell area RE: Peripheral Area TR1: FP Trench TR2: Gate Trench e1: end

Claims

1. First electrode and, A second electrode located above the first electrode, Provided between the first electrode and the second electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region and electrically connected to the second electrode, A semiconductor layer containing, A plurality of third electrodes are provided side by side in the cell region where the second electrode is provided, and face the first semiconductor region via a first insulating portion, A fourth electrode, which includes a portion located between two adjacent third electrodes and faces the second semiconductor region via a second insulating portion, A first insulating layer provided on the semiconductor layer, In the cell region, a wiring is provided within the first insulating layer, extending along the fourth electrode, being thinner than the fourth electrode, and electrically connected to the fourth electrode, A semiconductor device equipped with the following features.

2. The wiring further comprises a second insulating layer covering the upper end of the aforementioned wiring, The semiconductor device according to claim 1, wherein the second electrode is provided on the second insulating layer and is insulated from the wiring by the second insulating layer.

3. The first insulating layer has a slit, The aforementioned wiring is provided within the slit, The semiconductor device according to claim 2, wherein the second insulating layer is provided on the upper end of the wiring and the upper surface of the first insulating layer.

4. The semiconductor device according to claim 3, wherein the second insulating layer extends over and along the wiring.

5. A first contact located on the third electrode and electrically connecting the third electrode and the second electrode, A second contact is located on the second semiconductor region and electrically connects the third semiconductor region and the second electrode, Furthermore, The semiconductor device according to claim 3 or 4, wherein the height of the upper end of the wiring is the same as the height of the upper end of the first contact.

6. The first insulating layer is aligned with the wiring and the second insulating layer in a direction perpendicular to the first direction from the first electrode to the second electrode, The height of the upper surface of the first insulating layer is the same as the height of the upper surface of the second insulating layer. The semiconductor device according to claim 2, wherein the second electrode is provided on the first insulating layer and the second insulating layer.

7. A first contact located on the third electrode and electrically connecting the third electrode and the second electrode, A second contact is located on the second semiconductor region and electrically connects the third semiconductor region and the second electrode, Furthermore, The semiconductor device according to claim 6, wherein the height of the upper end of the wiring is lower than the height of the upper end of the first contact.

8. Further comprising lead wiring provided on the first insulating layer and electrically connected to the wiring, The fourth electrode is provided in the cell region, The semiconductor device according to any one of claims 1 to 4, wherein the lead wiring extends to the outside of the cell region.

9. The semiconductor device according to any one of claims 1 to 4, wherein the length of the wiring in the first direction from the first electrode to the second electrode is longer than the width of the wiring.

10. The semiconductor device according to claim 5, wherein the width of the wiring is narrower than the width of the first contact.

11. Multiple third electrodes are arranged in a first and second arrangement direction that intersect each other. The fourth electrode is A first extension portion located between two of the third electrodes adjacent to each other in the first alignment direction, A second extension portion located between two of the third electrodes adjacent to each other in the second alignment direction, Includes, The aforementioned wiring is A first wiring section extending along the first extending section above the first extending section, A second wiring section extending along the second extending section above the second extending section, A semiconductor device according to any one of claims 1 to 4, including

12. The second arrangement direction is a direction perpendicular to the first arrangement direction, The semiconductor device according to claim 11, wherein the wiring is in a grid pattern in which the first wiring section and the second wiring section intersect each other.

13. The fourth electrode contains polysilicon, The aforementioned wiring includes at least one of silicide and a metallic material. The silicide comprises at least one selected from the group consisting of Co, W, Ti, and Ni. The semiconductor device according to any one of claims 1 to 4, wherein the metal material comprises at least one selected from the group consisting of Ti, TiN, W, Cu, and Al.

14. A first contact located on the third electrode and electrically connecting the third electrode and the second electrode, A second contact is located on the second semiconductor region and electrically connects the third semiconductor region and the second electrode, Furthermore, The semiconductor device according to any one of claims 1 to 4, wherein the material of the wiring is the same as the material of the first contact and the material of the second contact.

15. A step of preparing a semiconductor layer comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type provided on the first semiconductor region; and a third semiconductor region having a first conductivity type provided on the second semiconductor region and electrically connected to a second electrode; wherein a plurality of first trenches and a second trench including a portion located between two adjacent first trenches are formed on the upper surface; a third electrode facing the first semiconductor region via a first insulating portion is formed in the first trench; and a fourth electrode facing the second semiconductor region via a second insulating portion is formed in the second trench; A step of forming a first insulating layer on the semiconductor layer, the third electrode and the fourth electrode, The first insulating layer, A first through-hole extending along the fourth electrode, narrower than the second trench, and reaching the fourth electrode from the upper surface of the first insulating layer, Above the second semiconductor region, a second through-hole is provided that extends from the upper surface of the first insulating layer to the second semiconductor region, A third through-hole is provided above the third electrode, extending from the upper surface of the first insulating layer to the third electrode, A process for simultaneously forming, A step of forming a conductive film on the first insulating layer, forming wiring located in the first through-hole and electrically connected to the fourth electrode, a first contact located in the third through-hole and electrically connected to the third electrode, and a second contact located in the second through-hole and electrically connected to the second semiconductor region, A step of forming a second insulating layer on the aforementioned wiring, A step of forming the second electrode on the first insulating layer and the second insulating layer, which is insulated from the wiring and electrically connected to the first contact and the second contact, A method for manufacturing a semiconductor device equipped with [the specified features].

16. The manufacturing method according to claim 15, wherein the second insulating layer is formed on the first insulating layer and the wiring.

17. Remove a portion of the conductive film formed in the upper part of the first through hole, The manufacturing method according to claim 15, wherein the second insulating layer is formed in the upper part of the first through hole.

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