Junction field effect transistor

Abstract

The invention provides a junction field effect transistor. The junction field effect transistor comprises a substrate of a second doping type; the drain electrode metal is formed on the back side of the substrate; the epitaxial layer of the second doping type is formed on the substrate; the source region of the second doping type is formed downwards from the top surface of the epitaxial layer; the grounded source electrode metal is formed on the source region; the two gate regions of the first doping type are spaced and are respectively adjacent to the source region; each gate region and a part, between the two gate regions, in the epitaxial layer form a PN junction as a first PN junction; wherein the source region, the epitaxial layer and the substrate are connected to form a longitudinal channel; and the gate region is used for connecting gate-source voltage Vgs so as to control the on and off of the longitudinal channel. The technical problems that the on resistance Rds, on of a traditional vertical capacitance coupling grid-control junction field effect transistor is large, and the grid-control capacity is weak are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a junction field effect transistor. Background Art

[0002] The structure of the vertical capacitively coupled gate-controlled junction field effect transistor of patent CN117637854B is as follows: Figure 1 shown. Figure 1 The names corresponding to the reference numerals in the figures are as follows:

[0003] Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel one 1-5, channel two 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9, coupling capacitor upper electrode 1-10, source 1-12, drain 1-13.

[0004] The vertical capacitively coupled gate-controlled junction field effect transistor of patent CN117637854B has the following problems:

[0005] (1) The on-resistance Rds,on is large.

[0006] (2) The manufacturing process of the top gate 1-8 is added, and the mass production cost is high.

[0007] Figure 1 In the figure, when the voltage bias Vgs applied to the upper electrode 1-10 of the coupling capacitor serving as the gate is greater than the threshold voltage, the drain-source current Ids path is as shown by the arrow direction, including longitudinal and lateral parts, and the lateral carrier mobility is smaller than the longitudinal one, so the on-resistance Rds,on is large.

[0008] At the same time, the source region 1-7 and the top gate 1-8 are closely connected to form a Zener diode, and the gate-source leakage current Igss and the gate-source capacitance Cgs are large.

[0009] Therefore, the on-resistance Rds,on of the conventional vertical capacitively coupled gate-controlled junction field effect transistor is relatively large, which is a technical problem that needs to be urgently solved by those skilled in the art.

[0010] The above information disclosed in the Background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the Invention

[0011] The present application provides a junction field effect transistor to solve the technical problem of large on-resistance Rds,on of traditional vertical capacitive-coupled gate-controlled junction field effect transistors.

[0012] The present application provides a junction field-effect transistor, comprising:

[0013] a substrate of a second doping type;

[0014] a drain metal formed on the back side of the substrate;

[0015] an epitaxial layer of a second doping type formed on the substrate;

[0016] A source region of a second doping type is formed downward from the top surface of the epitaxial layer;

[0017] a grounded source metal formed on the source region;

[0018] two gate regions of the first doping type, the two gate regions being spaced apart and respectively connected to the source region so that the source region covers a portion between the two gate regions; each gate region and a portion of the epitaxial layer located between the two gate regions forming a PN junction as a first PN junction;

[0019] The source region, the epitaxial layer, and the substrate are connected to form a longitudinal channel; the gate region is used to connect a gate-source voltage Vgs to control the on and off of the longitudinal channel.

[0020] By adopting the above technical solution, this application has the following technical effects:

[0021] In the junction field-effect transistor of the present application, a second-doped source region, a second-doped epitaxial layer, and a second-doped substrate are connected to form a longitudinal channel. Each gate region and the portion of the epitaxial layer located between the two gate regions form a PN junction serving as a first PN junction, thereby forming two first PN junctions. The gate-source voltage Vgs connected to the gate regions controls the width of the depletion regions of the two first PN junctions, thereby controlling the conduction and shutdown of the longitudinal channel and enhancing gate control capability.

[0022] The on-state current flows from the drain metal through the substrate, epitaxial layer, and source region to the source metal. Because the on-state current flows along the longitudinal channel, it only needs to overcome the on-state resistance in the vertical direction, without any on-state resistance in the lateral direction, making the on-state resistance of the junction field-effect transistor of the present application relatively low. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0024] Figure 1 It is a schematic diagram of patent CN117637854B in the background technology;

[0025] Figure 2-A Schematic diagram of the junction field effect transistor in the off state according to the first embodiment of the present application;

[0026] Figure 2-B Schematic diagram of the junction field effect transistor in the on-state according to the first embodiment of the present application;

[0027] Figure 3-A Schematic diagram of the junction field effect transistor in the off state according to the second embodiment of the present application;

[0028] Figure 3-B Schematic diagram of the junction field effect transistor in the on-state according to the second embodiment of the present application;

[0029] Figure 4 Schematic diagram of a junction field effect transistor according to the third embodiment of the present application;

[0030] Figure 5 Schematic diagram of a junction field effect transistor according to a fourth embodiment of the present application;

[0031] Figure 6 Schematic diagram of a junction field effect transistor according to a fifth embodiment of the present application;

[0032] Figure 7 Schematic diagram of a junction field effect transistor according to a sixth embodiment of the present application;

[0033] Figure 8 Schematic diagram of a junction field effect transistor according to a seventh embodiment of the present application;

[0034] Figure 9 Schematic diagram of a junction field effect transistor according to an eighth embodiment of the present application;

[0035] Figure 10 Schematic diagram of a junction field effect transistor according to a ninth embodiment of the present application;

[0036] Figure 11 Schematic diagram of a junction field effect transistor according to the tenth embodiment of the present application;

[0037] Figure 12 Schematic diagram of a junction field effect transistor according to the eleventh embodiment of the present application;

[0038] Figure 13 A schematic diagram of a junction field effect transistor according to a twelfth embodiment of the present application;

[0039] Figure 14 Schematic diagram of a junction field effect transistor according to a thirteenth embodiment of the present application;

[0040] Figure 15 A schematic diagram of a junction field effect transistor according to a fourteenth embodiment of the present application;

[0041] Figure 16 Schematic diagram of a junction field effect transistor according to a fifteenth embodiment of the present application;

[0042] Figure 17 A schematic diagram of a junction field effect transistor according to a sixteenth embodiment of the present application;

[0043] Figure 18 Schematic diagram of the junction field effect transistor in the on-state according to the seventeenth embodiment of the present application;

[0044] Figure 19 Schematic diagram of the junction field effect transistor in the on-state according to the eighteenth embodiment of the present application;

[0045] Figure 20 This is a simulation diagram of the on-state current Ids-gate-source voltage Vgs curve of the junction field effect transistor of the present application and CN117637854B in the background art;

[0046] Figure 21 A simulation diagram of the blocking current Idss-blocking voltage Vdss curve of the junction field effect transistor of the present application and CN117637854B in the background art;

[0047] Figure 22 This is a simulation diagram of the on-state current Ids-drain-source voltage Vds curve of the junction field effect transistor of the present application and CN117637854B in the background art.

[0048] Description of reference numerals:

[0049] In the background technology:

[0050] Substrate 1-1, epitaxial layer 1-2, bottom gate 1-3, second doping type source region 1-4, channel 1-5,

[0051] Channel 2 1-6, first doping type source region 1-7, top gate 1-8, dielectric layer 1-9,

[0052] Coupling capacitor upper electrode 1-10, source 1-12, drain 1-13;

[0053] In this application:

[0054] Substrate 1, buffer layer 100, drift region 2, gate region 3, gate region contact region 4, gate electrode 5,

[0055] Current guiding layer 6, source region 7, trench 81, recess 82, gate dielectric layer 9,

[0056] Coupling capacitor upper electrode 10, voltage divider resistor 11, source metal 12, drain metal 13,

[0057] Gate capacitor 14. DETAILED DESCRIPTION

[0058] In order to make the technical solutions and advantages of this application more clearly understood, the following further describes the exemplary embodiments of this application in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other unless there is a conflict.

[0059] Example 1

[0060] like Figure 2-A 、 Figure 2-B As shown, the junction field effect transistor of the present application includes:

[0061] a substrate 1 of a second doping type;

[0062] A drain metal 13 is formed on the back side of the substrate 1;

[0063] An epitaxial layer of a second doping type is formed on the substrate 1;

[0064] A source region 7 of a second doping type is formed downward from the top surface of the epitaxial layer;

[0065] A grounded source metal 12 is formed on the source region 7;

[0066] Two gate regions 3 of the first doping type, the two gate regions 3 being spaced apart and respectively located on both sides of the source region 7; a PN junction formed between each gate region 3 and a portion of the epitaxial layer located between the two gate regions 3 serving as a first PN junction;

[0067] Among them, the second doping type source region 7, the second doping type epitaxial layer, and the second doping type substrate 1 are connected to form a longitudinal channel; the gate region 3 is used to connect the gate-source voltage Vgs to control the conduction and cutoff of the first PN junction, thereby controlling the conduction and cutoff of the longitudinal channel.

[0068] In the junction field-effect transistor of the present application, a second-doped source region 7, a second-doped epitaxial layer, and a second-doped substrate 1 are connected to form a longitudinal channel. Each gate region 3 and the portion of the epitaxial layer located between two gate regions 3 form a PN junction serving as a first PN junction, thereby forming two first PN junctions. The gate-source voltage Vgs connected to the gate region 3 controls the width of the depletion regions of the two first PN junctions, thereby controlling the conduction and shutdown of the longitudinal channel and enhancing gate control capability.

[0069] like Figure 2-A As shown, when the gate-source voltage Vgs connected to the gate region 3 does not reach the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type epitaxial layer is wider. Figure 2-AThe dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type epitaxial layer. The depletion regions of the two first PN junctions in the second doping type epitaxial layer are connected to shut down the vertical channel.

[0070] like Figure 2-B As shown, when the gate-source voltage Vgs connected to the gate region 3 reaches the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type epitaxial layer becomes narrower. Figure 2-B The dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type epitaxial layer. There is a gap between the two first PN junctions in the depletion region of the second doping type epitaxial layer, which conducts the vertical channel. The on-current flows from the drain metal 13 through the substrate 1, the epitaxial layer, and the source region 7 to the source metal 12. Because the on-current flows along the vertical channel, it only needs to overcome the on-resistance in the vertical direction, and there is no on-resistance in the lateral direction, so the on-resistance of the junction field effect transistor of the present application is relatively small.

[0071] Specifically, the junction field effect transistor also includes:

[0072] a current guiding layer 6 of a second doping type, formed in a portion of the epitaxial layer between the two gate regions 3 and in a portion of the epitaxial layer below the gate region 3; wherein the portion of the epitaxial layer below the current guiding layer 6 serves as the drift region 2;

[0073] A buffer layer 100 of a second doping type is formed between the substrate 1 and the drift region 2 .

[0074] Corresponding:

[0075] Each gate region 3 and the portion of the current guiding layer 6 located between two gate regions 3 form a PN junction as a first PN junction;

[0076] The second doping type source region 7 , the second doping type current guiding layer 6 , the second doping type drift region 2 , the second doping type buffer layer 100 , and the second doping type substrate 1 are connected to form a vertical channel.

[0077] like Figure 2-A As shown, when the gate-source voltage Vgs connected to the gate region 3 does not reach the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type current guiding layer 6 is wider. Figure 2-A The dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type current guiding layer 6. The depletion regions of the two first PN junctions in the second doping type current guiding layer 6 are connected to shut down the longitudinal channel.

[0078] like Figure 2-BAs shown, when the gate-source voltage Vgs connected to the gate region 3 reaches the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type current guiding layer 6 becomes narrower. Figure 2-B The dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type current guiding layer 6. There is a gap between the two first PN junctions in the depletion region of the second doping type current guiding layer 6, which conducts the vertical channel. The on-current flows from the drain metal 13 through the substrate 1, the current guiding layer 6, the epitaxial layer, and the source region 7 to the source metal 12. Because the on-current flows along the vertical channel, it only needs to overcome the on-resistance in the vertical direction, and there is no on-resistance in the lateral direction, so the on-resistance of the junction field effect transistor of the present application is relatively small.

[0079] There are many ways to position the two gate regions 3 on both sides of the source region 7 . The gate region 3 and the source region 7 may be connected, or the gate region and the source region may be disconnected.

[0080] One way to connect the gate region 3 and the source region 7:

[0081] like Figure 2-A 、 Figure 2-B As shown, the gate region 3 is formed downward from the top surface of the epitaxial layer; the top surfaces of the gate region 3 and the source region 7 are flush.

[0082] In this way, the gate region 3 can be formed by ion implantation from the top surface of the epitaxial layer downwards. The source region 3 can be formed by ion implantation from the top surface of the epitaxial layer downwards. The structure is simple and the preparation is also simple.

[0083] Specifically, such as Figure 2-A 、 Figure 2-B As shown, the connection position between the gate region 3 and the source region 7 is specifically:

[0084] The gate region 3 forms a gate region L-shaped connection surface at the connection position between the source region 7 and the gate region 3;

[0085] In the lateral direction, the lateral portion of the gate region L-shaped connecting surface is connected to the bottom surface of the source region 7;

[0086] In the vertical direction, the vertical portion of the L-shaped connecting surface of the gate region is connected to the side surface of the source region 7 .

[0087] like Figure 2-A and Figure 2-A The junction field effect transistor shown further includes:

[0088] a gate dielectric layer 9 formed on the gate region 3;

[0089] The coupling capacitor upper electrode 10 is formed on the gate dielectric layer 9 .

[0090] In this way, the gate-source voltage Vgs of the junction field-effect transistor is not directly applied to the gate region 3, but is instead connected to the coupling capacitor top electrode 10. The coupling capacitor top electrode 10 is an electrode connected to a voltage. The gate region 3 is not directly controlled by the gate-source voltage Vgs, but is indirectly controlled via the coupling capacitor top electrode 10 through the gate dielectric layer 9. The gate-source voltage applied to the coupling capacitor top electrode 10 is coupled to the gate region 3 through a coupling method, so that no current flows through the gate region 3, thereby improving reliability.

[0091] Specifically, the gate dielectric layer 9 prevents the upper electrode 10 of the coupling capacitor from injecting current when it is turned on and affects the reliability of the device, thereby increasing the operating voltage.

[0092] Specifically, the coupling capacitor upper electrode 10 is a polysilicon electrode or a metal electrode.

[0093] Example 2

[0094] The junction field effect transistor of the second embodiment, such as Figure 3-A and Figure 3-B , in Example 1 ( Figure 2-A and Figure 2-B ), it also includes:

[0095] A voltage-dividing resistor 11 has a first end connected to the gate region 3 , and a second end connected to the upper electrode 10 of the coupling capacitor, and the connection serves as an input end of the gate-source voltage Vgs.

[0096] Thus, a parallel circuit is formed between the gate-source voltage Vgs and the gate region 3: the voltage divider resistor 11 is connected in parallel with the gate dielectric layer 9 as a whole and the coupling capacitor upper electrode 10. Thus, the voltage divider resistor 11 plays a voltage divider role, so that the on-state current decays with time without reducing the threshold voltage of the present application.

[0097] like Figure 3-A As shown, when the gate-source voltage Vgs does not reach the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type epitaxial layer is wider. Figure 3-A The dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type epitaxial layer. The depletion regions of the two first PN junctions in the second doping type epitaxial layer are connected to shut down the vertical channel.

[0098] like Figure 3-B As shown, when the gate-source voltage Vgs reaches the threshold voltage of the first PN junction, the depletion region of the first PN junction in the second doping type epitaxial layer becomes narrower. Figure 3-BThe dotted line in the figure is a depletion line, which is the boundary of the depletion region of the first PN junction in the second doping type epitaxial layer. There is a gap between the two first PN junctions in the depletion region of the second doping type epitaxial layer, which conducts the vertical channel. The on-current flows from the drain metal 13 through the substrate 1, the epitaxial layer, and the source region 7 to the source metal 12. Because the on-current flows along the vertical channel, that is, it only needs to overcome the on-resistance in the vertical direction, and there is no on-resistance in the lateral direction, so the on-resistance of the junction field effect transistor of the present application is relatively small.

[0099] Specifically, the resistance range of the voltage divider resistor is greater than or equal to 1×10 2 Ω is less than or equal to 1×10 9 Ω.

[0100] It should be noted that, Examples 2 to 8 (corresponding to Figure 3-A to Figure 9 ) are located on both sides of the source region 7 in the same manner as in the first embodiment (corresponding to Figure 2-A Therefore, it is only described in Example 1 and is not repeated in Examples 2 to 8.

[0101] Example 3

[0102] The junction field effect transistor of the third embodiment, Figure 4 As shown, based on the first embodiment, it also includes:

[0103] a gate contact region 4 of a first doping type, each gate region corresponding to one gate contact region 4, the gate contact region 4 being formed downward from the top surface of the gate region 3, and having a gap between the corresponding gate contact region 4 and the source region 7;

[0104] a gate dielectric layer 9 formed on the gate contact region 4;

[0105] A coupling capacitor upper electrode 10 is formed on the gate dielectric layer 9;

[0106] The doping concentration of the gate contact region 4 is greater than the doping concentration of the gate region 3 .

[0107] The doping concentration of the gate contact region 4 is greater than that of the gate region 3 , so that the potential drop of the gate region 3 is reduced, and carriers are more easily introduced into and out of the gate contact region 4 , thereby achieving better gate control.

[0108] The partitioning of the gate contact region 4 and the gate region 3 allows for flexible setting of the doping concentrations of the gate contact region 4 and the gate region 3. The PN junction formed at the junction of the gate region 3 and the source region 7 affects the threshold voltage of the first PN junction. Therefore, the doping concentration of the gate region 3 can be set relatively low.

[0109] The gate contact region 4 can be formed by ion implantation from the top surface of the epitaxial layer downwards, which has a simple structure and is easy to prepare.

[0110] The gate contact area 4 is not directly controlled by the gate-source voltage Vgs, but is indirectly controlled by the gate dielectric layer 9 separated by the upper electrode 10 of the coupling capacitor. The gate-source voltage applied to the upper electrode 10 of the coupling capacitor is coupled to the gate contact area 4 by coupling, so that no current passes through the gate contact area 4, and the reliability is high.

[0111] Example 4

[0112] The junction field effect transistor of the fourth embodiment, such as Figure 5 As shown, in Example 3 ( Figure 4 ), it also includes:

[0113] A voltage-dividing resistor 11 has a first end connected to the gate region 3 , and a second end connected to the upper electrode 10 of the coupling capacitor, and the connection serves as an input end of the gate-source voltage.

[0114] Example 5

[0115] The junction field effect transistor of the fifth embodiment is different from the first embodiment in that the gate electrode 5 and the gate capacitor 14 (such as Figure 6 As shown in FIG2 , the gate dielectric layer 9 and the coupling capacitor upper electrode 10 in the first embodiment are replaced.

[0116] The junction field effect transistor of the fifth embodiment further includes:

[0117] A gate electrode 5 , each gate region 3 corresponds to one gate electrode 5 , and the gate electrode 5 is formed on the gate region 3 ;

[0118] The gate capacitor 14 has a first plate connected to the gate electrode 5 , and a second plate serving as an input terminal of a gate-source voltage.

[0119] That is, the gate capacitor 14 is connected in series between the gate electrode 5 of the junction field effect transistor and the gate-source voltage Vgs provided by the external control voltage circuit. The gate capacitor 14 is part of the junction field effect transistor (essentially a switching device) of the present application.

[0120] Figure 6 The gate electrode 5 and the gate capacitor 14 are arranged in the manner Figure 4 The advantage of the arrangement of the gate dielectric layer 9 and the coupling capacitor upper electrode 10 is that the gate capacitor 14 can be adjusted as needed, which is more flexible.

[0121] Example 6

[0122] The junction field effect transistor of embodiment 6 is as follows: Figure 7 As shown, in Example 5 ( Figure 6 ), it also includes:

[0123] A voltage-dividing resistor 11 has a first end connected to the gate region 3 , and a second end connected to the upper electrode 10 of the coupling capacitor, and the connection serves as an input end of the gate-source voltage.

[0124] Example 7

[0125] The junction field effect transistor of embodiment 7 is as follows Figure 8 As shown, based on the sixth embodiment, it also includes:

[0126] a gate contact region 4 of a first doping type, each gate region corresponding to one gate contact region 4, the gate contact region 4 being formed downward from the top surface of the gate region 3, and having a gap between the corresponding gate contact region 4 and the source region 7;

[0127] Each gate contact region 4 corresponds to one gate electrode 5 , and the gate electrode 5 is formed on the gate contact region 4 ;

[0128] The first plate of the gate capacitor 14 is connected to the gate electrode 5 , and the second plate of the gate capacitor 14 serves as an input end of the gate-source voltage.

[0129] That is, the gate capacitor 14 is connected in series between the gate electrode 5 of the junction field effect transistor and the gate-source voltage Vgs provided by the external control voltage circuit. The gate capacitor 14 is part of the junction field effect transistor (essentially a switching device) of the present application.

[0130] Figure 8 The gate electrode 5 and the gate capacitor 14 are arranged in the manner Figure 4 The advantage of the arrangement of the gate dielectric layer 9 and the coupling capacitor upper electrode 10 is that the gate capacitor 14 can be adjusted as needed, which is more flexible.

[0131] Example 8

[0132] The junction field effect transistor of embodiment 8 is as follows: Figure 9 As shown, in Example 7 ( Figure 8 ), it also includes:

[0133] A voltage divider resistor 11 has a first end connected to the gate contact region 4 , and a second end connected to the second plate of the gate capacitor 14 , and the connection serves as an input end of the gate-source voltage.

[0134] Embodiment 9

[0135] Example 9 ( Figure 10 ) shows another way of connecting the gate region 3 and the source region 7:

[0136] like Figure 10 As shown, the top surface of the gate region 3 and the bottom surface of the source region 7 are connected only in the lateral direction through the trench 81, and the side surfaces of the gate region 3 and the source region 7 are not connected in the vertical direction.

[0137] The junction field effect transistor of embodiment 9, such as Figure 10 As shown, based on the first embodiment, it also includes:

[0138] Grooves 81 are formed downward from the top surface of the epitaxial layer, and the preset positions of the source regions and the grooves 81 are alternately arranged;

[0139] The source region 7 is formed downward from a preset position of the source region 7 , and the gate region 3 is formed downward from the bottoms of the two trenches 81 , respectively. The gate region 3 is connected to the source region 7 .

[0140] By etching downward from the top surface of the epitaxial layer, etching is performed in the area other than the preset position of the source region, thereby forming an alternating arrangement of the preset position of the raised source region and the recessed grooves 81;

[0141] Afterwards, a source region 7 is formed at a preset location of the source region by ion implantation, and a gate region 3 or a gate region contact region 4 is formed at the bottom of the trench 81 by ion implantation.

[0142] In this way, the top surface of the gate region 3 and the bottom surface of the source region 7 are adjacent only in the lateral direction. In the vertical direction, the side surfaces of the gate region 3 and the side surfaces of the source region 7 are not connected. Therefore, the side surfaces of the gate region 3 and the side surfaces of the source region 7 cannot form a Zener diode. Only the top surface of the gate region 3 and the bottom surface of the source region 7 form a Zener diode, which reduces the tunneling leakage of the Zener diode, thereby achieving low gate-source leakage current Igss. At the same time, the gate-source contact area is reduced, thereby reducing the gate-source capacitance Cgs. Moreover, the structure is simple and the preparation is also simple.

[0143] The junction field effect transistor of embodiment 9, such as Figure 10 As shown, it also includes:

[0144] a gate dielectric layer 9 formed on the gate region 3;

[0145] The coupling capacitor upper electrode 10 is formed on the gate dielectric layer 9 .

[0146] It should be noted that, in the ninth to twelfth embodiments ( Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 ) shows the same method of connecting the top surface of the gate region 3 and the bottom surface of the source region 7 only in the lateral direction through the trench 81. In the vertical direction, the side surfaces of the gate region 3 and the source region 7 are not connected. This is only described in Example 9 and will not be repeated in Examples 10 to 12.

[0147] Example 10

[0148] The junction field effect transistor of embodiment 10 is as follows: Figure 11 As shown, in Example 9 ( Figure 10 ), it also includes:

[0149] A voltage-dividing resistor 11 has a first end connected to the gate region 3 , and a second end connected to the upper electrode 10 of the coupling capacitor, and the connection serves as an input end of the gate-source voltage Vgs.

[0150] Example 11

[0151] The junction field effect transistor of the eleventh embodiment is as follows: Figure 12 As shown, based on the ninth embodiment, it also includes:

[0152] a gate contact region 4 of a first doping type, each gate region corresponding to one gate contact region 4, the gate contact region 4 being formed downward from the top surface of the gate region 3, and having a gap between the corresponding gate contact region 4 and the source region 7;

[0153] Each gate contact region 4 corresponds to one gate electrode 5 , and the gate electrode 5 is formed on the gate contact region 4 ;

[0154] The first plate of the gate capacitor 14 is connected to the gate electrode 5, and the second plate of the gate capacitor 14 serves as the input end of the gate-source voltage;

[0155] The doping concentration of the gate contact region 4 is greater than the doping concentration of the gate region 3 .

[0156] Example 12

[0157] The junction field effect transistor of the twelfth embodiment is as follows Figure 13 As shown, in Example 11 ( Figure 12 ), it also includes:

[0158] A voltage divider resistor 11 has a first end connected to the gate contact region 4 , and a second end connected to the second plate of the gate capacitor 14 , and the connection serves as an input end of the gate-source voltage.

[0159] It should be noted that the technical solution of connecting the top surface of the gate region 3 and the bottom surface of the source region 7 in the lateral direction only by using the trench 81 is not only applicable to the ninth embodiment to the twelfth embodiment ( Figures 10 to 13 ), there are four other embodiments that can be used, namely, embodiment nine to embodiment twelve ( Figures 10 to 13 ) is replaced by the gate electrode 5 and the gate capacitor 14. This technical solution corresponds to the first to eighth embodiments of the present application, and the technical features and effects are also corresponding, which can support the claims of the present application.

[0160] Example 13

[0161] Example 13 ( Figure 14 ) shows another way of connecting the gate region 3 and the source region 7:

[0162] like Figure 14 As shown, the notch 82 is used to connect the top surface of the gate region 3 and the bottom surface of the source region 7 only in the lateral direction, while the side surfaces of the gate region 3 and the source region 7 are not connected in the vertical direction.

[0163] The junction field effect transistor of the thirteenth embodiment is as follows Figure 14 As shown, the difference from the first embodiment is that the gate electrode 5 and the gate capacitor 14 (such as Figure 6 As shown in FIG2 , the gate dielectric layer 9 and the coupling capacitor upper electrode 10 in the first embodiment are replaced.

[0164] The junction field effect transistor of the thirteenth embodiment is as follows Figure 14 As shown, it also includes:

[0165] A notch 82 is formed on the top surface of the epitaxial layer, with the preset position of the source region and the epitaxial layer reserved regions spaced apart on both sides of the preset position of the source region. The notch 82 is formed downward from the top surface of the epitaxial layer between the preset position of the source region and the epitaxial layer reserved regions;

[0166] The source region 7 is formed downward from a preset position of the source region 7, and the gate region 3 is formed downward from the bottom of the recess 82 and from the retained area of ​​the epitaxial layer, so that the top surface of the gate region 3 is connected to the bottom surface of the source region 7 at the recess position.

[0167] The notch 82 is formed by etching, so that less material is etched away, saving material. At the same time, it is also achieved that only the top surface of the gate region 3 in the lateral direction is connected to the bottom surface of the source region 7 at the notch position. In the vertical direction, the side surface of the gate region 3 and the side surface of the source region 7 are not connected. The side surface of the gate region 3 and the side surface of the source region 7 cannot form a Zener diode. Only the top surface of the gate region 3 and the bottom surface of the source region 7 form a Zener diode, which reduces the tunneling leakage of the Zener diode, thereby achieving low gate-source leakage current Igss; at the same time, the gate-source contact area is reduced, thereby reducing the gate-source capacitance Cgs.

[0168] The junction field effect transistor of the thirteenth embodiment is as follows Figure 14 As shown, it also includes:

[0169] A gate electrode 5 , each gate region 3 corresponds to one gate electrode 5 , and the gate electrode 5 is formed on the gate region 3 ;

[0170] The gate capacitor 14 has a first plate connected to the gate electrode 5 , and a second plate serving as an input terminal of a gate-source voltage.

[0171] It should be noted that, in the embodiments 13 to 16 ( Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 ) shows the same method of connecting the top surface of the gate region 3 and the bottom surface of the source region 7 only in the lateral direction through the notch 82. This is only described in the thirteenth embodiment and will not be repeated in the fourteenth to sixteenth embodiments.

[0172] Example 14

[0173] The junction field effect transistor of the fourteenth embodiment is as follows Figure 15 As shown, in Example 13 ( Figure 14 ), it also includes:

[0174] A voltage-dividing resistor 11 has a first end connected to the gate region 3 , and a second end connected to the upper electrode 10 of the coupling capacitor, and the connection serves as an input end of the gate-source voltage Vgs.

[0175] Example 15

[0176] The junction field effect transistor of the fifteenth embodiment is as follows Figure 16 As shown, based on the thirteenth embodiment, it also includes:

[0177] A gate contact region 4, each gate region corresponding to one gate contact region 4, the gate contact region 4 being formed downward from the reserved region of the epitaxial layer;

[0178] Each gate contact region 4 corresponds to one gate electrode 5 , and the gate electrode 5 is formed on the gate contact region 4 ;

[0179] The first plate of the gate capacitor 14 is connected to the gate electrode 5 , and the second plate of the gate capacitor 14 serves as an input end of the gate-source voltage.

[0180] Example 16

[0181] The junction field effect transistor of embodiment 16 is as follows: Figure 17 As shown, in Example 15 ( Figure 16 ), it also includes:

[0182] A voltage divider resistor 11 has a first end connected to the gate contact region 4 , and a second end connected to the second plate of the gate capacitor 14 , and the connection serves as an input end of the gate-source voltage.

[0183] It should be noted that the technical solution of using the notch 82 to connect the top surface of the gate region 3 and the bottom surface of the source region 7 in the lateral direction only includes the thirteenth to sixteenth embodiments ( Figures 14 to 17 ), there are four more embodiments that can be used, and the ninth to the twelfth embodiments ( Figures 14 to 17 ) is replaced by a gate dielectric layer 9 and a coupling capacitor upper electrode 10. This technical solution corresponds to Embodiments 1 to 8 of the present application, and the technical features and effects are also corresponding, which can support the claims of the present application.

[0184] Example 17

[0185] The first embodiment adopts a method of connecting the gate region 3 and the source region 7. The junction field effect transistor of the seventeenth embodiment adopts a method of not connecting the gate region 3 and the source region 7. Figure 18 As shown, the gate region 3 and the source region 7 remain spaced apart and are completely disconnected.

[0186] The gate region 3 and the source region 7 cannot form a Zener diode, thereby eliminating the tunneling leakage of the Zener diode and achieving low gate-source leakage current Igss; at the same time, the gate and source are completely disconnected, and there is no gate-source contact area, thereby reducing the gate-source capacitance Cgs.

[0187] Specifically, such as Figure 18 As shown, the gate region 3 is rectangular, the source region 7 is rectangular, and the gate region 3 and the source region 7 are spaced apart in the lateral direction so that the gate region 3 and the source region 7 are completely unconnected.

[0188] It should be noted that the rectangular gate region 3 and the rectangular source region 7 are kept apart and are not connected to each other. Figure 18 ), and also Embodiment 1 to Embodiment 8 ( Figure 2-A to Figure 9 ) is replaced by Figure 18 The form of "the rectangular gate region 3 and the rectangular source region 7 are kept spaced apart and are completely unconnected" corresponds to the first to eighth embodiments of the present application, and the technical features and technical effects also correspond, which can support the claims of the present application.

[0189] Embodiment 18

[0190] The first embodiment adopts a method of connecting the gate region 3 and the source region 7. The junction field effect transistor of the eighteenth embodiment adopts another implementation method in which the gate region 3 and the source region 7 are not connected. Figure 19 As shown, the gate region 3 and the source region 7 remain spaced apart and are completely disconnected.

[0191] The gate region 3 and the source region 7 cannot form a Zener diode, thereby eliminating the tunneling leakage of the Zener diode and achieving low gate-source leakage current Igss; at the same time, the gate and source are completely disconnected, and there is no gate-source contact area, thereby reducing the gate-source capacitance Cgs.

[0192] Specifically, such as Figure 19 As shown, the gate region 3 has an L-shaped avoidance notch on the side facing the source region 7 for avoiding the source region 7. The source region 7 is rectangular. The vertical portion of the L-shaped avoidance notch of the gate region 3 is spaced apart from the source region 7 in the lateral direction, and the lateral portion of the L-shaped avoidance notch of the gate region 3 is also spaced apart from the source region 7 in the vertical direction, so that the gate region 3 and the source region 7 are completely disconnected.

[0193] It should be noted that the technical solution in which the gate region 3 with the L-shaped avoidance gap and the rectangular source region 7 are kept apart and not connected at all is not limited to the embodiment 18 ( Figure 19 ), and also Embodiment 1 to Embodiment 8 ( Figure 2-A to Figure 9 ) is replaced by Figure 19 The form of "the gate region 3 with the L-shaped avoidance gap and the rectangular source region 7 are kept apart and are completely unconnected" corresponds to the first to eighth embodiments of the present application, and the technical features and technical effects also correspond, which can support the claims of the present application.

[0194] The manner in which the two gate regions 3 are respectively located on both sides of the source region 7 in the first to eighteenth embodiments can be summarized as follows:

[0195] In the first way, the gate region 3 and the source region 7 are connected.

[0196] like Figure 2-A 、 Figure 2-B 、 Figure 3-A 、 Figure 3-B 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 As shown (i.e. corresponding to embodiment 1 to embodiment 16).

[0197] In the second mode, the gate region 3 and the source region 7 are not connected, that is, a gap is maintained between the gate region 3 and the source region 7. Figure 18 、 Figure 19 As shown (i.e. corresponding to embodiment 17 and embodiment 18).

[0198] The gate region 3 and the source region 7 are kept apart and are completely disconnected. The gate region 3 and the source region 7 cannot form a Zener diode, thereby eliminating the tunneling leakage of the Zener diode and achieving a low gate-source leakage current Igss. At the same time, the gate and source are completely disconnected, and there is no gate-source contact area, which makes the gate-source capacitance Cgs extremely small.

[0199] The first method has a more complex structure, but has lower requirements on the precision of the preparation process and is a more economical structural method.

[0200] The second method corresponds to Figure 18 and Figure 19 The structure is simple and requires high precision in the preparation process.

[0201] Figure 20 This is a simulation diagram of the on-state current Ids-gate-source voltage Vgs curve of the junction field effect transistor of the present application and CN117637854B in the background art.

[0202] The threshold voltage Vth (the threshold voltage Vth is the intersection of the vertical dotted line and the horizontal axis) of the junction field effect transistor of the present application and CN117637854B in the background art is not much different and can be considered to be the same.

[0203] Figure 21 This is a simulation diagram of the blocking current Idss-blocking voltage Vdss curve of the junction field effect transistor of the present application and CN117637854B in the background art.

[0204] The blocking voltage Vdss of the junction field effect transistor of the present application and CN117637854B in the background art are not much different and can be considered to be the same.

[0205] Figure 22This is a simulation diagram of the on-state current Ids-drain-source voltage Vds curve of the junction field effect transistor of the present application and CN117637854B in the background art.

[0206] On-resistance Rds,on=drain-source voltage Vds / on-current Ids. Figure 22 It can be seen that when the drain-source voltage Vds is the same, the on-current Ids of the junction field effect transistor of the present application is larger, and therefore, the on-resistance Rds,on of the junction field effect transistor of the present application is smaller.

[0207] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0208] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0209] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0210] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1The steps for the function specified in one or more boxes.

[0211] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0212] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A junction field effect transistor, characterized in that include: A substrate (1) of a second doping type; A drain metal (13) formed on the back side of the substrate (1); An epitaxial layer of a second doping type is formed on the substrate (1); A source region (7) of a second doping type is formed downward from the top surface of the epitaxial layer; A grounded source metal (12) is formed on the source region (7); Two gate regions (3) of a first doping type, the two gate regions (3) being spaced apart and respectively located on both sides of the source region (7); each gate region (3) and a portion of the epitaxial layer located between the two gate regions forming a PN junction as a first PN junction; The source region (7), the epitaxial layer, and the substrate (1) are connected to form a longitudinal channel; and the gate region (3) is used to connect a gate-source voltage Vgs to control the on and off of the longitudinal channel.

2. The junction field effect transistor according to claim 1, wherein A gap is maintained between the gate region (3) and the source region (7).

3. The junction field effect transistor according to claim 1, wherein The gate region (3) is connected to the source region (7), and the gate region (3) forms a gate region L-shaped connection surface at a connection position between the source region (7) and the gate region (3); The connection between the gate region (3) and the source region (7) includes: In the lateral direction, the lateral portion of the gate region L-shaped connecting surface is connected to the bottom surface of the source region (7); In the vertical direction, the vertical portion of the gate region L-shaped connecting surface is connected to the side surface of the source region (7).

4. The junction field effect transistor according to claim 1, wherein The gate region (3) and the source region (7) are connected; the connection between the gate region (3) and the source region (7) includes: Only in the lateral direction, the top surface of the gate region (3) and the bottom surface of the source region (7) are connected; In the vertical direction, a side surface of the gate region (3) and a side surface of the source region (7) have a preset interval.

5. The junction field effect transistor according to claim 4, wherein: Also includes: Grooves (81), the grooves (81) being formed downward from the top surface of the epitaxial layer, and the preset positions of the source regions and the grooves (81) being arranged alternately; The source region (7) is formed downward from a preset position of the source region (7), the gate region (3) is formed downward from the bottoms of the two trenches (81), and the gate region (3) and the source region (7) are connected.

6. The junction field effect transistor according to claim 4, wherein: Also includes: A notch (82), the top surface of the epitaxial layer is planned to have a preset position of the source region and an epitaxial layer reserved region spaced apart on both sides of the preset position of the source region, the notch (82) being formed downward from the top surface of the epitaxial layer between the preset position of the source region and the reserved region of the epitaxial layer; The source region (7) is formed downward from a preset position of the source region (7), and the gate region (3) is formed downward from the bottom of the recess (82), so that the top surface of the gate region (3) is connected to the bottom surface of the source region (7) at the recess position.

7. The junction field effect transistor according to any one of claims 2 to 6, characterized in that: Also includes: a gate dielectric layer (9) formed on the gate region (3); A coupling capacitor upper electrode (10) is formed on the gate dielectric layer (9).

8. The junction field effect transistor according to claim 7, wherein: Also includes: A voltage-dividing resistor (11) is provided, wherein a first end of the voltage-dividing resistor (11) is connected to the gate region (3), and a second end of the voltage-dividing resistor (11) is connected to the upper electrode (10) of the coupling capacitor, and the connection point serves as an input end of a gate-source voltage Vgs.

9. The junction field effect transistor according to any one of claims 2 to 6, characterized in that: Also includes: a gate contact region (4) of a first doping type, each gate region corresponding to one gate contact region (4), the gate contact region (4) being formed downward from the top surface of the gate region (3), and having a gap between the corresponding gate contact region (4) and the source region (7); A gate dielectric layer (9) formed on the gate contact region (4); A coupling capacitor upper electrode (10) is formed on the gate dielectric layer (9); The doping concentration of the gate region contact area (4) is greater than the doping concentration of the gate region (3).

10. The junction field effect transistor according to claim 9, wherein: Also includes: A voltage-dividing resistor (11) is provided, wherein a first end of the voltage-dividing resistor (11) is connected to the gate region (3), and a second end of the voltage-dividing resistor (11) is connected to the upper electrode (10) of the coupling capacitor, and the connection point serves as an input end of the gate-source voltage.

11. The junction field effect transistor according to any one of claims 2 to 6, characterized in that: Also includes: A gate electrode (5), each gate region (3) corresponds to one gate electrode (5), and the gate electrode (5) is formed on the gate region (3); A gate capacitor (14), wherein a first plate of the gate capacitor (14) is connected to the gate electrode (5), and a second plate of the gate capacitor (14) serves as an input end of a gate-source voltage.

12. The junction field effect transistor according to claim 7, wherein: Also includes: A voltage-dividing resistor (11) is provided, wherein a first end of the voltage-dividing resistor (11) is connected to the gate region (3), and a second end of the voltage-dividing resistor (11) is connected to the upper electrode (10) of the coupling capacitor, and the connection point serves as an input end of a gate-source voltage Vgs.

13. The junction field effect transistor according to any one of claims 2 to 6, characterized in that: Also includes: a gate contact region (4) of a first doping type, each gate region corresponding to one gate contact region (4), the gate contact region (4) being formed downward from the top surface of the gate region (3), and having a gap between the corresponding gate contact region (4) and the source region (7); A gate electrode (5), each gate contact region (4) corresponds to one gate electrode (5), and the gate electrode (5) is formed on the gate contact region (4); A gate capacitor (14), wherein a first plate of the gate capacitor (14) is connected to the gate electrode (5), and a second plate of the gate capacitor (14) serves as an input end of a gate-source voltage; The doping concentration of the gate region contact area (4) is greater than the doping concentration of the gate region (3).

14. The junction field effect transistor according to claim 13, wherein: Also includes: A voltage divider resistor (11), wherein a first end of the voltage divider resistor (11) is connected to the gate contact region (4), and a second end of the voltage divider resistor (11) is connected to the second plate of the gate capacitor (14), and the connection serves as an input end of the gate-source voltage.

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