Silicon-based germanium photodetector and manufacturing method
By forming a V-groove and depositing a germanium epitaxial layer in a silicon-based germanium photodetector, the problems of high dark current and low reliability of silicon-based germanium photodetectors are solved, thereby improving the performance and reliability of the photodetector.
Patent Information
- Application Number
- CN202511179150.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2045-08-22
AI Technical Summary
Existing silicon-based germanium photodetectors have large dark currents and low device reliability. This is mainly due to the increased dislocation defects caused by lattice mismatch between silicon and germanium, which lead to thermally excited currents under non-illuminated conditions, affecting the sensitivity and reliability of the detector.
A V-groove is formed in a silicon substrate, and a germanium epitaxial layer is deposited on it. Dislocations are used to slide away from the active light absorption region along the slope of the V-groove. At the same time, the bottom of the tip of the V-groove is rounded to reduce dark current and improve reliability.
It effectively reduces the dark current of the photodetector, improves the performance and reliability of the detector, and exhibits extremely high stability, especially under high temperature conditions.
Smart Images
Figure CN120676752B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of photoelectric detection, and relates to a silicon-based germanium photoelectric detector and a manufacturing method. BACKGROUND
[0002] A high-performance photoelectric detector should have the characteristics of high responsivity, high bandwidth and low dark current (noise) in the response band. At room temperature, the cutoff wavelength of silicon is 1.1 mu m, which limits the application of silicon in the near-infrared band of 1.3-1.5 mu m. Germanium extends the response wavelength of the detector to more than 1.55 mu m, becoming the most ideal material for silicon-based long-wavelength photoelectric detectors.
[0003] The quality of the germanium crystal in the silicon-based germanium photoelectric detector is crucial to the dark current. Due to the huge lattice mismatch between silicon and germanium, high-density dislocation defects are generated. As an additional carrier generation-recombination center, the dislocation defects significantly increase the current generated by thermal excitation under non-light conditions (i.e., dark current), reduce the sensitivity of the detector, and even cause the device to fail.
[0004] Therefore, how to provide a silicon-based germanium photoelectric detector and a manufacturing method to reduce the dark current and improve the performance of the detector has become a technical problem to be solved by those skilled in the art. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a silicon-based germanium photoelectric detector and a manufacturing method, which are used to solve the problems of large dark current and low device reliability of the silicon-based germanium photoelectric detector in the prior art.
[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a manufacturing method of a silicon-based germanium photoelectric detector, comprising the following steps:
[0007] S1: providing a silicon substrate, and forming a stacked thermal silicon oxide layer and a deposited silicon oxide layer on the silicon substrate;
[0008] S2: forming a vertical groove, wherein the vertical groove extends from the upper surface of the deposited silicon oxide layer to the silicon substrate;
[0009] S3: placing the structure after forming the vertical groove into a deposition chamber, introducing H2 into the deposition chamber, and baking for a first preset time under the H2 atmosphere;
[0010] S4: introducing H2 and HCl into the deposition chamber, and baking for a second preset time under the H2 atmosphere and the HCl atmosphere, so as to convert the vertical groove in the silicon substrate into a V-shaped groove;
[0011] S5: introducing H2 into the deposition chamber, baking for a third preset time under the H2 atmosphere to make the V-shaped groove circular, and the circular V-shaped groove and the vertical groove above the V-shaped groove together form a deposition groove;
[0012] S6: forming a germanium epitaxial layer in the deposition groove.
[0013] Optionally, in step S6, the selective epitaxy growth method is used to form the germanium epitaxial layer in the deposition groove, and the upper surface of the germanium epitaxial layer is an arc surface.
[0014] Optionally, in step S1, before forming the thermal silicon oxide layer and the deposition silicon oxide layer on the silicon substrate, the step of forming a first conductive type doped region and a second conductive type doped region in the silicon substrate is further included, one side of the germanium epitaxial layer is electrically connected to the first conductive type doped region, and the other side of the germanium epitaxial layer is electrically connected to the second conductive type doped region.
[0015] Optionally, after forming the germanium epitaxial layer, the following steps are further included:
[0016] S7: forming a dielectric layer on the deposition silicon oxide layer, the dielectric layer covering the germanium epitaxial layer;
[0017] S8: forming a first contact hole penetrating through the dielectric layer, the deposition silicon oxide layer and the thermal silicon oxide layer, the first contact hole exposing the first conductive type doped region, and forming a second contact hole penetrating through the dielectric layer, the deposition silicon oxide layer and the thermal silicon oxide layer, the second contact hole exposing the second conductive type doped region;
[0018] S9: filling metal in the first contact hole to form a first metal layer, and filling metal in the second contact hole to form a second metal layer, the first metal layer being electrically connected to the first conductive type doped region, and the second metal layer being electrically connected to the second conductive type doped region.
[0019] Optionally, in step S3, the flow rate of H2 is 40-80 slm, the temperature of the deposition chamber is 850-950℃, the pressure is 10-50 Torr, and the first preset time is 5-8 min;
[0020] In step S4, the flow rate of H2 is 40-80 slm, the flow rate of HCl is 100-300 sccm, the temperature of the deposition chamber is 850-950℃, the pressure is 10-50 Torr, and the second preset time is 3-5 min;
[0021] In step S5, the flow rate of H2 is 40-80 slm, the temperature of the deposition chamber is 750-800 DEG C, the pressure is 80-100 Torr, and the third preset time is 3-5 min.
[0022] Optionally, the silicon substrate is a top silicon layer in an SOI wafer.
[0023] The application further provides a silicon-based germanium photodetector, comprising:
[0024] a silicon substrate;
[0025] a thermal silicon oxide layer above the silicon substrate;
[0026] a deposited silicon oxide layer above the thermal silicon oxide layer;
[0027] a vertical groove penetrating the deposited silicon oxide layer and the thermal silicon oxide layer;
[0028] a circularly-arc V-shaped groove extending from the upper surface of the silicon substrate to the interior of the silicon substrate, the bottom end of the vertical groove and the top end of the V-shaped groove being communicated;
[0029] a germanium epitaxial layer in the V-shaped groove and the vertical groove.
[0030] Optionally, the upper surface of the germanium epitaxial layer is an arc surface.
[0031] Optionally, further comprising:
[0032] a first-conductivity-type doped region in the silicon substrate;
[0033] a second-conductivity-type doped region in the silicon substrate;
[0034] wherein one side of the germanium epitaxial layer is electrically connected to the first-conductivity-type doped region, and the other side of the germanium epitaxial layer is electrically connected to the second-conductivity-type doped region.
[0035] Optionally, further comprising:
[0036] a dielectric layer above the deposited silicon oxide layer, the dielectric layer covering the germanium epitaxial layer;
[0037] a first metal layer penetrating the dielectric layer, the deposited silicon oxide layer and the thermal silicon oxide layer to be electrically connected to the first-conductivity-type doped region;
[0038] a second metal layer penetrating the dielectric layer, the deposited silicon oxide layer and the thermal silicon oxide layer to be electrically connected to the second-conductivity-type doped region.
[0039] As described above, in the silicon-based germanium photoelectric detector and the manufacturing method thereof, the V-shaped groove is formed in the silicon substrate, when the germanium epitaxial layer is deposited, the dislocation can slide outward along the inclined surface of the V-shaped groove, so that the dislocation is far away from the active light absorption area, the dark current of the photoelectric detector can be reduced, and the performance of the photoelectric detector is improved; and the tip bottom of the V-shaped groove is rounded, which can prevent the tip bottom from having adverse effects on the high-temperature reliability test, and greatly improve the reliability of the photoelectric detector. BRIEF DESCRIPTION OF DRAWINGS
[0040] Figure 1 A flow chart of the manufacturing method of the silicon-based germanium photoelectric detector in the embodiment of the present application is shown.
[0041] Figure 2 A schematic diagram of providing a silicon substrate, forming a thermal silicon oxide layer and depositing a silicon oxide layer on the silicon substrate in the embodiment of the present application is shown.
[0042] Figure 3 A schematic diagram of forming a vertical groove in the embodiment of the present application is shown.
[0043] Figure 4 A schematic diagram of forming a V-shaped groove in the embodiment of the present application is shown.
[0044] Figure 5 A schematic diagram of rounding the V-shaped groove in the embodiment of the present application is shown.
[0045] Figure 6 A schematic diagram of forming a germanium epitaxial layer in the embodiment of the present application is shown.
[0046] Figure 7 A scanning electron microscope picture of the germanium epitaxial layer in the embodiment of the present application is shown.
[0047] Figure 8 A schematic diagram of forming a dielectric layer in the embodiment of the present application is shown.
[0048] Figure 9 A schematic diagram of forming a first contact hole and a second contact hole in the embodiment of the present application is shown.
[0049] Figure 10 A schematic diagram of forming a first metal layer and a second metal layer in the embodiment of the present application is shown.
[0050] Figure 11 A dark current data graph of the embodiment of the present application without high-temperature storage is shown.
[0051] Figure 12 A dark current data graph of the embodiment of the present application after high-temperature storage is shown.
[0052] Figure 13The dark current data after high-temperature storage is shown in the graph.
[0053] Figure 14 The electron microscope picture of the germanium epitaxial layer in Comparative Example One is shown.
[0054] Figure 15 The dark current data without high-temperature storage in Comparative Example One is shown in the graph.
[0055] Figure 16 The electron microscope picture of the germanium epitaxial layer in Comparative Example Two is shown.
[0056] Figure 17 The dark current data without high-temperature storage in Comparative Example Two is shown in the graph.
[0057] Figure 18 The dark current data after high-temperature storage in Comparative Example Two is shown in the graph.
[0058] Figure 19 The change of the dark current data after high-temperature storage compared with that before high-temperature storage in Comparative Example Two is shown in the graph.
[0059] Element number explanation: 1-SOI wafer, 100-base silicon layer, 101-buried oxygen layer, 102-top silicon layer; 2-first conductive type doped region; 3-second conductive type doped region; 4-thermal silicon oxide layer; 5-deposited silicon oxide layer; 6-vertical groove; 7-V-shaped groove; 8-germanium epitaxial layer; 9-dielectric layer; 10-first contact hole; 11-second contact hole; 12-first metal layer; 13-second metal layer. DETAILED DESCRIPTION
[0060] The embodiments of the present application will be described herein below with reference to specific embodiments. Other advantages and effects of the present application, which can be easily understood by those skilled in the art, can be easily obtained from this description. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in this description based on different views and applications without departing from the spirit of the present application.
[0061] Please refer to Figures 1 to 19 . It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be randomly changed in terms of shape, number and proportion, and the layout pattern of the components can also be more complex.
[0062] This embodiment provides a manufacturing method of a silicon-based germanium photodetector, please refer to Figure 1 , which comprises the following steps:
[0063] S1: Provide a silicon substrate, and form a stacked thermal silicon oxide layer and a deposited silicon oxide layer on the silicon substrate;
[0064] S2: Forming a vertical groove that extends from the upper surface of the deposited silicon oxide layer into the silicon substrate;
[0065] S3: Place the structure after forming the vertical groove in the deposition chamber, introduce H2 into the deposition chamber, and bake for a first preset time under the H2 atmosphere;
[0066] S4: H2 and HCl are introduced into the deposition chamber, and the substrate is baked for a second preset time under the atmosphere of H2 and HCl, so that the vertical groove in the silicon substrate is transformed into a V-shaped groove.
[0067] S5: H2 is introduced into the deposition chamber, and the chamber is baked for a third preset time under the H2 atmosphere to make the V-shaped groove rounded. The rounded V-shaped groove and the vertical groove above the V-shaped groove together form a deposition groove.
[0068] S6: A germanium epitaxial layer is formed in the deposition groove.
[0069] The fabrication method of the silicon-based germanium photodetector in this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0070] First, please refer to Figure 2 Step S1: Provide a silicon substrate, and form a stacked thermal silicon oxide layer 4 and a deposited silicon oxide layer 5 on the silicon substrate.
[0071] As an example, in this embodiment, the silicon substrate is the top silicon layer 102 of SOI wafer 1. SOI wafer 1 includes a base silicon layer 100, a buried oxide layer 101, and a top silicon layer 102 arranged from bottom to top. Using SOI wafer 1 as the supporting substrate for the detector, the buried oxide layer 101 provides good electrical isolation, effectively reducing parasitic capacitance and leakage current between the device and the base silicon layer 100, thereby improving the detector's response speed and sensitivity. Furthermore, SOI wafers support the integration of various passive devices (such as waveguides, gratings, and couplers) and active devices (such as modulators and detectors) on the same substrate, which is beneficial for realizing complex photonic integrated circuits. In another example, the silicon substrate can also be a silicon wafer, and this embodiment is not a limitation.
[0072] As an example, before forming the thermal oxide layer 4 and the deposited oxide layer 5 on the top silicon layer 102, the method further comprises the step of forming a first conductive type doped region 2 and a second conductive type doped region 3 in the top silicon layer 102, wherein the first conductive type and the second conductive type are opposite. In the embodiment, the first conductive type doped region 2 is a P-type doped region, and the second conductive type doped region 3 is an N-type doped region.
[0073] As an example, the top surface of the top silicon layer 102 is oxidized to form the thermal oxide layer 4 by a thermal oxidation process, and then the deposited oxide layer 5 is formed on the thermal oxide layer 4 by a chemical vapor deposition process. By thermal oxidation of the top surface of the top silicon layer 102, the interface state density between the thermal oxide layer 4 and the top silicon layer 102 is extremely low, which can greatly reduce the surface defects of the top silicon layer 102 and significantly reduce the dark current (especially the edge leakage) from the top silicon layer / thermal oxide layer interface; in addition, the thermal oxide layer 4 has excellent compactness, uniformity and stability, which provides a flat and clean platform for the deposited oxide layer 5 and improves the quality of the deposited oxide layer 5.
[0074] Next, referring to Figure 3 , step S2 is performed: forming a vertical recess 6 extending from the upper surface of the deposited oxide layer 5 into the silicon substrate.
[0075] As an example, a photoresist layer is formed on the upper surface of the deposited oxide layer 5 and is patterned, and the patterned photoresist layer defines the position of the vertical recess 6, and then the deposited oxide layer 5, the thermal oxide layer 4 and the top silicon layer 102 are etched with the patterned photoresist layer as a mask to form the vertical recess 6.
[0076] As an example, the dry etching process is used to form the vertical recess 6, and the anisotropy of dry etching makes the sidewall of the vertical recess 6 relatively vertical.
[0077] As an example, after the dry etching process is used to form the vertical recess 6, a wet cleaning process is used to remove the etching by-products.
[0078] As an example, after the vertical recess 6 is formed, the photoresist layer is removed.
[0079] As an example, in the embodiment, the opening size CD of the vertical groove 6 is 300-800 nm, and the depth of the vertical groove 6 in the top silicon layer 102 is 100-120 nm, which is conducive to the subsequent formation of the V-shaped groove in the top silicon layer 102. If the opening size CD of the vertical groove 6 is too large, since the topography structure formed by process optimization is limited, the subsequent V-shaped groove cannot be effectively formed.
[0080] Next, step S3 is performed: the structure after the vertical groove 6 is formed is placed in a deposition chamber, H2 is introduced into the deposition chamber, and the first preset time is baked under the H2 atmosphere.
[0081] As an example, the deposition chamber is an epitaxial process chamber, the flow rate of H2 introduced into the deposition chamber is 40-80 slm (standard liters per minute), the temperature of the deposition chamber is 850-950°C (degrees Celsius), the pressure is 10-50 Torr (torr), and the baking time is 5-8 min (minutes). Through H2 baking, carbon, oxygen and other impurities on the surface of the top silicon layer 102 are removed.
[0082] Next, referring to Figure 4 , step S4 is performed: H2 and HCl are introduced into the deposition chamber, and the second preset time is baked under the H2 atmosphere and the HCl atmosphere, so that the vertical groove 6 in the silicon substrate is converted into a V-shaped groove 7.
[0083] As an example, the flow rate of H2 introduced into the deposition chamber is 40-80 slm, the flow rate of HCl introduced is 100-300 sccm (standard cubic centimeters per minute), the temperature of the deposition chamber is 850-950°C, the pressure is 10-50 Torr, and the second preset time is 3-5 min, that is, on the basis of step S3, the temperature and pressure of the deposition chamber are not changed, and on the basis of introducing H2, HCl gas is also introduced for baking. Under the hydrogen environment, the exposed silicon atoms in the vertical groove 6 are subjected to energy migration (Si Move), and the silicon surface tends to have a low surface potential topography, which tends to be circular. At the same time, due to the etching effect of HCl on silicon, the V-shaped groove 7 is formed in the top silicon layer 102.
[0084] Next, referring to Figure 5 , step S5 is performed: H2 is introduced into the deposition chamber, and the third preset time is baked under the H2 atmosphere, so that the V-shaped groove 7 is circularly arcuate, and the circularly arcuate V-shaped groove 7 and the vertical groove 6 located above the V-shaped groove 7 together constitute a deposition groove.
[0085] As an example, the flow rate of H2 introduced into the deposition chamber is 40-80 slm, the temperature of the deposition chamber is 750-800℃, the pressure is 80-100 Torr, and the third preset time is 3-5 min. Since the bottom of the V-shaped groove 7 formed in step S4 is a pointed structure, the pointed structure can cause the following problems: (1) a pointed stress and a through defect caused by a lattice mismatch between silicon and germanium; (2) a local electric field can be greatly increased due to a very small radius of curvature of the pointed structure; and (3) a local high-temperature hot spot can cause heat to accumulate at the pointed structure. By means of the hydrogen baking in step S5, the V-shaped groove 7 is rounded by silicon migration, the pointed bottom of the V-shaped groove 7 can be converted into a rounded bottom, and the reliability of the device can be improved to prevent the pointed bottom from having an adverse effect on a subsequent high-temperature reliability test.
[0086] Next, referring to Figure 6 , step S6 is performed: forming the germanium epitaxial layer 8 in the deposition groove.
[0087] As an example, the selective epitaxial growth method is used to form the germanium epitaxial layer 8 in the deposition groove, and the upper surface of the germanium epitaxial layer 8 is an arc surface, which can increase the light absorption area and ensure the responsivity of the device.
[0088] As an example, when the germanium epitaxial layer 8 is formed, a dislocation can be generated due to a lattice mismatch between silicon and germanium. Silicon and germanium are diamond cubic structures, and the (111) crystal plane is the first crystal plane for dislocation slip. In the present application, since the bottom of the deposition groove is a V-shaped groove, the dislocation can slip outward along the (111) crystal plane of the inclined surface of the V-shaped groove 7, so that the dislocation is far away from the active light absorption area, i.e., the dislocation is pushed to the edge of the groove or the deep part of the top silicon layer 102, thereby reducing the dark current of the photodetector and improving the performance of the photodetector.
[0089] As an example, referring to Figure 7 , which shows an electron microscope picture of the germanium epitaxial layer formed in the embodiment of the present application. The bottom of the formed germanium epitaxial layer 8 falls in the V-shaped groove, and the top surface of the formed germanium epitaxial layer 8 is an arc surface.
[0090] As an example, after the germanium epitaxial layer 8 is formed, the following steps are further included:
[0091] S7: as shown in Figure 8 , a dielectric layer 9 is formed on the surface of the deposited silicon oxide layer 5, and the dielectric layer 9 covers the germanium epitaxial layer 8;
[0092] S8: as shown in Figure 9As shown, a first contact hole 10 is formed through the dielectric layer 9, the deposited silicon oxide layer 5 and the thermal silicon oxide layer 4, the first contact hole 10 exposing the first conductive type doped region 2, a second contact hole 11 is formed through the dielectric layer 9, the deposited silicon oxide layer 5 and the thermal silicon oxide layer 4, the second contact hole 11 exposing the second conductive type doped region 3;
[0093] S9: As Figure 10 shown, the first metal layer 12 is filled with metal in the first contact hole 10, the second metal layer 13 is filled with metal in the second contact hole 11, the first metal layer 12 is electrically connected with the first conductive type doped region 2, and the second metal layer 13 is electrically connected with the second conductive type doped region 3.
[0094] As an example, after the first metal layer 12 and the second metal layer 13 are formed, a step of reliability test is further included.
[0095] As an example, please refer to Figure 11 , which shows a dark current data graph without high temperature storage in the embodiment of the present application, wherein the reverse bias voltage for testing is -1V, the unit of dark current is ampere (A), a plurality of photodetector units are formed on a SOI wafer, the width of the germanium absorption module in each photodetector unit is 0.5μm, and the length is 20μm, from Figure 11 it can be known that the dark current is less than 40nA under the condition of -1V reverse bias voltage.
[0096] As an example, please refer to Figure 12 , which shows a dark current data graph after high temperature storage in the embodiment of the present application, wherein the dark current is tested under the condition of 150℃ storage for 500 hours, and the reverse bias voltage for testing is -1V. Please refer to Figure 13 , which shows a dark current data change graph after high temperature storage compared with that before high temperature storage in the embodiment of the present application, from Figure 13 it can be known that the dark current data change is less than 5% after 500 hours of high temperature storage under the condition of -1V reverse bias voltage, and the industry-recognized qualified standard is less than 15%, that is, the silicon-based germanium photodetector of the present application has extremely high reliability.
[0097] As an example, please refer to Figure 14 , which shows a scanning electron microscope (SEM) picture of the germanium epitaxial layer in Comparative Example 1, wherein the bottom surface of the groove in the silicon substrate is a conventional plane; please refer to Figure 15 , which shows a dark current data graph without high temperature storage in Comparative Example 1, wherein the dark current is greater than 50nA under the condition of -1V reverse bias voltage, indicating that the photodetector of the present application has a smaller dark current.
[0098] As an example, please refer toFigure 16 , which is an electron microscope picture of the germanium epitaxial layer in the second comparative example, in which the V-shaped groove of the silicon substrate is not arc-shaped, i.e., the bottom of the V-shaped groove is a pointed structure. Please refer to Figure 17 , which is a dark current data chart of the second comparative example without high-temperature storage; please refer to Figure 18 , which is a dark current data chart of the second comparative example after high-temperature storage, in which the dark current test is performed at 150℃ for 168 hours, and the reverse bias voltage is -1V; please refer to Figure 19 , which is a dark current data change chart of the second comparative example after high-temperature storage compared with that before high-temperature storage, in which the dark current change of most photodetectors exceeds the qualified value (15%), i.e., in the second comparative example, the photodetector is invalid after being stored at 150℃ for 168 hours, while in the present application, the dark current data change is less than 5% after being stored at 150℃ for 500 hours, which indicates that the photodetector of the present application has extremely high reliability.
[0099] As described above, in the manufacturing method of the silicon-based germanium photodetector of the present embodiment, the V-shaped groove is formed in the silicon substrate, and when the germanium epitaxial layer is deposited, the dislocation can slip outward along the inclined surface of the V-shaped groove, so as to make the dislocation away from the active light absorption region, which can reduce the dark current of the photodetector and improve the performance of the photodetector; and the pointed bottom of the V-shaped groove is arc-shaped, which can prevent the pointed bottom from having an adverse effect on the high-temperature reliability test, and greatly improve the reliability of the photodetector.
[0100] Thus, a silicon-based germanium photodetector is prepared, please refer to Figure 10 , which comprises a silicon substrate, a thermal silicon oxide layer 4, a deposited silicon oxide layer 5, a vertical groove, an arc-shaped V-shaped groove and a germanium epitaxial layer 8, wherein the thermal silicon oxide layer 4 is located above the silicon substrate; the deposited silicon oxide layer 5 is located above the thermal silicon oxide layer 4; the vertical groove penetrates through the deposited silicon oxide layer 5 and the thermal silicon oxide layer 4; the arc-shaped V-shaped groove extends from the upper surface of the silicon substrate to the inside of the silicon substrate, and the bottom end of the vertical groove and the top end of the V-shaped groove are communicated; and the germanium epitaxial layer 8 is located in the V-shaped groove and the vertical groove.
[0101] As an example, in the embodiment, the silicon substrate is a top silicon layer 102 in an SOI wafer 1, the SOI wafer 1 comprises a base silicon layer 100, a buried oxide layer 101 and the top silicon layer 102 arranged from bottom to top, the SOI wafer 1 is used as a support substrate of the detector, the buried oxide layer 101 provides good electrical isolation, can effectively reduce the parasitic capacitance and leakage current between the device and the base silicon layer 100, and improve the response speed and sensitivity of the detector; and the SOI wafer supports multiple passive devices (such as waveguides, gratings, couplers) and active devices (such as modulators, detectors) on the same substrate, which is conducive to realizing a complex photonic integrated circuit. In another example, the silicon substrate can also use a silicon wafer, which is not limited to the embodiment.
[0102] As an example, the first conductive type doped region 2 and the second conductive type doped region 3 are also included, both of which are located in the silicon substrate, one side of the germanium epitaxial layer 8 is electrically connected with the first conductive type doped region 2, and the other side of the germanium epitaxial layer 8 is electrically connected with the second conductive type doped region 3. Wherein, the first conductive type and the second conductive type are opposite, specifically, in the embodiment, the first conductive type doped region 2 is a P-type doped region, and the second conductive type doped region 3 is an N-type doped region.
[0103] As an example, the upper surface of the germanium epitaxial layer 8 is an arc surface, which can increase the light absorption area and ensure the responsivity of the device.
[0104] As an example, the following are also included:
[0105] The medium layer 9 is located above the deposited silicon oxide layer 5, and the medium layer 9 covers the germanium epitaxial layer 8;
[0106] The first metal layer 12 penetrates through the medium layer 9, the deposited silicon oxide layer 5 and the thermal silicon oxide layer 4 to be electrically connected with the first conductive type doped region 2;
[0107] The second metal layer 13 penetrates through the medium layer 9, the deposited silicon oxide layer 5 and the thermal silicon oxide layer 4 to be electrically connected with the second conductive type doped region 3.
[0108] In summary, in the silicon-based germanium photodetector and manufacturing method, the V-shaped groove is formed in the silicon substrate, when the germanium epitaxial layer is deposited, the dislocation can slide outward along the inclined surface of the V-shaped groove, so that the dislocation is far away from the active light absorption area, which can reduce the dark current of the photodetector and improve the performance of the photodetector; and the tip bottom of the V-shaped groove is rounded, which can prevent the tip bottom from having an adverse effect on the high-temperature reliability test, and greatly improve the reliability of the photodetector. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.
[0109] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any modification or change made by those skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.
Claims
1. A method for fabricating a silicon-based germanium photodetector, characterized in that, Includes the following steps: S1: Provide a silicon substrate, form a first conductivity type doped region and a second conductivity type doped region in the silicon substrate, and form a stacked thermal silicon oxide layer and a deposited silicon oxide layer on the silicon substrate; S2: Forming a vertical groove that extends from the upper surface of the deposited silicon oxide layer into the silicon substrate; S3: Place the structure after forming the vertical groove in the deposition chamber, introduce H2 into the deposition chamber, and bake for a first preset time under the H2 atmosphere; S4: H2 and HCl are introduced into the deposition chamber, and the substrate is baked for a second preset time under the atmosphere of H2 and HCl, so that the vertical groove in the silicon substrate is transformed into a V-shaped groove. S5: H2 is introduced into the deposition chamber, and the chamber is baked for a third preset time under the H2 atmosphere to make the V-shaped groove rounded. The rounded V-shaped groove and the vertical groove above the V-shaped groove together form a deposition groove. S6: A germanium epitaxial layer is formed in the deposition groove using selective epitaxial growth. The upper surface of the germanium epitaxial layer is an arc-shaped surface. One side of the germanium epitaxial layer is electrically connected to the first conductivity type doped region, and the other side of the germanium epitaxial layer is electrically connected to the second conductivity type doped region.
2. The method for fabricating a silicon-based germanium photodetector according to claim 1, characterized in that, After forming the germanium epitaxial layer, the method further includes the following steps: S7: A dielectric layer is formed on the deposited silicon oxide layer, the dielectric layer covering the germanium epitaxial layer; S8: A first contact hole is formed penetrating the dielectric layer, the deposited silicon oxide layer, and the thermally heated silicon oxide layer, the first contact hole exposing the first conductivity type doped region; a second contact hole is formed penetrating the dielectric layer, the deposited silicon oxide layer, and the thermally heated silicon oxide layer, the second contact hole exposing the second conductivity type doped region. S9: A first metal layer is formed by filling the first contact hole with metal, and a second metal layer is formed by filling the second contact hole with metal. The first metal layer is electrically connected to the first conductivity type doped region, and the second metal layer is electrically connected to the second conductivity type doped region.
3. The method for fabricating a silicon-based germanium photodetector according to claim 1, characterized in that: In step S3, the flow rate of H2 is 40~80 slm, the temperature of the deposition chamber is 850~950℃, the pressure is 10~50 Torr, and the first preset time is 5~8 min; In step S4, the flow rate of H2 is 40~80 slm, the flow rate of HCl is 100~300 sccm, the temperature of the deposition chamber is 850~950℃, the pressure is 10~50 Torr, and the second preset time is 3~5 min; In step S5, the flow rate of H2 is 40~80 slm, the temperature of the deposition chamber is 750~800℃, the pressure is 80~100 Torr, and the third preset time is 3~5 min.
4. The method for fabricating a silicon-based germanium photodetector according to claim 1, characterized in that: The silicon substrate is the top silicon layer in an SOI wafer.
5. A silicon-based germanium photodetector, characterized in that, include: silicon substrate; A first conductivity type doped region is located in the silicon substrate; A second conductivity type doped region is located in the silicon substrate; A thermally oxidized silicon layer is located above the silicon substrate; A silicon oxide layer is deposited above the thermally heated silicon oxide layer; A vertical groove extends through the deposited silicon oxide layer and the thermally heated silicon oxide layer into the silicon substrate, wherein the vertical groove located in the silicon substrate is transformed into a rounded V-shaped groove after baking under H2 atmosphere; A germanium epitaxial layer is located in the V-groove and the vertical groove. The upper surface of the germanium epitaxial layer is an arc-shaped surface. One side of the germanium epitaxial layer is electrically connected to the first conductivity type doped region, and the other side of the germanium epitaxial layer is electrically connected to the second conductivity type doped region.
6. The silicon-based germanium photodetector according to claim 5, characterized in that, Also includes: A dielectric layer is located above the deposited silicon oxide layer, and the dielectric layer covers the germanium epitaxial layer; A first metal layer extends through the dielectric layer, the deposited silicon oxide layer, and the thermally heated silicon oxide layer to be electrically connected to the first conductivity type doped region; A second metal layer extends through the dielectric layer, the deposited silicon oxide layer, and the thermally heated silicon oxide layer to be electrically connected to the doped region of the second conductivity type.
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