Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a base layer; a circuit layer on the base layer, and the circuit layer includes a power line; a first electrode on the circuit layer; an auxiliary electrode on the power line; an emission layer on the first electrode and the auxiliary electrode; and a second electrode electrically connected to the auxiliary electrode. The emission layer has a plurality of opening portions overlapping the auxiliary electrode. The power line includes a first line portion and a second line portion. The plurality of opening portions includes a plurality of first opening portions and a plurality of second opening portions. When viewed in the second direction, the plurality of first opening portions are spaced apart from each other by "2a" in the first direction, where "a" is a positive real number, and one first opening portion and one second opening portion adjacent to the first opening portion are spaced apart from each other by "a".

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0036991 filed in the Korean Intellectual Property Office on March 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device having improved reliability, and a method for manufacturing the display device. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, or game consoles include a display panel to display images. The display panel may include a plurality of pixels. Each pixel may include a light-emitting element for generating light and a driver element connected to the light-emitting element.

[0005] Display panels including organic light-emitting elements (OLEDs), among various light-emitting elements, offer wider viewing angles, faster response times, and lower power consumption. Consequently, OLED display panels have attracted attention as next-generation display panels. However, as the area of ​​electronic devices increases, the brightness of the display panel may become irregular.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] Embodiments of the present disclosure may be directed to a display device having improved reliability, and a method for manufacturing the display device.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a base layer; a circuit layer on the base layer, and the circuit layer includes a power line configured to provide a power supply voltage; a first electrode on the circuit layer; an auxiliary electrode on the circuit layer, and the auxiliary electrode is located on the power line; an emission layer on the first electrode and the auxiliary electrode; and a second electrode on the emission layer, and the second electrode is electrically connected to the auxiliary electrode. The emission layer has a plurality of opening portions overlapping with the auxiliary electrode. The power line includes: a first line portion extending in a first direction; and a second line portion extending in the first direction, and the second line portion is spaced apart from the first line portion in a second direction intersecting the first direction. The plurality of opening portions include: a plurality of first opening portions overlapping with the first line portion in a plan view; and a plurality of second opening portions overlapping with the second line portion in a plan view. When viewed in the second direction, the multiple first opening portions are spaced apart from each other by "2a" in the first direction, where "a" is a positive real number, and a first opening portion from among the multiple first opening portions and a second opening portion adjacent to the first opening portion from among the multiple second opening portions are spaced apart from each other by "a".

[0009] In an embodiment, in a plan view, the one first opening portion may be spaced apart from the one second opening portion in a direction crossing the first direction and the second direction.

[0010] In an embodiment, the first electrode and the auxiliary electrode may be located in the same layer as each other.

[0011] In an embodiment, the first line portion and the second line portion may be spaced apart from each other by '2a' in the second direction.

[0012] In an embodiment, the plurality of first opening portions may not overlap with the plurality of second opening portions when viewed in the second direction.

[0013] In an embodiment, the base layer may include a display area and a non-display area adjacent to the display area. The plurality of opening portions may further include an auxiliary opening portion, the auxiliary opening portion being spaced apart from another second opening portion adjacent to the non-display area from among the plurality of second opening portions in the second direction, and the auxiliary opening portion overlapping the first line portion.

[0014] In an embodiment, the auxiliary opening portion can be spaced apart from the other second opening portion by "2a" in the second direction, and the auxiliary opening portion can be spaced apart from another first opening portion adjacent to the auxiliary opening portion from among multiple first opening portions in the first direction by "a".

[0015] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: providing a target substrate including a first electrode and an auxiliary electrode; stacking an emission layer on the first electrode and the auxiliary electrode; forming a plurality of opening portions penetrating the emission layer by irradiating a laser beam; and forming a second electrode on the emission layer, and the second electrode is electrically connected to the auxiliary electrode. The plurality of opening portions include: a plurality of first opening portions arranged along a first direction; and a plurality of second opening portions spaced apart from the plurality of first opening portions in a second direction intersecting the first direction, and the plurality of second opening portions are arranged along the first direction. The forming of the plurality of opening portions includes forming the plurality of first opening portions spaced apart from each other by "2a" in the first direction in a plan view, where "a" is a positive real number, and in a plan view, one first opening portion from among the plurality of first opening portions is spaced apart from one second opening portion adjacent to the one first opening portion from among the plurality of second opening portions in a direction intersecting the first direction and the second direction.

[0016] In an embodiment, the one first opening portion and the one second opening portion may be spaced apart from each other by “a” when viewed in the second direction.

[0017] In an embodiment, providing the target substrate may include disposing the first electrode and the auxiliary electrode in the same layer as each other.

[0018] However, the present disclosure is not limited to the above-mentioned aspects and features, and the above-mentioned and additional aspects and features will be set forth in part in the detailed description that follows with reference to the accompanying drawings, and in part may become apparent from the description, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0020] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0021] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0022] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0023] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0024] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure.

[0025] Figure 6 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0026] Figure 7 This is a diagram showing an embodiment of the present disclosure. Figure 2 An enlarged plan view of area AA'.

[0027] Figure 8 According to the embodiment of the present disclosure Figure 7 A cross-sectional view taken along line II'.

[0028] Figure 9 According to the embodiment of the present disclosure Figure 7 A cross-sectional view taken along line II-II'.

[0029] Figure 10 is a plan view illustrating power lines and a plurality of opening portions according to an embodiment of the present disclosure.

[0030] Figure 11 is a flowchart of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0031] 12A to 12C 2 is a cross-sectional view corresponding to a process in a method for manufacturing a display device according to an embodiment of the present disclosure.

[0032] Figure 13 is a plan view showing a portion of a display device according to an embodiment of the present disclosure.

[0033] Figure 14 is a plan view showing a portion of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always indicate the same elements. However, the present disclosure can be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, in the description of the drawings and the specification, the same reference numerals always refer to the same elements, and therefore, their redundant descriptions may not be repeated.

[0035] When a specific embodiment can be implemented in different ways, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0036] In addition, unless otherwise stated or implied, as will be understood by those skilled in the art, in view of the entire content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole, or in combination with each other, and may be technically interlocked and operated in various suitable manners, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0037] In the accompanying drawings, for the sake of clarity, the relative sizes, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. Spatial relative terms (such as "under...", "below...", "below...", "below...", "above...", and "on...", etc.) may be used herein to describe, for ease of explanation, the relationship between an element or a feature and another element (other multiple elements) or another feature (other multiple features) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the accompanying drawings, the element described as "under" or "below" or "below" other elements or features will then be oriented as "above" other elements or features. Therefore, the example terms "under..." and "below..." can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0038] Furthermore, it should be anticipated that the shapes shown in the drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of the present disclosure should not be construed as limited to the specific shapes shown in the drawings, but rather should take into account variations in shape that may occur, for example, due to manufacturing. Therefore, the shapes shown in the drawings may not depict the actual shape of a region of the device, and the present disclosure is not limited thereto.

[0039] In the drawings, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0040] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part without departing from the spirit and scope of the present disclosure.

[0041] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being “electrically connected to” another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements positioned therebetween. Furthermore, it will be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0042] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that, when used in this specification, the terms "comprises, comprising", "includes, including", and "has, has, having" illustrate the presence of stated features, integral bodies, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components, and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. For example, the statement "A and / or B" represents A, B, or A and B. When used after a list of elements, statements such as "at least one (kind / person) in ... " modify the entire list of elements rather than modifying the individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, c, or variations thereof.

[0043] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "using," "being used," and "has been used" may be considered synonymous with the terms "utilizing," "being utilized," and "has been utilized," respectively.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined otherwise herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0045] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0046] Reference Figure 1, the display device DD can be activated in response to the electrical signal to display the image IM. According to various embodiments, the display device DD can include various form factors. For example, in some embodiments, the display device DD can be a small or medium-sized electronic device such as a monitor, a mobile phone, a tablet personal computer (PC), a navigation device, or a game console. In some embodiments, the display device DD can be a large electronic device such as a television or an external billboard. However, the present disclosure is not limited to this, and the display device DD is not limited to any particular embodiment.

[0047] In a plan view, the display device DD may have a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. However, the present disclosure is not limited thereto, and the display device DD may have various suitable shapes such as a circle or other polygons.

[0048] The display device DD can display an image IM on a display surface IS in a third direction DR3, where the display surface IS is parallel or substantially parallel to a plane defined in the first direction DR1 and the second direction DR2. The third direction DR3 can be parallel or substantially parallel to the normal direction. The display surface IS for displaying the image IM can correspond to the front surface of the display device DD. The image IM can include a still image and / or a dynamic image. Figure 1 Icon images are shown by way of some examples of images IM.

[0049] According to an embodiment, the front side (e.g., top side) and back side (e.g., bottom side) of a component or unit are defined based on the direction used to display the image IM. The front side and back side face away from each other in the third direction DR3, and the normal directions of the front side and back side can be parallel or substantially parallel to the third direction DR3. The distance between the front side and back side defined in the third direction DR3 can correspond to the thickness of the component (or unit). According to an embodiment, the third direction DR3 can be referred to as the "thickness direction."

[0050] As used herein, the phrase "in a plan view" may refer to a state when viewed in the third direction DR3. The phrase "in a cross-sectional view" may refer to a state when viewed in the first direction DR1 or the second direction DR2. However, the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and may be changed to different appropriate directions.

[0051] The display device DD may be a flexible display device. The "flexible" characteristic refers to the ability to bend, and flexible structures may include any suitable structure, ranging from fully foldable structures to structures that bend on the order of a few nanometers. For example, the flexible display device DD may include a bendable device or a foldable device. However, the present disclosure is not limited thereto. For example, the display device DD may be rigid.

[0052] The display surface IS of the display device DD may include an active area D-DA and a peripheral area D-NDA. An image IM may be displayed in the active area D-DA. A user may view the image IM through the active area D-DA. Although the active area D-DA is shown as having a rectangular shape in plan view according to an embodiment, the present disclosure is not limited thereto. For example, the active area D-DA may have various suitable shapes.

[0053] The peripheral area D-NDA may not display the image IM. The peripheral area D-NDA may correspond to a portion having a suitable color (e.g., a specific or predetermined color) to block light. The peripheral area D-NDA may be adjacent to the active area D-DA. For example, the peripheral area D-NDA may be disposed outside the active area D-DA to surround the active area D-DA (e.g., around the periphery of the active area D-DA). However, the present disclosure is not limited thereto. For example, the peripheral area D-NDA may be adjacent to only one side of the active area D-DA, or may be disposed on the side of the display device DD rather than on the front of the display device DD. However, the present disclosure is not limited thereto, and the peripheral area D-NDA may be omitted as needed or desired.

[0054] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 2 , the display device DD may include a window WM, a display module (eg, a display or a touch display) DM, and a housing HAU. The display module DM may include a display panel DP and a light control member LCM.

[0056] The window WM may be connected to (eg, coupled to or attached to) the housing HAU to define an appearance of the display device DD and to provide an internal space to accommodate components in the display device DD.

[0057] The window WM may be provided on the display module DM. The window WM may protect the display module DM from external impact. The front surface of the window WM may correspond to the display surface IS of the display device DD (eg, see FIG. 1 ). Figure 1 ). The front surface of the window WM may include a transmissive area TA and a frame area BA.

[0058] The transmission area TA of the window WM may be an optically transparent area. The window WM may transmit an image provided by the display module DM through the transmission area TA, and a user may view the image. The transmission area TA may correspond to the active area D-DA of the display device DD (e.g., see FIG. Figure 1 ).

[0059] The window WM may comprise an optically transparent insulating material. For example, the window WM may comprise glass, sapphire, or plastic. The window WM may have a single-layer structure or a multi-layer structure. The window WM may also include a functional layer such as an anti-fingerprint layer, a phase control layer, or a hard coating layer disposed on an optically transparent substrate.

[0060] The frame area BA of the window WM may be provided by depositing, coating, or printing a suitable material including a suitable color (e.g., a specific or predetermined color). The frame area BA of the window WM may prevent or substantially prevent components of the display module DM that are arranged to overlap with the frame area BA from being seen from the outside. The frame area BA may correspond to a peripheral area D-NDA of the display device DD (e.g., see FIG. Figure 1 ).

[0061] The display module DM may be located (eg, inserted) between the window WM and the housing HAU. The display module DM may display an image in response to an electrical signal. The display module DM may include a display area DA and a non-display area NDA adjacent to the display area DA.

[0062] The display area DA can be activated in response to an electrical signal. The display area DA can be defined as an area for outputting an image provided by the display area DA. The display area DA of the display module DM can correspond to the aforementioned transmissive area TA. As used herein, the phrase "an area / portion corresponds to another area / portion" may mean that the area / portion overlaps with the other area / portion, and does not mean that the areas / portions are identical in area and / or shape. The image displayed in the display area DA can be viewed from the outside through the transmissive area TA.

[0063] The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA (e.g., around the periphery of the display area DA). However, the present disclosure is not limited thereto, and the non-display area NDA may be defined in various suitable shapes. A driving circuit or driving line for driving the display area DA and / or various signal lines or pads for applying electrical signals may be provided in the non-display area NDA. The non-display area NDA of the display module DM may correspond to the above-mentioned border area BA. The components of the display module DM provided in the non-display area NDA may be prevented or substantially prevented from being seen from the outside through the border area BA.

[0064] According to an embodiment of the present disclosure, the display panel DP may be an emissive display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro light-emitting diode (LED) light-emitting display panel, or a nano-LED light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. The light-emitting layer of the micro-LED display panel may include micro-LEDs. The light-emitting layer of the nano-LED display layer may include nano-LEDs.

[0065] The light control member LCM may be provided on the display panel DP. After being provided on the display panel DP, the light control member LCM may be connected to (e.g., coupled to or attached to) the display panel DP by a bonding process using a sealing member. However, the present disclosure is not limited thereto. For example, the light control member LCM may be provided directly on the display panel DP. As used herein, the phrase “directly provided” may refer to being formed by a subsequent process without the need for an additional additive layer or an additional adhesive member. For example, the statement “the light control member LCM may be provided directly on the display panel DP” may mean that after the display panel DP is formed, a component of the light control member LPM is formed on the substrate surface having the display panel DP by a subsequent process.

[0066] The light control member LCM may include a light control pattern to change the optical properties of the source light emitted from the display panel DP. The light control member LCM may selectively convert the wavelength or color of the source light or transmit the source light. The light control member LCM may control the color purity or color reproducibility of the light emitted from the display device DD and may prevent or substantially prevent external light that may be incident on the display device DD from being reflected.

[0067] The housing HAU may be disposed below the display module DM to accommodate the display module DM. The housing HAU may absorb external impact and protect the display module DM by preventing or substantially preventing foreign matter or moisture from penetrating into the display module DM. Depending on the embodiment, the housing HAU may be provided in a form in which a plurality of accommodating members are connected (e.g., coupled or attached) to each other.

[0068] In some embodiments, the display module DM may further include an input sensing unit (e.g., an input sensing layer or an input sensing panel). The input sensing unit may obtain information about the coordinates of an external input applied to the display device DD from the outside. The input sensing unit may be located (e.g., inserted) between the display panel DP and the light control member LCM. For example, the input sensing unit may be directly provided on the display panel DP through a subsequent process, but the present disclosure is not limited thereto. For example, the input sensing unit may be formed separately and attached to the display panel DP via an adhesive layer.

[0069] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0070] Reference Figure 3 , the display device DD may include an electronic module EM, a power supply module PSM, a display module DM, a window (window module) WM, and an electro-optical module ELM.

[0071] The electronic module EM may include a control module 100, a wireless communication module 200, an image input module 300, a sound input module 400, a sound output module 500, a memory 600, and an external interface module 700. These modules may be mounted on a circuit board or may be electrically connected to each other via a flexible circuit board. The electronic module EM may be electrically connected to the power supply module PSM.

[0072] The control module 100 can control the overall operation of the electronic device. For example, the control module 100 activates or deactivates the display device DD in response to user input. The control module 100 can also control the image input module 300, the sound input module 400, and the sound output module 500 in response to user input. The control module 100 may include at least one microprocessor.

[0073] The wireless communication module 200 can send and receive wireless signals to and from another terminal via Bluetooth or Wi-Fi. The wireless communication module 200 can also send and receive voice signals using a universal communication line. The wireless communication module 200 includes a transmitting circuit 220 that modulates a signal to be transmitted and transmits the modulated signal, and a receiving circuit 240 that demodulates a received signal.

[0074] The image input module 300 processes image signals and converts them into image data that can be displayed on the display device DD. The sound input module 400 receives external sound signals through a microphone in a recording mode or a voice recognition mode and converts the external sound signals into electronic voice data. The sound output module 500 converts sound data received from the wireless communication module 200 or sound data stored in the memory 600 and then outputs the converted data to the outside.

[0075] The external interface module 700 serves as an interface connected to an external charger, a wired / wireless data port, a card (eg, a memory card or a SIM / UIM card) slot.

[0076] The power supply module PSM may supply power for the overall operation of the electronic device. The power supply module PSM may include a suitable battery device.

[0077] The electro-optical module ELM may be an electronic component that outputs or receives an optical signal. The electro-optical module ELM may transmit or receive an optical signal through a partial area of ​​the display module DM. According to some embodiments of the present disclosure, the electro-optical module ELM may include a camera module CAM and a sensor module SNM.

[0078] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0079] Reference Figure 4 The display panel DP may include a base layer BS, a circuit layer DP-CL, a display element layer DP-LED, and an encapsulation layer TFE.

[0080] The base layer BS may include a display area DA and a non-display area NDA. The base layer BS may provide a base surface for setting the circuit layer DP-CL. The base layer BS may be a rigid substrate, but the present disclosure is not limited thereto. For example, the base layer BS may be a flexible substrate. The base layer BS provides a base surface that is parallel to or substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The circuit layer DP-CL, the display element layer DP-LED, and the encapsulation layer TFE may be sequentially arranged on the base surface of the base layer BS. The third direction DR3 may be a direction perpendicular to or substantially perpendicular to the base surface of the base layer BS, and the circuit layer DP-CL, the display element layer DP-LED, and the encapsulation layer TFE may be sequentially arranged along the third direction DR3.

[0081] The circuit layer DP-CL may be disposed on the base layer BS. The circuit layer DP-CL may include driving elements, signal lines, and signal pads. The display element layer DP-LED may include light-emitting elements disposed to overlap the display area DA. The light-emitting elements of the display element layer DPS-LED may be electrically connected to the driving elements of the circuit layer DP-CL to provide source light through the display area DA in response to signals from the driving elements.

[0082] The encapsulation layer TFE can be provided on the display element layer DP-LED to seal the light emitting element. The encapsulation layer TFE can include multiple thin films. The thin films of the encapsulation layer TFE can be provided to improve optical efficiency and / or protect the light emitting element.

[0083] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure.

[0084] Reference Figure 5 , a display area DA and a non-display area NDA adjacent to the display area DA may be defined in the base layer BS.

[0085] The display panel DP may include pixels PX11 to PXnm disposed in a display area DA, and signal lines SL1 to SLn and DL1 to DLm electrically connected to the pixels PX11 to PXnm, where n and m are positive integers. The display panel DP may include a driving circuit GDC and pads PD disposed in a non-display area NDA.

[0086] Each of the pixels PX11 to PXnm may include a light emitting element, which will be described in more detail later, and a pixel driving circuit including a capacitor and a plurality of transistors (e.g., a switching transistor and / or a driving transistor) connected to the light emitting element. Each of the pixels PX11 to PXnm may emit light corresponding to an electrical signal applied to the corresponding pixel. Although Figure 5 The pixels PX11 to PXnm are shown arranged in a matrix form, but the arrangement of the pixels PX11 to PXnm is not limited thereto.

[0087] The signal lines SL1 to SLn and DL1 to DLm may include scan lines SL1 to SLn and data lines DL1 to DLm. Each of the pixels PX11 to PXnm may be connected to a corresponding scan line from among the scan lines SL1 to SLn and a corresponding data line from among the data lines DL1 to DLm. Depending on the desired configuration of the pixel driving circuit in each of the pixels PX11 to PXnm, a wider variety of signal lines may be provided in the display panel DP.

[0088] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the gate signal to the scan lines SL1 to SLn. The gate driving circuit may also output another control signal to the pixel driving circuits of the pixels PX11 to PXnm.

[0089] The driving circuit GDC and the pixels PX11 to PXnm according to an embodiment may include a plurality of thin film transistors formed by a low temperature polysilicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, or an oxide semiconductor process.

[0090] The pads PD may be arranged in the non-display area NDA along one direction. The pads PD may be a component connected to a circuit board. Each of the pads PD may be connected to a corresponding signal line from among the signal lines SL1 to SLn and DL1 to DLm, and may be electrically connected to a corresponding pixel through the corresponding signal line. The pads PD may have an integral shape with the signal lines SL1 to SLn and DL1 to DLm. However, the present disclosure is not limited thereto. For example, the pads PD may be provided in a layer different from the layer of the signal lines SL1 to SLn and DL1 to DLm, and may be connected to the signal lines SL1 to SLn and DL1 to DLm, respectively, through contact holes.

[0091] Figure 6 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0092] Figure 6 A pixel PXnm connected to an nth scan line SLn, an nth sensing line SSLn, an mth data line DLm, and an mth reference line RLm is shown.

[0093] Reference Figure 6 , the pixel PXnm may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC.

[0094] The pixel circuit PC may include a plurality of transistors T1, T2, and T3 and a capacitor Cst. The plurality of transistors T1, T2, and T3 may include a first transistor T1 (e.g., a drive transistor), a second transistor T2 (e.g., a switch transistor), and a third transistor T3 (e.g., a sensing transistor). The first transistor T1, the second transistor T2, and the third transistor T3 may be thin film transistors.

[0095] The first transistor T1, the second transistor T2, and the third transistor T3 may be N-type metal oxide semiconductor (NMOS) transistors, but the present disclosure is not limited thereto. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type metal oxide semiconductor (PMOS) transistors. The first transistor T1, the second transistor T2, and the third transistor T3 may include a source S1, a source S2, and a source S3, a drain D1, a drain D2, and a drain D3, and a gate G1, a gate G2, and a gate G3, respectively.

[0096] The light-emitting element OLED may be an organic light-emitting element including a first electrode AE ​​and a second electrode CE. The first electrode AE ​​may be referred to as an anode. The second electrode CE may be referred to as a cathode. The first electrode AE ​​may receive a first power supply voltage ELVDD via a driving transistor T1, and the second electrode CE may receive a second power supply voltage ELVSS. The light-emitting element OLED may receive the first power supply voltage ELVDD and the second power supply voltage ELVSS to emit light.

[0097] The driving transistor T1 may include a drain electrode D1 for receiving the first power voltage ELVDD, a source electrode S1 connected to the first electrode AE, and a gate electrode G1 connected to the capacitor Cst. The driving transistor T1 may control a driving current flowing from the first power voltage ELVDD to the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0098] The switching transistor T2 may include a drain electrode D2 connected to the mth data line DLm, a source electrode S2 connected to the capacitor Cst, and a gate electrode G2 for receiving the nth write scan signal SCn. The mth data line DLm may receive a data voltage Vd and a sense data voltage. The switching transistor T2 may transmit the data voltage Vd input from the mth data line DLm to the driving transistor T1 based on a switching voltage input from the nth write scan signal SCn.

[0099] The sensing transistor T3 may include a source S3 connected to the mth reference line RLm, a drain D3 connected to the first electrode AE, and a gate G3 for receiving the nth sampling scan signal SSn. The mth reference line RLm may receive a reference voltage Vr.

[0100] The capacitor Cst may be connected to the gate G1 of the driving transistor T1 and the first electrode AE. The capacitor Cst may include a first capacitor electrode connected to the gate G1 of the driving transistor T1 and a second capacitor electrode connected to the first electrode AE. The capacitor Cst may store a voltage corresponding to the difference between the voltage received from the switching transistor T2 and the voltage received from the first electrode AE.

[0101] However, the present disclosure is not limited to Figure 6 According to another embodiment of the present disclosure, as understood by those skilled in the art, the equivalent circuit diagram of the pixel PXnm can be implemented in various suitable forms to emit light from the light emitting element OLED.

[0102] Figure 7 This is a diagram showing an embodiment of the present disclosure. Figure 2 An enlarged plan view of area AA'.

[0103] Reference Figure 2 、 Figure 5 ,as well as Figure 7 The display panel DP may include a plurality of pixel groups PXG. The plurality of pixel groups PXG may be arranged along a first direction DR1 and a second direction DR2.

[0104] Each of the plurality of pixel groups PXG may include a plurality of pixels PX. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3.

[0105] A first pixel region PXA1 may be defined in the first pixel PX1. The first pixel region PXA1 may correspond to a region for providing first color light.

[0106] A second pixel area PXA2 may be defined in the second pixel PX2. The second pixel area PXA2 may correspond to a region for providing second color light.

[0107] A third pixel area PXA3 may be defined in the third pixel PX3. The third pixel area PXA3 may correspond to a region for providing third color light.

[0108] According to an embodiment of the present disclosure, the first to third color lights may be lights having different colors from each other. For example, the first color light may be green light, the second color light may be red light, and the third color light may be blue light. However, the present disclosure is not limited thereto.

[0109] The non-pixel region NPXA may be adjacent to the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. The non-pixel region NPXA may define a boundary between the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3, and may prevent or substantially prevent colors from being mixed between the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3.

[0110] The first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3 may have a suitable arrangement (e.g., a specific or predetermined arrangement) in the display area DA. The first pixel area PXA1 may be spaced apart from the second pixel area PXA2 and the third pixel area PXA3 in the first direction DR1. In a plan view, the second pixel area PXA2 and the third pixel area PXA3 may be arranged along the second direction DR2. For example, the center of the second pixel area PXA2 may be aligned in a straight line with the center of the third pixel area PXA3 in the second direction DR2. However, the present disclosure is not limited thereto, but the arrangement relationship between the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3 according to the embodiment of the present disclosure may be provided in various suitable manners.

[0111] In a plan view, the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a rectangular shape. Each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a rectangular shape having a size different from that of the other emission regions. The first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may be designed in various ways in shape and area based on the desired emission efficiency of the color of light emitted by the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3, and therefore, the present disclosure is not limited thereto. Figure 7For example, each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have another polygonal shape or a circular shape. As another example, the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a rectangular shape with rounded corners.

[0112] The display panel DP may include a power line EL disposed on the base layer BS to receive a second power voltage ELVSS (eg, see Figure 6 ). The power lines EL may be arranged to overlap with the non-pixel area NPXA.

[0113] The power line EL may have a linear shape extending in the first direction DR1 or the second direction DR2. The power line EL may have a grid form for surrounding the pixel electrode constituting one pixel (for example, around the periphery of the pixel electrode constituting one pixel). The power line EL may have various suitable forms without being limited to any specific embodiment, as long as the power line EL is configured to supply the second power supply voltage ELVSS to the plurality of pixels PX (for example, see Figure 6 )

[0114] The power line EL may include a first line portion ELP1 and a second line portion ELP2. The first line portion ELP1 may extend in a first direction DR1. The second line portion ELP2 may extend in the first direction DR1. The first line portion ELP1 and the second line portion ELP2 may be spaced apart from each other in a second direction DR2. A second power supply voltage ELVSS (eg, Figure 6 ) may be applied to the first line portion ELP1 and the second line portion ELP2.

[0115] The power lines EL may be connected to the second electrode CE through the plurality of opening portions OP (see, for example, FIG. Figure 6 ). The plurality of opening portions OP may include a plurality of first opening portions OP1 and a plurality of second opening portions OP2.

[0116] The plurality of first opening portions OP1 may overlap the first line portion ELP1, and the plurality of second opening portions OP2 may overlap the second line portion ELP2.

[0117] The plurality of first opening portions OP1 and the plurality of second opening portions OP2 may be arranged in a zigzag shape along the first direction DR1 .

[0118] Figure 8 According to the embodiment of the present disclosure Figure 7 A cross-sectional view taken along line II'.

[0119] Reference Figure 8The display module DM may include a display panel DP and a light control member LCM spaced apart from the display panel DP while facing the display panel DP. A cell gap GAP may be formed between the display panel DP and the light control member LCM. The cell gap GAP may be maintained by a sealant for connecting (e.g., coupling or attaching) the display panel DP to the light control member LCM. The sealant may be provided in the non-display area NDA (e.g., FIG. 1 ). Figure 5 ). According to an embodiment of the present disclosure, a synthetic resin material may be provided in the cell gap GAP. However, the present disclosure is not limited thereto, and the structure of the display module DM is not limited thereto.

[0120] A first pixel area PXA1 , a second pixel area PXA2 , a third pixel area PXA3 , and a non-pixel area NPXA may be defined in the display module DM.

[0121] The display panel DP may include a base layer BS, a circuit layer DP-CL, a display element layer DP-LED, and an encapsulation layer TFE.

[0122] The base layer BS may be a stack structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0123] The circuit layer DP-CL may include a plurality of transistors and a plurality of insulating layers IL1 , IL2 , IL3 , IL4 , and IL5 . Figure 8 1 shows a driving transistor TD from among the plurality of transistors. The plurality of insulating layers IL1, IL2, IL3, IL4, and IL5 may include a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5. The driving transistor TD may also be referred to as a first transistor T1 (e.g., see FIG. 1 ). Figure 6 ).

[0124] A first insulating layer IL1 may be disposed on the base layer BS, and a driving transistor TD may be disposed on the first insulating layer IL1. The driving transistor TD may include an active portion AD, a source electrode SD, a drain electrode DD, and a gate electrode GD.

[0125] The active portion AD, the source electrode SD, and the drain electrode DD may be regions defined based on the doping concentration or conductivity of the semiconductor pattern. The active portion AD, the source electrode SD, and the drain electrode DD may be disposed on the first insulating layer IL1. The active portion AD, the source electrode SD, and the drain electrode DD may have a higher bonding strength with the first insulating layer IL1 than with the base layer BS.

[0126] The first insulating layer IL1 may be a barrier layer for protecting the bottom surfaces of the active portion AD, the source electrode SD, and the drain electrode DD. In this case, the first insulating layer IL1 may prevent or substantially prevent contaminants or moisture from penetrating into the base layer BS or penetrating into the active portion AD, the source electrode SD, and the drain electrode DD through the base layer BS. As another example, the first insulating layer IL1 may be a light-blocking layer to block external light from entering the active portion AD through the base layer BS. In this case, the first insulating layer IL1 may further include a light-blocking material.

[0127] The second insulating layer IL2 is disposed on the first insulating layer IL1 to cover the active portion AD, the source electrode SD, and the drain electrode DD. The second insulating layer IL2 may include an inorganic material. The inorganic material may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0128] The gate GD may be disposed on the second insulating layer IL2. A third insulating layer IL3 may be disposed on the second insulating layer IL2 to cover the gate GD. The third insulating layer IL3 may be formed in a single layer or multiple layers. For example, a single layer may include an inorganic layer. Multiple layers may include an organic layer and an inorganic layer.

[0129] The gate GD may be disposed on the second insulating layer IL2. A third insulating layer IL3 may be disposed on the second insulating layer IL2 to cover the gate GD. The third insulating layer IL3 may be formed in a single layer or multiple layers. For example, a single layer may include an inorganic layer. Multiple layers may include an organic layer and an inorganic layer.

[0130] The fourth insulating layer IL4 and the fifth insulating layer IL5 may be provided on the third insulating layer IL3. Each of the fourth insulating layer IL4 and the fifth insulating layer IL5 may be formed as a single layer or multiple layers. For example, a single layer may include an organic layer. A multiple layer may include an organic layer and an inorganic layer. The fourth insulating layer IL4 and the fifth insulating layer IL5 may be planarized layers to provide a planarized surface at their upper portions.

[0131] The display element layer DP-LED may be provided on the fifth insulating layer IL5. The display element layer DP-LED may include a light emitting element OLED and a pixel defining layer PDL. According to an embodiment, the light emitting element OLED may be an organic light emitting element, but the present disclosure is not limited thereto. The pixel defining layer PDL may be an organic layer. For example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin, but the PDL material of the pixel defining layer is not limited thereto. The pixel defining layer PDL may be formed of an inorganic material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x Ny ), but the material of the pixel defining layer PDL is not limited thereto.

[0132] The pixel defining layer PDL may include a light absorbing material, or may have a suitable color (eg, a specific or predetermined color).For example, the pixel defining layer PDL may include a base resin, a mixture of a base resin and a black pigment, and / or a black pigment.

[0133] The light-emitting element OLED may include a first electrode (hereinafter referred to as a third pixel electrode) AE3, a hole control layer HCL, an emission layer EML, an electron control layer ECL, and a second electrode CE (e.g., a common electrode). The third pixel electrode AE3 may be provided separately for each pixel. The light-emitting element OLED may include a first light-emitting element overlapping with the first pixel area PXA1, a second light-emitting element overlapping with the second pixel area PXA2, and a third light-emitting element overlapping with the third pixel area PXA3. Figure 8 As shown in FIG1 , a first pixel electrode AE1 included in a first light-emitting element, a second pixel electrode AE2 included in a second light-emitting element, and a third pixel electrode AE3 included in a third light-emitting element are shown by way of example. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be referred to as a first electrode AE1, AE2, and AE3.

[0134] The first pixel electrode AE1 may be provided corresponding to the first pixel area PXA1. The second pixel electrode AE2 may be provided corresponding to the second pixel area PXA2. The third pixel electrode AE3 may be provided corresponding to the third pixel area PXA3. In this case, the phrase "corresponding to" refers to two components overlapping each other when viewed in the thickness direction DR3 of the display module DM (e.g., in a plan view), and is not limited to the two components having equal areas.

[0135] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the fifth insulating layer IL5. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be directly or indirectly electrically connected to a corresponding driving transistor. For example, the second pixel electrode AE2 may be directly or indirectly connected to Figure 8 The driving transistor TD is shown in FIG. Figure 8 In FIG, the connection structure between the second pixel electrode AE2 and the driving transistor TD is not shown.

[0136] The pixel defining layer PDL may expose a portion of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. For example, an emission opening portion PDL-OP may be defined in the pixel defining layer PDL. A portion of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be exposed through the emission opening portion PDL-OP.

[0137] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined by the emission opening portion PDL-OP, respectively. Furthermore, the first emission area EA1 may be defined corresponding to the first pixel area PXA1, the second emission area EA2 may be defined corresponding to the second pixel area PXA2, and the third emission area EA3 may be defined corresponding to the third pixel area PXA3. In this case, "corresponding to" refers to two components overlapping each other when viewed in the thickness direction DR3 of the display module DM (e.g., in a plan view), and is not limited to the two components having equal areas.

[0138] The hole control layer HCL, the emission layer EML, the electron control layer ECL, and the second electrode CE may be commonly disposed in the first pixel area PXA1, the second pixel area PXA2, the third pixel area PXA3, and the non-pixel area NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer.

[0139] The emission layer EML may have a single-layer structure or a series structure. The emission layer EML may generate blue light as the source light. The blue light may include a wavelength ranging from 410 nm to 480 nm. The emission spectrum of the blue light may have a peak wavelength ranging from 440 nm to 460 nm. The emission layer EML may be commonly provided or may be independently provided in the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3. The phrase "independently provided" means that the emission layer EML is separated for each of the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3.

[0140] The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The second electrode CE may be provided on the electron control layer ECL. The second electrode CE may be provided in common on a plurality of pixels PX11 to PXnm (eg, see Figure 5 )middle.

[0141] The second electrode CE may be formed to have light transmittance. The second electrode CE may be a semi-transmissive and semi-reflective electrode or a transmissive electrode. When the second electrode CE is provided as a transmissive electrode, the second electrode CE may include a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). When the second electrode CE is provided as a semi-transmissive and semi-reflective electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, In, Zn, Sn, or a suitable compound or mixture including at least some of the above materials (e.g., AgMg, AgYb, or MgYb), or a material having a multilayer structure such as LiF / Ca or LiF / Al. However, the present disclosure is not limited thereto. For example, the second electrode CE may have a structure including a plurality of layers, wherein the plurality of layers include a reflective film or a semi-transmissive semi-reflective film formed of at least one of the above materials, and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (ZnO) or indium tin zinc oxide (ITZO).

[0142] The encapsulation layer TFE may be disposed on the second electrode CE. For example, the encapsulation layer TFE may be disposed directly on the display element layer DP-LED. The encapsulation layer TFE may include a first inorganic encapsulation layer ITL1, an organic encapsulation layer OTL, and a second inorganic encapsulation layer ITL2 stacked in sequence. The organic encapsulation layer OTL may be inserted between the first inorganic encapsulation layer ITL1 and the second inorganic encapsulation layer ITL2. The first inorganic encapsulation layer ITL1 and the second inorganic encapsulation layer ITL2 may be formed by depositing an inorganic material, and the organic encapsulation layer OTL may be formed by depositing, printing, or coating an organic material.

[0143] The first inorganic encapsulation layer ITL1 and the second inorganic encapsulation layer ITL2 can protect the display element layer DP-LED from moisture and oxygen, and the organic encapsulation layer OTL can protect the display element layer DP-LED from foreign matter such as dust particles. The first inorganic encapsulation layer ITL1 and the second inorganic encapsulation layer ITL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic encapsulation layer OTL may be an organic layer including a polymer (such as an acrylic polymer). However, the present disclosure is not limited thereto.

[0144] although Figure 8The encapsulation layer TFE is shown to include two inorganic layers and one organic layer, but the present disclosure is not limited thereto. For example, the encapsulation layer TFE may include three inorganic layers and two organic layers. In this case, the inorganic layers and the organic layers may be stacked alternately. In some embodiments, the display panel DP may further include a refractive index control layer to improve the luminous efficiency of the upper side of the encapsulation layer TFE.

[0145] A light control member LCM may be provided on the display panel DP. The light control member LCM may include a cover base layer BL, a first color filter CF1, a second color filter CF2, a third color filter CF3, a first light control pattern WC1, a second light control pattern WC2, a third light control pattern WC3, a partition wall BW, and a plurality of insulating layers 200-1, 200-2, and 200-3, wherein the plurality of insulating layers 200-1, 200-2, and 200-3 include a first insulating layer 200-1, a second insulating layer 200-2, and a third insulating layer 200-3.

[0146] The cover base layer BL may be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers. The bottom surface BS2-B of the cover base layer BL may be flat or substantially flat.

[0147] A plurality of color filters CF1, CF2, and CF3 may be disposed on one surface of the cover base layer BL. For example, the plurality of color filters CF1, CF2, and CF3 may be disposed on the bottom surface BS2-B of the cover base layer BL. The first color filter CF1 may be disposed to overlap the first emission area EA1, the second color filter CF2 may be disposed to overlap the second emission area EA2, and the third color filter CF3 may be disposed to overlap the third emission area EA3.

[0148] The second color filter CF2 may be disposed in the second pixel region PXA2 and the non-pixel region NPXA. A plurality of openings may be defined in the second color filter CF2. The plurality of openings may define the first pixel region PXA1 and the third pixel region PXA3. The first color filter CF1 may be disposed to overlap the first pixel region PXA1, and the third color filter CF3 may be disposed to overlap the third pixel region PXA3.

[0149] The third color filter CF3 may be disposed on the partition wall BW in the non-pixel area NPXA. The first color filter CF1 may be disposed on the third color filter CF3. The second color filter CF2 may be disposed on the first color filter CF1.

[0150] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 transmits light within a desired wavelength range (e.g., a specific or predetermined wavelength range) and blocks light outside the desired wavelength range. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 includes a matrix resin and a dye and / or pigment dispersed in the matrix resin. The matrix resin can be a medium for dispersing the dye and / or pigment, and can include various suitable resin compositions, which can generally be referred to as a binder.

[0151] The first color filter CF1 can transmit the first color light, the second color filter CF2 can transmit the source light provided by the emission layer EML, and the third color filter CF3 can transmit the third color light. For example, the first color filter CF1 can be a red filter, the second color filter CF2 can be a blue filter, and the third color filter CF3 can be a green filter. According to an embodiment of the present disclosure, the first color filter CF1 and the third color filter CF3 can be yellow filters. In this case, the first color filter CF1 and the third color filter CF3 can be connected to each other.

[0152] The first color filter CF1 may be arranged adjacent to the second color filter CF2. The third color filter CF3 may overlap with the first color filter CF1 and the second color filter CF2. The area where the multiple color filters CF1, CF2, and CF3 all overlap with each other may block light. In this case, a black pad (not shown) containing a light-blocking material may not be included. The area where the multiple color filters CF1, CF2, and CF3 all overlap with each other may correspond to the non-pixel area NPXA and may correspond to the partition wall BW. The phrase "corresponding to" refers to two components that overlap with each other when viewed in the thickness direction DR3 of the display panel DP (for example, in a plan view), and is not limited to the two components having equal areas to each other.

[0153] The first insulating layer 200-1 may be disposed below the first color filter CF1, the second color filter CF2, and the third color filter CF3 to cover the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second insulating layer 200-2 may cover the first insulating layer 200-1 and may provide a flat or substantially flat surface for the lower side of the second insulating layer 200-2. The first insulating layer 200-1 may be an inorganic layer, and the second insulating layer 200-2 may be an organic layer. However, the present disclosure is not limited thereto, and the second insulating layer 200-2 according to an embodiment of the present disclosure may be omitted as needed or desired.

[0154] The partition wall BW may be disposed below the second insulating layer 200-2. The partition wall BW may be disposed in the non-pixel area NPXA. A plurality of partition wall openings BW-OP1 may be defined in the partition wall BW. The partition wall BW may include a suitable material having a transmittance equal to or less than a specific value. For example, the partition wall BW may include a light-blocking material and may include, for example, a black component. The partition wall BW may include a black pigment or a mixture of a black pigment and a matrix resin. For example, the partition wall BW may include at least one of propylene glycol methyl ether acetate, 3-methoxybutyl acetate, an organic pigment, and an acrylate.

[0155] A bottom surface BW-B of the partition wall BW may be defined on a surface facing the encapsulation layer TFE.

[0156] The plurality of partition wall opening portions BW-OP1 may correspond to the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3, respectively. The plurality of partition wall opening portions BW-OP1 may correspond to the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The phrase "corresponding to" refers to two components overlapping each other when viewed in the thickness direction DR3 of the display module DM (e.g., in a plan view), and is not limited to the two components having equal areas.

[0157] The first light-controlling pattern WC1 may be disposed in one of the plurality of partition wall openings BW-OP1 to convert source light into first color light. The second light-controlling pattern WC2 may be disposed in another of the plurality of partition wall openings BW-OP1 to transmit the source light. The third light-controlling pattern WC3 may be disposed in yet another of the plurality of partition wall openings BW-OP1 to convert source light into second color light.

[0158] Each of the first light-controlling pattern WC1, the second light-controlling pattern WC2, and the third light-controlling pattern WC3 can be formed by an inkjet process. The first light-controlling pattern WC1, the second light-controlling pattern WC2, and the third light-controlling pattern WC3 can be formed by supplying a suitable composition into a space defined by the partition wall BW, such as a plurality of partition wall opening portions BW-OP1.

[0159] Each of the first light-control pattern WC1 and the third light-control pattern WC3 may include a base resin, quantum dots, and scattering particles. The second light-control pattern WC2 may include a base resin and scattering particles. However, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, each of the first light-control pattern WC1, the second light-control pattern WC2, and the third light-control pattern WC3 may include a base resin and scattering particles, and at least two of the first light-control pattern WC1, the second light-control pattern WC2, and the third light-control pattern WC3 may include quantum dots. According to an embodiment of the present disclosure, scattering particles may not be present in any of the first light-control pattern WC1, the second light-control pattern WC2, and the third light-control pattern WC3.

[0160] The matrix resin may be a medium in which quantum dots or scattering particles are dispersed, and may be formed from various suitable resin compositions commonly referred to as adhesives. However, the present disclosure is not limited thereto. For example, as long as the matrix resin is a medium for dispersing quantum dots, the matrix resin may have various suitable names, various suitable additional functions, or various suitable materials. The matrix resin may be a polymer resin. For example, the matrix resin may be an acrylic resin, a urethane resin, a silicone resin, or an epoxy resin. The matrix resin may be a transparent resin.

[0161] The scattering particles may be titanium oxide (TiO2) or silicon dioxide-based nanoparticles. The scattering particles may scatter incident light and increase the amount of light provided to the outside. According to an embodiment of the present disclosure, at least one of the first light-controlling pattern WC1 and the third light-controlling pattern WC3 may not include scattering particles.

[0162] Quantum dots can be particles that convert the wavelength of incident light. Quantum dots can be suitable materials with a crystal structure of several nanometers, can include hundreds to thousands of atoms, and due to their small size, can exhibit a quantum confinement effect that increases the energy band gap. When light with a wavelength higher than the band gap enters the quantum dot, the quantum dot absorbs the light, becomes excited, and drops to the ground state while emitting light with a desired wavelength (e.g., a specific or predetermined wavelength). The emitted light with the desired wavelength has a value corresponding to the band gap. When the size and composition of the quantum dots are adjusted, the quantum dots can control the luminescence properties due to the quantum confinement effect.

[0163] Quantum dots can adjust the color of emitted light according to the particle size. Therefore, quantum dots can have various suitable emission colors such as blue, red, and green.

[0164] The third insulating layer 200-3 may cover the partition wall BW, the first light-controlling pattern WC1, the second light-controlling pattern WC2, and the third light-controlling pattern WC3. For example, the third insulating layer 200-3 may be an inorganic layer to seal the partition wall BW, the first light-controlling pattern WC1, the second light-controlling pattern WC2, and the third light-controlling pattern WC3.

[0165] Figure 9 According to the embodiment of the present disclosure Figure 7 A cross-sectional view taken along line II-II'. Figure 9 In the above reference Figure 8 Components that are the same or substantially the same as those described may be referred to with the same reference numerals, and thus, redundant descriptions thereof may not be repeated.

[0166] Reference Figure 9 The connection electrode CNE may be inserted between the driving transistor TD and the light-emitting element OLED to connect the driving transistor TD to the light-emitting element OLED. The connection electrode CNE may be disposed on the fourth insulating layer IL4. The connection electrode CNE may be connected to the source electrode SD of the driving transistor TD through a first contact hole CH1 formed through (e.g., penetrating) the second insulating layer IL2 and the third insulating layer IL3.

[0167] The first line portion ELP1 of the power line EL (see, for example, Figure 7 ) may be disposed on the fourth insulating layer IL4. A fifth insulating layer IL5 may cover the connection electrode CNE and the first line portion ELP1.

[0168] The display element layer DP-LED may be disposed on the circuit layer DP-CL.

[0169] The first electrode AE1 may be disposed on the fifth insulating layer IL5 . The first electrode AE1 may be connected to the connection electrode CNE through a second contact hole CH2 formed through (eg, penetrating) the fifth insulating layer IL5 . The first electrode AE1 may be connected to the driving transistor TD through the connection electrode CNE.

[0170] The pixel defining layer PDL may be disposed on the fifth insulating layer IL5. An emission opening portion PDL-OP exposing a portion of the first electrode AE1 may be defined in the pixel defining layer PDL. The pixel defining layer PDL may cover a portion of the top surface of the first electrode AE1. The portion of the first electrode AE1 exposed by the emission opening portion PDL-OP in the pixel defining layer PDL may correspond to the first pixel region PXA1. The first pixel region PXA1 may substantially correspond to Figure 8The first emission area EA1 in the first pixel area PXA1 and the non-pixel area NPXA may be defined by various definition methods and are not limited thereto.

[0171] The auxiliary electrode SE may be disposed on the base layer BS. According to an embodiment, the auxiliary electrode SE may be disposed on the fifth insulating layer IL5 in the circuit layer DP-CL. The auxiliary electrode SE may be connected to the first line portion ELP1 through a third contact hole CH3 formed through (e.g., penetrating) the fifth insulating layer IL5. The auxiliary electrode SE may receive the second power supply voltage ELVSS (e.g., see FIG. 1 ) through the first line portion ELP1. Figure 6 ).

[0172] The auxiliary electrode SE may be provided at the same layer as the first electrode AE1 (e.g., in the middle or above the layer). The auxiliary electrode SE may be provided in an island shape so as to be spaced apart from the first electrode AE1 in plan view. In plan view, the auxiliary electrode SE may not overlap with the first electrode AE1. However, the present disclosure is not limited thereto. For example, the auxiliary electrode SE may be provided in a linear shape extending in one direction in plan view. The shape of the auxiliary electrode SE is not limited to any particular embodiment, as long as the auxiliary electrode SE is spaced apart from the first electrode AE1.

[0173] When viewed in a plan view, portions of the hole control layer HCL, the emission layer EML, and the electron control layer ECL may overlap with the auxiliary electrode SE. An opening portion S-OP may be defined in the pixel defining layer PDL to expose portions of the auxiliary electrode SE. Portions of the hole control layer HCL, the emission layer EML, and the electron control layer ECL may be disposed in the opening portion S-OP. Portions of the hole control layer HCL, the emission layer EML, and the electron control layer ECL may be interposed between the auxiliary electrode SE and the second electrode CE.

[0174] A plurality of opening portions OP (for example, see Figure 7 ) can be respectively defined in the hole control layer HCL, the emission layer EML, and the electron control layer ECL. Figure 9 A first opening portion OP1 is shown. The first opening portion OP1 may expose a portion of the auxiliary electrode SE. The portion of the auxiliary electrode SE may be defined as an aperture area HA. ​​The second electrode CE may contact the auxiliary electrode SE through the aperture area HA. ​​An area surrounding the aperture area HA (e.g., around the periphery of the aperture area HA) may be defined as a protrusion area MA. The protrusion area MA may be an area having a suitable diameter (e.g., a specific or predetermined diameter).

[0175] The second electrode CE may cover the emission layer EML. The second electrode CE may be provided in the form of an electrode having a high light transmittance so that light passes through the second electrode CE from the emission layer EML toward the display surface IS (eg, see FIG. 2 ). Figure 1 ) emission. For example, the second electrode CE may be provided as a transparent electrode or an electrode having a thin thickness. In this case, the resistance of the second electrode CE may increase, thereby causing an IR drop phenomenon. However, according to some embodiments of the present disclosure, since the second electrode CE is in contact with the auxiliary electrode SE, the resistance of the second electrode EC can be reduced, and the IR drop phenomenon can be prevented or substantially prevented. Therefore, a display device DD with improved reliability can be provided (for example, see Figure 1 ).

[0176] Figure 10 : is a plan view showing power lines and a plurality of opening portions according to an embodiment of the present disclosure. Figure 10 In the above reference Figure 7 Components that are the same or substantially the same as those described may be referred to with the same reference numerals, and thus, redundant descriptions thereof may not be repeated.

[0177] Reference Figure 9 and Figure 10 , the power line EL may include a first line portion ELP1 and a second line portion ELP2. The first line portion ELP1 may extend in a first direction DR1. The second line portion ELP2 may extend in the first direction DR1.

[0178] The power line EL may be electrically connected to the auxiliary electrode SE. The second power supply voltage ELVSS (eg, see Figure 6 ) can be provided to the auxiliary electrode SE.

[0179] A plurality of opening portions OP overlapping the auxiliary electrode SE may be defined in the emission layer EML. The auxiliary electrode SE may contact the second electrode CE through the plurality of opening portions OP. The second power supply voltage ELVSS (eg, see Figure 6 ) may be applied to the second electrode CE.

[0180] A circle having a radius R may be defined around each of the plurality of opening portions OP. The radius R may be the radius of the second power supply voltage ELVSS (eg, see Figure 6 ) effective transmission distance.

[0181] The plurality of opening portions OP may include a plurality of first opening portions OP1 and a plurality of second opening portions OP2. When viewed in the second direction DR2, the plurality of first opening portions OP1 and the plurality of second opening portions OP2 may be in a state of not overlapping each other.

[0182] A plurality of first opening portions OP1 may overlap with a first line portion ELP1. The plurality of first opening portions OP1 may be arranged along a first direction DR1. The plurality of first opening portions OP1 may be spaced apart from each other in the first direction DR1 by a first distance DS1. The first distance DS1 may be defined as "2a" (where "a" is a positive real number). In this case, "a" may be less than the radius R. "2a" may be greater than the radius R. In other words, the first distance DS1 and the radius R may satisfy the relationship a < R < 2a, and "a" may have a suitable value to prevent or substantially prevent the occurrence of an IR drop phenomenon.

[0183] A plurality of second opening portions OP2 may overlap with a second line portion ELP2. The plurality of second opening portions OP2 may be arranged along the first direction DR1. The plurality of second opening portions OP2 may be spaced apart from each other in the first direction DR1 by "2a".

[0184] When observed in a second direction DR2, a first opening portion OP1 among the plurality of first opening portions OP1 and a second opening portion OP2 adjacent to the first opening portion OP1 among the plurality of second opening portions OP2 may be spaced apart by a second distance DS2. The second distance DS2 may be defined as "a". In other words, the second distance DS2 in the first direction DR1 between the portion obtained by projecting the first opening portion OP1 onto the second line portion ELP2 in the second direction DR2 and the second opening portion OP2 may be defined as "a". The second distance DS2 may be half of the first distance DS1.

[0185] When observed in the first direction DR1, the first opening portion OP1 and the second opening portion OP2 may be spaced apart from each other by a third distance DS3. The third distance DS3 may be defined as "2a". In other words, the first line portion ELP1 and the second line portion ELP2 may be spaced apart from each other in the second direction DR2 by "2a".

[0186] The first opening portion OP1 and the second opening portion OP2 may be spaced apart from each other in a direction DRa that intersects the first direction DR1 and the second direction DR2. The fourth distance DS4 may be defined as For example, the second distance DS2, the third distance DS3, and the fourth distance DS4 may define a right triangle.

[0187] According to some embodiments of the present disclosure, the arrangement relationship between the power lines EL and the plurality of opening portions OP can be designed to satisfy the first distance DS1 to the fourth distance DS4. Therefore, the second electrode CE may not have a portion that does not overlap with the circle having the radius R. Therefore, a weak area with the possibility of an IR drop phenomenon can be prevented or eliminated. Therefore, a display device DD with improved reliability can be provided (for example, see Figure 1 ).

[0188] According to some embodiments of the present disclosure, a method for manufacturing a display device DD (for example, see Figure 1 ) may include forming a desired number (eg, an optimized number) of the plurality of opening portions OP. The number of laser drilling processes for forming the plurality of opening portions OP may be minimized or reduced. Figure 1 ), unnecessary tact time can be prevented or substantially prevented. In the process for manufacturing the display device DD (for example, see Figure 1 ) method, the takt time can be reduced. Therefore, a display device DD with improved reliability can be provided (for example, see Figure 1 ) and for manufacturing a display device DD (see, for example, Figure 1 ) method.

[0189] Compared to the comparative example, according to some embodiments of the present disclosure, the number of the plurality of opening portions OP can be reduced. Design in a space where the plurality of opening portions OP are not provided can be freely performed, thereby saving space. The area of ​​each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 can be expanded using the saved space. Therefore, the display device DD (for example, see Figure 1 ) aperture ratio. Due to the increase in the aperture ratio, a larger amount of light can be displayed per unit area. Therefore, a display device DD with improved display quality can be provided (for example, see Figure 1 ).

[0190] Furthermore, according to some embodiments of the present disclosure, energy efficiency can be improved by increasing the aperture ratio. In other words, even with lower power consumption, the display device DD (e.g., see Figure 1 ) can also display light with the same or substantially the same brightness. When considering the display device DD (see, for example, Figure 1 ) is inversely proportional to the power consumption, the display device DD (see, for example, Figure 1 ) can also increase its lifespan. Therefore, a display device DD with improved reliability can be provided (for example, see Figure 1 ).

[0191] Figure 11 is a flowchart of a method for manufacturing a display device according to an embodiment of the present disclosure. 12A to 12C is a cross-sectional view corresponding to a process in a method for manufacturing a display device according to an embodiment of the present disclosure. 12A to 12C , and refer to the above Figure 9 Components that are the same or substantially the same as those described may be referred to with the same reference numerals, and thus, redundant descriptions thereof may not be repeated.

[0192] Reference Figures 11 to 12C , according to the embodiment of the present disclosure for manufacturing a display device DD (for example, see Figure 1 ) includes providing a target substrate P-SUB (S100). The target substrate P-SUB may include an auxiliary electrode SE. The method may further include stacking a light emitting layer (ie, an emission layer EML) (S200). For example, the emission layer EML may be stacked on the first electrode AE ​​and the auxiliary electrode SE. The method may further include forming a plurality of opening portions OP (eg, Figure 10 )(S300). For example, a laser beam LL may be irradiated to form a plurality of opening portions OP through the emission layer EML. The method may further include forming a second electrode (S400). For example, the second electrode CE may be disposed on the emission layer EML and may be electrically connected to the auxiliary electrode SE.

[0193] According to the method for manufacturing a display device DD (see, for example, Figure 1 ) method, a target substrate P-SUB may be provided (S100). A hole control layer HCL, an emission layer EML, and an electron control layer ECL may be formed on the first electrode AE ​​and the auxiliary electrode SE (S200). In this case, the hole control layer HCL, the emission layer EML, and the electron control layer ECL may cover the auxiliary electrode SE.

[0194] A preliminary hole area P-HA may be defined in the hole control layer HCL, the emission layer EML, and the electron control layer ECL to overlap with the auxiliary electrode SE in a plan view.

[0195] The light irradiation unit LS may be provided on the target substrate P-SUB to correspond to the preparation hole area P-HA. The light irradiation unit LS may irradiate the laser beam LL toward the preparation hole area P-HA.

[0196] The laser beam LL can be provided in the form of a Gaussian beam with excellent intensity uniformity. When a through hole is formed using a laser with reduced uniformity, a portion of the emission layer corresponding to the prepared hole area may not be sufficiently removed or may be broken. However, when a hole is formed using a laser beam LL with excellent uniformity, process reliability and accuracy can be improved. Therefore, even the display device DD manufactured by the method for manufacturing a display device according to some embodiments of the present disclosure (for example, see Figure 1 ) reliability.

[0197] The wavelength of the laser beam LL may be within the ultraviolet wavelength range. For example, the wavelength of the laser beam LL may be greater than or equal to 300 nm and less than or equal to 400 nm. However, the wavelength of the laser beam LL is not limited thereto.

[0198] The output per unit area of ​​the laser beam LL may be 200 mJ / cm 2 In more detail, the output per unit area of ​​the laser beam LL may be 50 mJ / cm 2 or greater and 200mJ / cm 2 When the output per unit area of ​​the laser beam LL is less than 50 mJ / cm 2 When the output per unit area of ​​the laser beam LL is greater than or equal to 200 mJ / cm 2 When the emitting layer EML is removed, the emitting layer EML may be removed, and the auxiliary electrode SE formed under the emitting layer EML may be damaged.

[0199] When viewed in a plane, the laser beam LL may have a circular phase. The phase of the laser beam LL may include a central area CA and an edge area EA surrounding the central area CA (e.g., around the periphery of the central area CA). The intensity of the laser beam LL corresponding to the central area CA may be greater than the intensity of the laser beam corresponding to the edge area EA.

[0200] A plurality of opening portions OP can be formed by irradiating the laser beam LL to the central area CA (for example, see Figure 10 ) in each (S300). Figure 12C It is shown that the first opening portion OP1 is formed.

[0201] The hole control layer HCL, the emission layer EML, and the electron control layer ECL, which overlap with the edge area EA and are exposed to the laser beam LL, may be partially deformed.

[0202] A hole area HA may be formed through the hole control layer HCL, the emission layer EML, and the electron control layer ECL to expose a portion of the auxiliary electrode SE such that the hole area HA corresponds to the center area CA of the laser beam LL. The hole area HA may correspond to a region of the auxiliary electrode SE exposed to the opening area that overlaps the assembly of the hole control layer HCL, the emission layer EML, and the electron control layer ECL that are formed to overlap with the auxiliary electrode SE.

[0203] A second electrode CE may be formed on the electron control layer ECL (S400). The second electrode CE may be formed on the first opening portion OP1 through a deposition process to face the first electrode AE ​​and the auxiliary electrode SE. The second electrode CE and the auxiliary electrode SE may contact each other through the first opening portion OP1. The second electrode CE and the auxiliary electrode SE may be electrically connected to each other.

[0204] Figure 13 1 is a plan view showing a portion of a display device according to an embodiment of the present disclosure. Figure 13 In the above reference Figure 7 Components that are the same or substantially the same as those described may be referred to with the same reference numerals, and thus, redundant descriptions thereof may not be repeated.

[0205] Reference Figure 9 and Figure 13 , can be in the base layer BS (for example, see Figure 5 ) defines a display area DA and a non-display area NDA adjacent to the display area DA.

[0206] The plurality of opening portions OPa may include a plurality of first opening portions OP1 overlapping the first line portion ELP1 , a plurality of second opening portions OP2 overlapping the second line portion ELP2 , and a subsidiary opening portion SOP.

[0207] When viewed in a plan view, the auxiliary opening portion SOP may overlap with the first line portion ELP1.

[0208] The auxiliary opening portion SOP may be spaced apart from the second opening portion OP2 adjacent to the non-display area NDA from among the plurality of second opening portions OP2 in the second direction DR2. The auxiliary opening portion SOP may be spaced apart from the second opening portion OP2 adjacent to the non-display area NDA in the second direction DR2 by a (1-1)th distance DSa-1. The (1-1)th distance DSa-1 may be defined as "2a" (where "a" is a positive real number).

[0209] The auxiliary opening portion SOP may be spaced apart from the first opening portion OP1 adjacent to the non-display area NDA from among the plurality of first opening portions OP1 in the first direction DR1. The auxiliary opening portion SOP may be spaced apart from the first opening portion OP1 adjacent to the non-display area NDA in the first direction DR1 by a (2-1)th distance DSa-2. The (2-1)th distance DSa-2 may be defined as "a". In other words, the (2-1)th distance DSa-2 may be half of the (1-1)th distance DSa-1.

[0210] According to some embodiments of the present disclosure, the auxiliary opening portion SOP may prevent the second electrode CE from having a radius “R” (eg, see Figure 10 ) appears in the display area DA adjacent to the non-display area NDA. Therefore, a weak area with a possibility of an IR drop phenomenon can be prevented or eliminated. Therefore, a display device DD with improved reliability can be provided (for example, see Figure 1 ).

[0211] Figure 14 1 is a plan view showing a portion of a display device according to an embodiment of the present disclosure. Figure 14 In the above reference Figure 7 Components that are the same or substantially the same as those described may be referred to with the same reference numerals, and thus, redundant descriptions thereof may not be repeated.

[0212] Reference Figure 9 and Figure 14 Combined with Figure 13 , a plurality of dummy opening portion patterns DOPa and DOPb arranged in the first direction DR1 and the second direction DR2 may be defined in the emission layer EML. However, the present disclosure is not limited thereto, and the plurality of dummy opening portion patterns DOPa and DOPb according to an embodiment of the present disclosure may be formed in a layer other than the emission layer EML.

[0213] Two adjacent dummy opening portion patterns from among the plurality of dummy opening portion patterns DOPa and DOPb may be spaced apart from each other by a (1-2)th distance DSb-1 in the second direction DR2. The (1-2)th distance DSb-1 may be half of a distance DSa-1 between the first line portion ELP1 and the second line portion ELP2 in the second direction DR2.

[0214] Two adjacent dummy opening portion patterns from among the plurality of dummy opening portion patterns DOPa and DOPb may be spaced apart from each other by a (2-2)th distance DSb-2 in the first direction DR1. The (2-2)th distance DSb-2 may be half of the distance DSa-2 between the plurality of first opening portions OP1 in the first direction DR1.

[0215] The plurality of dummy opening portion patterns DOPa and DOPb may include a first dummy opening portion pattern DOPa and a second dummy opening portion pattern DOPb. The first dummy opening portion pattern DOPa may overlap with the plurality of opening portions OP. The second dummy opening portion pattern DOPb may not overlap with the plurality of opening portions OP.

[0216] As described above, the arrangement relationship between the power lines and the multiple openings can be designed in various ways to meet specific conditions. Considering the effective transmission distance of the power supply voltage, the second electrode can have no portion that does not overlap with the circular radius. This prevents or eliminates weak areas that could potentially cause IR drop. Consequently, a display device with improved reliability can be provided.

[0217] The foregoing is an illustration of some embodiments of the present disclosure and should not be construed as limiting the present disclosure. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It should be understood that, unless otherwise stated, the description of the features or aspects in each embodiment should generally be considered to be applicable to other similar features or fields in other embodiments. Therefore, as will be apparent to those skilled in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in conjunction with the features, characteristics and / or element descriptions of other embodiments. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device includes: base layer; a circuit layer on the base layer, wherein the circuit layer includes a power line configured to provide a power supply voltage; a first electrode on the circuit layer; an auxiliary electrode on the circuit layer, and the auxiliary electrode is located on the power line; an emission layer on the first electrode and the auxiliary electrode; and a second electrode on the emission layer, and the second electrode is electrically connected to the auxiliary electrode, wherein the emission layer has a plurality of openings overlapping with the auxiliary electrode; Wherein, the power line includes: a first line portion extending in a first direction; and a second line portion extending in the first direction and spaced apart from the first line portion in a second direction crossing the first direction, Wherein, the plurality of opening portions include: a plurality of first opening portions overlapping the first line portion in a plan view; and a plurality of second opening portions overlapping with the second line portion in a plan view, and wherein, when viewed in the second direction, the plurality of first opening portions are spaced apart from each other by "2a" in the first direction, where "a" is a positive real number, and a first opening portion from among the plurality of first opening portions and a second opening portion adjacent to the one first opening portion from among the plurality of second opening portions are spaced apart from each other by "a".

2. The display device according to claim 1, wherein In a plan view, the one first opening portion is spaced apart from the one second opening portion by “√5a” in a direction crossing the first direction and the second direction.

3. The display device according to claim 1, wherein The first electrode and the auxiliary electrode are located in the same layer as each other.

4. The display device according to claim 1, wherein The first line portion and the second line portion are spaced apart from each other by “2a” in the second direction.

5. The display device according to claim 1, wherein When viewed in the second direction, the plurality of first opening portions do not overlap with the plurality of second opening portions. The display device according to claim 1 , wherein: The base layer includes a display area and a non-display area adjacent to the display area, and The plurality of opening portions further include an auxiliary opening portion, which is spaced apart from another second opening portion adjacent to the non-display area from among the plurality of second opening portions in the second direction, and the auxiliary opening portion overlaps with the first line portion.

7. The display device according to claim 6, wherein: The auxiliary opening portion is spaced apart from the another second opening portion by "2a" in the second direction, and is spaced apart from another first opening portion adjacent to the auxiliary opening portion from among the plurality of first opening portions by "a" in the first direction.

8. A method for manufacturing a display device, wherein: The method comprises: providing a target substrate including a first electrode and an auxiliary electrode; stacking an emission layer on the first electrode and the auxiliary electrode; forming a plurality of opening portions penetrating the emission layer by irradiating a laser beam; and forming a second electrode on the emission layer, and electrically connecting the second electrode to the auxiliary electrode; Wherein, the plurality of opening portions include: a plurality of first opening portions arranged along a first direction; and a plurality of second opening portions spaced apart from the plurality of first opening portions in a second direction intersecting the first direction, and the plurality of second opening portions are arranged along the first direction, wherein said forming the plurality of opening portions comprises forming the plurality of first opening portions spaced apart from each other by "2a" in the first direction in a plan view, wherein "a" is a positive real number, and In a plan view, one first opening portion from among the plurality of first opening portions is spaced apart from one second opening portion adjacent to the one first opening portion from among the plurality of second opening portions by "√5a" in a direction intersecting the first direction and the second direction.

9. The method of claim 8, wherein: When viewed in the second direction, the one first opening portion and the one second opening portion are spaced apart from each other by “a”.

10. The method of claim 8, wherein: The providing the target substrate includes disposing the first electrode and the auxiliary electrode in the same layer as each other.

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