Apparatus and method for operating semiconductor spin qubit quantum computer

Abstract

A method of operating a quantum chip (10) using a microprocessor wherein the quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12) for providing a plurality of shuttle channels (16) for moving a plurality of qubits along a plurality of paths (45); the plurality of gate electrodes (50) are further arranged to form a plurality of manipulation regions (20) and a plurality of T-junctions (18), any of the plurality of manipulation regions (20) comprising an interface (25) at which two of the plurality of shuttle channels (16) meet each other, and any of the plurality of T-junctions (18) comprising a junction (28) at which two of the plurality of shuttle channels (16) meet each other. One of the plurality of shuttle channels (16) is linked to another of the plurality of shuttle channels (16): the method comprising the steps of: calibrating voltage parameters relating to a voltage to be applied to the plurality of gate electrodes (50), one of the parameters relating to one of the plurality of gate electrodes (50); selecting a path (45s) along a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) between the position (S) of the qubit and the selected manipulation zone (20); determining, for any one of a selected shuttle channel (16-1, 16-2, 16-n) of the plurality of shuttle channels (16), at least one shuttle voltage time process to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for moving the qubit from the current position to the selected manipulation zone (20) based on the voltage parameter; moving the qubit along a selected one of the plurality of shuttle channels (16-1, 16-2, 16-n) of the plurality of shuttle channels (16) from the current position (S) to the selected manipulation zone (20) by applying a shuttle voltage time process to a subset (50-1, 50-2, 50-n) of the plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16-1, 16-2, 16-n); determining, for the selected manipulation region (20), a manipulation voltage-time process for manipulating qubits to be applied to an associated subset (50-n, 50-s) of the plurality of gate electrodes (50), based on the voltage parameter; and manipulating the qubits in the selected manipulation region (20) by applying at least one manipulation voltage time process to a subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

Description

Technical Field

[0001] The field of the present disclosure relates to the operation of quantum processors. Background Art

[0002] Quantum processor architectures must take scalability into account in order to achieve a sufficiently high number of logical qubits to implement quantum computer chips, which enable quantum computing in the NISQ (noisy intermediate-scale quantum) era or universal quantum computing. In the case of quantum computing based on spin qubits, the qubits are arranged in a two-dimensional plane. A disadvantage of this two-dimensional architecture is the so-called "fan-out problem," which refers to the space required for routing the control circuits of the quantum processor between the quantum processor and the traditional control circuits. These space requirements scale faster with the number of qubits than the size of the spin qubit-based quantum processor architectures proposed so far can scale.

[0003] Recently, a spin qubit architecture based on direct electron shuttling in Si / SiGe semiconductor heterostructures has been proposed. This architecture includes shuttle paths along which qubits can theoretically be transported over arbitrary distances, for example, up to approximately 50 μm. These shuttle paths allow components of a quantum processor (such as the loading, readout, and manipulation regions) to be spaced apart from one another, resulting in lower crosstalk. The provision of shuttle paths also enables operating modes that require relatively low operating frequencies and reduce local magnetic field gradients.

[0004] In these shuttle-based architectures, high-fidelity shuttling is crucial for reliable computation. This high fidelity can be compromised by, for example, charge defects or valley splitting on the shuttle path. Valley splitting can lead to leakage of the computational basis (e.g., two spin states) used for computation.

[0005] There is a need to identify points in a quantum processor (e.g., a shuttle path or other component of the quantum processor) at which the reliability of qubit processing decreases, which ultimately affects the performance of the quantum processor. Summary of the Invention

[0006] A method for operating a quantum chip (10) using a microprocessor, wherein the quantum chip includes a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12), the plurality of gate electrodes (50) being used to provide a plurality of shuttle channels (16) for moving a plurality of quantum bits along a plurality of paths (45);

[0007] The plurality of gate electrodes (50) are further arranged to form a plurality of steering regions (20) and a plurality of T-junctions (18),

[0008] Any one of the plurality of maneuvering zones (20) includes an interface 25 where two of the plurality of shuttle channels (16) meet each other, and

[0009] Any one of the plurality of T-junctions 18 comprises a junction (28), one of the plurality of shuttle channels (16) and another of the plurality of shuttle channels (16).

[0010] The shuttle channels (16) are connected at a junction (28);

[0011] The method comprises the following steps:

[0012] calibrating a voltage parameter associated with a voltage to be applied to the plurality of gate electrodes (50), wherein one of the parameters is associated with one of the plurality of gate electrodes (50);

[0013] selecting a path (45s) along a selected shuttle channel (16-1, 16-2, ..., 16-n) of a plurality of shuttle channels (16) between the location (S) of the qubit and the selected manipulation region (20);

[0014] Based on the voltage parameter, for any one of the selected shuttle channels (16-1, 16-2, ..., 16-n) of the plurality of shuttle channels (16), a voltage to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for moving the qubit from the current position to the

[0015] at least one shuttle voltage time course in the selected manipulation region (20);

[0016] The method further comprises: moving a qubit from a current position (S) to a selected manipulation region (20) along a selected one of the plurality of shuttle channels (16) by applying a shuttle voltage time course to a subset (50-1, 50-2, ..., 50-n) of a plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16); and determining, for the selected manipulation region (20), a manipulation voltage to be applied to the associated subset (50-n, 50-s) of the plurality of gate electrodes (50) for manipulating the qubit based on a voltage parameter.

[0017] Time course; and

[0018] A qubit is manipulated in a selected manipulation region (20) by applying at least one manipulation voltage time course to a subset (50-n, 50-s) of a plurality of gate electrodes (50) associated with the selected manipulation region (20).

[0019] The method of claim 1 , wherein the manipulation of the qubit comprises performing a single qubit action on the qubit.

[0020] A method according to claim 1 or 2, wherein the manipulation of a qubit comprises performing a two-qubit operation on the qubit and a second qubit located in the selected manipulation region (20).

[0021] The method according to any one of claims 1 to 3, further comprising: moving the qubit to position (S).

[0022] The method according to any one of claims 1 to 4, wherein the path (45s) is selected so that at least two selected shuttle channels (16-1, 16-2, ..., 16-n) of the plurality of shuttle channels (16) meet at an interface (25) of at least one intermediate steering area (20) of the plurality of steering areas (20) or are connected at a junction (28i) of at least one intermediate T-junction (18) of the plurality of T-junctions (18).

[0023] The method according to any one of claims 1 to 5, further comprising: moving a third quantum bit located in the selected manipulation region (20) from the selected manipulation region (20) by applying at least one additional shuttle voltage time course to a subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

[0024] The method of claim 6, wherein moving the third qubit located in the selected manipulation region (20) comprises moving the third qubit across an interface (25) of the selected manipulation region (20).

[0025] The method according to any one of claims 1 to 7, further comprising coordinating the application of the shuttle voltage time course, the application of the steering voltage time course, and the application of at least one further shuttle voltage time course.

[0026] The method of claim 8, further comprising coordinating the time course of additional voltages applied to other gate electrodes of the plurality of gate electrodes (50).

[0027] The method according to any one of claims 1 to 9, further comprising: recalibrating and / or adjusting voltage parameters.

[0028] The method according to any one of claims 1 to 10, further comprising: improving the coherence of one of the quantum bits.

[0029] The method of claim 11, wherein increasing the coherence comprises applying dynamic decoupling, such as applying Car-Purcell-Meiboom-Gill pulses.

[0030] A computing system comprising a quantum processor (10), a voltage source and a microprocessor,

[0031] The quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12), wherein

[0032] A plurality of gate electrodes (50) are arranged to provide a plurality of manipulation regions (20) for manipulating the plurality of qubits, a plurality of T-junctions 18 for interconnecting the plurality of qubits, and a plurality of shuttle channels (16) providing a plurality of paths (45) along which the plurality of qubits are movable, and

[0033] The plurality of manipulation zones (20) are interconnected via a plurality of paths (45) and a plurality of T-junctions (18),

[0034] A voltage source is electrically connected to the plurality of gate electrodes (50) to apply a voltage to the plurality of gate electrodes (50) for manipulating the plurality of qubits, for interconnecting the plurality of qubits, and / or for moving the plurality of qubits; and

[0035] The microprocessor is communicatively connected to the voltage source to control the voltage and includes a memory storing voltage parameters of the voltage to be applied, the parameters being associated with one or more subsets of the plurality of gate electrodes (50).

[0036] The computing system according to claim 13 or 14, wherein any one of the plurality of operating areas (20) has an interface (25) at which two of the plurality of shuttle channels (16) meet each other.

[0037] The computing system according to claim 14, wherein the operating region in the operating region (20) further comprises at least one plug gate and / or at least one barrier gate at the interface (25).

[0038] The computing system according to any one of claims 13 to 15, wherein any one of the plurality of T-junctions (18) has a junction (28) at which two connected shuttle channels of the plurality of shuttle channels (16) are connected to each other.

[0039] The computing system of claim 16, wherein the T-junction of the plurality of T-junctions (18) further comprises at least one plug gate and / or at least one barrier gate at the junction (28).

[0040] The computing system according to any one of claims 13 to 17, wherein at least one of the plurality of steering regions (16) further comprises a top gate (50d).

[0041] The computing system according to any one of claims 13 to 18, wherein the voltage source is configured to provide at least one DC voltage and / or at least one AC voltage.

[0042] A computing system according to any one of claims 13 to 19, wherein the quantum processor (10) is arranged to be at a first cryogenic temperature.

[0043] A computing system according to any one of claims 13 to 20, wherein the microprocessor is arranged to be at ambient temperature or a second cryogenic temperature, the second cryogenic temperature being equal to or different from the first cryogenic temperature.

[0044] The computing system according to any one of claims 13 to 21, wherein the plurality of gate electrodes (50) are arranged in a periodic manner on the semiconductor heterostructure (12).

[0045] The computing system according to any one of claims 13 to 22, further comprising at least one further memory arranged at the quantum chip (10), and the at least one further memory being configured to store some voltage parameters associated with some of the gate electrodes (50) arranged adjacent to the at least one memory.

[0046] A system comprising a computing system according to any one of claims 13 to 23 and an external magnet for providing an external magnetic field B0. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Shown is a top view of a quantum processor.

[0048] Figure 2 Show Figure 2 A top view of the unit cell of a quantum processor is shown in FIG.

[0049] Figure 3A Shown is a top view of one aspect of the shuttle channel.

[0050] Figure 3B A longitudinal cross-section showing another aspect of the shuttle channel.

[0051] Figure 3C A pair of path-defining gates are shown arranged on the path of the qubit.

[0052] Figure 3D A longitudinal cross-section showing another aspect of the shuttle channel.

[0053] Figure 4AA top view illustrating one aspect of a shuttle channel with segmented path-defining gate electrodes.

[0054] Figure 4B A longitudinal cross-section showing another aspect of the shuttle channel.

[0055] Figure 4C A pair of segmented path-defining gates are shown arranged on the path of one or more qubits.

[0056] Figure 5 A grayscale-coded panorama of the valley splitting of the shuttle channel is shown, along with examples of possible trajectories of qubits along the shuttle channel, which bypass a series of sites of reduced fidelity as the valley splitting decreases.

[0057] Figure 6A Shown is a top view of a T-junction.

[0058] Figure 6B Show Figure 6A A top view of the gate electrode is shown with the T-junction path defined in FIG.

[0059] Figure 7 Simulations showing track splitting during straight-line movement (left panel) and during turning at the knot during movement past the knot.

[0060] Figure 8 Shown is a simulation of the potential well at a T-junction during turning of at least one qubit at the junction.

[0061] Figure 9 Another aspect of the segmented path definition gate is shown.

[0062] Figure 10A Shown is a top view of a T-junction with a segmented path-defining gate.

[0063] Figure 10B Show Figure 6A A top view of the gate is shown with the segmented path of the T-junction defined.

[0064] Figure 11A Shows a top view of one aspect of the handling area.

[0065] Figure 11B Longitudinal section showing further aspects of the handling area.

[0066] Figure 11C Longitudinal section showing further aspects of the handling area.

[0067] Figure 11D Longitudinal section showing further aspects of the handling area.

[0068] Figure 11ELine cut plots showing a time series of simulations of the evolution of the potential energy landscape at the interface of the maneuvering zone.

[0069] Figure 12 The effect of the shuttle voltage on applying a tuning voltage to change the confinement of a qubit is shown in the upper panel. Figure 4 shows the effect of the shuttle voltage on applying a tuning voltage to shift the confinement of a qubit in the lower panel.

[0070] Figure 13A Another aspect of a quantum processor according to the present disclosure is shown.

[0071] Figure 13B Show Figure 13B The unit cell of a quantum processor is shown in . DETAILED DESCRIPTION

[0072] The present disclosure relates to a method of operating a quantum processor and a method of manufacturing a quantum processor.

[0073] Quantum processors can operate based on spin qubits. Spin qubits are two-level quantum systems with a spin degree of freedom. An example of a spin qubit is a two-level quantum system of electron spins confined in a quantum dot, and another example is a hole spin qubit. Furthermore, a group of electrons (e.g., two or three electrons) can be used to realize a spin qubit, such as the S-T0 singlet-triplet system of two electrons in a double quantum dot.

[0074] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in the semiconductor heterostructure 12. Using an electron-based spin qubit involves placing the electron spin in a known state. To this end, the electron state is initialized. In one aspect, the selected qubit is associated with the same electron throughout the execution of the quantum algorithm. On the other hand, a qubit implemented by a first electron can be initialized and subsequently operated on, and the qubit can be implemented by a second electron. On the other hand, without affecting the execution of the quantum algorithm, there is a situation where it is impossible to distinguish whether the qubit is implemented by the first electron or the second electron. Similarly, the method of the present disclosure can be applied to any type of hole spin qubit.

[0075] The use of semiconductor materials to form structures for implementing quantum processors (e.g., semiconductor heterostructures 12) is advantageous for manufacturing because the materials are easy to process and inexpensive (e.g., in the case of silicon). The use of silicon in computing hardware is an established technology. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be confined within a semiconductor heterostructure 12 formed of semiconductor materials in quantum wells 69 (see below and, for example, Figure 3D). 2DEG or 2DHG can be further confined based on an electric potential. The electric potential can be a static electric potential or a non-static electric potential. The electric potential can form at least one quantum dot, wherein at least one electron or hole in the 2DEG or 2DHG is captureable or confined. The spin of at least one trapped (confined) electron or hole can be used to realize a spin qubit. Moving the electric potential causes moving at least one quantum dot. The movement of at least one quantum dot enables the movement of at least one trapped (confined) electron / hole and the qubit associated with at least one trapped (confined) electron / hole. Changing the strength of the electric potential changes the degree of confinement of at least one trapped (confined) electron or hole.

[0076] The quantum processor may include a plurality of unit cells 26. A unit cell 26 in the plurality of unit cells includes a component that performs at least one action or operation on one or more qubits located in the unit cell 26. The at least one action on the one or more qubits may include: loading one or more qubits into the unit cell 26; unloading one or more qubits from the unit cell 26; moving (shuttling) one or more qubits into or out of the unit cell 26 (i.e., to another unit cell 26 of the quantum processor); manipulating the quantum state of the one or more qubits; and reading out the quantum state of the one or more qubits. Manipulating the one or more qubits may include: manipulating a single qubit or manipulating two qubits. Manipulating a single qubit may include: rotating the spin of the single qubit, for example, to drive a transition between multiple spin states. The multiple spin states may include an up spin state and a down spin state. Manipulating two qubits may be used to implement a CPHASE gate, a CNOT gate, and / or a SWAP gate. Manipulating two qubits may further be used to implement a SQRT(SWAP) gate. Implementing a CNOT gate and one or more single-qubit gates (such as rotation or phase shift) is sufficient to realize a quantum computer. In a quantum computer based on spin qubits, the CNOT gate can be implemented as a CPHASE gate.

[0077] In one aspect, several actions performed by components of unit cell 26 on one or more qubits can be performed one after another as a sequence of actions. For example, two actions can be performed one after another. In another aspect, several actions performed by components of unit cell 26 on one or more qubits can be performed in parallel. For example, two actions can be performed in parallel.

[0078] In one aspect, several actions on one or more qubits may be performed within a single unit cell in plurality of unit cells 26 or across several units of plurality of unit cells 26 .

[0079] In one aspect, several actions may be performed as part of determining gate fidelity (see below for more details). For example, determining gate fidelity may include performing a sequence of actions on one or more qubits.

[0080] In another aspect, several actions may be performed as part of executing an algorithm. For example, executing an algorithm may include performing a sequence of actions on one or more qubits.

[0081] Components are arranged within unit cells 26. Some components are connected to one another. The components and their connections constitute the layout or structure of unit cells 26. Unit cells in plurality of unit cells 26 may have substantially the same structure, with the same components arranged and connected to one another in substantially the same manner. Other units in plurality of unit cells 26 may have different structures, with different components and / or connections between the components.

[0082] One aspect of a quantum processor is disclosed in International Patent Application No. WO 2021 / 052541 A1, the entire contents of which are incorporated herein by reference. Figure 1 and Figure 2 As shown, the quantum processor 10 includes a semiconductor heterostructure 12. The semiconductor heterostructure 12 includes several layers of different material compositions. The semiconductor heterostructure 12 can be a Si / SiGe or GaAs / AlGaAs heterostructure, however, it is possible to use other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS or Ge / SiGe. The semiconductor heterostructure can be undoped and / or strained. The semiconductor heterostructure 12 can serve as a substrate for the quantum processor 10. The semiconductor heterostructure 12 can include a 2DEG. The 2DEG or 2DHG can be arranged or located in a quantum well 69 (see, for example Figure 3D ). One or more qubits may be arranged in quantum well 69. One or more qubits may be arranged in at least one quantum dot formed in quantum well 69. One or more qubits may be generated from a 2DEG.

[0083] In one aspect, the semiconductor heterostructure 12 may further include a silicon capping layer 64 having a dielectric or insulating layer 66 disposed thereon (see Figure 3D ). Gate electrodes 50a, 50b, 50d may be arranged on top of a dielectric or insulating layer 66.

[0084] On the other hand, the semiconductor heterostructure 12 may further include a strained silicon layer 63 (see Figure 3D In yet another aspect, the semiconductor heterostructure 12 may further include a silicon dioxide layer 62 (see Figure 3D or Figure 11C ).

[0085] exist Figure 1 and Figure 2 In the aspect of the quantum processor 10 shown, the components 16, 18, 20, 22, 24 are disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 1 As shown, the illustrated aspect of quantum processor 10 includes one or more of each of components 16, 18, 20, 22, 24. In another aspect, quantum processor 10 may include one or more of only some of components 16, 18, 20, 22, 24.

[0086] Figure 1 and Figure 2 The illustrated quantum processor 10 is a substantially two-dimensional device defined by at least one surface 14. The third dimension of the quantum processor 10 is defined by the thickness of the semiconductor structure 12 and the thicknesses of the components 16, 18, 20, 22, 24.

[0087] The plurality of unit cells 26 of the quantum processor 10 includes several unit cells 26 (e.g. Figure 2 shown). Figure 2 In the illustrated aspect, unit cell 26 includes components 16, 18, 20, 22, 24. In another aspect of the present disclosure, unit cell 26 includes only some of components 16, 18, 20, 22, 24. In yet another aspect, unit cell 26 may include more than one of at least one of components 16, 18, 20, 22, 24.

[0088] The components 16, 18, 20, 22, 24 include a plurality of gate electrodes 50 arranged on at least one surface 14 of the semiconductor heterostructure 12 (see Figures 3A to 3D ). The plurality of gate electrodes 50 may be arranged to define at least one path 45 within the quantum well 69 of an associated one of the components 16, 18, 20, 22, 24 (see Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3C 、 Figure 3D 、 Figure 4A 、 Figure 4C ), one or more qubits can move (shuttle) along these paths.

[0089] exist Figure 1 and Figure 2 , at least one path 45 is shown as being oriented substantially in two directions on the surface 14, the two directions being substantially perpendicular to each other, forming a grid-like structure of a plurality of paths 45. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0090] The plurality of gate electrodes 50 may also be arranged to move (shuttle) one or more qubits along the at least one path 45. The movement (shuttling) may occur in either of two directions (forward and backward) along the at least one path 45. The plurality of gate electrodes 50 may also be arranged to perform at least one action performed by the components 16, 18, 20, 22, 24 on the one or more qubits.

[0091] Multiple gate electrodes 50 can be provided with a voltage. Multiple gate electrodes 50 can be made of metal. Multiple gate electrodes 50 can be superconducting. The voltage can be used for one or more purposes, such as defining at least one path 45, moving (shuttling) one or more qubits, and / or performing at least one action on one or more qubits. The voltage can include a DC (direct current) voltage and an AC (alternating current) voltage. The voltage can include one or more static voltages and one or more non-static voltages. The voltage can be applied via a DC line, an AC line, and / or a biasing device.

[0092] One or more of the components 16, 18, 20, 22, 24 may also include at least one magnet 35, such as a micromagnet (see Figures 11B-11D ). At least one micromagnet 35 can be placed on top of the components 16, 18, 20, 22, 24. The at least one micromagnet provides a magnetic field. The magnetic field can have a zero gradient or a non-zero gradient. The at least one magnet 35 can be 150 nm away from the quantum well 69. The dimensions of the at least one magnet 35 can be 400 nm x 200 nm x 20 nm. The at least one magnet 35 can be arranged on a dielectric or insulating layer 68 (see Figures 11B-11D ). A dielectric or insulating layer 68 may be disposed on the transfer gate 50b (see Figure 11B ) or top gate 50d (see Figure 11C and Figure 11D and below).

[0093] The external magnetic field B0 splits multiple spin states (e.g., up spin state and down spin state) used as the basis for computation of one or more qubits into spin-dependent energy levels (Zeeman splitting). The external magnetic field B0 can be provided by an external magnet (e.g., an electromagnet (not shown)) located near the quantum processor 10. The quantum processor 10 can be at least partially placed in the external magnetic field provided by the external magnet.

[0094] One or more components 16, 18, 20, 22, 24 may further include a device for providing electromagnetic radiation (e.g., microwaves) for manipulating the quantum state of one or more qubits (e.g., switching the spin of one or more qubits between multiple spin states). Electromagnetic radiation can be provided by one or more gate electrodes 50b. By electromagnetic radiation based on electron spin resonance (ESR), the spin of one or more qubits can thereby be switched, for example, between an up spin state and a down spin state, or vice versa. The frequency of the electromagnetic radiation can be equal to the energy difference of the separated energy levels. ESR provides another way to manipulate the quantum state of one or more qubits. Microwaves can have a frequency in the range of hundreds of MHz to hundreds of GHz. In one aspect, the frequency is in the range of 9-10 GHz, but is not limited thereto.

[0095] For example, a non-uniform magnetic field is provided by at least one magnet 35, i.e., with a non-zero gradient, so that the quantum state of one or more qubits can be manipulated, such as the spin of a rotation qubit. This rotation makes it possible to drive the transition between multiple spin states by the displacement of one or more qubits in a non-uniform magnetic field based on, for example, an AC electric field. The AC electric field can be provided by one or more gate electrodes 50b. The AC electric field can be provided by one or more gate electrodes 50b. This effect is called electric dipole spin resonance (EDSR). The displacement can cause one or more qubits to oscillate between multiple spin states (for example, spin states forming the basis of calculation, such as an up spin state and a down spin state). For example, one or more qubits can oscillate so that an up spin state can be switched to a down spin state, and vice versa.

[0096] Alternatively, EDSR may be implemented in a semiconductor heterostructure 12 in which spin-orbit coupling exists. The semiconductor heterostructure 12 may be made of a semiconductor material that provides spin-orbit coupling.

[0097] The plurality of gate electrodes 50 may be provided as one or more gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may include one or more laterally positioned gate electrodes 50a (also referred to as "shielding gates") (see Figure 3A ), which is arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 5) to move (shuttle) one or more qubits within or outside the unit cell 26. Trajectory 80 can be the trajectory of one or more potential wells (described further below) in which one or more qubits can be arranged. The one or more potential wells can therefore be one or more traveling potential wells. The trajectory 80 of the one or more potential wells can therefore correspond to the trajectory of one or more qubits arranged on at least one path 45. Therefore, the lateral position of trajectory 80 can correspond to the lateral position of one or more potential wells and / or one or more qubits. Arranging one or more qubits on at least one path 45 should be understood to mean that the one or more qubits are arranged within quantum well 69.

[0098] The plurality of gate electrodes 50 may further include one or more shuttle gate electrodes 50b (also referred to as "transfer gates" or "finger gates") (see Figure 3A ), which is arranged to move (shuttle) one or more qubits along at least one path 45 to move (shuttle) one or more qubits within the unit cell 26 or outside the unit cell 26.

[0099] The plurality of gate electrodes 50 may further include at least one pitch-enhanced gate electrode 50d (also referred to as a "top gate") arranged so as to enhance the pitch or gap of the transfer gates 50b.

[0100] The plurality of gate electrodes 50 may further include at least one vertically positioned gate electrode 50c (also referred to as a "back gate") arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 3D ) to move (shuttle) one or more qubits within or outside unit cell 26. The vertical position of trajectory 80 may correspond to the vertical position of one or more potential wells and / or one or more qubits.

[0101] The plurality of gate electrodes 50 may further include qubit processing gate electrodes, which are configured to perform at least one action on one or more qubits. The qubit processing electrodes include plunger gates and barrier gates. The plunger gates can be used to control quantum dot occupancy, control detuning in a double quantum dot, and / or perform a swap between two qubits. The barrier gates can be used to form a double potential well and / or control the tunneling barrier in the double quantum dot.

[0102] A plurality of gate electrodes 50 may be arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers separated by an insulating or dielectric layer 60 and / or an insulating or dielectric layer 66 (see Figure 3B and Figure 3DIn one aspect, the layers can be arranged in a direction substantially perpendicular to the direction of at least one path 45.

[0103] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67 may be planarized. One method of manufacturing the shuttle element 16 may include the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before the transfer gate 50b is positioned on the insulating or dielectric layer 60. Planarization facilitates the use of processes such as electron beam epitaxy, deep ultraviolet (DUV), and / or spacer lithography. Planarization reduces the thickness of one or more of the dielectric or insulating layers 60, 66, and 67. For example, before fabricating the transfer gate 50b, the insulating or dielectric layers 66 and / or 60 may be planarized to reduce the thickness of the insulating or dielectric layers 66 and / or 60, respectively. After planarization, the insulating or dielectric layers 66 and / or 60 are tightly positioned on the semiconductor heterostructure 12. Planarizing insulating or dielectric layer 66 and / or 60 results in a reduced thickness of insulating or dielectric layer 66 and / or 60 between at least one via 45 and transfer gate 50b. In one aspect, the thickness of insulating or dielectric layer 60 is required to cover the top and side surfaces of shield gate 50a.

[0104] Component 16 is used to move (shuttle) one or more quantum dots in semiconductor heterostructure 12 to move (shuttle) one or more qubits within or outside unit cell 26. Component 16 is also referred to as a "shuttle channel." Various aspects of shuttle channel 16 are disclosed in International Patent Application No. WO 2021 / 052531A1, the entire disclosure of which is incorporated herein by reference.

[0105] Component 18 provides a junction at which one or more quantum dots can be diverted into at least one branch 45' (at least one second path in at least one path 45) branching out from at least one path 45 for moving (shuttling) one or more quantum bits within or outside the unit cell 26. Component 18 is also referred to as a "T-junction". The at least one path 45 and the at least one branch 45' of the T-junction 18 are arranged substantially perpendicular to each other. In one aspect, the at least one path 45 and the at least one branch 45' of the T-junction 18 can substantially form a T-shape. Various aspects of the T-junction 16 are disclosed in International Patent Application No. WO2021 / 052539 A1, the entire disclosure of which is incorporated herein by reference.

[0106] Component 20 is provided for manipulating qubits in quantum dots. Component 20 is also referred to as a "manipulation zone." Manipulation zone 20 enables manipulation of one or more current spin states of one or more qubits. Any qubit has a current spin state. In one aspect, multiple spin states may include the current spin state. In another aspect, the current spin state may be a linear combination of multiple spin states. During manipulation, one or more current spin states may change. Aspects of manipulation zone 20 are disclosed in WO 2021 / 052537 A1, the entire disclosure of which is incorporated herein by reference.

[0107] Component 22 is used to initialize one or more spin states of one or more quantum bits. When one or more spin states have been initialized, any one of the one or more current spin states is equal to one spin state in the plurality of spin states. After initialization, one or more current spin states may remain unchanged during the relaxation time. The relaxation time describes the transition between the upper spin state and the lower spin state due to interaction with the environment (such as the lattice of the semiconductor heterostructure 12). Component 22 is also referred to as an "initialization zone". Various aspects of the initialization zone 22 are disclosed in WO 2021 / 052538 A1, the entire disclosure of which is incorporated herein by reference.

[0108] Component 24 is used to read out one or more current spin states of one or more qubits. When one or more spin states have been read out, any one of the one or more current spin states before the readout is known. Component 24 is also referred to as the "readout region." Various aspects of readout region 24 are disclosed in WO 2021 / 052536 A1, the entire disclosure of which is incorporated herein by reference.

[0109] In one aspect of the present disclosure, one component 22 , 24 for initialization and readout includes an initialization area 22 and a readout area 24 .

[0110] The quantum processor 10 is operated to execute an algorithm, such as a quantum algorithm. As described above, executing the algorithm includes performing a sequence of actions on one or more qubits. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cell 26.

[0111] Operating quantum processor 10 involves controlling at least one action performed by components 16, 18, 20, 22, and 24. In one aspect of the present disclosure, the at least one action is controlled by applying voltages to a plurality of gate electrodes 50. The voltages can be set and / or adjusted to improve the fidelity F of the at least one action and / or sequence of actions. Fidelity F is a measure of how reliably the at least one action or sequence of actions produces the expected result based on the design of quantum processor 10 and the voltages applied to the plurality of gate electrodes 50. To determine fidelity F, at least one action or sequence of actions is repeated; the proportion of repetitions in which the actual result equals the expected result is then determined. The actual result includes one or more current spin states that have been read out at readout region 24 after the at least one action or sequence of actions. The expected result includes one or more current spin states that are expected to be read out at readout region 24 after the at least one action or sequence of actions based on the known fidelity of components 16, 18, 20, 22, and 24 and / or the relaxation time of one or more qubits.

[0112] For example, at least one action may include moving (shuttling) one or more qubits along at least one path 45 of the shuttling channel 16. In this case, the fidelity F is the shuttling fidelity. Shuttling fidelity is understood as the probability that one or more current spin states of one or more qubits are preserved during shuttling. For example, the shuttling fidelity may be determined by repeatedly performing a sequence of actions: initializing one or more qubits, moving (shuttling) one or more qubits, and reading out one or more qubits; then determining whether the initialized spin state of the one or more qubits is equal to the one or more current spin states after shuttling and before reading out; and finally calculating the proportion of repetitions in which one or more current spin states are unchanged.

[0113] Another example is turning one or more qubits during the movement of one or more qubits. When one or more qubits approach the T-junction 18, moving the one or more qubits may include turning the one or more qubits at the junction 28. Turning means changing the direction in which the one or more qubits are moving. The T-junction 18 may be connected to the straight-line shuttle fidelity F. ss During a straight-line shuttle, one or more qubits do not change the direction in which one or more qubits are moving (see below Figure 7 ). Linear shuttling fidelity is similar to the shuttling fidelity described above. However, linear shuttling involves moving one or more qubits through the junction 28. In addition, the T-junction 18 can be used with the off fidelity F To During the off period, one or more qubits change the direction in which one or more qubits are moving (see below Figure 7Switching off involves changing the direction in which one or more qubits move at junction 28.

[0114] As explained above, determining the shuttle fidelity Fs involves an initialization step and a readout step. M In a manner similar to that described above, the shuttle fidelity F can be determined by determining the fidelity F (which is a combination, i.e., the product, of the initialization fidelity, the shuttle fidelity, and the readout fidelity) and then dividing the fidelity F by the initialization fidelity and the readout fidelity. s Similarly, the straight-line shuttle fidelity F ss Can be determined as: initialization fidelity, straight-line shuttle fidelity F ss The combined fidelity F is then divided by the initialization fidelity and the readout fidelity. Similarly, the shutdown fidelity F To Can be determined as: initialization fidelity, shutdown fidelity F To The combined fidelity F is calculated as the combined fidelity of the initialization fidelity and the readout fidelity, and the combined fidelity F is then divided by the initialization fidelity and the readout fidelity.

[0115] In another example, the at least one action may include moving (shuttling) one or more qubits along at least one path 45 of the shuttle channel 16 (e.g., to the manipulation region 20), and manipulating the quantum state of the one or more qubits in the manipulation region 20. In this case, the fidelity F of performing the at least one action is the shuttling fidelity F S and manipulation fidelity F M The combination (i.e., product), that is, F = F S ×F M Then, the manipulation fidelity F associated with the manipulation area 20 M It can be calculated by dividing the fidelity F by the shuttle fidelity. M is understood as the probability that one or more current spin states of one or more qubits change as expected during the manipulation. For example, the shuttling fidelity F can be determined by repeatedly performing the following sequence of actions S : Initialize the qubit, move (shuttle) the qubit, and read out the qubit; then determine whether the initialized spin state of one or more qubits is equal to one or more current spin states after shuttling and before reading out; and finally calculate the proportion of repetitions in which one or more spin states remain unchanged. For example, the manipulation fidelity F can be determined by repeatedly performing the following sequence of actions M: initialize one or more qubits, move (shuttle) one or more qubits, manipulate one or more qubits, and read out one or more qubits; then determine whether one or more initialized current spin states of the one or more qubits change as expected; calculate the proportion of repetitions in which one or more current spin states change as expected, and divide the result by the shuttling fidelity F S .

[0116] Fidelity F may also be gate fidelity. Gate fidelity F is a measure of how well the results of a gate operation (i.e., a sequence of actions performed by components 16, 18, 20, 22, 24 on one or more qubits associated with the gate that quantum processor 10 is designed to implement) match expected results (e.g., theoretical results) based on the design of quantum processor 10 and components 16, 18, 20, 22, 24. Gate fidelity F can be determined through randomized benchmark testing.

[0117] As an example, improving the shuttling fidelity F of a single qubit along the shuttling channel 16 will be described. Figure 3A 1 shows aspects of a shuttle channel 16. The shuttle channel 16 includes a shield gate 50a and a transfer gate 50b disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 3A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 3B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0118] The shield 50a is arranged to extend on either side of at least one path 45 as shields 50a-1 and 50a-2 (see also Figure 3C ). In one aspect, as Figure 3A-3C As shown, the shielding grids 50a-1 and 50a-2 may extend continuously along at least one path 45. Figure 6A-6B As shown, one of the shield gates 50a-1 and 50a-2 can be interrupted along at least one path 45, for example, where a branch 45' branches off from at least one path 45. Shield gates 50a-1 and 50a-2 can be separated by approximately 200 nm. Shield gate 50a can be made of metal and can be fabricated by embedding the metal into semiconductor heterostructure 12 or by localized implantation of the metal into semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0119] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extends into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0120] The transfer gate 50b is arranged to extend laterally across at least one path 45 (eg Figure 3A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b may be arranged along at least one path 45.

[0121] In such Figure 3A In the aspect shown, transfer gates 50b are provided in the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 (in Figure 3A The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding electrode subsets. Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B The tops of the columns are marked with the same index, either 1, 2, 3, or 4. Figure 3A The number of electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 shown in FIG is four. However, the number of electrode subsets of the transfer gate 50b can be different from this example, for example, three or five. Any number of electrode subsets of the transfer gate 50b can be selected as long as one or more traveling potential wells can be generated for moving (shuttling) the qubit or one or more qubits (see below).

[0122] One or more traveling potential wells provide confinement for trapped electrons or holes, which are strong enough to overcome disorder during movement (shuttling) in the quantum well 69, and whose height provides a barrier between adjacent potential wells to inhibit tunneling. The trapped electron or holes adiabatically follow a sufficiently slow transition in potential. The disorder is due to one or more of defects at the layer boundaries of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and / or defects within the dielectric layers 60, 66, and / or 67. The defects at the layer boundaries of the semiconductor heterostructure 12 include charge defects at the interface between the layer made of semiconductor material and the dielectric or insulating layer 60 and / or 66. These charge defects are randomly distributed, for example at the interface. The density of the charge defects is set to 5E10 / cm 2 Transitions of electrons confined in one or more traveling potential wells to excited orbital states are disorder-induced. Quasi-static fluctuations of disorder in the moving frame of one or more traveling potential wells transform into dynamic noise at the coupled orbital level. Setting the shuttle velocity to v = 10 m / s results in a reduced orbital excitation rate and subthreshold phase errors.

[0123] As another example, increasing the manipulation fidelity F of one or more qubits (e.g., a single qubit or two qubits) at the manipulation region 20 will be described. M . Figure 11A 1 shows aspects of the steering region 20. The steering region 20 includes a shield gate 50a and a transfer gate 50b disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 11A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 11B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0124] The shielding grid 50a is arranged to extend as shielding grids 50a-1 and 50a-2 on either side of the first path 451 and the second path 452 (see also Figure 11A ). In one aspect, as Figures 11A-11C As shown, shield gates 50a-1 and 50a-2 can extend continuously along at least one path 45. In another aspect, shield gates 50a-1 and 50a-2 can be interrupted. Shield gates 50a-1 and 50a-2 can be separated by about 200 nm, such as 190 nm, 195 nm, 200 nm, 205 nm, 210 nm, or values ​​between or exceeding 190 nm or 210 nm. Shield gate 50a can be made of metal and can be manufactured by embedding metal into semiconductor heterostructure 12 or by localized implantation of semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0125] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, with the semiconductor heterostructure 12 extending into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0126] The transfer gate 50b may extend laterally across the first path 451 and / or the second path 452 (eg, Figure 11A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b is arranged along at least one path 45.

[0127] exist Figure 11A In the illustrated aspect, the transfer gate 50b has a first transfer gate assembly 50b1 and a second transfer gate assembly 50b2. Figures 11A-11D , the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are indicated by the curly brackets at the top of the drawing. In addition, for clarity, Figures 11A-11D 1 and 2. Three electrodes belonging to the first transfer gate assembly 50b1 and three electrodes belonging to the second transfer gate assembly 50b2 are shown in FIG. The first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 are arranged to extend laterally across at least a portion of the first path 451 and / or the second path 452, respectively. The first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are arranged at the interface 25 such that the first path 451 and the second path 452 meet at the interface 25 (see FIG. Figure 11A and Figure 11B ).

[0128] First path 451 and second path 452 meet at interface 25, allowing a first qubit trapped in the first quantum dot and shuttled to interface 25 along first path 451 and a second qubit trapped in the second quantum dot and shuttled along second path 452 to undergo at least one two-qubit action (or operation) at interface 25. The one or more potential wells may include one or more first potential wells. The first qubit may be shuttled (moved) along first path 451 by one or more first traveling potential wells. The one or more first traveling potential wells may be generated by applying a voltage to first transfer gate assembly 50b1. Similarly, the one or more potential wells may include one or more second potential wells. The second qubit may be shuttled (moved) along second path 452 by one or more second traveling potential wells. The one or more second traveling potential wells may be generated by applying a voltage to second transfer gate assembly 50b2.

[0129] At least one two-qubit action (or operation) at the interface 25 is achieved by forming a potential well in one or more potential wells ("one or more static potential wells") that are static at the interface. The one or more static potential wells may include at least one first static potential well and at least one second static potential well.

[0130] At least one first static potential well can be disposed at interface 25. For example, the at least one first static potential well can be adjacent to the interface. The at least one first static potential well can be generated by first transfer gate assembly 50b1. Similarly, at least one second static potential well can be disposed at interface 25. For example, the at least one second static potential well can be adjacent to the interface. The at least one second static potential well can be generated by second transfer gate assembly 50b2.

[0131] A first qubit can be trapped in at least one first static potential well. Similarly, a second qubit can be trapped in at least one second static potential well. When the at least one first static potential well and the at least one second static potential well are arranged at the interface 25, the first qubit trapped in the at least one first static potential well and the second qubit trapped in the at least one second potential well can undergo at least one two-qubit action (or two-qubit operation).

[0132] For example, a potential barrier may be formed between the at least one first static potential well and the at least one second static potential well by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 at the interface 25. For example, the potential barrier may be formed by the electrode subset 50b1-4 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-1 (described below) of the second transfer gate assembly 50b2.

[0133] Lowering / raising the potential barrier can increase / decrease tunneling coupling through the barrier (also referred to as the "tunneling barrier"). In one aspect, the height of the potential barrier can be modulated by pulses, such as non-adiabatic pulses. The confinement in the at least one first static potential well and the at least one second static potential well can be different from each other, or not, which is referred to as detuning. The detuning can be zero or non-zero. The detuning can be generated by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2. For example, the detuning can be generated by the electrode subset 50b1-3 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-2 (described below) of the second transfer gate assembly 50b2.

[0134] The tunneling coupling and the detuning determine the exchange coupling J between a first qubit trapped in a first static potential well and a second qubit trapped in a second static potential well. The exchange coupling J enables the first qubit and / or the second qubit to tunnel through the potential barrier to at least one first static well or at least one second static potential well.

[0135] The first transfer gate assembly 50b1 has electrode subsets 50b1-1, 50b1-2, 50b1-3. As an example, increasing the manipulation fidelity F of one or more qubits (eg, a single qubit or two qubits) at the manipulation region 20 will be described. M . Figure 11A 1 shows aspects of the steering region 20. The steering region 20 includes a shield gate 50a and a transfer gate 50b disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 11A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 11B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0136] The shielding grid 50a is arranged to extend on either side of the first path 451 and the second path 452 as shielding grids 50a-1 and 50a-2 (see also FIG. 123A ). Figures 11A-3C As shown, shield gates 50a-1 and 50a-2 can extend continuously along at least one path 45. In another aspect, shield gates 50a-1 and 50a-2 can be interrupted. Shield gates 50a-1 and 50a-2 can be separated by approximately 200 nm. Shield gate 50a can be made of metal and can be fabricated by embedding the metal into semiconductor heterostructure 12 or by localized implantation of the semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0137] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, with the semiconductor heterostructure 12 extending into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0138] The transfer gate 50b may extend laterally across the first path 451 and / or the second path 452 (eg, Figure 11A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b is arranged along at least one path 45.

[0139] exist Figure 11A In the illustrated aspect, the transfer gate 50b has a first transfer gate assembly 50b1 and a second transfer gate assembly 50b2. Figures 11A-11D , the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are indicated by the curly brackets at the top of the drawing. In addition, for clarity, Figures 11A-11D 1 and 2. Three electrodes belonging to the first transfer gate assembly 50b1 and three electrodes belonging to the second transfer gate assembly 50b2 are shown in FIG. The first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 are arranged to extend laterally across at least a portion of the first path 451 and / or the second path 452, respectively. The first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are arranged at the interface 25 such that the first path 451 and the second path 452 meet at the interface 25 (see FIG. Figure 11A and Figure 11B ).

[0140] First path 451 and second path 452 meet at interface 25, allowing a first qubit trapped in the first quantum dot and shuttled to interface 25 along first path 451 and a second qubit trapped in the second quantum dot and shuttled along second path 452 to undergo at least one two-qubit action (or operation) at interface 25. The one or more potential wells may include one or more first potential wells. The first qubit may be shuttled (moved) along first path 451 by one or more first traveling potential wells. The one or more first traveling potential wells may be generated by applying a voltage to first transfer gate assembly 50b1. Similarly, the one or more potential wells may include one or more second potential wells. The second qubit may be shuttled (moved) along second path 452 by one or more second traveling potential wells. The one or more second traveling potential wells may be generated by applying a voltage to second transfer gate assembly 50b2.

[0141] At least one two-qubit action (or operation) at the interface 25 is achieved by forming a potential well in one or more potential wells ("one or more static potential wells") that are static at the interface. The one or more static potential wells may include at least one first static potential well and at least one second static potential well.

[0142] At least one first static potential well can be disposed at interface 25. For example, the at least one first static potential well can be adjacent to the interface. The at least one first static potential well can be generated by first transfer gate assembly 50b1. Similarly, at least one second static potential well can be disposed at interface 25. For example, the at least one second static potential well can be adjacent to the interface. The at least one second static potential well can be generated by second transfer gate assembly 50b2.

[0143] A first qubit can be trapped in at least one first static potential well. Similarly, a second qubit can be trapped in at least one second static potential well. When the at least one first static potential well and the at least one second static potential well are arranged at the interface 25, the first qubit trapped in the at least one first static potential well and the second qubit trapped in the at least one second potential well can undergo at least one two-qubit action (or two-qubit operation).

[0144] For example, a potential barrier may be formed between the at least one first static potential well and the at least one second static potential well by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 at the interface 25. For example, the potential barrier may be formed by the electrode subset 50b1-4 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-1 (described below) of the second transfer gate assembly 50b2.

[0145] Lowering / raising the potential barrier can increase / decrease tunneling coupling through the barrier (also referred to as the "tunneling barrier"). In one aspect, the height of the potential barrier can be modulated by pulses, such as non-adiabatic pulses. The confinement in the at least one first static potential well and the at least one second static potential well can be different from each other, or not, which is referred to as detuning. The detuning can be zero or non-zero. The detuning can be generated by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2. For example, the detuning can be generated by the electrode subset 50b1-3 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-2 (described below) of the second transfer gate assembly 50b2.

[0146] The tunneling coupling and the detuning determine the exchange coupling J between a first qubit trapped in a first static potential well and a second qubit trapped in a second static potential well. The exchange coupling J enables the first qubit and / or the second qubit to tunnel through the potential barrier to at least one first static well or at least one second static potential well.

[0147] The first transfer gate assembly 50b1 has a subset of electrodes 50b1-1, 50b1-2, 50b1-3, 50b1-4 (at Figures 11A-11D The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding electrode subsets. Figures 11A-11D The tops of the columns are marked with the same index, either 1, 2, 3, or 4. Figure 11A The number of electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 shown is four. Similarly, the second transfer gate assembly 50b2 has electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 (in Figures 11A-11D The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding subset. Figures 11A-11D The tops of are marked with the same index, i.e., index 1, 2, 3, or 4. Figures 11A-11D As shown, interface 25 is located at one electrode of the subset of electrodes 50b1-4 of first transfer gate assembly 50b1 and at one electrode of the subset of electrodes 50b2-1 of second transfer gate assembly 50b2. Figure 11AThe number of electrode subsets 50b2-1, 50b2-2, 50b2-3, and 50b2-4 shown in FIG is four. However, the number of electrode subsets of the first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 may be different from this example, for example, three or five. Any number of electrode subsets of the transfer gate 50b may be selected as long as one or more traveling potential wells for moving (shuttling) qubits (see below) can be generated. 50b1-4 (in FIG Figures 11A-11D The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding electrode subsets. Figures 11A-11D The tops of the columns are marked with the same index, either 1, 2, 3, or 4. Figure 11A The number of electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 shown is four. Similarly, the second transfer gate assembly 50b2 has electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 (in Figures 11A-11D The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding subset. Figures 11A-11D The tops of are marked with the same index, i.e., index 1, 2, 3, or 4. Figures 11A-11D As shown, interface 25 is located at one electrode of the subset of electrodes 50b1-4 of first transfer gate assembly 50b1 and at one electrode of the subset of electrodes 50b2-1 of second transfer gate assembly 50b2. Figure 11A The number of electrode subsets 50b2-1, 50b2-2, 50b2-3, and 50b2-4 shown in FIG is four. However, the number of electrode subsets of the first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 can be different from this example, for example, three or five. Any number of electrode subsets of the transfer gate 50b can be selected as long as one or more traveling potential wells for moving (shuttling) qubits (see below) can be generated, as explained above with respect to the shuttle channel 16.

[0148] In one aspect, the transfer gates 50b may be arranged at at least one path 45 in such a manner that juxtaposed ones of the transfer gates 50b extend different distances in the lateral (or transverse) direction D3 (eg, Figure 3A In another aspect, transfer gate 50b may extend equally far in lateral direction (or transverse direction) D3.

[0149] The transfer gates 50b can be arranged in a substantially equidistant manner with a substantially constant transfer gate gap between any two adjacent transfer gates 50b. If the transfer gate width of the transfer gates 50b, i.e., the extension of the transfer gates 50b in the longitudinal direction D3, is substantially constant, then the transfer gate pitch (the sum of the transfer gate gap and the transfer gate width) is substantially constant. In one aspect of the present disclosure, the transfer gate pitch can be approximately 80 nm. The transfer gates 50b can be arranged in a periodic manner. In one aspect, the transfer gates 50b of any one of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged in a substantially equidistant manner from one another based on the spatial period of the periodically arranged transfer gates. In another aspect, any two transfer gates 50b belonging to any selected electrode subset of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 have one transfer gate of each other unselected electrode subset of these electrode subsets arranged therebetween. The periodic arrangement of the transfer gates 50b facilitates industrial manufacturing of the shuttle channel 16.

[0150] like Figure 3A As shown, the transfer gates 50b belonging to one of the four electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically connected to each other by electrical connections (not shown). The element gates of any electrode subset selected from the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically disconnected (or not electrically connected) from the element gates of the corresponding unselected electrode subsets. The electrical connection can be provided by a metal strip arranged parallel to the shield gate 50a. The electrode subsets of the transfer gates 50b indexed 1 and 3 can be on one side of at least one path 45 (e.g., Figure 3A The subset of electrodes of the transfer gates 50b indexed 2 and 4 may have an electrical connection on the other side of at least one path 45 (as shown). Figure 3AAs shown, below at least one path 45). In one aspect of the present disclosure, the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged at different levels in the stacking direction D1. For example, the metal strips connecting the transfer gates of the electrode subset 50b-1 can be arranged on one side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-3; and the metal strips connecting the transfer gates of the electrode subset 50b-2 can be arranged on the other side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-4. The electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can each be arranged at the level where the corresponding metal strips are arranged. On the other hand, the metal strips can all be arranged on one side of at least one path 45. In a further aspect, the metal strips in the metal strips connecting the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be electrically connected to the transfer gates of the corresponding electrode subsets through through-holes; and the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be basically arranged on one level in the stacking direction D1.

[0151] Likewise, if Figure 11A As shown, the transfer gates belonging to any one of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4 are electrically connected to each other via electrical connections (not shown). The transfer gates of any selected electrode subset from the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4 are electrically disconnected (or not electrically connected) from the transfer gates of the other electrode subsets (i.e., the corresponding unselected electrode subsets) from the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4. The electrical connection can be provided by a metal strip arranged parallel to the shielding grid 50a. The electrode subsets of the transfer gates 50b1 and / or 50b2 indexed 1 and 3 may be on one side of at least one path 45 (e.g., Figure 11A The electrode subsets of the transfer gates 50b indexed 2 and 4 may be on the other side of the at least one path 45 (e.g., Figure 11AAs shown, there is an electrical connection below at least one path 45. In one aspect of the present disclosure, the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged at different levels in the stacking direction D1. For example, the metal strips connecting the transfer gates of the electrode subset 50b-1 can be arranged on one side of at least one path 45, which is arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-3; and the metal strips connecting the transfer gates of the electrode subset 50b-2 can be arranged on the other side of at least one path 45, which is arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-4. The electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can each be arranged at the level where the corresponding metal strips are arranged. In another aspect, all of the metal strips can be arranged on one side of at least one path 45. In a further aspect, the metal strips in the metal strips connecting the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be electrically connected to the transfer gates of the corresponding electrode subsets through through-holes; and the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be basically arranged on one level in the stacking direction D1.

[0152] The electrical connection of the element gates of any of the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 or 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4 enables a single voltage to be supplied to the corresponding electrode subset. In other words, the number of voltage signals applied to the transfer gate 50b is given by the number of electrode subsets selected. Thus, the number of voltage signals applied to the shield grid 50a and the transfer grid 50b is independent of the length of the shuttle element 16. In the case of Figure 3A and Figure 3B In the example shown, the number of electrode subsets is four. However, this number can be smaller or larger than four. For example, using three electrode subsets can achieve the movement of one or more qubits through the traveling potential well.

[0153] At least one magnet 35 provides a magnetic field (not shown). The magnetic field can be a non-uniform magnetic field. The magnetic field provided by the at least one magnet 35 can have a non-zero magnetic field strength at the quantum well 69. The magnetic field can have a longitudinal component of a non-zero longitudinal magnetic field strength along the shuttling direction (or longitudinal direction) D2 at the quantum well 69. The magnetic field can have a transverse component of a non-zero transverse magnetic field strength along the lateral (or transverse) direction D3 at the quantum well 69.

[0154] Furthermore, the magnetic field of the at least one magnet 35 may have a transverse component with a non-zero transverse magnetic field strength and be transverse to the external magnetic field B0. The transverse component of the magnetic field may have a gradient in the shuttling direction D2. Additionally or alternatively, the magnetic field of the at least one magnet 35 may have a parallel component with a non-zero parallel magnetic field strength and be parallel to the external magnetic field B0. The parallel component of the magnetic field may have a gradient in the shuttling direction D2.

[0155] This enables a magnetic field to act on one or more qubits when one or more qubits are trapped in a potential well in a quantum well 69 having a non-zero magnetic field strength. Utilizing the non-uniform magnetic field of at least one magnet 35, EDSR (see above) can be used to rotate one or more spins of one or more qubits.

[0156] like Figures 11A-11D As shown, the at least one magnet 35 may include a first magnet 35-1 and a second magnet 35-2. An example of the first magnet 35-1 is a first micro magnet. An example of the second magnet 35-2 is a second micro magnet.

[0157] The first magnet 35-1 can be disposed at the first transfer gate assembly 50b1. The first magnet 35-1 can be disposed a distance from the interface 25. The first magnetic field of the first magnet 39-1 (which can be non-uniform) has a non-zero first magnetic field strength (having a longitudinal component and / or a transverse component, as described above) at the first portion 69-1 of the quantum well 69. In one aspect, the first magnetic field strength substantially vanishes at the interface 25.

[0158] The second magnet 35-2 can be disposed at the first transfer gate assembly 50b1. The second magnet 35-2 can be disposed near the interface 25. In one aspect, the second magnet 35-2 can be disposed at the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2. In other words, the second magnet 35-2 can extend across the interface 25 in the shuttling direction (or longitudinal direction) D2.

[0159] The second magnetic field of the second magnet 39-2 (which may be non-uniform) has a non-zero second magnetic field strength (having a longitudinal component and / or a transverse component, as described above) at the second portion 69-2 of the quantum well 69. The second portion 69-2 may be located near the interface 25. In one aspect, the second portion 69-2 of the quantum well 69 may be located on both sides of the interface 25 along the shuttling direction (or longitudinal direction) D2. The second magnetic field strength may have a non-zero value at the interface 25.

[0160] In another aspect of the present disclosure, the manipulation area 20 may include only the first magnet 35 - 1 or only the second magnet 35 - 2 .

[0161] In a further aspect of the present disclosure, the shuttle path 16 and / or the manipulation region 20 may include a top gate 50d (see Figure 3D 、 Figure 11C and Figure 11D ). The top gate 50d can extend in the lateral (transverse) direction D3. The top gate can extend in the shuttling direction (or longitudinal direction) D2. The top gate 50d can cover at least a portion of the first path 451 and / or the second path 452. In one aspect, at least in the lateral (transverse) direction D3, the top gate 50d completely covers the first path 451 and / or the second path 452.

[0162] In another aspect of the present disclosure, a top gate electrode 50d may be disposed above the transfer gate 50b with a dielectric or insulating layer 67 disposed therebetween. The dielectric or insulating layer 67 may be partially disposed on the dielectric or insulating layer 60 (see FIG. Figure 3D 、 Figure 11C and Figure 11D ). Portions of the dielectric or insulating layer 67 disposed between the transfer gates 50b may be disposed on the dielectric or insulating layer 60. The dielectric or insulating layer 67 may be structured in the shuttle direction D2, for example segmented or profiled (see Figure 3D 、 Figure 11C and Figure 11D ). The dielectric or insulating layer 67 can be structured in the shuttle direction D2, for example segmented or profiled (see Figure 3D and Figure 11D ). Dielectric or insulating layer 67 insulates transfer gates 50b belonging to different subsets of subsets 50b-1, 50b-2, 50b-3, 50b-4 from each other. In one aspect of the present disclosure, dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67 in which transfer gates 50b are embedded.

[0163] A constant voltage can be applied to the top gate 50d. In a further aspect, the voltage applied to the top gate 50d can be modified to perform one or more actions on one or more qubits. For example, the voltage applied to the top gate 50d can be modified to shuttle one or more qubits, to initialize one or more qubits, to read out one or more qubits, or to manipulate one or more qubits. In another example, the voltage applied to the top gate 50d can be modified based on a sequence of actions performed on one or more qubits, for example as part of an execution algorithm. In a further aspect, the voltage applied to the top gate 50d can be modified periodically or non-periodically. Periodically modifying and / or non-periodically modifying the voltage applied to the top gate 50d can depend on the actions performed on the one or more qubits. Periodically modifying the voltage applied to the top gate 50d includes adding a superposition of a square wave, a sawtooth wave, or a sine wave. Periodically modifying the voltage applied to the top gate 50d includes adding stepwise increments to the voltage applied to the top gate 50d. The step increment may depend on one or more actions performed on one or more qubits.

[0164] In one aspect, the top gate can have a flat top surface (not shown). In another aspect of the present disclosure, the top gate 50d can be structured. An example of a structured top gate 50d is a segmented top gate 50d. Another example of a structured top gate 50d is a top gate with a surface profile (or a shaped top gate), such as Figure 3D or Figure 11D In one aspect, the top gate 50d may be a segmented and shaped top gate. Figure 3D and Figure 11D As shown, the top grid 50d can be constructed along the shuttle direction (or longitudinal direction) D2, such as segmented and / or profiled. In addition to or instead of the longitudinal construction, the top grid 50d can be constructed along the lateral direction (or transverse direction) D3, such as segmented and / or profiled. Figure 11D In the illustrated aspect, the top gate 50d includes a plurality of electrodes 50d-1, 50d-2, ..., 50d-12.

[0165] The top gate 50d enables the spacing between the transfer gates 50b to be increased while maintaining the ability to shuttle one or more qubits along at least one path 45. In addition, Figure 11D The constructed (e.g., segmented) top gate 50d shown in FIG enables tuning of the Rabi frequency of the EDSR generated by the magnetic field of at least one magnet 35 and the applied AC electric field, for example by applying one or more adjustment voltages (see below) to one or more of the multiple electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d.

[0166] In aspects of the present disclosure, at least one surface 14 may further include a back surface 142. At least one back gate 50c may be disposed on the back surface 142 of the semiconductor heterostructure 12 opposite to the top surface 141 (see FIG. Figure 3D ).exist Figure 3D In the illustrated aspect, the back surface 142 is disposed at the bottom of the semiconductor heterostructure. The back surface 142 is disposed opposite the top surface 141. The back surface 142 may be a surface of the silicon dioxide layer 62 (described above).

[0167] exist Figure 3D In the illustrated aspect, the at least one back gate 50c extends along the shuttling direction or longitudinal direction D2 of the shuttle channel 16. The at least one back gate 50c can also extend laterally (or transversely to the at least one path 45). For example, the at least one back gate 50c can also extend along a lateral (or transverse) direction D3 of the shuttle channel 16 that is transverse to the at least one path 45. The at least one back gate 50c can overlap or intersect the shield gate 50a in the lateral direction D3. The at least one back gate 50c can be arranged opposite the shield gate 50a. A voltage can be applied to the at least one back gate 50c to provide an electric potential to modify the confinement at the quantum well 69.

[0168] In one aspect of the present disclosure, at least one back gate 50c can be configured along the shuttling direction (or longitudinal direction) D2, e.g., segmented and / or profiled. In another aspect of the present disclosure, at least one back gate 50c can be configured along the lateral direction D3 (i.e., transverse to at least one path 45), e.g., segmented and / or profiled. In a further aspect of the present disclosure, at least one back gate can be configured along the shuttling direction (or longitudinal direction) D2 and the lateral direction D3, e.g., segmented and / or profiled.

[0169] For example Figure 3B As shown, shield gate 50a and transfer gate 50b are separated by an insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during fabrication before transfer gate 50b is disposed on the insulating or dielectric layer 60. The four electrode subsets of transfer gate 50b are separated by an additional insulating or dielectric layer or material (not shown). In addition, a dielectric or insulating layer 66 may be disposed on semiconductor heterostructure 12 (see FIG. Figure 3B and Figure 4B The shield gate 50a is separated from the semiconductor heterostructure 12 by an insulating or dielectric layer 66. The shield gate 50a may be disposed on the insulating layer 66.

[0170] The shuttle channel 16 is configured to move (shuttle) one or more qubits along at least one path 45. During operation of the quantum processor 10, the shuttle channel 16 will be used to move one or more qubits, for example, from the initialization region 22 to the manipulation region 20 and then to the readout region 24. During this sequence of actions on one or more qubits, in one aspect of the present disclosure, two shielding grids (or "gates") 50a-1, 50a-2 (see FIG. 1 ) of the shielding grids 50a of the shuttle channel 16 may be moved. Figure 3A and Figure 3C ) are provided with the same voltage, for example 0V. An AC voltage is provided to the transfer gate 50b to provide one or more traveling potential wells in which one or more quantum bits can be moved (shuttled). The AC voltage provided to the transfer gate 50b can be a sinusoidal voltage. On the other hand, the AC voltage provided to the transfer gate 50b can be a non-sinusoidal voltage. Alternatively, the AC voltage provided to the transfer gate 50b can be a non-periodic voltage. The AC voltage provided to the transfer gate 50b can be phase-shifted between the electrode subsets of the transfer gates 50b-1, 50b-2, 50b-3, and 50b-4. The phase shifts of the transfer gates 50b-2, 50b-3, and 50b-4 relative to the transfer gate 50b-1 can be set to π / 2, π, and 3π / 2, respectively. However, other settings for the phase shift are also possible. The phase shift can deviate from being set to a multiple of π / 2.

[0171] One or more qubits are transmitted along at least one path 45 (along Figure 5 The x-axis extension of the trajectory 80 (see Figure 5 ) in the lateral direction D3 is determined by applying the two gate electrodes 50a-1, 50a-2 in the shielding grid 50a (see, for example, Figure 3C). If the voltage applied to gate 50a-1 is substantially equal to the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will be substantially in the middle of the two gates 50a-1, 50a-2. On the other hand, if the voltage applied to gate 50a-1 is different from the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will deviate from the middle of the two gates 50a-1, 50a-2. The different voltages on gates 50a-1, 50a-2 may be the result of changing the voltage applied to gate 50a-1 or the voltage applied to gate 50a-2 by adding an adjustment voltage ΔV. In other words, the voltage applied to gate 50a-1 or gate 50a becomes V+ΔV. For example, in the case where heterostructure 12 is an undoped Si / SiGe heterostructure, if the voltage applied to gate 50a-1 is reduced relative to the voltage applied to the other gate 50a-2, one or more locations of the generated one or more potential wells (i.e., one or more minima of the one or more potential wells) will shift toward the other gate 50a-2. In the case where heterostructure 12 is doped, such as when GaAs / AlGaAs is used, increasing the voltage applied to gate 50a-1 will shift the one or more potential wells toward the other gate 50a-2. In this way, the trajectory 80 of one or more qubits along at least one path 45 can be shifted laterally (i.e., in a lateral or transverse direction D3 relative to the at least one path 45).

[0172] In one aspect of the present disclosure, the lateral shift of the trajectory 80 of one or more qubits may be transient (at Figure 5 The transient lateral shift is the result of the addition of the time-varying adjustment voltage ΔV(t) to the voltage applied to gate 50a-1 or to gate 50a-2. In other words, the track 80 only temporarily deviates from the lateral position initially set during calibration (i.e., at Figure 5 A y-position of 0 nm in the example shown). A temporal lateral shift results in e.g. Figure 5 Trajectory 80-1 is shown.

[0173] In one aspect, the time-varying adjustment voltage ΔV(t) can be an AC voltage, such as a square pulse or square wave. Figure 5If the qubits are spaced an average distance of 1000 nm (or 1 μm) from each other along the x-axis in FIG45 and the shuttle speed of one or more qubits along at least one path 45 is 10 nm / ns (or 10 m / s), then on average, it takes 100 ns for one or more qubits to travel a distance equal to this average distance. Therefore, the time-varying modulation voltage ΔV(t) can last for 100 ns. For example, half a period of the square wave can be selected to be equal to 100 ns. In other words, the square wave can be selected to have a frequency of 5 MHz.

[0174] In a further aspect of the present disclosure, the adjustment voltage comprises a DC voltage added to the AC voltage applied to the transfer gate 50b. This DC voltage may be applied to the transfer gate 50b in addition to or in lieu of the adjustment voltage ΔV(t) applied to the shield gate 50a. The further adjustment voltage may provide a modification to the confinement provided by the transfer gate 50b, for example, to enhance the confinement when one or more qubits are near a fidelity reduction site 70 (see below).

[0175] The lateral shifting of the lateral position of trajectory 80-1 enables bypassing of reduced fidelity sites 70 in shuttle channel 16. When one or more qubits pass through reduced fidelity sites 70 in shuttle channel 16, the shuttling fidelity F may be reduced. The reduced shuttling fidelity F results in lower shuttling reliability of the one or more qubits along shuttle channel 16. Reduced fidelity sites 70 may be the result of, for example, manufacturing impurities, manufacturing defects, charge defects, crystal defects, and / or locally reduced valley splitting. Figure 5 A grayscale-coded valley splitting distribution plot is shown for valley splitting energies between 0 μeV and 300 μeV (lighter shaded areas correspond to higher valley splitting energies; darker shaded areas correspond to lower valley splitting energies). Fidelity reduction sites 70 are located at valley splitting energies between 0 μeV and approximately 30-50 μeV (illustrated by light shaded areas within dark shaded areas, some of which are surrounded by dashed ovals). Figure 5 In the example shown, the trajectory 80-1 bypasses several fidelity degradation sites 70 located at y positions of 0 nm. The fidelity degradation sites 70-1, 70-2, 70-3, ..., 70-10 are indicated by arrows and, in some cases, by white dashed elliptical markers. In the example shown, the deviation Δy from the lateral position of the trajectory 80 initially set during calibration (i.e., the y position of 0 nm set during the calibration step described below) is Figure 5 The peak value of about 20 nm is reached in the lateral direction D3 along the positive y-axis. Figure 5In another embodiment, the maximum values ​​of the deviation Δy in the two lateral directions (along the positive and negative y axes, respectively) may be different from 20 nm and -20 nm, respectively.

[0176] The lateral displacement of the lateral position y of the track 80 - 1 is further enabled to continuously adjust the lateral position y of the track 80 - 1 by a time-varying adjustment voltage ΔV(t). The time-varying adjustment voltage ΔV(t) results in a time-varying deviation Δy(t). Continuous adjustment may be required in the case of voltage fluctuations applied to the plurality of gate electrodes 50 .

[0177] In one aspect of the present disclosure, similar to the lateral shift described above, one or more vertical positions of one or more potential wells can be vertically shifted, i.e., in the stacking direction D1 (as described below). As a result, the vertical position of the track 80-3 (the position along the stacking direction D1) can be changed. When the voltage applied to at least one back gate 50c is changed, the confinement of the one or more potential wells changes. The voltage applied to at least one back gate 50c can be changed relative to the voltage applied to the shield gate 50a. According to at least one fidelity reduction site 70 (at Figure 3D The vertical position of the track 80 can be changed upward or downward in the stacking direction D1 by the position indicated by the asterisk in the figure. As a result, at least one fidelity reduction point 70 can be bypassed and the reliability (ie, fidelity) of the shuttle channel 16 can be improved.

[0178] Determination of the shuttle fidelity F enables identification of the location of the fidelity degradation site 70 at (e.g., along and / or near) the track 80-1 or 80-3. During identification of the location of the fidelity degradation site 70, the applied voltage V is iteratively adjusted. Thus, the lateral position of the track 80-1 and / or the vertical position of the track 80-3 are iteratively adjusted. Identification of the location of the fidelity degradation site 70 results in a method for controlling the shuttle channel 16.

[0179] In one aspect of the present disclosure, lateral and / or vertical shifting of trajectory 80 may be used in manipulation region 20 to move one or more qubits to a manipulation position that is inconsistent with a fidelity reduction site 70 .

[0180] Figure 6A The illustrated T-junction 18 includes a shuttling element 16 along at least one path 45 .

[0181] The T-junction 18 further includes a second shuttle element 16' (referred to as the "second shuttle element") in the shuttle element 16 along the branch 45'. Figure 6AAs shown, the second shuttle element 16' has two screens 50a'-1 and 50a'-2 extending in a second longitudinal (or shuttle) direction D2'. The second shuttle element 16' further includes a shuttle grid (or finger grid) 50b'. The shuttle grid 50b' extends in a second transverse (or lateral) direction D3'.

[0182] The at least one path 45 and the at least one branch 45' are arranged substantially perpendicular to each other. The second longitudinal direction D2' is perpendicular to the longitudinal direction D2. The second lateral direction D3' is perpendicular to the lateral direction D3.

[0183] Shuttle element 16 (referred to as "first shuttle element") and second shuttle element 16' are joined at junction 28. At least one path 45 and branch 45' meet at junction 28. Two shielding gates 50a'-1 and 50a'-2 terminate at junction 28. Transfer gate 50b' terminates at junction 28.

[0184] The screen 50a-1 of the first shuttle element 16 is interrupted in the longitudinal direction D2 at the junction 28. The screen 50a-1 is interrupted where the screens 50a'-1 and 50a'-2 of the second shuttle element 16' end. The screen 50a-1 is interrupted where the first shuttle element 16 and the second shuttle element 16' are joined to each other at the junction 28. The interruption can extend along the lateral direction D3' between at least the screens 50a'-1 and 50a'-2.

[0185] The shield grid 50a'-1 of the second shuttle element 16' can be connected to a portion of the shield grid 50a-1 of the first shuttle element 16. The shield grid 50a'-2 of the second shuttle element 16' can be connected to another portion of the shield grid 50a-1 of the first shuttle element 16. The shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be electrically connected in such a way that the shield grids 50a-1 and 50a'-1 (50a-2 and 50a'-2) effectively form a single continuous shield grid. In another aspect, the shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be designed as a single continuous shield grid. In another aspect, the shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be separated by a dielectric or insulating layer.

[0186] The transfer gates 50b' of the second shuttle element 16' can be arranged at the junction 28 in the second longitudinal direction D2' (or the lateral direction D3 of the first transfer gate 16) such that at least one of the transfer gates 50b' contacts or overlaps the shield gate 50a-1 of the first shuttle element 16 along the second longitudinal direction D2' (or the first lateral direction D3). Some of the transfer gates 50b' can have curved or angled ends in the lateral direction D3'. Some of the transfer gates 50b' can be arranged adjacent to the junction 28.

[0187] exist Figure 6A In the illustrated aspect, the transfer grid of the electrode subset 50b'-1 of the second shuttle element 16' closest to the junction 28 ("the last transfer grid 50b'") overlaps the shield grid 50a-1. The last transfer grid 50b' extends in the lateral direction D3' at least between the shield grids 50b'-1 and 50b'-2. The last transfer grid 50b is arranged adjacent to the lower edge of the shield grid 50a-1 along the lateral direction D3 (as shown in FIG. Figure 6A (as shown). This arrangement of the last transfer gate 50b' enables a shielding potential to be provided by applying a voltage to the last transfer gate 50b' to provide sufficient confinement for one or more qubits. The voltage applied to provide confinement can be fixed. Providing a shielding potential enables compensation for interruptions in the shield gate 50a-1 while shuttling one or more qubits along the shuttling element 16 at the junction 28.

[0188] The transfer gate 50b of the first shuttle element 16 is arranged at the junction 28 so that the transfer gate 50b does not contact the transfer gate 50b' of the second shuttle element 16'. Figure 6A As shown, the transfer gate 50b of the first shuttle element 50b at the junction is arranged below the last transfer gate 50b' of the second transfer element 16' along the lateral direction D3 (or the second longitudinal direction D2') (as shown in FIG. Figure 6A ).

[0189] As the one or more qubits move along branch 45' toward junction 28, a voltage V can be applied to transfer gate 50b of first shuttle element 16 to provide a quasi-stable potential well into the minimum of which the one or more qubits can adiabatically move by traveling the potential well along second shuttle element 16'. The quasi-stable potential well is generated by applying a static voltage to transfer gate 50b of first shuttle element 16. Once the one or more qubits are moved to the minimum of the quasi-stable potential well provided by transfer gate 50b of first shuttle element 16, the voltage applied to transfer gate 50b can be changed to an AC voltage to move (shuttle) the one or more qubits along at least one path 45 through first shuttle element 16.

[0190] To reverse the movement, the voltage applied to the transfer gates 50b and 50b' can be adjusted. Thus, the difference in confinement strength between the first shuttling element 16 and the branch 16' can be managed.

[0191] When one or more qubits are located at junction 28, the one or more qubits can be moved along longitudinal direction D3 or along second longitudinal direction D3'. One or more qubits can be shuttled along at least one path 45 without turning into branch 45'. One or more qubits can be shuttled along at least one path 45 and turned along branch 45' (or vice versa). Thus, T-junction 18 enables movement of one or more qubits on quantum chip 10.

[0192] Figure 7 A simulation of the orbital splitting between the ground state and the first excited state of one or more qubits during movement of the one or more qubits in a straight line along the first shuttle element 16 (left panel) is shown. The simulation shows that the orbital splitting is above 1 meV throughout the simulated movement. For a shuttle speed of about 10 m / s, decoherence can be prevented if the orbital splitting remains above about 1 meV, which is Figure 7 The left panel shows the case of linear shuttling.

[0193] During the movement of one or more qubits, one or more qubits are transferred from the second shuttle element 16' to the first shuttle element 16 (see Figure 7 The orbital splitting drops below 1 meV (right panel of the figure). The orbital splitting can be improved by dynamically adjusting the offset between the transfer gates 50b and 50b' to increase the confinement at the junction 28. Another option is to adjust the shuttle speed.

[0194] Figure 8 A simulation of a quasi-stable potential well located at junction 28 and a traveling potential well moving along the second shuttle element 16' is shown (as described above). The results show that one or more qubits trapped in the traveling potential well moving along the second shuttle element 16' can be adiabatically transferred to the quasi-stable potential well. Tunneling of the one or more qubits can be prevented.

[0195] The method of adjusting the voltages applied to the plurality of gate electrodes 50 according to the present disclosure implements a method of controlling the quantum processor 10 .

[0196] Furthermore, when multiple voltages V are calibrated, at least one interaction between some of the multiple voltages is considered. The at least one interaction can be expressed as a boundary condition or as a functional relationship. The functional relationship can take into account a target range. For example, in Figure 3A and Figure 3BIn the case of the shuttle channel 16 shown, the voltages applied to the shield gate 50a and the transfer gate 50b generate electric fields (in the case where the voltage V is a DC voltage) and / or electromagnetic fields (in the case where the voltage V is an AC voltage). The generated fields superimpose on each other, for example at the trajectory 80, and result in a composite electric field and / or composite electromagnetic field. The effects of this superposition, i.e., the interaction, need to be considered in terms of the material composition and target behavior of the shuttle channel 16. Other interactions between the voltages applied to the gate electrodes 50 will exist and may depend on the actual design of the quantum processor 10.

[0197] Based on determining the density of the fidelity reduction sites 70 in a portion of the quantum processor 10, such as along one of the shuttle channels 16, at the T-junction 18, or throughout the quantum processor 10, the elevated density may point to characteristics of the quantum processor 10 fabrication process or materials used in the fabrication process. In this case, the quantum processor 10 may be fabricated such that the shielding grids 50a-1 and 50a-2 disposed thereon (see FIG. Figure 3A and Figure 3B ) is segmented.

[0198] In one aspect, the shield 50a-1 and / or the shield 50a-2 of the shuttle channel 16 can be segmented into electrically disconnected shield segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively. Figure 4A and Figure 4B shown.

[0199] exist Figure 4A and Figure 4B In the illustrated aspect, dielectric or insulating layer 60 includes a first dielectric or insulating layer 60a and a second dielectric or insulating layer 60b. Shield gates 50a-1 and 50a-2 and transfer gate 50b are separated by first insulating or dielectric layer 60a and / or by second insulating or dielectric layer 60b.

[0200] A dielectric or insulating layer 66 separates shield gates 50a-1 and 50a-2 from semiconductor heterostructure 12. Figure 4A and Figure 4B In the illustrated aspect, the shield segments 50a-11, 50a-21 may be disposed on the insulating layer 66. Figure 4A and Figure 4B In the illustrated aspect, a portion of the first dielectric and insulating layer 60 a is disposed between the shield fence segments 50 a - 12 , 50 a - 22 and the dielectric or insulating layer 66 .

[0201] For example, if an average of two fidelity degradation sites 70 are found per 1 μm along at least one path 45 of the shuttle channel 16, the shield segments 50a-11, 50a-12, 50a-21, and 50a-22 of the shield 50a can be designed to be no longer than approximately 500 nm. In one aspect, the shield 50a can be subdivided into four shield segments each approximately 250 nm in length.

[0202] The electrically disconnected shield fence segments 50a-11, 50a-12, 50a-21, 50a-22 are disconnected at a segmentation point (or disconnection point) 55. The shield fence segments 50a-11, 50a-12, 50a-21, 50a-22 of the shield fence 50a may be disconnected by a first dielectric or insulating layer 60a at the segmentation point 55. At the segmentation point 55, the first dielectric or insulating layer 60a may be disposed between the shield fence segments 50a-11 and 50a-12 and / or between the segments 50a-21 and 50a-22, respectively.

[0203] The shield gate 50a can be separated from the transfer gate 50b by a dielectric or insulating layer 60. In one aspect, the first dielectric or insulating layer 60a can at least partially separate the shield gate 50a from the transfer gate 50b. In this aspect, the second dielectric or insulating layer 60b can at least partially separate the shield gate 50a from the transfer gate 50b. For example, in Figure 4B In the aspect shown, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a are separated from the transfer gate 50b by a second dielectric or insulating layer 60b. In this aspect, the first dielectric or insulating layer 60a and the second dielectric or insulating layer 60b can be partially arranged on each other. The first portion 60a1 of the first dielectric or insulating layer 60a can be arranged on the shielding gate segments 50a-11, 50a-21 of the shielding gate 50a. In addition, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a can be at least partially arranged on the second portion 60a2 of the first dielectric or insulating layer 60a. Therefore, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a can be arranged at a higher level relative to the segments 50a-11, 50a-21 of the shielding gate 50a along the stacking direction D1 (see Figure 4B ).

[0204] The first dielectric or insulating layer 60a may form a step 60as at the segmentation point 55. The step 60as may be a portion of the first dielectric or insulating layer 60a. The first portion 60a1 and the second portion 60a2 may be connected by the step 60as. The step 60as may extend in the stacking direction D1. Furthermore, the step 60as may extend in the longitudinal direction D2.

[0205] In another aspect, the shuttle channel 16 may include a protrusion 161. The protrusion may be located at the segmentation point 55. At the protrusion 161, the protruding transfer gate 50bp of the transfer gate 50b, the protruding portion 60bp of the second dielectric or insulating layer 60b, the protruding portion 50a-12p of the segment 50a-12 of the shield gate 50a, and / or the protruding portion 50a-22p of the segment 50a-22 of the shield gate 50a may protrude relative to at least one surface 14 in the stacking direction D1 (see FIG. Figure 4B ). The protruding transfer gate 50bp of the transfer gate 50b, the protruding portion 60bp of the second dielectric or insulating layer 60b, the protruding portion 50a-12p of the shield gate segment 50a-12 of the shield gate 50a, and / or the protruding portion 50a-22p of the shield gate segment 50a-22 of the shield gate 50a can protrude relative to the transfer gate 50b, the second dielectric or insulating layer 60b, the shield gate segment 50a-12, and / or the shield gate segment 50a-22, respectively. Therefore, the transfer gate 50bp, the portion 60bp, the portion 50a-12p, and the portion 50a-22p can be arranged at a higher level along the stacking direction D1 relative to the transfer gate 50b, the second dielectric or insulating layer 60b, the shield gate segment 50a-12, and the shield gate segment 50a-22, respectively. The protruding portion 60bp of the second dielectric or insulating layer 60b can have a portion extending in the stacking direction D1. The raised portion 60bp of the second dielectric or insulating layer may cover the raised portion 50-12p of the shield gate segment 50a-12 and / or the raised portion 50-22p of the shield gate segment 50a-22. The protrusion 161 may extend through the shield gate 50a-1 and / or the shield gate 50a-2 in the lateral (transverse) direction D3.

[0206] In another aspect, the protruding portions 50a-12p of the shield fence segments 50a-12 and / or the protruding portions 50a-22p of the shield fence segments 50a-22 of the shield fence 50a may be arranged to contact or intersect the line L extending along the stacking direction D1 along the longitudinal direction D2 (see FIG. Figure 4B ). Line L may also contact the shielding fence segment 50a-11 and / or the shielding fence segment 50a-21 of the shielding fence 50a along the longitudinal direction D2. On the other hand, the shielding fence segment 50a-12 and / or the shielding fence segment 50a-22 may intersect with the line L or overlap with the line L. In a further aspect, the shielding fence segment 50a-11 and / or the shielding fence segment 50a-21 may intersect with the line L or overlap with the line L along the longitudinal direction D2. In other words, through the protrusions 50a-12p and / or 50a-22p, the shielding fence segments 50a-11 and / or 50a-21 may overlap with the shielding fence segments 50a-12 and / or 50a-22, respectively, in the shuttling direction (or longitudinal direction) D2 (see Figure 4B) without contacting each other. The shield fence segment 50a-11 and / or the shield fence segment 50a-21 are arranged to overlap with the shield fence segment 50a-12 and / or 50a-22, respectively, in a contactless manner in the shuttling direction (or longitudinal direction) D2, so that a continuous electric potential can be provided by the voltage applied to the shield fence segments 50a-11, 50a-12 of the shield fence 50a-1 and / or the voltage applied to the shield fence segments 50a-21, 50a-22 of the shield fence 50a-2.

[0207] Alternatively, the shuttle channel 16 does not have the protrusion 161. In this case, the second dielectric or insulating layer 60b can have a flat surface. In this case, the transfer gates 50b will be arranged at the same level along the stacking direction D1; or the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 will be arranged at different levels along the stacking direction D1 (see above) without any transfer gate 50b protruding.

[0208] In another aspect, a gap in the shield grids 50a-1 and / or 50a-2 can be provided at segmentation points 55 along the shuttling direction (or longitudinal direction) D2, wherein the shield grids 50a-1 and / or 50b-2 are segmented. A gap can be provided along the shuttling direction (or longitudinal direction) D2 between the shield grid segments 50a-11, 50a-12 of the shield grid 50a-1 and / or between the shield grid segments 50a-21, 50a-22 of the shield grid 50a-2. A step 60as can be provided in the gap. In this aspect, no transfer gate 50b can be arranged above the gap in the stacking direction D1. Arranging the transfer gate 50b (which provides a potential well for moving (shuttling) one or more qubits) without any overlap between the transfer gate 50b and the gap prevents the transfer gate 50b from generating a potential that would interfere with the potential provided by the shield grids (or path-defining grids) 50a-1, 50a-2 that define the trajectory 80.

[0209] The shielding grid 50a is segmented into shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22 so that a voltage can be applied to the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively. The voltage applied to the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively, can be a DC voltage, in which case, given a corresponding duration of the DC voltage, the trajectory 80-2 will remain constant along the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-2, as shown in FIG. Figure 5 As shown. Figure 5 In the example shown, the shield grid 50a is segmented into three sections, to which individual DC voltages are applied, as can be seen from the position of the trace 80-2 relative to the line of y=0 nm.

[0210] Based on the determined density of the fidelity degradation sites 70, one or more segmentation points (or disconnection points) 55 may be arranged in the quantum processor 10. The segmentation points 55 may be arranged in the quantum processor 10 based on the distribution of the fidelity degradation sites 70 derived from the locations of the identified fidelity degradation sites 70. For example, assuming that the distances between the fidelity degradation sites 70 are Gaussian distributed with a mean distance d and a standard deviation σ d , then the segmentation points 55 can be arranged in the quantum processor 10, wherein the distance between any two segmentation points 55 is, for example, approximately d-2xσ d .

[0211] In one aspect of the present disclosure, the shielding grid 50a-1 and the shielding grid 50a-2 are segmented into shielding grid segments 50a-11, 50a-12 and 50a-21, 50a-22, respectively. Alternatively, one of the shielding grid 50a-1 and the shielding grid 50a-2 is segmented. In this case, the shielding grid 50a-1 is segmented into shielding grid segments 50a-11, 50a-12, or the shielding grid 50a-2 is segmented into shielding grid segments 50a-21, 50a-22.

[0212] Figure 9 An aspect of the present disclosure is shown wherein the shuttle channel 16 has two segmentation points 55. The screen 50a-1 is segmented into three segments 50a-11, 50a-12, 50a-13, and / or the screen 50a-2 is segmented into three segments 50a-21, 50a-22, 50a-23.

[0213] As described above, the shuttle channel 16 may include two protrusions 161. Similarly, as described above, the transfer gate 50b may include two protruding transfer gates 50bp. Similarly, as described above, the second dielectric or insulating layer 60b may include two protruding portions 60bp. Figure 9 As shown, the two protrusions 60bp can belong to a single dielectric or insulating layer 60b. Similarly, the shield 50a-1 can include two protrusions 50a-12p, as described above; and / or the shield 50a-12 can include two protrusions 50a-22p, as described above. The two protrusions 50a-12p can belong to a single shield portion 50a-12, as described above. Figure 9 The two protruding portions 50a-22p may belong to a single shielding grid portion 50a-22, as shown. Figure 9 As shown. The first dielectric or insulating layer 60a may include two steps 60as. Figure 9 As shown, the two steps 60as may belong to a single first dielectric or insulating layer 60a.

[0214] Figure 10Aand Figure 10B Shows the Figure 9 The aspects of the present disclosure shown are applied to Figure 6A The shielding grid 50a-2 of the first shuttle element 16 of the shielding grid 18 is divided into three sections, as shown in FIG. Figure 9 As shown. Figure 10A and Figure 10B As shown, the segments 50a-22 can be arranged at the junction 28. This arrangement enables adjustment of the voltage applied to the shield segments 50a-22 in the presence of a fidelity degradation site 70 at the junction 70. The adjustment voltage ΔV can be added to the voltage applied to the shield segments 50a-22 to bypass the fidelity degradation site 70 at the junction 28 by changing the trajectory 80, or to offset the effect of the fidelity degradation site 70 at the junction 28 by adding restrictions created by the shield segments 50a-22 (which may be combined with the last transfer gate 50b' of the second shuttle element 16'). The shield segments 50a-22 have contact points 50a-22c for applying the adjustment voltage ΔV.

[0215] Manipulation region 20 is configured to manipulate one or more qubits at at least one magnet 35. During operation of quantum processor 10, manipulation region 20 will be used to manipulate one or more qubits. The manipulation may be a single qubit action or a two qubit action.

[0216] FIG3E shows a time series (in four panels I, II, III, and IV) of a simulation of the evolution of a potential energy profile generated by applying a voltage to the gate electrode 50 to move the two qubits (represented by the solid circles) toward the interface 25 (represented by the dashed vertical line) and lower the tunneling barrier between the two qubits to enable the exchange interaction J. In this simulation, the detuning between the confinement potentials of the two qubits is zero. The x-axis represents the distance from the interface 25 along the shuttling direction D2. The y-axis represents the potential energy (or confinement energy). The horizontal bar above the potential energy represents the relative value of the voltage applied to the transfer gate 50b at the interface 25.

[0217] The use of two shuttling elements 16 that meet the interface 25 enables independent control of the distance between the two qubits at the interface and the tunnelling barrier between the two qubits. Effectively, the independent control of the tunnelling barrier height and width leads to reduced charge noise sensitivity and increased robustness to disorder. Compared to multi-quantum dot arrays, the control is greatly simplified because the high external barrier is automatically achieved during shuttling and only the inter-dot barrier needs to be precisely controlled. The actual gate operation is based on adiabatically turning on the exchange interaction J, which shifts the energy levels of the antiparallel spin states in such a way that they acquire an additional phase. In the accumulation After the phase, the subsequent single-qubit gate can realize the CPHASE gate.

[0218] In one aspect of the present disclosure, a single qubit action is to rotate one or more qubits by EDSR, which is based on moving one or more wave functions of one or more electrons (or holes) trapped (confined) in a potential well located in the first portion 69-1 of the quantum well 69 by applying an AC electric field, wherein the first magnetic field strength of the non-uniform first magnetic field of the first magnet 35-1 is non-zero. The AC electric field can be generated by a microwave signal, for example, applied to one or more transmission gates 50b. The resulting Rabi frequency is given by Ω=(gμ B E0 / 2k)(dB ⊥ / dx) where g is the g factor, μ B is the Bohr magneton, E0 is the amplitude of the AC electric field, dB ⊥ / dx is the gradient of the magnetic field of the at least one magnet 35 in the shuttling direction D2 (denoted by x) transverse to the external magnetic field B0 (i.e., the transverse component of the magnetic field of the at least one magnet 35 mentioned above), and k is the curvature of the confining potential well, which can be expressed in a first approximation as the parabolic potential (1 / 2)kx around the minimum of the confining potential well at x=0. 2 The strength of the confining potential and the orbital energy level splitting are determined by the curvature k. From the equation for the Rabi frequency Ω, it can be seen that a change Δk in the curvature k of the confining potential well results in a change ΔΩ in the Rabi frequency Ω, which is given by ΔΩ = -(Ω / k)Δk.

[0219] In one aspect of the present disclosure, one or more qubits are moved (shuttled) in an oscillatory manner at the location of the gradient maximum in the shuttling direction D2 of the magnetic field of at least one magnet 35 transverse to the external magnetic field B0. For a high-fidelity single-qubit gate, the amplitude of the oscillations that move one or more qubits is estimated to be approximately 20 nm, which is significantly larger than that of conventional EDSR, where the amplitude is on the order of several picometers. The higher amplitude allows the use of weaker magnetic field gradients, which in turn improves the overall robustness to charge noise.

[0220] The change Δk in the curvature k of the confining potential may be generated by applying one or more adjustment voltages to one or more of the plurality of electrodes 50 d - 1 , 50 d - 2 , . . . , 50 d - 12 of the top gate 50 d .

[0221] We consider a tuning voltage ΔV applied to a single electrode (hereinafter referred to as a “tuning gate”) among the multiple electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. The tuning gate can be located at the first portion 69-1 or the second portion 69-2 of the quantum well 69. The tuning gate can be located near the potential well that captures one or more quantum bits. For example, Figure 11DIn the case of , the tuning gate can be one of the electrodes 50d-2, 50d-3, 50d-6, 50d-7 or 50d-8 of the top gate 50d, but is not limited thereto. If the potential well that captures one or more qubits is located in the first portion 69-1 or the second portion 69-2, the Rabi frequency for rotating one or more qubits can be changed. The adjustment voltage ΔV applied to the tuning gate results in a potential that can be modeled as being generated by a dipole line oriented perpendicular to the shuttling direction D2 (i.e., oriented along the lateral or transverse direction D3) and pointing in the stacking direction D1: in, is a preset factor proportional to the tuning voltage ΔV applied to the tuning gate relative to the voltage applied to the plurality of gate electrodes 50 and the width of the tuning gate, x is the position along the shuttling direction D2, and d is the distance between the dipole line and the at least one path 45. In addition, the potential well that captures one or more qubits can be modeled as Where k = 2π / λ, λ is the spatial period, is a preset factor determined by the voltage applied to the transfer gate 50b, and x0 is the position along the shuttling direction D2 of the minimum of the potential well where one or more qubits are trapped.

[0222] In order to keep one or more qubits trapped in the potential well, there is an upper limit on the tuning voltage ΔV applied to the tuning gate. The upper limit of the tuning voltage ΔV can correspond to The adjustability or tunability of the Rabi frequency Ω is quantified by the ratio of the confinement strength (or curvature) of the regulating potential and the shuttling potential, i.e., the second derivative and The upper limit of the regulation voltage estimated above results in an adjustability (or adjustment range) or tunability (or tuning range) of the Rabi frequency Ω of 0.25d / λ. For typical values ​​of d = 50nm and λ = 300nm, the tuning range of the limiting intensity is much larger than that due to the shuttle potential alone. The resulting confinement is 1.5 times greater. For deconfinement (or deconfinement tuning) of the Rabi frequency Ω, it is recommended to stay below the upper limit to preserve the shape of the potential well with a harmonic minimum. Further considerations lead to the conclusion that, to ensure that the potential well can be approximated by a first-order quadratic potential described by the curvature k, the amplitude of the displacement of one or more qubits in an inhomogeneous magnetic field is limited to approximately 15 nm.

[0223] Figure 12 The upper panel shows the regulated potential and regulating the potential Shuttle potential Figure 2 shows an example of the sum of the potential wells (also referred to as "tuned potential wells"), where values ​​of d = 50 nm and λ = 300 nm are chosen. Figure 2 shows two examples of tuned potential wells, where tuning the voltage either weakens the confinement ("deconfined") or strengthens the confinement ("confined"). Figure 2 shows the corresponding untuned potential wells, where tuning the voltage does not change the confinement ("undisturbed"). The solid line indicates the tuned potential well. The dashed line indicates the tuned or tuned potential well. Also shown is a Gaussian charge density indicative of the spatial distribution of one or more qubits trapped in the potential well.As previously described, a tuned potential well produces a adjusted Rabi frequency Ω.

[0224] In another aspect of the present disclosure, there is a non-zero gradient dB in the shuttling direction D2 of the magnetic field of the at least one magnet 35 parallel to the external magnetic field B0 (the parallel component of the magnetic field of the at least one magnet 35). || In the case of dx / dx, the splitting of the spin-dependent energy levels by the external magnetic field B0 can be adjusted by changing the average position of the potential well minimum using another adjustment potential. The adjustment potential can be generated by applying an adjustment voltage ΔV to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. Applying the adjustment voltage can cause the average position of one or more qubits trapped in the potential well to change.

[0225] We consider a tuning voltage ΔV applied to two electrodes (“tuning gates”) of one or more electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. The two tuning gates can be located near the potential well in which one or more qubits are trapped. For example, in Figure 11D In the case of the top gate 50d, the two tuning gates can be selected from the electrodes 50d-2, 50d-3, 50d-6, 50d-7 or 50d-8 of the top gate 50d, but are not limited thereto. In one aspect, the two tuning gates can be located around the location of the potential well. For example, the two tuning gates can be located at a minimum distance of the potential well along the shuttle direction D2. The two tuning gates can include electrodes located at Figure 11D The first tuning gate on the left side of the potential well minimum and Figure 11D If the potential well in which one or more qubits are trapped is located in the first portion 69-1 or the second portion 69-2, the selection of the two tuning gates mentioned above will result in a change in the average position of the potential well, such as the minimum of the potential well in which one or more qubits are trapped. The change in the average position of the potential well results in a change in the magnetic field, thereby generating a spin-dependent energy level B0+ΔB0, where ΔB0=(dB || / dx)△x. Due to the change of magnetic field, the resonant frequency v=(gμ B / h)B0 changes △v=(gμB / h)△B0.

[0226] Figure 12 The lower panel shows the regulated potential and an example of a tuned potential well, where the values ​​of d = 50 nm and λ = 300 nm are chosen. An example of a tuned potential well is shown, where the tuning voltage changes the position of the potential well minimum ("shift"). A corresponding untuned potential well is shown, where the tuning voltage does not change the position of the potential well minimum ("undisturbed"). Solid lines indicate tuned or untuned potential wells. Dashed lines indicate tuned or tuned potential wells. Here it is the sum of the potentials generated by the dipole lines having opposite values ​​of the tuning voltage applied to them. Also shown is a Gaussian charge density indicating the spatial distribution of one or more qubits trapped in the potential well. As explained above, the tuned potential well produces a tuned resonant frequency.

[0227] The same considerations regarding the upper limit of the tuning voltage apply to the case of tuning the resonant frequency so as not to impair the shuttling of one or more qubits. Similar assumptions (see above) lead to a maximum shift of about 15 nm for the sum of the potential well minimum and the displacement of the one or more qubits trapped within the potential well.

[0228] In another aspect of the present disclosure, the potential barrier (or tunneling barrier) and detuning at the interface 25 can be adjusted. A tuning voltage ΔV can be applied to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. For example, one of the tuning voltages ΔV can be applied to electrode 50d-8 to increase or decrease tunneling coupling across the potential barrier (tunneling barrier). Other tuning voltages ΔV can be applied to electrodes 50d-7 and 50d-9 to change the detuning between the at least one first static potential well and the at least one second static potential well.

[0229] In another aspect of the present disclosure, the adjustment voltage may be applied to the transfer gate 50b instead of being applied to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. Figure 11B and Figure 11C In the illustrated aspect of the present disclosure, the transfer gate 50b has a subset of electrodes 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4 that are independently voltaged. Figure 11DIn the illustrated aspect, at least three electrodes belonging to the electrode subsets 50b1-2, 50b1-3, 50b1-4 are located at the first portion 69-1 of the quantum well 69. In addition, at least three electrodes belonging to the electrode subsets 50b1-3, 50b1-4, 50b2-1 are located at the second portion 69-2 of the quantum well 69. One or more electrode subsets can be provided with an AC voltage for shuttling the potential well and a regulating voltage (DC voltage) for adjusting the manipulation parameter in a manner similar to when the regulating voltage is applied to the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d.

[0230] The above examples of adjusting the Rabi frequency Ω, the resonance frequency v, or the exchange coupling J illustrate how the manipulation fidelity F can be improved by adjusting the parameters associated with manipulating one or more qubits (or “manipulation parameters”). M . The manipulation parameters include the Rabi frequency Ω, the resonant frequency v and the exchange coupling J. Adjustment of the manipulation parameters makes it possible to overcome the effects of fidelity reduction sites or disorder in the quantum well 69. The fidelity reduction sites 70 can be the result of, for example, manufacturing impurities, manufacturing defects, charge defects, crystal defects and / or locally reduced valley splitting. The fidelity reduction sites 70 can also be the result of a non-zero magnetic field strength of at least one magnet 35 parallel to the external magnetic field B0, which may affect the Rabi frequency Ω (see, for example, formula (2) in Kloeffel and Loss, Perspectives on Spin-Based Quantum Computing, 2012). When determining the manipulation fidelity F M When the requirements for reliable operation of the quantum processor 10 are not met, one or more manipulation parameters are adjusted so that the manipulation fidelity F can be improved. M .

[0231] Figure 13A Another aspect of a quantum processor 10 according to the present disclosure is shown. Figure 13A The quantum processor 10 shown has several unit cells 26, one of which is as shown in FIG. Figure 13B The quantum processor 10 has a plurality of manipulation regions 20 , a plurality of components 22 , 24 for initialization and readout, a plurality of T-junctions 18 , and a plurality of shuttle channels 16 .

[0232] In the illustrated aspect, several of the unit cells 26 have the same layout. However, in another aspect, the several unit cells 26 may not all have the same layout. For example, the number of T-junctions 18 of a selected unit cell 26 (indicated by a dashed rectangle) may be three (e.g., Figure 13A shown), or a different quantity.

[0233] like Figure 13B As shown, Figure 13AEach of the unit cells 26 of the illustrated quantum processor 10 has one of the manipulation regions 20, one of the components 22, 24 for initialization and readout, and two of the T-junctions 18. However, in one aspect, one or more of the unit cells 26 may not have the components 22, 24 for initialization and readout. In another aspect, the manipulation regions 20 of two adjacent unit cells 26 may be directly connected by a shuttle channel 16 (i.e., without a T-junction 18 disposed therebetween).

[0234] Figure 13B Shown Figure 13B Aspects of a unit cell 26 of the quantum processor 10 are shown. Figure 13B The unit cell 26 shown in FIG. 2 includes one of the manipulation regions 20 , three of the T-junctions 18 18 - 1 , 18 - 2 , 18 - 3 , one of the components 22 , 24 for initialization and readout, and several of the shuttle channels 16 16 - 11 , 16 - 12 , 16 - 2 , 16 - 31 , 16 - 32 .

[0235] As indicated by the arrows, the unit cell has an extension of approximately 10 μm. However, the present disclosure is not limited to this extension. The shuttle channel 16 according to the present disclosure enables shuttling and connecting one or more qubits of the quantum chip 10 over almost any distance. The extension shown can be 20 μm, 50 μm or 100 μm, any value between or outside these given values. The extension may depend on the requirements, such as the number of DC lines, the number of AC lines and / or the number of T-type bias ties that must be connected to the quantum chip 10. The extension may also depend on the cooling power of the refrigerator in which the quantum chip 10 is arranged.

[0236] Shuttle channels 16-12 and 16-11 connect unit cells 26 to other unit cells 26, e.g. Figure 13A As shown. As described above, at the T-junction 18-1, the shuttle channels 16-11 and 16-2 are connected to each other. The shuttle channel 16-31 connects the components 22 and 24 for initialization and readout to the T-junction 18-2. As described above, at the T-junction 18-2, the shuttle channels 16-2 and 16-31 are connected to each other. The shuttle channel 16-2 connects the T-junction 18-1 to the interface 25 of the operating area 20. As described above, at the interface 25, the shuttle channels 16-2 and 16-32 meet each other. The shuttle channel 16-32 connects the interface 25 to the T-junction 18-3. As described above, at the T-junction 18-3, the shuttle channels 16-32 and 16-12 are connected to each other.

[0237] Figure 13AThe quantum chip 10 shown can be used to implement a code for quantum error correction. An example of a code for quantum error correction is a surface code. Fowler et al. proposed an example of a surface code for quantum error correction (2012 6 Phys. Rev. A 86, 032324).

[0238] Surface codes allow for error detection rather than correction. Measuring more than one qubit at a time allows for non-destructive quantum error detection. Correction can then be implemented in conventional electronics. Faulty qubits are corrected by appropriate actions (e.g., single-qubit operations).

[0239] The surface code is manipulated as a so-called stabilizer code. The product of a suitable manipulation is called a stabilizer. Stabilizers help preserve the quantum state: by repeatedly measuring a quantum system using a complete set of commutative stabilizers, the system is brought into a synchronized and unique eigenstate of all stabilizers. Measuring a stabilizer allows the system to be undisturbed. Changes in the measurement results indicate one or more qubit errors. Through these measurements, the quantum state is projected onto different stabilizer eigenstates. Evaluating the stabilizer eigenstates allows qubit errors to be detected.

[0240] A physical qubit is either a data qubit, which stores the quantum state of a computation, or a measurement qubit. A measurement qubit is also called an ancillary qubit. By choosing an appropriate number of data and ancillary qubits, at least 13 physical qubits can be used to implement a single logical qubit. Logical qubits are used to implement algorithms that solve real-world problems. Depending on the error rate of the physical qubits, the number of physical qubits needed to implement a logical qubit can be even higher.

[0241] To implement stabilizers and thus detect errors, two types of auxiliary qubits are used: "measurement-Z" qubits and "measurement-X" qubits. Their measurement outcomes are often referred to as "Z syndrome" and "X syndrome." In one example, each data qubit is coupled to two measurement-Z and two measurement-X qubits, and each auxiliary qubit is coupled to four data qubits. Determining the measurement outcome of each syndrome, i.e., the eigenstate, enables each data qubit to detect possible errors. The incomplete set of surface code stabilizers allows for additional degrees of freedom that can be used to define logical operators, which is the first step in defining logical qubits.

[0242] The surface code selects some of the one or more qubits arranged in the quantum chip 10 as auxiliary qubits. The surface code selects other qubits in the one or more qubits arranged in the quantum chip 10 as data qubits. Thus, an auxiliary qubit subset and a data qubit subset of one or more qubits are formed. The surface code associates the position of any one manipulation region 20 of the quantum chip 10 with an auxiliary qubit or a data qubit. In one aspect, the position can be defined by an x-coordinate and a y-coordinate (see the x-direction and the y-direction). Figure 13A In other words, the surface code provides a mapping from the location of the plurality of manipulation regions 20s1 to one of the auxiliary qubit subsets or the data qubit subsets. In one aspect, the plurality of manipulation regions 20 can be alternately associated with the auxiliary qubit subsets or the data qubit subsets.

[0243] A distance between any two of the plurality of steering regions 20 can be defined. In one aspect, the distance can be measured in nanometers. In another aspect, the distance can be determined based on the number of T-junctions 18 disposed between two steering regions 20 along a connected path in the plurality of paths 45. Based on the distance between the two steering regions, a subset of adjacent steering regions in the plurality of steering regions 20 can be defined for any one steering region. For example, no more than a maximum number of T-junctions 18 can be disposed between a steering region 20 and an adjacent steering region in the plurality of steering regions 20.

[0244] The mapping of the surface code results in an arrangement of the auxiliary qubit subsets and the data qubit subsets such that any one auxiliary qubit has one or more adjacent data qubits. Likewise, any one data qubit has one or more adjacent auxiliary qubits.

[0245] In one example of a surface code implementation, one qubit can be associated with any manipulation region 20, such as Figure 13A In another aspect, one or more qubits can be associated with any one of the plurality of manipulation regions 20 of the quantum chip 10 .

[0246] An example of generating a mapping will now be described. In a first step 100, a first selected manipulation area 20s1 is selected in the manipulation area 20. A first adjacent manipulation area 20n1 is selected. A first path 45s connecting the first selected manipulation area 20s1 and the first adjacent manipulation area 20n1 is selected.

[0247] In step 200, as described above, the fidelity of a sequence of actions performed on a first qubit associated with a first selected manipulation zone 20s1 and a first neighboring qubit associated with a first neighboring manipulation zone 20n1 is then calculated. The sequence of actions includes (a) moving an auxiliary qubit from the first selected manipulation zone 20s1 to the neighboring manipulation zone 20n1 along at least one path 45s1; (b) manipulating the auxiliary qubit and the neighboring qubit in the neighboring manipulation zone 20n1 by performing at least one two-qubit action on the auxiliary qubit and the neighboring qubit; and (c) moving the auxiliary qubit from the neighboring manipulation zone 20n1 to the first selected manipulation zone 20s1 along at least one path 45s1. The fidelity of the calculated sequence of actions is the shuttling fidelity Fs of the path 45s1, the manipulation fidelity F at the first neighboring manipulation zone 20n1, and the fidelity F M The product of the shuttling fidelity Fs of the path 45s1. If the path 45s1 passes through one of the T-junctions 18, the shuttling fidelity may include the shuttling fidelity Fs. TO .exist Figure 13A In the aspect shown, the path 45 s 1 passes through two T-junctions 18 .

[0248] The first adjacent manipulation region 20n1 may be a nearest neighbor, ie, none of the plurality of manipulation regions 20 of the quantum chip 10 has a smaller distance from the first selected manipulation region 20s1.

[0249] In step 300, the calculated fidelity may be compared to a target value. A determination may be made as to whether the calculated fidelity is greater than the target value. If the fidelity is not greater than the target value, an alternative path 45s2 between the first selected manipulation area 20s1 and the first adjacent manipulation area 20n1 is selected.

[0250] In another aspect, several paths 45s1, 45s2 may be selected at the outset and the fidelity of some of these paths 45s1, 45s2 may be calculated. A path among the several paths 45s1, 45s2 having a greater fidelity may be selected as the path for moving the first selected qubit from the first selected manipulation region 20s1 to the first adjacent manipulation region 20n1.

[0251] Applying a voltage pulse may increase the electron temperature due to heat ingress. This increase in electron temperature can reduce fidelity due to unwanted thermal excitation. In one aspect, if both fidelities are above target fidelity, and if the time course of the voltage pulse that enables shuttling along path 45s1 is of short duration, thereby reducing heat ingress into the system, then selecting the shuttling path 45s1 associated with lower fidelity may be advantageous over selecting another shuttling path 45s2 with higher fidelity.

[0252] If none of the fidelities associated with individual ones of the several paths 45s1, 45s2 are greater than the target value for the several paths 45s1, 45s2, then steps 100 and 200 may be repeated for an alternative first selected manipulation region 20s1'. In this case, the first selected manipulation region 20s1 may not be used to operate the quantum chip 10.

[0253] Method steps 100 and 200 can be repeated for a further selected operating area 20s2 , which is selected such that at least one of the adjacent operating areas 20n of the first selected operating area 20s1 is a neighboring operating area 20n of the further selected operating area 20s2 .

[0254] The method may be repeated until all manipulation regions 20 have been associated with one of the auxiliary qubit subsets or the data qubit subsets or are not used to operate quantum chip 10. Alternatively, the method may be repeated until a predefined number of manipulation regions 20 have been associated with one of the auxiliary qubit subsets or the data qubit subsets.

[0255] In another aspect, at least a first qubit from the auxiliary qubit subset or the data qubit subset may need to be shuttled through manipulation region 20. The voltage pulses controlling first and second shuttle elements 16, 16' forming manipulation region 20 (which meet each other at interface 25) are coordinated (or synchronized) in such a way that first and second shuttle elements 16, 16' allow for continuous transfer across interface 25. In another aspect, the voltage pulse used to control first transfer gate assembly 50b1 of first shuttle element 16 is identical to the voltage pulse used to control second transfer gate assembly 50b2 of second shuttle element 16'. In yet another aspect, manipulation region 20 can be populated with at least another second qubit from the auxiliary qubit subset or the data qubit subset. Thus, before the first qubit is transferred to the shuttle element, the second qubit that has already populated the manipulation region can be transferred to the shuttle element opposite the shuttle element along which the first qubit is approaching manipulation region 20. Once the first qubit has been transferred to interface 25, the first and second qubits can change positions, for example by performing a SWAP operation. The first qubit can then be transmitted further, while the second qubit can remain in the manipulation region.

[0256] Dynamic decoupling can be used to suppress decoherence by modulation of a temporal sequence of fast, time-dependent control voltage pulses. In one aspect, a sequence of actions suitable for dynamic decoupling can be selected to be compatible with quantum gate operations. In another aspect, Carr-Purcell and / or Carr-Purcell-Meiboom-Gill schemes can be employed. These schemes can be based on Hahn spin echo techniques to achieve refocusing by applying periodic pulses. In another aspect, an idle qubit (which is a qubit in a subset of auxiliary qubits or a subset of data qubits for which all necessary actions have been performed, while an action is still being performed on at least one other qubit in the subset of auxiliary qubits or a subset of data qubits) can perform an action suitable for dynamic decoupling, such as a Carr-Purcell-Meiboom-Gill scheme.

[0257] Coordination of the time courses of signals applied to electrodes describes the necessary coordination of various different types of time courses, such as changes in time duration, voltage amplitude, and voltage ramp. While individual time courses can have similar lengths, there may always be a specific point in such a time course where a process must sometimes be synchronized with other processes. In this context, synchronization can mean the arrangement of multiple voltages applied to electrodes that produce sinusoidal voltage signals of identical amplitude and frequency, but may differ only in relative phase, which is constant during the synchronized time course, such as for the shuttle element. On the other hand, the time courses of signals used for completely different operations (such as shuttle vs. CPMG pulse sequences) may be asynchronous relative to each other.

[0258] The coordination of these time processes and the corresponding coordination of the voltage signals defines a specific portion of the time process during which these signals must be synchronized with other predefined signal processes. In yet another aspect, while at least a first qubit in the auxiliary qubit subset or the data qubit subset can be shuttled, at least a second qubit in the auxiliary qubit subset or the data qubit subset can be subjected to a CPMG sequence. Here, both time process signals can be asynchronous. However, at the specific time point when the first qubit reaches the manipulation region associated with the second qubit, the CPMG sequence executed on the qubit must have completed. Subsequently, a two-qubit manipulation is performed on the first and second qubits.

[0259] The operation of a quantum computing chip requires different control signals. These signals are divided into DC with a constant voltage and AC with an oscillating signal and are generated in a signal source. Each signal source can provide multiple channels. Depending on the gate design of the chip, these signals are applied to different electrodes. The connection between the signal source (or more specifically, between the channels of the signal source) and the electrodes is completed through cables between the signal source and the cryostat, wires inside the cryostat, and wiring on the chip. The decision on which signals must be generated to perform the operation of the chip occurs on a conventional computer outside the cryostat and is transmitted via communication lines. Depending on these decisions, commands are sent to the signal source, which provides the necessary voltage on the corresponding channel.

[0260] At the time of writing, the signal sources are mainly located outside the cryostat at room temperature. The total number of possible differently connected electrodes is therefore limited by the maximum number of signal lines inside the cryostat. Depending on the number of electrodes that must be connected to the signal sources / channels, there are two different situations that affect the operational flexibility: (1) The number of signal lines is smaller than the number of electrodes to be controlled: this means that exactly the same signal must be supplied to several electrodes. Due to the fact that the number of signal lines in the cryostat is limited, the corresponding electrodes are connected together on the chip itself (e.g. hard-wired). (2) The number of signal lines is greater than the number of electrodes to be controlled: each electrode can be freely supplied with an individual signal. This results in the chip having the greatest flexibility in operation. However, it is possible to supply several electrodes with the same signal from several signal sources. Conventional computers ensure this on the software side.

[0261] By using cryogenic electronics, the signal source is transmitted to the cryostat and operated at a lower / cryogenic temperature. Communication lines are not a limiting factor. Here, the number of cryogenic signal sources can be limited by the available cooling power of the cryostat and the placement of the cryogenic signal sources on a specific temperature stage. Therefore, the two aforementioned differences may limit operational flexibility.

[0262] The placement of the cryogenic signal source varies depending on the size and radiation power of the source. There are approaches that place these cryogenic signal sources directly on the qubit chip (which is limited by the amount of wiring) to be integrated on a single layer. Basically, the amount of wiring can be considered an unattainable limit. As an alternative to these on-chip approaches, the signal source is placed on a separate chip next to the actual qubit chip (limitation: the number of connections between the chips). To date, commercially available cryogenic signal sources are mostly placed on a higher temperature stage within a cryostat (due to higher power consumption) and are therefore in principle again limited by the number of signal lines. To circumvent this limitation, qubit chips are also operated at higher temperatures (1-4 K). However, this is not possible in principle.

Claims

1. A method of operating a quantum chip (10) using a microprocessor, The quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12), wherein the plurality of gate electrodes (50) are used to provide a plurality of shuttle channels (16) for moving a plurality of quantum bits along a plurality of paths (45); The plurality of gate electrodes (50) are further arranged to form a plurality of steering regions (20) and a plurality of T-junctions (18), Any one of the plurality of maneuvering areas (20) includes an interface (25) at which two of the plurality of shuttle channels (16) meet each other, and Any one of the plurality of T-junctions (18) includes a knot (28), and one of the plurality of shuttle channels (16) is connected to another of the plurality of shuttle channels (16) at the knot (28); The method comprises the following steps: calibrating a voltage parameter associated with a voltage to be applied to the plurality of gate electrodes (50), one of the parameters being associated with one gate electrode (50) of the plurality of gate electrodes (50); selecting a path (45s) along a selected shuttle channel (16-1, 16-2, ..., 16-n) of the plurality of shuttle channels (16) between the location (S) of the qubit and the selected manipulation region (20); determining, based on the voltage parameters, at least one shuttle voltage time course to be applied to an associated subset (50i) of the plurality of gate electrodes (50) for any selected one of the selected shuttle channels (16-1, 16-2, ..., 16-n) of the plurality of shuttle channels (16) for moving the qubit from a current position to the selected manipulation region (20); Moving the qubit from the current position (S) to the selected manipulation region (20) along the selected one of the plurality of shuttle channels (16) by applying the shuttle voltage time course to a subset (50-1, 50-2, ..., 50-n) of the plurality of gate electrodes (50) associated with the selected one of the plurality of shuttle channels (16); determining, for the selected manipulation region (20), a manipulation voltage time course to be applied to an associated subset (50-n, 50-s) of the plurality of gate electrodes (50) for manipulating the qubit based on the voltage parameter; as well as The qubit is manipulated at the selected manipulation region (20) by applying at least one manipulation voltage time course to the subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected manipulation region (20).

2. The method according to claim 1, wherein Manipulating the qubit includes performing a single qubit action on the qubit.

3. The method according to claim 1 or 2, wherein: Manipulating the qubit includes performing a two-qubit operation on the qubit and a second qubit located in the selected manipulation region (20).

4. The method according to any one of claims 1 to 3, further comprising: Move the qubit to the position (S).

5. The method according to any one of claims 1 to 4, wherein The path (45s) is selected so that at least two selected shuttle channels (16-1, 16-2, ..., 16-n) among the plurality of shuttle channels (16) meet at the interface (25) of at least one intermediate manipulation area (20) among the plurality of manipulation areas (20), or are connected at a junction (28i) of at least one intermediate T-junction (18) among the plurality of T-junctions (18).

6. The method according to any one of claims 1 to 5, further comprising: A third qubit located in the selected steering region (20) is moved from the selected steering region (20) by applying at least one additional time course of a shuttle voltage to the subset (50-n, 50-s) of the plurality of gate electrodes (50) associated with the selected steering region (20).

7. The method according to claim 6, wherein: Moving the third qubit located in the selected manipulation region (20) includes moving the third qubit through the interface (25) of the selected manipulation region (20).

8. The method according to any one of claims 1 to 7, further comprising: The application of the shuttle voltage time course, the application of the steering voltage time course, and the application of the at least one additional shuttle voltage time course are coordinated.

9. The method according to claim 8, further comprising: The time course of additional voltages applied to other gate electrodes of the plurality of gate electrodes (50) is coordinated.

10. The method according to any one of claims 1 to 9, further comprising: Recalibrate and / or adjust the voltage parameters.

11. The method according to any one of claims 1 to 10, further comprising: The coherence of one of the qubits is increased.

12. The method according to claim 11, wherein Improving the coherence includes applying dynamic decoupling, such as applying Car-Purcell-Meiboom-Gill pulses.

13. A computing system comprising a quantum processor (10), a voltage source and a microprocessor, The quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12), wherein a) the plurality of gate electrodes (50) are arranged to provide a plurality of manipulation regions (20) for manipulating a plurality of qubits, a plurality of T-junctions (18) for interconnecting the plurality of qubits, and a plurality of shuttle channels (16) providing a plurality of paths (45) along which the plurality of qubits are movable, and b) the plurality of manipulation zones (20) are interconnected via the plurality of paths (45) and the plurality of T-junctions (18), The voltage source is electrically connected to the plurality of gate electrodes (50) to apply a voltage to the plurality of gate electrodes (50) for manipulating the plurality of qubits, for interconnecting the plurality of qubits, and / or for moving the plurality of qubits; and The microprocessor is communicatively connected to the voltage source to control the voltage and includes a memory storing voltage parameters of the voltage to be applied, the parameters being associated with one or more subsets of the plurality of gate electrodes (50).

14. The computing system according to claim 13 or 14, wherein: Any one of the plurality of maneuvering areas (20) has an interface (25), and two of the plurality of shuttle channels (16) that meet each other meet at the interface (25).

15. The computing system of claim 14, wherein: The operating region in the operating region (20) further comprises at least one plug grid and / or at least one barrier grid at the interface (25).

16. The computing system according to any one of claims 13 to 15, wherein: Any one T-junction (18) of the plurality of T-junctions (18) has a knot (28) at which two connected shuttle channels of the plurality of shuttle channels (16) are connected to each other.

17. The computing system of claim 16, wherein: The T-junction (18) of the plurality of T-junctions (18) further comprises at least one plug gate and / or at least one barrier gate at the junction (28).

18. The computing system according to any one of claims 13 to 17, wherein: At least one steering region (16) of the plurality of steering regions (16) further comprises a top gate (50d).

19. The computing system of any one of claims 13 to 18, wherein: The voltage source is configured to provide at least one DC voltage and / or at least one AC voltage.

20. The computing system of any one of claims 13 to 19, wherein: The quantum processor (10) is arranged to be at a first cryogenic temperature.

21. A computing system according to any one of claims 13 to 20, wherein the microprocessor is arranged to be at ambient temperature or a second cryogenic temperature, the second cryogenic temperature being equal to or different from the first cryogenic temperature.

22. The computing system according to any one of claims 13 to 21, wherein the plurality of gate electrodes (50) are arranged in a periodic manner on the semiconductor heterostructure (12).

23. The computing system according to any one of claims 13 to 22, further comprising at least one further memory arranged at the quantum chip (10), and the at least one further memory being configured to store some of the voltage parameters associated with some of the gate electrodes (50) arranged adjacent to the at least one memory.

24. A system comprising a computing system according to any one of claims 13 to 23 and an external magnet for providing an external magnetic field B0.

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