Apparatus for manipulating qubits for semiconductor spin qubit quantum computer

Abstract

A manipulation region of a spin qubit quantum processor includes a plurality of gate electrodes (50b-1, 50b-2) disposed on a semiconductor heterostructure (12). The plurality of gate electrodes includes a first finger gate assembly (50b-1) arranged at a first path (451) in the semiconductor heterostructure and a second finger gate assembly (50b-2) arranged at a second path (452) in the semiconductor heterostructure. The first path and the second path meet at an interface (25). The first finger gate assembly and the second finger gate assembly are configured to be provided with at least one voltage V to move at least one qubit along the first path and / or the second path, and / or to manipulate a current spin state of at least one qubit located in the first path and / or the second path. The spin qubit device also includes a local magnet (35-1, 35-2) and an external magnetic field. One embodiment uses a top gate (50d in Figure 3D).

Description

Technical Field

[0001] The field of the present disclosure relates to the operation of quantum processors. Background Art

[0002] Quantum processor architectures must take scalability into account in order to achieve a sufficiently high number of logical qubits to implement quantum computer chips, which enable quantum computing in the NISQ (noisy intermediate-scale quantum) era or universal quantum computing. In the case of quantum computing based on spin qubits, the qubits are arranged in a two-dimensional plane. A disadvantage of this two-dimensional architecture is the so-called "fan-out problem," which refers to the space required for routing the control circuits of the quantum processor between the quantum processor and the traditional control circuits. These space requirements scale faster with the number of qubits than the size of the spin qubit-based quantum processor architectures proposed so far can scale.

[0003] Recently, a spin qubit architecture based on direct electron shuttling in Si / SiGe semiconductor heterostructures has been proposed. This architecture includes shuttle paths along which qubits can theoretically be transported over arbitrary distances, for example, up to approximately 50 μm. These shuttle paths allow components of a quantum processor (such as the loading, readout, and manipulation regions) to be spaced apart from one another, resulting in lower crosstalk. The provision of shuttle paths also enables operating modes that require relatively low operating frequencies and reduce local magnetic field gradients.

[0004] In these shuttle-based architectures, high-fidelity shuttling is crucial for reliable computation. This high fidelity can be compromised by, for example, charge defects or valley splitting on the shuttle path. Valley splitting can lead to leakage of the computational basis (e.g., two spin states) used for computation.

[0005] There is a need to identify points in a quantum processor (e.g., a shuttle path or other component of the quantum processor) at which the reliability of qubit processing decreases, which ultimately affects the performance of the quantum processor. Summary of the Invention

[0006] A manipulation region of a quantum processor includes a plurality of gate electrodes disposed on a semiconductor heterostructure, wherein the plurality of gate electrodes includes a first finger gate assembly disposed at a first path in the semiconductor heterostructure and a second finger gate assembly disposed at a second path in the semiconductor heterostructure. The first path and the second path meet at an interface. The first finger gate assembly and the second finger gate assembly are configured to be supplied with at least one voltage V to move at least one qubit along the first path and / or the second path and / or manipulate the current spin state of the at least one qubit located at the first path and / or the second path.

[0007] The manipulation zone further includes at least one magnet.

[0008] The at least one magnet may be arranged at the interface.

[0009] The at least one magnet may be arranged at a distance from the interface.

[0010] The semiconductor heterostructure may be made of a semiconductor material that provides spin-orbit coupling.

[0011] At least one of the first finger-gate assembly and the second finger-gate assembly may include a plurality of electrode subsets.

[0012] Subsets of the plurality of electrode subsets may be electrically disconnected from each other.

[0013] Subsets of the plurality of electrode subsets may have dielectric or insulating layers disposed between each other.

[0014] The steering region may further include a top gate disposed over the first finger-gate assembly and / or the second finger-gate assembly.

[0015] The top grid is structured in the longitudinal direction.

[0016] A dielectric or insulating layer may be disposed between the semiconductor heterostructure and the plurality of gate electrodes.

[0017] The gate electrodes of the plurality of gate electrodes may have a dielectric or insulating layer disposed therebetween.

[0018] The plurality of gate electrodes may be arranged on at least one surface of the semiconductor heterostructure.

[0019] A system includes a magnet according to the present disclosure for manipulating and providing an external magnetic field.

[0020] A method for manipulating at least one quantum bit located in a first path and / or a second path in a semiconductor heterostructure is disclosed. The first path and the second path meet at an interface. The semiconductor heterostructure includes a plurality of gate electrodes disposed thereon. The method comprises the step of providing an external magnetic field B0. The method further comprises the step of changing a current spin state of the at least one quantum bit by moving the at least one quantum bit along the first path and / or the second path using an AC electric field applied to a gate electrode among the plurality of gate electrodes, or by irradiating the at least one quantum bit with electromagnetic radiation.

[0021] The method may further include adjusting a Rabi frequency or a resonant frequency associated with changing the current spin state of the at least one qubit.

[0022] The method may further include changing the tunneling barrier at the interface.

[0023] The method may further comprise varying a detuning between two qubits confined on either side of the interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic top view of a quantum processor is shown.

[0025] Figure 2 Show Figure 2 Schematic top view of the unit cell of the quantum processor shown in FIG.

[0026] Figure 3A A top view showing aspects of the operating area.

[0027] Figure 3B A longitudinal section showing another aspect of the operating area.

[0028] Figure 3C A longitudinal section showing another aspect of the operating area.

[0029] Figure 3D A longitudinal section showing another aspect of the operating area.

[0030] Figure 3E Line cut plots showing a time series of simulations of the evolution of the potential energy landscape at the interface of the maneuvering zone.

[0031] Figure 4 The effect of the shuttle voltage on applying a tuning voltage to change the confinement of the qubit is shown in the upper panel. Figure 4 The effect of the shuttle voltage on the tuning voltage applied to shift the confines of the qubit is shown in the lower panel. DETAILED DESCRIPTION

[0032] The present disclosure relates to a method of operating a quantum processor and a method of manufacturing a quantum processor.

[0033] Quantum processors can operate based on spin qubits. Spin qubits are two-level quantum systems with a spin degree of freedom. An example of a spin qubit is a two-level quantum system of electron spins confined in a quantum dot, and another example is a hole spin qubit. Furthermore, a group of electrons (e.g., two or three electrons) can be used to realize a spin qubit, such as the S-T0 singlet-triplet system of two electrons in a double quantum dot.

[0034] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in the semiconductor heterostructure 12. Using an electron-based spin qubit involves placing the electron spin in a known state. To this end, the electron state is initialized. In one aspect, the selected qubit is associated with the same electron throughout the execution of the quantum algorithm. On the other hand, a qubit implemented by a first electron can be initialized and subsequently operated on, and the qubit can be implemented by a second electron. On the other hand, without affecting the execution of the quantum algorithm, there is a situation where it is impossible to distinguish whether the qubit is implemented by the first electron or the second electron. Similarly, the method of the present disclosure can be applied to any type of hole spin qubit.

[0035] The use of semiconductor materials to form structures for implementing quantum processors (e.g., semiconductor heterostructures) is advantageous for manufacturing because the materials are easy to process and are inexpensive (e.g., in the case of silicon). The use of silicon in computing hardware is an established technology. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be confined within a structure formed of semiconductor materials in a quantum well 69 (see below and Figure 3B-3D ). 2DEG or 2DHG can be further confined based on an electric potential. The electric potential can be a static electric potential or a non-static electric potential. The electric potential can form at least one quantum dot, wherein at least one electron or hole in the 2DEG or 2DHG is captureable or confined. The spin of at least one trapped (confined) electron or hole can be used to realize a spin qubit. Moving the electric potential causes moving at least one quantum dot. The movement of at least one quantum dot enables the movement of at least one trapped (confined) electron / hole and the qubit associated with at least one trapped (confined) electron / hole. Changing the strength of the electric potential changes the degree of confinement of at least one trapped (confined) electron or hole.

[0036] The quantum processor may include a plurality of unit cells. A unit cell in the plurality of unit cells includes a component that performs at least one action or operation on one or more qubits located in the unit cell. The at least one action on the one or more qubits includes: loading one or more qubits into the unit cell; unloading one or more qubits from the unit cell; moving (shuttling) one or more qubits into or out of the unit cell (i.e., to another unit cell of the quantum processor); manipulating the quantum state of one or more qubits; and reading out the quantum state of one or more qubits. Manipulating one or more qubits includes: manipulating a single qubit or manipulating two qubits. Manipulating a single qubit includes: rotating the spin of a single qubit, for example, to drive a transition between multiple spin states. The multiple spin states may include an up spin state and a down spin state. Manipulating two qubits includes implementing a CPHASE gate, a CNOT gate, and / or a SWAP gate.

[0037] In one aspect, several actions performed by components of a unit cell on one or more qubits can be performed one after another as a sequence of actions. For example, two actions can be performed one after another. In another aspect, several actions performed by components of a unit cell on one or more qubits can be performed in parallel. For example, two actions can be performed in parallel.

[0038] In one aspect, several actions on one or more qubits may be performed within a single unit cell of a plurality of unit cells or across several unit cells of the plurality of unit cells.

[0039] In one aspect, several actions may be performed as part of determining gate fidelity (see below for more details). For example, determining gate fidelity may include performing a sequence of actions on one or more qubits.

[0040] In another aspect, several actions may be performed as part of executing an algorithm. For example, executing an algorithm may include performing a sequence of actions on one or more qubits.

[0041] Components are arranged within the unit cells. Some of the components are connected to one another. The components and their connections together constitute the layout or structure of the unit cell. Unit cells within a plurality of unit cells may have substantially the same structure, wherein the same components are arranged and connected to one another in substantially the same manner. Other units within the plurality of unit cells may have different structures, wherein the components and / or connections of the components are different.

[0042] Aspects of the quantum processor are disclosed in International Patent Application No. WO 2021 / 052541 A1, the entire contents of which are incorporated herein by reference. Figure 1 and Figure 2 As shown, the quantum processor 10 includes a semiconductor heterostructure 12. The semiconductor heterostructure 12 includes several layers of different material compositions. The semiconductor heterostructure 12 can be a Si / SiGe or GaAs / AlGaAs heterostructure, however, it is possible to use other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS or Ge / SiGe. The semiconductor heterostructure can be undoped and / or strained. The semiconductor heterostructure 12 can serve as a substrate for the quantum processor 10. The semiconductor heterostructure 12 can include a 2DEG. The 2DEG or 2DHG can be arranged or located in a quantum well 69 (see Figure 3B-3D ). One or more qubits may be arranged in quantum well 69. One or more qubits may be arranged in at least one quantum dot formed in quantum well 69. One or more qubits may be generated from a 2DEG.

[0043] In one aspect, semiconductor heterostructure 12 can further include a silicon capping layer 64 with a dielectric or insulating layer 66 (not shown) disposed thereon. Gate electrodes 50a, 50b, 50d can be disposed on top of and / or over dielectric or insulating layer 66.

[0044] On the other hand, the semiconductor heterostructure 12 may further include a strained silicon layer 63 (see Figure 3C In yet another aspect, the semiconductor heterostructure 12 may further include a silicon dioxide layer 62 (see Figure 3C ).

[0045] exist Figure 1 and Figure 2 In the aspect of the quantum processor 10 shown, the components 16, 18, 20, 22, 24 are disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 1 As shown, the illustrated aspect of quantum processor 10 includes one or more of each of components 16, 18, 20, 22, 24. In another aspect, quantum processor 10 may include one or more of only some of components 16, 18, 20, 22, 24.

[0046] Figure 1 and Figure 2 The illustrated quantum processor 10 is a substantially two-dimensional device defined by at least one surface 14. The third dimension of the quantum processor 10 is defined by the thickness of the semiconductor structure 12 and the thicknesses of the components 16, 18, 20, 22, 24.

[0047] The plurality of unit cells of the quantum processor 10 includes a plurality of unit cells 26 (e.g. Figure 2 shown). Figure 2 In the illustrated aspect, unit cell 26 includes components 16, 18, 20, 22, 24. In another aspect of the present disclosure, unit cell 26 includes only some of components 16, 18, 20, 22, 24. In yet another aspect, unit cell 26 may include more than one of at least one of components 16, 18, 20, 22, 24.

[0048] The components 16, 18, 20, 22, 24 include a plurality of gate electrodes 50 arranged on at least one surface 14 of the semiconductor heterostructure 12 (see Figure 3A and Figure 3B ). The plurality of gate electrodes 50 may be arranged to define at least one path 45 within a quantum well 69 within an associated one of the components 16, 18, 20, 22, 24 (see Figure 3A ), one or more qubits can move (shuttle) along these paths.

[0049] exist Figure 1 and Figure 2, at least one path 45 is shown as being oriented substantially in two directions on the surface 14, the two directions being substantially perpendicular to each other, forming a grid-like structure of a plurality of paths 45. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0050] The plurality of gate electrodes 50 may also be arranged to move (shuttle) one or more qubits along the at least one path 45. The movement (shuttling) may occur in either of two directions (forward and backward) along the at least one path 45. The plurality of gate electrodes 50 may also be arranged to perform at least one action performed by the components 16, 18, 20, 22, 24 on the one or more qubits.

[0051] Multiple gate electrodes 50 can be provided with a voltage. Multiple gate electrodes 50 can be made of metal. Multiple gate electrodes 50 can be superconducting. The voltage can be used for one or more purposes, such as defining at least one path 45, moving (shuttling) one or more qubits, and / or performing at least one action on one or more qubits. The voltage can include a DC (direct current) voltage and an AC (alternating current) voltage. The voltage can include one or more static voltages and one or more non-static voltages. The voltage can be applied via a DC line, an AC line, and / or a biasing device.

[0052] One or more of the components 16, 18, 20, 22, 24 may also include at least one magnet 35, such as a micromagnet (see Figure 3B-3D ). At least one micromagnet 35 can be placed on top of the components 16, 18, 20, 22, 24. The at least one micromagnet 35 provides a magnetic field. The magnetic field can have a zero gradient or a non-zero gradient. The at least one magnet 35 can be 150 nm away from the quantum well 69. The dimensions of the at least one magnet 35 can be 400 nm x 200 nm x 20 nm. The at least one magnet 35 can be arranged on a dielectric or insulating layer 68 (see Figure 3B-3D ). A dielectric or insulating layer 68 may be disposed on the transfer gate 50b (see Figure 3B ) or top gate 50d (see Figure 3C and Figure 3D and below).

[0053] The external magnetic field B0 splits multiple spin states (e.g., up spin state and down spin state) used as the basis for computation of one or more qubits into spin-dependent energy levels (Zeeman splitting). The external magnetic field B0 may be provided by an external magnet (e.g., an electromagnet (not shown)) located near the quantum processor 10. The quantum processor 10 may be at least partially placed in the external magnetic field B0 provided by the external magnet.

[0054] One or more components 16, 18, 20, 22, 24 may further include a device for providing electromagnetic radiation (e.g., microwaves) for manipulating the quantum state of one or more qubits (e.g., switching the spin of one or more qubits between multiple spin states). Electromagnetic radiation can be provided by one or more gate electrodes 50b. By electromagnetic radiation based on electron spin resonance (ESR), the spin of a qubit can be switched between, for example, an up spin state and a down spin state, or vice versa. The frequency of the electromagnetic radiation can be equal to the energy difference of the separated energy levels. ESR provides another way to manipulate the quantum state of one or more qubits. Microwaves can have a frequency in the range of hundreds of MHz to hundreds of GHz. In one aspect, the frequency is in the range of 9-10 GHz, but is not limited thereto.

[0055] A non-uniform magnetic field is provided, i.e., with a non-zero gradient, so that the quantum state of one or more qubits can be manipulated, such as the spin of a rotation qubit. The rotation enables the transition between multiple spin states to be driven by the displacement of one or more qubits in a non-uniform magnetic field based on, for example, an AC electric field. The AC electric field can be provided by one or more gate electrodes 50b. This effect is called electric dipole spin resonance (EDSR). The displacement can cause the qubit to oscillate between multiple spin states (for example, the spin state forming the basis of calculation, such as an up spin state and a down spin state). For example, the qubit can oscillate so that the up spin state can be switched to the down spin state, and vice versa.

[0056] Alternatively, EDSR may be implemented in a semiconductor heterostructure 12 in which spin-orbit coupling exists. The semiconductor heterostructure 12 may be made of a semiconductor material that provides spin-orbit coupling.

[0057] The plurality of gate electrodes 50 may be provided as one or more gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may include one or more laterally positioned gate electrodes 50a (also referred to as "shielding gates") (see Figure 3A), which is arranged to define and / or modify the lateral position of a trajectory in the quantum well 69 and / or at least one path 45 to move (shuttle) one or more qubits within or outside the unit cell. The trajectory can be the trajectory of one or more potential wells (described further below) in which one or more qubits can be arranged. The one or more potential wells can therefore be one or more traveling potential wells. The trajectory of the one or more potential wells can therefore correspond to the trajectory of one or more qubits arranged on the at least one path 45. Therefore, the lateral position of the trajectory can correspond to the lateral position of the one or more potential wells and / or one or more qubits. Arranging one or more qubits on at least one path 45 should be understood to mean that the one or more qubits are arranged within the quantum well 69.

[0058] The plurality of gate electrodes 50 may further include one or more shuttle gate electrodes 50b (also referred to as "transfer gates" or "finger gates" or "keyboard gates") (see Figure 3A ) which is arranged to move (shuttle) one or more qubits along at least one path 45 to move (shuttle) one or more qubits within a unit cell or outside a unit cell.

[0059] The plurality of gate electrodes 50 may further include at least one vertically positioned gate electrode 50c (also referred to as a "back gate") arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 3C ) to move (shuttle) one or more qubits within or outside the unit cell. The vertical position of trajectory 80 can correspond to the vertical position of one or more potential wells and / or one or more qubits.

[0060] The plurality of gate electrodes 50 may further include qubit processing gate electrodes, which are configured to perform at least one action on one or more qubits. The qubit processing electrodes include plunger gates and barrier gates. The plunger gates can be used to control quantum dot occupancy, control detuning in a double quantum dot, and / or perform a swap between two qubits. The barrier gates can be used to form a double potential well and / or control the tunneling barrier in the double quantum dot.

[0061] A plurality of gate electrodes 50 may be arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers separated by an insulating or dielectric layer 60 and an insulating or dielectric layer 66 (see Figure 3B-3D In one aspect, the layers can be arranged in a direction substantially perpendicular to the direction of at least one path 45.

[0062] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67 may be planarized. One method of manufacturing the shuttle element 16 may include the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before the transfer gate 50b is positioned on the insulating or dielectric layer 60. Planarization facilitates the use of processes such as electron beam epitaxy, deep ultraviolet (DUV), and / or spacer lithography. Planarization reduces the thickness of one or more of the dielectric or insulating layers 60, 66, and 67. For example, before fabricating the transfer gate 50b, the insulating or dielectric layers 66 and / or 60 may be planarized to reduce the thickness of the insulating or dielectric layers 66 and / or 60, respectively. After planarization, the insulating or dielectric layers 66 and / or 60 are tightly positioned on the semiconductor heterostructure 12. Planarizing insulating or dielectric layer 66 and / or 60 results in a reduced thickness of insulating or dielectric layer 66 and / or 60 between at least one via 45 and transfer gate 50b. In one aspect, the thickness of insulating or dielectric layer 60 is required to cover the top and side surfaces of shield gate 50a.

[0063] Component 16 is used to move (shuttle) one or more quantum dots in semiconductor heterostructure 12 to move (shuttle) one or more qubits within or outside the unit cell. Component 16 is also referred to as a "shuttle channel." Various aspects of shuttle channel 16 are disclosed in International Patent Application No. WO 2021 / 052531A1, the entire disclosure of which is incorporated herein by reference.

[0064] Component 18 provides a junction at which one or more quantum dots can be diverted into at least one branch (at least one second path in at least one path 45) branching out from at least one path 45 for moving (shuttling) one or more quantum bits within or outside the unit cell. Component 18 is also referred to as a "T-junction". The at least one path 45 and at least one branch of the T-junction 18 can be arranged perpendicularly or non-perpendicularly to each other. In one aspect, the at least one path 45 and at least one branch of the T-junction 18 can substantially form a T-shape. Various aspects of the T-junction 16 are disclosed in International Patent Application No. WO 2021 / 052539 A1, the entire disclosure of which is incorporated herein by reference.

[0065] Component 20 is provided for manipulating qubits in quantum dots. Component 20 is also referred to as a "manipulation zone." Manipulation zone 20 enables manipulation of one or more current spin states of one or more qubits. Any qubit has a current spin state. In one aspect, multiple spin states may include the current spin state. In another aspect, the current spin state may be a linear combination of multiple spin states. During manipulation, one or more current spin states may change. Aspects of manipulation zone 20 are disclosed in WO 2021 / 052537 A1, the entire disclosure of which is incorporated herein by reference.

[0066] Component 22 is used to initialize one or more spin states of one or more quantum bits. When one or more spin states have been initialized, any one of the one or more current spin states is equal to one spin state in the plurality of spin states. After initialization, one or more current spin states may remain unchanged during the relaxation time. The relaxation time describes the transition between the upper spin state and the lower spin state due to interaction with the environment (such as the lattice of the semiconductor heterostructure 12). Component 22 is also referred to as an "initialization zone". Various aspects of the initialization zone 22 are disclosed in WO 2021 / 052538 A1, the entire disclosure of which is incorporated herein by reference.

[0067] Component 24 is used to read out one or more spin states of one or more qubits. When one or more spin states have been read out, any one of the one or more current spin states before the readout is known. Component 24 is also referred to as the "readout region." Various aspects of readout region 24 are disclosed in WO 2021 / 052536 A1, the entire disclosure of which is incorporated herein by reference.

[0068] In one aspect of the present disclosure, the initialization region 22 and the readout region 24 are the same component.

[0069] The quantum processor 10 is operated to execute an algorithm, such as a quantum algorithm. As described above, executing the algorithm includes performing a sequence of actions on one or more qubits. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cell 26.

[0070] Operating quantum processor 10 involves controlling at least one action performed by components 16, 18, 20, 22, and 24. In one aspect of the present disclosure, the at least one action is controlled by applying voltages to a plurality of gate electrodes 50. The voltages can be set and / or adjusted to improve the fidelity F of the at least one action and / or sequence of actions. Fidelity F is a measure of how reliably the at least one action or sequence of actions produces the expected result based on the design of quantum processor 10 and the voltages applied to the plurality of gate electrodes 50. To determine fidelity F, at least one action or sequence of actions is repeated; the proportion of repetitions in which the actual result equals the expected result is then determined. The actual result includes one or more current spin states that have been read out at readout region 24 after the at least one action or sequence of actions. The expected result includes one or more current spin states that are expected to be read out at readout region 24 after the at least one action or sequence of actions based on the known fidelity of components 16, 18, 20, 22, and 24 and / or the relaxation time of one or more qubits.

[0071] For example, the at least one action may include moving (shuttling) one or more qubits along at least one path 45 of the shuttle channel 16 (e.g., moving (shuttling) to the manipulation region 20), and manipulating the quantum state of the one or more qubits in the manipulation region 20. In this case, the fidelity F of performing the at least one action is the shuttling fidelity F S and manipulation fidelity F M The combination (i.e., product), that is, F = F S ×F M Then, the manipulation fidelity F associated with the manipulation area 20 M It can be calculated by dividing the fidelity F by the shuttle fidelity. M is understood as the probability that one or more current spin states of one or more qubits change as expected during the manipulation. For example, the shuttling fidelity F can be determined by repeatedly performing the following sequence of actions S : Initialize the qubit, move (shuttle) the qubit, and read out the qubit; then determine whether the initialized spin state of one or more qubits is equal to one or more current spin states after shuttling and before reading out; and finally calculate the proportion of repetitions in which one or more spin states remain unchanged. For example, the manipulation fidelity F can be determined by repeatedly performing the following sequence of actions M : initialize one or more qubits, move (shuttle) one or more qubits, manipulate one or more qubits, and read out one or more qubits; then determine whether one or more initialized current spin states of the one or more qubits change as expected; calculate the proportion of repetitions in which one or more current spin states change as expected, and divide the result by the shuttling fidelity FS .

[0072] Fidelity F may also be gate fidelity. Gate fidelity F is a measure of how well the results of a gate operation (i.e., a sequence of actions performed by components 16, 18, 20, 22, 24 on one or more qubits associated with the gate that quantum processor 10 is designed to implement) match expected results (e.g., theoretical results) based on the design of quantum processor 10 and components 16, 18, 20, 22, 24. Gate fidelity F can be determined through randomized benchmark testing.

[0073] As an example, a method of improving the manipulation fidelity F of one or more qubits (eg, single qubit or double qubit) in the manipulation region 20 will be described. M . Figure 3A 1. Aspects of the steering region 20 are shown. The steering region 20 includes a shield gate 50a and a transfer gate 50b arranged on at least one surface 14 of the semiconductor heterostructure 12. Figure 3A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 3B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0074] The shielding grid 50a is arranged to extend as shielding grids 50a-1 and 50a-2 on either side of the first path 451 and the second path 452 (see also Figure 3A ). In one aspect, as Figure 3A-3C As shown, shield gates 50a-1 and 50a-2 can extend continuously along at least one path 45. In another aspect, shield gates 50a-1 and 50a-2 can be interrupted. Shield gates 50a-1 and 50a-2 can be separated by approximately 200 nm. Shield gate 50a can be made of metal and can be fabricated by embedding the metal into semiconductor heterostructure 12 or by localized implantation of the semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0075] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extends into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0076] The transfer gate 50b may extend laterally across the first path 451 and / or the second path 452 (eg, Figure 3A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b is arranged along at least one path 45.

[0077] exist Figure 3A In the illustrated aspect, the transfer gate 50b has a first transfer gate assembly 50b1 and a second transfer gate assembly 50b2. Figures 3A-3D , the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are indicated by the curly brackets at the top of the drawing. In addition, for clarity, Figures 3A-3D 1 and 2. Three electrodes belonging to the first transfer gate assembly 50b1 and three electrodes belonging to the second transfer gate assembly 50b2 are shown in FIG. The first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 are arranged to extend laterally across at least a portion of the first path 451 and / or the second path 452, respectively. The first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 are arranged at the interface 25 such that the first path 451 and the second path 452 meet at the interface 25 (see FIG. Figure 3A and Figure 3B ).

[0078] First path 451 and second path 452 meet at interface 25, allowing a first qubit trapped in the first quantum dot and shuttled to interface 25 along first path 451 and a second qubit trapped in the second quantum dot and shuttled along second path 452 to undergo at least one two-qubit action (or operation) at interface 25. The one or more potential wells may include one or more first potential wells. The first qubit may be shuttled (moved) along first path 451 by one or more first traveling potential wells. The one or more first traveling potential wells may be generated by applying a voltage to first transfer gate assembly 50b1. Similarly, the one or more potential wells may include one or more second potential wells. The second qubit may be shuttled (moved) along second path 452 by one or more second traveling potential wells. The one or more second traveling potential wells may be generated by applying a voltage to second transfer gate assembly 50b2.

[0079] At least one two-qubit action (or operation) at the interface 25 is achieved by forming a potential well in one or more potential wells ("one or more static potential wells") that are static at the interface. The one or more static potential wells may include at least one first static potential well and at least one second static potential well.

[0080] At least one first static potential well can be disposed at interface 25. For example, the at least one first static potential well can be adjacent to the interface. The at least one first static potential well can be generated by first transfer gate assembly 50b1. Similarly, at least one second static potential well can be disposed at interface 25. For example, the at least one second static potential well can be adjacent to the interface. The at least one second static potential well can be generated by second transfer gate assembly 50b2.

[0081] A first qubit can be trapped in at least one first static potential well. Similarly, a second qubit can be trapped in at least one second static potential well. When the at least one first static potential well and the at least one second static potential well are arranged at the interface 25, the first qubit trapped in the at least one first static potential well and the second qubit trapped in the at least one second potential well can undergo at least one two-qubit action (or two-qubit operation).

[0082] For example, a potential barrier may be formed between the at least one first static potential well and the at least one second static potential well by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2 at the interface 25. For example, the potential barrier may be formed by the electrode subset 50b1-4 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-1 (described below) of the second transfer gate assembly 50b2.

[0083] Lowering / raising the potential barrier can increase / decrease tunneling coupling through the barrier (also referred to as the "tunneling barrier"). In one aspect, the height of the potential barrier can be modulated by pulses, such as non-adiabatic pulses. The confinement in the at least one first static potential well and the at least one second static potential well can be different from each other, or not, which is referred to as detuning. The detuning can be zero or non-zero. The detuning can be generated by the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2. For example, the detuning can be generated by the electrode subset 50b1-3 (described below) of the first transfer gate assembly 50b1 and the electrode subset 50b2-2 (described below) of the second transfer gate assembly 50b2.

[0084] The tunneling coupling and the detuning determine the exchange coupling J between a first qubit trapped in a first static potential well and a second qubit trapped in a second static potential well. The exchange coupling J enables the first qubit and / or the second qubit to tunnel through the potential barrier to at least one first static well or at least one second static potential well.

[0085] The first transfer gate assembly 50b1 has a subset of electrodes 50b1-1, 50b1-2, 50b1-3, 50b1-4 (at Figures 3A-3DThe transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding electrode subsets. Figures 3A-3D The tops of are marked with the same index, either 1, 2, 3, or 4. Figure 3A The number of electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4 shown is four. Similarly, the second transfer gate assembly 50b2 has electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 (in Figures 3A-3D The transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b2-1, 50b2-2, 50b2-3, 50b2-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding subset. Figures 3A-3D The tops of are marked with the same index, i.e., index 1, 2, 3, or 4. Figures 3A-3D As shown, interface 25 is located at one electrode of the subset of electrodes 50b1-4 of first transfer gate assembly 50b1 and at one electrode of the subset of electrodes 50b2-1 of second transfer gate assembly 50b2. Figure 3A The number of electrode subsets 50b2-1, 50b2-2, 50b2-3, and 50b2-4 shown in FIG is four. However, the number of electrode subsets of the first transfer gate assembly 50b1 and / or the second transfer gate assembly 50b2 can differ from this example, for example, three or five. Any number of electrode subsets of the transfer gate 50b can be selected, as long as one or more traveling potential wells can be generated for moving (shuttling) qubits (see below). The one or more traveling potential wells provide confinement for trapped electrons or holes, with a strength sufficient to overcome disorder during movement (shuttling) in the quantum well 69 and a height that provides a potential barrier between adjacent potential wells to inhibit tunneling. The trapped one or more electrons or holes adiabatically follow the sufficiently slow translation of the potential. The disorder is caused by one or more defects at the boundaries of the layers of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and / or defects within the dielectric layers 60, 66, and / or 67. The defects at the layer boundaries of the semiconductor heterostructure 12 include charge defects at the interface between the layer made of semiconductor material and the dielectric or insulating layer 60 and / or 66. These charge defects are randomly distributed, for example at the interface. The density of the charge defects is set to 5E10 / cm 2 Transitions to excited orbital states of electrons confined in one or more traveling potential wells are disorder-induced. Quasi-static fluctuations of disorder in the moving frame of one or more traveling potential wells transform into dynamic noise that couples to the orbital level. Setting the shuttle velocity to v = 10 m / s results in a reduced orbital excitation rate and sub-threshold phase errors.

[0086] In one aspect, the transfer gates 50b may be arranged at at least one path 45 in such a manner that juxtaposed ones of the transfer gates 50b extend different distances in the lateral (or transverse) direction D3 (eg, Figure 3A In another aspect, transfer gate 50b may extend equally far in lateral direction (or transverse direction) D3.

[0087] The transfer gates 50b can be arranged in a substantially equidistant manner with a substantially constant transfer gate gap between any two adjacent transfer gates 50b. If the transfer gate width of the transfer gates 50b, i.e., the extension of the transfer gates 50b in the longitudinal direction D3, is substantially constant, then the transfer gate pitch (the sum of the transfer gate gap and the transfer gate width) is also substantially constant. In one aspect of the present disclosure, the transfer gate pitch can be approximately 80 nm. The transfer gates 50b can be arranged in a periodic manner. In one aspect, the transfer gates 50b of any one of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged in a substantially equidistant manner from one another based on the spatial period of the periodically arranged transfer gates. In another aspect, any two transfer gates 50b belonging to any selected electrode subset of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 have one transfer gate of each other unselected electrode subset of those electrode subsets arranged therebetween. The periodic arrangement of the transfer gates 50b facilitates industrial manufacturing of the shuttle channel 16.

[0088] like Figure 3A As shown, the transfer gates belonging to any one of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4 are electrically connected to each other through electrical connections (not shown). The transfer gates of any electrode subset selected from the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4 are electrically disconnected from (or not electrically connected to) the transfer gates of the other electrode subsets (i.e., the corresponding unselected electrode subsets) in the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4. The electrical connections may be provided by metal strips arranged parallel to the shield grid 50a. The subset of electrodes of the transfer grids 50b1 and / or 50b2 indexed 1 and 3 may be on one side of at least one path 45 (e.g. Figure 3A The subset of electrodes of the transfer gates 50b indexed 2 and 4 may have an electrical connection on the other side of at least one path 45 (as shown). Figure 3AAs shown, below at least one path 45). In one aspect of the present disclosure, the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged at different levels in the stacking direction D1. For example, the metal strips connecting the transfer gates of the electrode subset 50b-1 can be arranged on one side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-3; and the metal strips connecting the transfer gates of the electrode subset 50b-2 can be arranged on the other side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-4. The electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can each be arranged at the level where the corresponding metal strips are arranged. On the other hand, the metal strips can all be arranged on one side of at least one path 45. In a further aspect, the metal strips in the metal strips connecting the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be electrically connected to the transfer gates of the corresponding electrode subsets through through-holes; and the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be basically arranged on one level in the stacking direction D1.

[0089] The electrical connection of the transfer gates of any of the electrode subsets 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, and 50b2-4 enables a single voltage to be supplied to the corresponding electrode subset of the transfer gates of the first transfer gate assembly 50b1 or the second transfer gate assembly 50b2. In other words, the number of voltage signals applied to the transfer gate 50b is given by the number of electrode subsets selected. Thus, the number of voltage signals applied to the shield gate 50a and the transfer gate 50b is independent of the length of the shuttle element 16. In the case of Figure 3A and Figure 3B In the example shown, the number of electrode subsets is four. However, this number can be smaller or larger than four. For example, using three electrode subsets can achieve the movement of one or more qubits through the traveling potential well.

[0090] At least one magnet 35 provides a magnetic field (not shown). The magnetic field can be a non-uniform magnetic field. The magnetic field provided by the at least one magnet 35 can have a non-zero magnetic field strength at the quantum well 69. The magnetic field can have a longitudinal component of a non-zero longitudinal magnetic field strength along the shuttling direction (or longitudinal direction) D2 at the quantum well 69. The magnetic field can have a transverse component of a non-zero transverse magnetic field strength along the lateral (or transverse) direction D3 at the quantum well 69.

[0091] Furthermore, the magnetic field of the at least one magnet 35 may have a transverse component with a non-zero transverse magnetic field strength and be transverse to the external magnetic field B0. The transverse component of the magnetic field may have a gradient in the shuttling direction D2. Additionally or alternatively, the magnetic field of the at least one magnet 35 may have a parallel component with a non-zero parallel magnetic field strength and be parallel to the external magnetic field B0. The parallel component of the magnetic field may have a gradient in the shuttling direction D2.

[0092] This enables a magnetic field to act on one or more qubits when one or more qubits are trapped in a potential well in a quantum well 69 having a non-zero magnetic field strength. Utilizing the non-uniform magnetic field of at least one magnet 35, EDSR (see above) can be used to rotate one or more spins of one or more qubits.

[0093] like Figures 3A-3D As shown, the at least one magnet 35 may include a first magnet 35-1 and a second magnet 35-2. An example of the first magnet 35-1 is a first micro magnet. An example of the second magnet 35-2 is a second micro magnet.

[0094] The first magnet 35-1 can be disposed at the first transfer gate assembly 50b1. The first magnet 35-1 can be disposed a distance from the interface 25. The first magnetic field of the first magnet 39-1 (which can be non-uniform) has a non-zero first magnetic field strength (having a longitudinal component and / or a transverse component, as described above) at the first portion 69-1 of the quantum well 69. In one aspect, the first magnetic field strength substantially vanishes at the interface 25.

[0095] The second magnet 35-2 can be disposed at the first transfer gate assembly 50b1. The second magnet 35-2 can be disposed near the interface 25. In one aspect, the second magnet 35-2 can be disposed at the first transfer gate assembly 50b1 and the second transfer gate assembly 50b2. In other words, the second magnet 35-2 can extend across the interface 25 in the shuttling direction (or longitudinal direction) D2.

[0096] The second magnetic field of the second magnet 39-2 (which may be non-uniform) has a non-zero second magnetic field strength (having a longitudinal component and / or a transverse component, as described above) at the second portion 69-2 of the quantum well 69. The second portion 69-2 may be located near the interface 25. In one aspect, the second portion 69-2 of the quantum well 69 may be located on both sides of the interface 25 along the shuttling direction (or longitudinal direction) D2. The second magnetic field strength may have a non-zero value at the interface 25.

[0097] In another aspect of the present disclosure, the manipulation area 20 may include only the first magnet 35 - 1 or only the second magnet 35 - 2 .

[0098] In a further aspect of the present disclosure, the steering region 20 may include a top gate 50d (see Figure 3C and Figure 3D ). The top gate 50d can extend in the lateral (transverse) direction D3. The top gate can extend in the shuttling direction (or longitudinal direction) D2. The top gate 50d can cover at least a portion of the first path 451 and / or the second path 452. In one aspect, at least in the lateral (transverse) direction D3, the top gate 50d completely covers the first path 451 and / or the second path 452.

[0099] In another aspect of the present disclosure, a top gate electrode 50d may be disposed above a transfer gate (or finger gate) 50b with a dielectric or insulating layer 67 disposed therebetween (see FIG. Figure 3C and Figure 3D ). The dielectric or insulating layer 67 may be partially disposed on the dielectric or insulating layer 60 (see Figure 3C 、 Figure 3D ). Portions of the dielectric or insulating layer 67 disposed between the transfer gates 50b may be disposed on the dielectric or insulating layer 60 (see Figure 3C 、 Figure 3D ). The dielectric or insulating layer 67 can be structured in the shuttle direction D2, for example segmented or profiled (see Figure 3D ). Dielectric or insulating layer 67 insulates transfer gates 50b belonging to different subsets of subsets 50b-1, 50b-2, 50b-3, 50b-4 from each other. In one aspect of the present disclosure, dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67 in which transfer gates 50b are embedded.

[0100] A constant voltage can be applied to the top gate 50d. In a further aspect, the voltage applied to the top gate 50d can be modified to be used for one or more actions on one or more qubits. For example, the voltage applied to the top gate 50d can be modified to be used to shuttle one or more qubits, to initialize one or more qubits, to read out one or more qubits, or to manipulate one or more qubits. In another example, the voltage applied to the top gate 50d can be modified based on a sequence of actions on one or more qubits, for example as part of executing an algorithm. In a further aspect, the voltage applied to the top gate 50d can be modified periodically or non-periodically. Periodically modifying and / or non-periodically modifying the voltage applied to the top gate 50d can depend on the actions performed on the one or more qubits. Periodically modifying the voltage applied to the top gate 50d includes adding a superposition of a square wave, a sawtooth wave, or a sine wave. Periodically modifying the voltage applied to the top gate 50d includes adding stepwise increments to the voltage applied to the top gate 50d. The step increment may depend on one or more actions performed on one or more qubits.

[0101] In one aspect, the top gate 50d can have a flat top surface (not shown). In another aspect of the present disclosure, the top gate 50d can be structured. An example of a structured top gate 50d is a segmented top gate 50d (see Figure 3D ) and / or a top grid 50d with a surface profile (or a top grid with a special shape). Figure 3D As shown, the top grid 50d can be constructed along the shuttle direction (or longitudinal direction) D2, such as segmented and / or profiled. In addition to or instead of the longitudinal construction, the top grid 50d can be constructed along the lateral direction (or transverse direction) D3, such as segmented and / or profiled. Figure 3D In the illustrated aspect, the top gate 50d includes a plurality of electrodes 50d-1, 50d-2, ..., 50d-12.

[0102] The top gate 50d enables the transfer gate spacing between transfer gates 50b to be increased while maintaining the ability to shuttle one or more qubits along at least one path 45. In addition, Figure 3D The constructed (e.g., segmented) top gate 50d shown in FIG enables adjustment or tuning of the Rabi frequency of the EDSR generated by the magnetic field of at least one magnet 35 and the applied AC electric field by applying one or more adjustment voltages (see below) to one or more of the multiple electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d.

[0103] In aspects of the present disclosure, at least one surface 14 may further include a back surface 142. At least one back gate 50c may be disposed on the back surface 142 of the semiconductor heterostructure 12 opposite to the top surface 141 (see FIG. Figure 3D ). The back surface 142 may be disposed at the bottom of the semiconductor heterostructure. The back surface 142 may be disposed opposite the top surface 141. The back surface 142 may be a surface of the silicon dioxide layer 62 (described above).

[0104] At least one back gate 50c can extend along a shuttling direction (or longitudinal direction) D2. At least one back gate 50c can also extend laterally (or transversely to at least one path 45). For example, at least one back gate 50c can also extend along a lateral (or transverse) direction D3 that is transverse to at least one path 45. At least one back gate 50c can overlap or intersect the shield gate 50a in the lateral direction D3. At least one back gate 50c can be arranged opposite the shield gate 50a. A voltage can be applied to at least one back gate 50c to provide an electric potential to modify the confinement at the quantum well 69.

[0105] In one aspect of the present disclosure, at least one back gate 50c can be configured along the shuttling direction D2, e.g., segmented and / or profiled. In another aspect of the present disclosure, at least one back gate 50c can be configured along the lateral direction D3 (transverse to at least one path 45), e.g., segmented and / or profiled. In a further aspect of the present disclosure, at least one back gate can be configured along the shuttling direction D2 and the lateral direction D3.

[0106] like Figure 3B-3D As shown, shield gate 50a and transfer gate 50b are separated by an insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during fabrication before transfer gate 50b is disposed on the insulating or dielectric layer 60. The four electrode subsets of transfer gate 50b may be separated by additional insulating or dielectric layers or materials (not shown). Additionally, a dielectric or insulating layer 66 may be disposed on semiconductor heterostructure 12 (see FIG. Figure 3B-3D The shield gate 50a is separated from the semiconductor heterostructure 12 by an insulating or dielectric layer 66. The shield gate 50a may be disposed on the insulating layer 66.

[0107] Manipulation region 20 is configured to manipulate one or more qubits at at least one magnet 35. During operation of quantum processor 10, manipulation region 20 will be used to manipulate one or more qubits. The manipulation may be a single qubit action or a two qubit action.

[0108] Figure 3E A time series (in four panels I, II, III, and IV) of a simulation showing the evolution of a potential energy profile generated by applying a voltage to gate electrode 50 to move two qubits (represented by solid circles) toward interface 25 (represented by a dashed vertical line) and lower the tunneling barrier between the two qubits to enable the exchange interaction J is shown. In this simulation, the detuning between the confining potentials of the two qubits is zero. The x-axis represents the distance from interface 25 along the shuttling direction D2. The y-axis represents the potential energy (or confinement energy). The horizontal bar above the potential energy represents the relative value of the voltage applied to transfer gate 50b at interface 25.

[0109] The use of two shuttling elements 16 that meet the interface 25 enables independent control of the distance between the two qubits at the interface and the tunnelling barrier between the two qubits. Effectively, the independent control of the tunnelling barrier height and width leads to reduced charge noise sensitivity and increased robustness to disorder. Compared to multi-quantum dot arrays, the control is greatly simplified because the high external barrier is automatically achieved during shuttling and only the inter-dot barrier needs to be precisely controlled. The actual gate operation is based on adiabatically turning on the exchange interaction J, which shifts the energy levels of the antiparallel spin states in such a way that they acquire an additional phase. In the accumulation After the phase, the subsequent single-qubit gate can realize the CPHASE gate.

[0110] In one aspect of the present disclosure, a single qubit action is to rotate one or more qubits by EDSR, which is based on moving one or more wave functions of one or more electrons (or holes) trapped (confined) in a potential well located in the first portion 69-1 of the quantum well 69 by applying an AC electric field, wherein the first magnetic field strength of the non-uniform first magnetic field of the first magnet 35-1 is non-zero. The AC electric field can be generated by, for example, a microwave signal applied to one or more transmission gates 50b. The resulting Rabi frequency is given by Ω=(gμ B E0 / 2k)(dB ⊥ / dx) where g is the g factor, μ B is the Bohr magneton, E0 is the amplitude of the AC electric field, dB ⊥ / dx is the gradient of the magnetic field of the at least one magnet 35 in the shuttling direction D2 (denoted by x) transverse to the external magnetic field B0 (i.e., the transverse component of the magnetic field of the at least one magnet 35 mentioned above), and k is the curvature of the confining potential well, which can be expressed in a first approximation as the parabolic potential (1 / 2)kx around the minimum of the confining potential well at x=0. 2 The strength of the confining potential and the orbital energy level splitting are determined by the curvature k. From the equation for the Rabi frequency Ω, it can be seen that a change Δk in the curvature k of the confining potential well results in a change ΔΩ in the Rabi frequency Ω, which is given by ΔΩ = -(Ω / k)Δk.

[0111] In one aspect of the present disclosure, one or more qubits are moved (shuttled) in an oscillatory manner at the location of the gradient maximum in the shuttling direction D2 of the magnetic field of at least one magnet 35 transverse to the external magnetic field B0. For a high-fidelity single-qubit gate, the amplitude of the oscillations that move one or more qubits is estimated to be approximately 20 nm, which is significantly larger than that of conventional EDSR, where the amplitude is on the order of several picometers. The higher amplitude allows the use of weaker magnetic field gradients, which in turn improves the overall robustness to charge noise.

[0112] The change Δk in the curvature k of the confining potential may be generated by applying one or more adjustment voltages to one or more of the plurality of electrodes 50 d - 1 , 50 d - 2 , . . . , 50 d - 12 of the top gate 50 d .

[0113] We consider a tuning voltage ΔV applied to a single electrode (hereinafter referred to as a “tuning gate”) among the multiple electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. The tuning gate can be located at the first portion 69-1 or the second portion 69-2 of the quantum well 69. The tuning gate can be located near the potential well that captures one or more quantum bits. For example, Figure 3DIn the case of , the tuning gate can be one of the electrodes 50d-2, 50d-3, 50d-6, 50d-7 or 50d-8 of the top gate 50d, but is not limited thereto. If the potential well that captures one or more qubits is located in the first portion 69-1 or the second portion 69-2, the Rabi frequency for rotating one or more qubits can be changed. The adjustment voltage ΔV applied to the tuning gate results in a potential that can be modeled as being generated by a dipole line oriented perpendicular to the shuttling direction D2 (i.e., oriented along the lateral or transverse direction D3) and pointing in the stacking direction D1: in, is a preset factor proportional to the tuning voltage ΔV applied to the tuning gate relative to the voltage applied to the plurality of gate electrodes 50 and the width of the tuning gate, x is the position along the shuttling direction D2, and d is the distance between the dipole line and the at least one path 45. In addition, the potential well that captures one or more qubits can be modeled as Where k = 2π / λ, λ is the spatial period, is a preset factor determined by the voltage applied to the transfer gate 50b, and x0 is the position along the shuttling direction D2 of the minimum of the potential well where one or more qubits are trapped.

[0114] In order to keep one or more qubits trapped in the potential well, there is an upper limit on the tuning voltage ΔV applied to the tuning gate. The upper limit of the tuning voltage ΔV can correspond to The adjustability or tunability of the Rabi frequency Ω is quantified by the ratio of the confinement strength (or curvature) of the regulating potential and the shuttling potential, i.e., the second derivative and The upper limit of the regulation voltage estimated above results in an adjustability (or adjustment range) or tunability (or tuning range) of the Rabi frequency Ω of 0.25d / λ. For typical values ​​of d = 50nm and λ = 300nm, the tuning range of the limiting intensity is much larger than that due to the shuttle potential alone. The resulting confinement is 1.5 times greater. For deconfinement (or deconfinement tuning) of the Rabi frequency Ω, it is recommended to stay below the upper limit to preserve the shape of the potential well with a harmonic minimum. Further considerations lead to the conclusion that, to ensure that the potential well can be approximated by a first-order quadratic potential described by the curvature k, the amplitude of the displacement of one or more qubits in an inhomogeneous magnetic field is limited to approximately 15 nm.

[0115] Figure 4 The upper panel shows the regulated potential and regulating the potential Shuttle potential Figure 2 shows an example of the sum of the potential wells (also referred to as "tuned potential wells"), where values ​​of d = 50 nm and λ = 300 nm are chosen. Figure 2 shows two examples of tuned potential wells, where tuning the voltage either weakens the confinement ("deconfined") or strengthens the confinement ("confined"). Figure 2 shows the corresponding untuned potential wells, where tuning the voltage does not change the confinement ("undisturbed"). The solid line indicates the tuned potential well. The dashed line indicates the tuned or tuned potential well. Also shown is a Gaussian charge density indicative of the spatial distribution of one or more qubits trapped in the potential well.As previously described, a tuned potential well produces a adjusted Rabi frequency Ω.

[0116] In another aspect of the present disclosure, there is a non-zero gradient dB in the shuttling direction D2 of the magnetic field of the at least one magnet 35 parallel to the external magnetic field B0 (the parallel component of the magnetic field of the at least one magnet 35). || In the case of dx / dx, the splitting of the spin-dependent energy levels by the external magnetic field B0 can be adjusted by changing the average position of the potential well minimum using another adjustment potential. The adjustment potential can be generated by applying an adjustment voltage ΔV to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. Applying the adjustment voltage can cause the average position of one or more qubits trapped in the potential well to change.

[0117] We consider a tuning voltage ΔV applied to two electrodes (“tuning gates”) of one or more electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. The two tuning gates can be located near the potential well in which one or more qubits are trapped. For example, in Figure 3D In the case of the top gate 50d, the two tuning gates can be selected from the electrodes 50d-2, 50d-3, 50d-6, 50d-7 or 50d-8 of the top gate 50d, but are not limited thereto. In one aspect, the two tuning gates can be located around the location of the potential well. For example, the two tuning gates can be located at a minimum distance of the potential well along the shuttle direction D2. The two tuning gates can include electrodes located at Figure 3D The first tuning gate on the left side of the potential well minimum and Figure 3D If the potential well in which one or more qubits are trapped is located in the first portion 69-1 or the second portion 69-2, the selection of the two tuning gates mentioned above will result in a change in the average position of the potential well, such as the minimum of the potential well in which one or more qubits are trapped. The change in the average position of the potential well results in a change in the magnetic field, thereby generating a spin-dependent energy level B0+ΔB0, where ΔB0=(dB || / dx)△x. Due to the change of magnetic field, the resonant frequency v=(gμ B / h)B0 changes △v=(gμB / h)△B0.

[0118] Figure 4 The lower panel shows the regulated potential and an example of a tuned potential well, where the values ​​of d = 50 nm and λ = 300 nm are chosen. An example of a tuned potential well is shown, where the tuning voltage changes the position of the potential well minimum ("shift"). A corresponding untuned potential well is shown, where the tuning voltage does not change the position of the potential well minimum ("undisturbed"). Solid lines indicate tuned or untuned potential wells. Dashed lines indicate tuned or tuned potential wells. Here it is the sum of the potentials generated by the dipole lines having opposite values ​​of the tuning voltage applied to them. Also shown is a Gaussian charge density indicating the spatial distribution of one or more qubits trapped in the potential well. As explained above, the tuned potential well produces a tuned resonant frequency.

[0119] The same considerations regarding the upper limit of the tuning voltage apply to the case of tuning the resonant frequency so as not to impair the shuttling of one or more qubits. Similar assumptions (see above) lead to a maximum shift of about 15 nm for the sum of the potential well minimum and the displacement of the one or more qubits trapped within the potential well.

[0120] In another aspect of the present disclosure, the potential barrier (or tunneling barrier) and detuning at the interface 25 can be adjusted. A tuning voltage ΔV can be applied to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. For example, one of the tuning voltages ΔV can be applied to electrode 50d-8 to increase or decrease tunneling coupling across the potential barrier (tunneling barrier). Other tuning voltages ΔV can be applied to electrodes 50d-7 and 50d-9 to change the detuning between the at least one first static potential well and the at least one second static potential well.

[0121] In another aspect of the present disclosure, the adjustment voltage may be applied to the transfer gate 50b instead of being applied to one or more of the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d. Figure 3B and Figure 3C In the illustrated aspect of the present disclosure, the transfer gate 50b has a subset of electrodes 50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4 that are independently voltaged. Figure 3DIn the illustrated aspect, at least three electrodes belonging to the electrode subsets 50b1-2, 50b1-3, 50b1-4 are located at the first portion 69-1 of the quantum well 69. In addition, at least three electrodes belonging to the electrode subsets 50b1-3, 50b1-4, 50b2-1 are located at the second portion 69-2 of the quantum well 69. One or more electrode subsets can be provided with an AC voltage for shuttling the potential well and a regulating voltage (DC voltage) for adjusting the manipulation parameter in a manner similar to when the regulating voltage is applied to the electrodes 50d-1, 50d-2, ..., 50d-12 of the top gate 50d.

[0122] The above examples of adjusting the Rabi frequency Ω, the resonance frequency v, or the exchange coupling J illustrate how the manipulation fidelity F can be improved by adjusting the parameters associated with manipulating one or more qubits (or “manipulation parameters”). M . The manipulation parameters include the Rabi frequency Ω, the resonant frequency v and the exchange coupling J. Adjustment of the manipulation parameters makes it possible to overcome the effects of fidelity reduction sites or disorder in the quantum well 69. The fidelity reduction sites 70 can be the result of, for example, manufacturing impurities, manufacturing defects, charge defects, crystal defects and / or locally reduced valley splitting. The fidelity reduction sites 70 can also be the result of a non-zero magnetic field strength of at least one magnet 35 parallel to the external magnetic field B0, which may affect the Rabi frequency Ω (see, for example, formula (2) in Kloeffel and Loss, Perspectives on Spin-Based Quantum Computing, 2012). When determining the manipulation fidelity F M When the requirements for reliable operation of the quantum processor 10 are not met, one or more manipulation parameters are adjusted so that the manipulation fidelity F can be improved. M .

Claims

1. A manipulation region (20) of a quantum processor (10), comprising a plurality of gate electrodes (50) arranged on a semiconductor heterostructure (12), wherein: The plurality of gate electrodes (50) include a first finger gate assembly (50b1) arranged at a first path (451) in the semiconductor heterostructure (12) and a second finger gate assembly (50b2) arranged at a second path (452) in the semiconductor heterostructure (12), The first path (451) and the second path (452) meet at an interface (25); The first finger gate assembly (50b1) and the second finger gate assembly (50b2) are configured to be provided with at least one voltage V to move at least one quantum bit along the first path (451) and / or the second path (452), and / or manipulate the current spin state of the at least one quantum bit located on the first path (451) and / or the second path (452).

2. The operating area (20) according to claim 1, wherein the operating area (20) further comprises at least one magnet (35).

3. The operating area (20) according to claim 2, wherein the at least one magnet is arranged at the interface (25).

4. The maneuvering area (20) according to claim 2, wherein the at least one magnet is arranged at a distance from the interface (25).

5. The steering region (20) according to any one of claims 1 to 4, wherein the semiconductor heterostructure (12) is made of a semiconductor material that provides spin-orbit coupling.

6. The manipulation area (20) according to any one of claims 1 to 5, wherein at least one of the first finger-gate assembly (50b1) and the second finger-gate assembly (50b2) comprises a plurality of electrode subsets (50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4).

7. The steering region (20) of claim 6, wherein the electrode subsets in the plurality of electrode subsets (50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4) are electrically disconnected from each other.

8. The manipulation region (20) of claim 6 or 7, wherein the electrode subsets of the plurality of electrode subsets (50b1-1, 50b1-2, 50b1-3, 50b1-4, 50b2-1, 50b2-2, 50b2-3, 50b2-4) have a dielectric or insulating layer (67) arranged between each other.

9. The manipulation area (20) according to any one of claims 1 to 8, further comprising a top gate (50d) arranged above the first finger gate assembly (50b1) and / or the second finger gate assembly (50b2).

10. The operating region (20) according to claim 9, wherein the top grid (50d) is configured in a longitudinal direction (D2).

11. The steering region (20) according to any one of claims 1 to 10, wherein a dielectric or insulating layer (66) is arranged between the semiconductor heterostructure (12) and the plurality of gate electrodes (50).

12. The steering region (20) according to any one of claims 1 to 11, wherein the gate electrodes of the plurality of gate electrodes (50) have a dielectric or insulating layer (60) arranged between each other.

13. The steering region (20) according to any one of claims 1 to 12, wherein the plurality of gate electrodes (50) are arranged on at least one surface (14) of the semiconductor heterostructure (12).

14. A system comprising a magnet for manipulating and providing an external magnetic field B0 according to any one of claims 1 to 13.

15. A method of manipulating at least one qubit located in a first path (451) in a semiconductor heterostructure (12) and / or a second path (452) in the semiconductor heterostructure (12), wherein the first path (451) and the second path (452) meet at an interface (25), and the semiconductor heterostructure (12) includes a plurality of gate electrodes (50) arranged thereon, the method comprising the steps of: Provide an external magnetic field B0; The current spin state of the at least one qubit is changed by moving the at least one qubit along the first path (451) and / or the second path (452) using an AC electric field applied to a gate electrode among the plurality of gate electrodes, or by irradiating the at least one qubit with electromagnetic radiation.

16. The method according to claim 15, further comprising: A Rabi frequency or a resonant frequency associated with changing the current spin state of the at least one qubit is adjusted.

17. The method according to claim 15 or 16, further comprising: The tunneling barrier at the interface (25) is changed.

18. The method according to any one of claims 15 to 17, further comprising: The detuning between two qubits confined to either side of the interface (25) is varied.

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