Apparatus for connecting qubits for semiconductor spin qubit quantum computer

Abstract

A T-junction for a quantum processor includes a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes includes a first transfer gate disposed at the at least one path and a second transfer gate disposed at the branch. The branch and the at least one path are arranged substantially perpendicular to each other and meet at a junction. The first transfer gate and the second transfer gate are configured to be supplied with at least one voltage V. The first and second transfer gates are configured to move at least one qubit disposed in the semiconductor heterostructure along the at least one path and / or along the branch, and to divert the at least one qubit from the at least one path into the branch or from the branch into the at least one path.

Description

Technical Field

[0001] The field of the present disclosure relates to the operation of quantum processors. Background Art

[0002] Quantum processor architectures must take scalability into account in order to achieve a sufficiently high number of logical qubits to implement quantum computer chips, which enable quantum computing in the NISQ (noisy intermediate-scale quantum) era or universal quantum computing. In the case of quantum computing based on spin qubits, the qubits are arranged in a two-dimensional plane. A disadvantage of this two-dimensional architecture is the so-called "fan-out problem," which refers to the space required for routing the control circuits of the quantum processor between the quantum processor and the traditional control circuits. These space requirements scale faster with the number of qubits than the size of the spin qubit-based quantum processor architectures proposed so far can scale.

[0003] Recently, a spin qubit architecture based on direct electron shuttling in Si / SiGe semiconductor heterostructures has been proposed. This architecture includes shuttle paths along which qubits can theoretically be transported over arbitrary distances, for example, up to approximately 50 μm. These shuttle paths allow components of a quantum processor (such as the loading, readout, and manipulation regions) to be spaced apart from one another, resulting in lower crosstalk. The provision of shuttle paths also enables operating modes that require relatively low operating frequencies and reduce local magnetic field gradients.

[0004] In these shuttle-based architectures, high-fidelity shuttling is crucial for reliable computation. This high fidelity can be compromised by, for example, charge defects or valley splitting on the shuttle path. Valley splitting can lead to leakage of the computational basis (e.g., two spin states) used for computation.

[0005] There is a need to identify points in a quantum processor (e.g., a shuttle path or other component of the quantum processor) at which the reliability of qubit processing decreases, which ultimately affects the performance of the quantum processor. Summary of the Invention

[0006] A T-junction for a quantum processor includes a plurality of gate electrodes arranged on a semiconductor heterostructure, wherein the plurality of gate electrodes includes a first transfer gate arranged at at least one path and a second transfer gate arranged at a branch. The branch and the at least one path are arranged substantially perpendicular to each other and meet at a junction; the first and second transfer gates are configured to be supplied with at least one voltage V to move at least one quantum bit arranged in the semiconductor heterostructure along the at least one path and / or along the branch, and to steer at least one quantum bit from the at least one path to the branch or from the branch to the at least one path.

[0007] The first transfer gate may also be configured to generate at least one traveling potential well for moving the at least one quantum bit along the at least one path or to generate a static potential well at the junction; and / or wherein the second transfer gate may also be configured to generate the traveling potential well for moving the at least one quantum bit along the branch or to generate a confining potential at the junction.

[0008] The first transfer gates may include electrode subsets that are electrically disconnected from each other, and the first transfer gates of any one of the electrode subsets are electrically connected to each other.

[0009] The T-junction may further include a shielding grid arranged along the at least one path, and / or a shielding grid arranged along the branch.

[0010] The shielding bars arranged along the branches may be connected to the shielding bars arranged along the at least one path at the junction, and the shielding bars may be interrupted between the shielding bars arranged along the branches.

[0011] At least one of the transfer gates may overlap a shield gate arranged along the at least one path at the junction.

[0012] The transfer gates may be disposed on a planarized dielectric or insulating layer.

[0013] The T-junction may further include a top gate disposed over the first transfer gate and / or the second transfer gate.

[0014] The T-type junction may further include a back gate disposed on the semiconductor heterostructure opposite to the first transfer gate and the second transfer gate.

[0015] A system includes a T-junction according to the present disclosure and an external magnet for providing an external magnetic field B0.

[0016] Disclosed is a method for moving at least one qubit, the at least one qubit being located at a junction of at least one path and a branch in a semiconductor heterostructure, the semiconductor heterostructure including a plurality of gate electrodes disposed thereon. The at least one path and the branch are perpendicular to each other and meet at the junction. The method includes: providing an external magnetic field B0; and providing a constraint at the junction for moving the at least one qubit along the at least one path, or providing a quasi-static potential well at the junction for adiabatically transferring the at least one qubit moving along the branch into the quasi-static potential well.

[0017] Providing the confinement may include providing a static voltage to at least some of the second transfer gates.

[0018] Providing the quasi-static potential well may include providing a static voltage to at least some of the transfer gates.

[0019] The method may further comprise moving the at least one qubit from the junction along the at least one path or the branch. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a top view of a quantum processor.

[0021] Figure 2 Show Figure 2 A top view of the unit cell of a quantum processor is shown in FIG.

[0022] Figure 3A Shown is a top view of one aspect of the shuttle channel.

[0023] Figure 3B A longitudinal cross-section showing another aspect of the shuttle channel.

[0024] Figure 3C A pair of path-defining gates are shown arranged on the path of the qubit.

[0025] Figure 3D A longitudinal cross-section showing another aspect of the shuttle channel.

[0026] Figure 4A A top view illustrating one aspect of a shuttle channel with segmented path-defining gate electrodes.

[0027] Figure 4B A longitudinal cross-section showing another aspect of the shuttle channel.

[0028] Figure 4C A pair of segmented path-defining gates are shown arranged on the path of one or more qubits.

[0029] Figure 5 A grayscale-coded panorama of the valley splitting of the shuttle channel is shown, along with examples of possible trajectories of qubits along the shuttle channel, which bypass a series of sites of reduced fidelity as the valley splitting decreases.

[0030] Figure 6A Shown is a top view of a T-junction.

[0031] Figure 6B Show Figure 6A A top view of the gate electrode is shown with the T-junction path defined in FIG.

[0032] Figure 7 Simulations showing track splitting during straight-line movement (left panel) and during turning at the knot during movement past the knot.

[0033] Figure 8 Shown is a simulation of the potential well at a T-junction during turning of at least one qubit at the junction.

[0034] Figure 9 Another aspect of the segmented path definition gate is shown.

[0035] Figure 10A Shown is a top view of a T-junction with a segmented path-defining gate.

[0036] Figure 10B Show Figure 6A A top view of the gate is shown with the segmented path of the T-junction defined. DETAILED DESCRIPTION

[0037] The present disclosure relates to a method of operating a quantum processor and a method of manufacturing a quantum processor.

[0038] Quantum processors can operate based on spin qubits. Spin qubits are two-level quantum systems with a spin degree of freedom. An example of a spin qubit is a two-level quantum system of electron spins confined in a quantum dot, and another example is a hole spin qubit. Furthermore, a group of electrons (e.g., two or three electrons) can be used to realize a spin qubit, such as the S-T0 singlet-triplet system of two electrons in a double quantum dot.

[0039] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in the semiconductor heterostructure 12. Using an electron-based spin qubit involves placing the electron spin in a known state. To this end, the electron state is initialized. In one aspect, the selected qubit is associated with the same electron throughout the execution of the quantum algorithm. On the other hand, a qubit implemented by a first electron can be initialized and subsequently operated on, and the qubit can be implemented by a second electron. On the other hand, without affecting the execution of the quantum algorithm, there is a situation where it is impossible to distinguish whether the qubit is implemented by the first electron or the second electron. Similarly, the method of the present disclosure can be applied to any type of hole spin qubit.

[0040] The use of semiconductor materials to form the semiconductor heterostructure 12 for implementing quantum processors is advantageous in manufacturing because the materials are easy to process and are inexpensive (e.g., in the case of silicon). The use of silicon in computing hardware has established technology. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be confined within the semiconductor heterostructure 12 formed of semiconductor materials in quantum wells 69 (see below and Figure 3D ). Quantum well 69 in Figure 3D However, the quantum well 69 will also be present in Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B In the semiconductor heterostructure 12 shown in . 2DEG or 2DHG can be further confined based on an electric potential. The electric potential can be a static electric potential or a non-static electric potential. The electric potential can form at least one quantum dot, wherein at least one electron or hole in the 2DEG or 2DHG is trappable or confined. The spin of the at least one trapped (confined) electron or hole can be used to realize a spin qubit. Moving the electric potential causes moving at least one quantum dot. The movement of at least one quantum dot enables the movement of at least one trapped (confined) electron / hole and the qubit associated with the at least one trapped (confined) electron / hole. Changing the strength of the electric potential changes the degree of confinement of the at least one trapped (confined) electron or hole.

[0041] A quantum processor may include a plurality of unit cells. A unit cell in the plurality of unit cells includes a component that performs at least one action or operation on one or more qubits located in the unit cell. The at least one action on the one or more qubits includes: loading the one or more qubits into the unit cell; unloading the one or more qubits from the unit cell; moving (shuttling) the one or more qubits into or out of the unit cell (i.e., to another unit cell of the quantum processor); manipulating the quantum state of the one or more qubits; and reading out the quantum state of the one or more qubits. Manipulating the one or more qubits may include: manipulating a single qubit or manipulating two qubits. Manipulating a single qubit includes: rotating the spin of the single qubit, for example, to drive a transition between multiple spin states. The multiple spin states may include an up spin state and a down spin state. Manipulating two qubits may be used to implement a CPHASE gate, a CNOT gate, and / or a SWAP gate. Manipulating the two qubits may further be used to implement a SQRT(SWAP) gate. Implementing a CNOT gate and one or more single-qubit gates (such as rotation or phase shift) is sufficient to realize a quantum computer. In a quantum computer based on spin qubits, the CNOT gate can be implemented as a CPHASE gate.

[0042] In one aspect, several actions performed by components of a unit cell on one or more qubits can be performed one after another as a sequence of actions. For example, two actions can be performed one after another. In another aspect, several actions performed by components of a unit cell on one or more qubits can be performed in parallel. For example, two actions can be performed in parallel.

[0043] In one aspect, several actions on one or more qubits may be performed within a single unit cell of a plurality of unit cells or across several unit cells of the plurality of unit cells.

[0044] In one aspect, several actions may be performed as part of determining gate fidelity (see below for more details). For example, determining gate fidelity may include performing a sequence of actions on one or more qubits.

[0045] In another aspect, several actions may be performed as part of executing an algorithm. For example, executing an algorithm may include performing a sequence of actions on one or more qubits.

[0046] Components are arranged within the unit cells. Some of the components are connected to one another. The components and their connections together constitute the layout or structure of the unit cell. Unit cells within a plurality of unit cells may have substantially the same structure, wherein the same components are arranged and connected to one another in substantially the same manner. Other units within the plurality of unit cells may have different structures, wherein the components and / or connections of the components are different.

[0047] One aspect of a quantum processor is disclosed in International Patent Application No. WO 2021 / 052541 A1, the entire contents of which are incorporated herein by reference. Figure 1 and Figure 2 As shown, the quantum processor 10 includes a semiconductor heterostructure 12. The semiconductor heterostructure 12 includes several layers of different material compositions. The semiconductor heterostructure 12 can be a Si / SiGe or GaAs / AlGaAs heterostructure, however, it is possible to use other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS. The semiconductor heterostructure can be undoped and / or strained. The semiconductor heterostructure 12 can serve as a substrate for the quantum processor 10. The semiconductor heterostructure 12 can include a 2DEG. The 2DEG or 2DHG can be arranged or located in a quantum well 69 (see Figure 3D ). One or more qubits may be arranged in quantum well 69. One or more qubits may be arranged in at least one quantum dot formed in quantum well 69. One or more qubits may be generated from a 2DEG.

[0048] In one aspect, the semiconductor heterostructure 12 may further include a silicon capping layer 64 having a dielectric or insulating layer 66 disposed thereon (see Figure 3D ). The gate electrodes 50a, 50b may be arranged on top of the dielectric or insulating layer 66.

[0049] On the other hand, the semiconductor heterostructure 12 may further include a strained silicon layer 63 (see Figure 3D In yet another aspect, the semiconductor heterostructure 12 may further include a silicon dioxide layer 62 (see Figure 3D ).

[0050] exist Figure 1 and Figure 2In the aspect of the quantum processor 10 shown, the components 16, 18, 20, 22, 24 are disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 1 As shown, the illustrated aspect of quantum processor 10 includes one or more of each of components 16, 18, 20, 22, 24. In another aspect, quantum processor 10 may include one or more of only some of components 16, 18, 20, 22, 24.

[0051] Figure 1 and Figure 2 The illustrated quantum processor 10 is a substantially two-dimensional device defined by at least one surface 14. The third dimension of the quantum processor 10 is defined by the thickness of the semiconductor structure 12 and the thicknesses of the components 16, 18, 20, 22, 24.

[0052] The plurality of unit cells of the quantum processor 10 includes a plurality of unit cells 26 (e.g. Figure 2 shown). Figure 2 In the illustrated aspect, unit cell 26 includes components 16, 18, 20, 22, 24. In another aspect of the present disclosure, unit cell 26 includes only some of components 16, 18, 20, 22, 24. In yet another aspect, unit cell 26 may include more than one of at least one of components 16, 18, 20, 22, 24.

[0053] The components 16, 18, 20, 22, 24 include a plurality of gate electrodes 50 arranged on at least one surface 14 of the semiconductor heterostructure 12 (see Figure 3A and Figure 3B ). The plurality of gate electrodes 50 may be arranged to define at least one path 45 within the quantum well 69 of an associated one of the components 16, 18, 20, 22, 24 (see Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3C 、 Figure 3D 、 Figure 4A 、 Figure 4C ), one or more qubits can move (shuttle) along these paths.

[0054] exist Figure 1 and Figure 2 , at least one path 45 is shown as being oriented substantially in two directions on the surface 14, the two directions being substantially perpendicular to each other, forming a grid-like structure of a plurality of paths 45. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0055] The plurality of gate electrodes 50 may also be arranged to move (shuttle) one or more qubits along the at least one path 45. The movement (shuttling) may occur in either of two directions (forward and backward) along the at least one path 45. The plurality of gate electrodes 50 may also be arranged to perform at least one action performed by the components 16, 18, 20, 22, 24 on the one or more qubits.

[0056] Multiple gate electrodes 50 can be provided with a voltage. Multiple gate electrodes 50 can be made of metal. Multiple gate electrodes 50 can be superconducting. The voltage can be used for one or more purposes, such as defining at least one path 45, moving (shuttling) one or more qubits, and / or performing at least one action on one or more qubits. The voltage can include a DC (direct current) voltage and an AC (alternating current) voltage. The voltage can include one or more static voltages and one or more non-static voltages. The voltage can be applied via a DC line, an AC line, and / or a biasing device.

[0057] One or more of the components 16, 18, 20, 22, 24 may also include a magnet, such as a micromagnet. The micromagnet may be placed on top of the components 16, 18, 20, 22, 24. The micromagnet provides a magnetic field. The magnetic field may have a zero gradient or a non-zero gradient.

[0058] The external magnetic field splits the multiple spin states (e.g., up spin and down spin) used as the basis for computation of one or more qubits into separate energy levels (Zeeman splitting). The external magnetic field can be provided by an external magnet (e.g., an electromagnet (not shown)) located near the quantum processor 10. The quantum processor 10 can be at least partially placed in the external magnetic field provided by the external magnet.

[0059] One or more components 16, 18, 20, 22, 24 may further include a device for providing electromagnetic radiation (e.g., microwaves) for manipulating the quantum state of one or more qubits (e.g., rotating the spin of one or more qubits between multiple spin states). By electromagnetic radiation based on electron spin resonance (ESR), the spin of one or more qubits can be switched between, for example, an up spin state and a down spin state, or vice versa. The frequency of the electromagnetic radiation can be equal to the energy difference of the separated energy levels. ESR provides another way to manipulate the quantum state of one or more qubits. Microwaves can have a frequency in the range of hundreds of MHz to hundreds of GHz. In one aspect, the frequency is in the range of 9-10 GHz, but is not limited thereto.

[0060] For example, a non-uniform magnetic field is provided by at least one magnet 35, i.e., with a non-zero gradient, so that the transition between multiple spin states can be driven by the displacement of one or more qubits in a non-uniform magnetic field based on, for example, an AC electric field. The AC electric field can be provided by one or more gate electrodes 50b. This effect is called electric dipole spin resonance (EDSR). The displacement causes one or more qubits to oscillate between multiple spin states (e.g., spin states that form the basis of calculation, such as an up spin state and a down spin state). For example, one or more qubits can oscillate so that an up spin state can be switched to a down spin state, and vice versa.

[0061] Alternatively, EDSR may be implemented in a semiconductor heterostructure 12 in which spin-orbit coupling exists. The semiconductor heterostructure 12 may be made of a semiconductor material that provides spin-orbit coupling.

[0062] The plurality of gate electrodes 50 may be provided as one or more gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may include one or more laterally positioned gate electrodes 50a (also referred to as "shielding gates") (see Figure 3A ), which is arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 5 ) to move (shuttle) one or more qubits within or outside the unit cell. Trajectory 80 can be the trajectory of one or more potential wells (described further below) in which one or more qubits can be arranged. The one or more potential wells can therefore be one or more traveling potential wells. The trajectory 80 of the one or more potential wells can therefore correspond to the trajectory of the one or more qubits arranged on at least one path 45. Therefore, the lateral position of trajectory 80 can correspond to the lateral position of the one or more potential wells and / or one or more qubits. Arranging one or more qubits on at least one path 45 should be understood to mean that the one or more qubits are arranged within quantum well 69.

[0063] The plurality of gate electrodes 50 may further include one or more shuttle gate electrodes 50b (also referred to as "transfer gates" or "finger gates") (see Figure 3A ) which is arranged to move (shuttle) one or more qubits along at least one path 45 to move (shuttle) one or more qubits within a unit cell or outside a unit cell.

[0064] The plurality of gate electrodes 50 may further include at least one pitch-enhanced gate electrode 50d (also referred to as a "top gate") arranged so as to enhance the pitch or gap of the transfer gates 50b.

[0065] The plurality of gate electrodes 50 may further include at least one vertically positioned gate electrode 50c (also referred to as a "back gate") arranged to define and / or modify a trajectory 80 in the quantum well 69 and / or at at least one path 45 (see Figure 3D ) to move (shuttle) one or more qubits within or outside the unit cell. The vertical position of trajectory 80 can correspond to the vertical position of one or more potential wells and / or one or more qubits.

[0066] The plurality of gate electrodes 50 may further include qubit processing gate electrodes, which are configured to perform at least one action on one or more qubits. The qubit processing electrodes include plunger gates and barrier gates. The plunger gates can be used to control quantum dot occupancy, control detuning in a double quantum dot, and / or perform a swap between two qubits. The barrier gates can be used to form a double potential well and / or control the tunneling barrier in the double quantum dot.

[0067] A plurality of gate electrodes 50 may be arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers separated by an insulating or dielectric layer 60 and an insulating or dielectric layer 66 (see Figure 3B and Figure 3D In one aspect, the layers can be arranged in a direction substantially perpendicular to the direction of at least one path 45.

[0068] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67 may be planarized. One method of manufacturing the shuttle element 16 may include the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and / or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before the transfer gate 50b is positioned on the insulating or dielectric layer 60. Planarization facilitates the use of processes such as electron beam epitaxy, deep ultraviolet (DUV), and / or spacer lithography. Planarization reduces the thickness of one or more of the dielectric or insulating layers 60, 66, and 67. For example, before fabricating the transfer gate 50b, the insulating or dielectric layers 66 and / or 60 may be planarized to reduce the thickness of the insulating or dielectric layers 66 and / or 60, respectively. After planarization, the insulating or dielectric layers 66 and / or 60 are tightly positioned on the semiconductor heterostructure 12. Planarizing insulating or dielectric layer 66 and / or 60 results in a reduced thickness of insulating or dielectric layer 66 and / or 60 between at least one via 45 and transfer gate 50b. In one aspect, the thickness of insulating or dielectric layer 60 is required to cover the top and side surfaces of shield gate 50a.

[0069] Component 16 is used to move (shuttle) one or more quantum dots in semiconductor heterostructure 12 to move (shuttle) one or more qubits within or outside the unit cell. Component 16 is also referred to as a "shuttle channel." Various aspects of shuttle channel 16 are disclosed in International Patent Application No. WO 2021 / 052531A1, the entire disclosure of which is incorporated herein by reference.

[0070] Component 18 provides a junction at which one or more quantum dots can be diverted into at least one branch 45' (at least one second path in at least one path 45) branching out from at least one path 45 for moving (shuttling) one or more quantum bits within or outside the unit cell. Component 18 is also referred to as a "T-junction". The at least one path 45 and at least one branch 45' of the T-junction 18 are arranged substantially perpendicular to each other. In one aspect, the at least one path 45 and at least one branch 45' of the T-junction 18 can substantially form a T-shape. Various aspects of the T-junction 16 are disclosed in International Patent Application No. WO2021 / 052539 A1, the entire disclosure of which is incorporated herein by reference.

[0071] Component 20 is provided for manipulating qubits in quantum dots. Component 20 is also referred to as a "manipulation zone." Manipulation zone 20 enables manipulation of one or more current spin states of one or more qubits. Any qubit has a current spin state. In one aspect, multiple spin states may include the current spin state. In another aspect, the current spin state may be a linear combination of multiple spin states. During manipulation, one or more current spin states may change. Aspects of manipulation zone 20 are disclosed in WO 2021 / 052537 A1, the entire disclosure of which is incorporated herein by reference.

[0072] Component 22 is used to initialize one or more spin states of one or more quantum bits. When one or more spin states have been initialized, any one of the one or more current spin states is equal to one spin state in the plurality of spin states. After initialization, one or more current spin states may remain unchanged during the relaxation time. The relaxation time describes the transition between the upper spin state and the lower spin state due to interaction with the environment (such as the lattice of the semiconductor heterostructure 12). Component 22 is also referred to as an "initialization zone". Various aspects of the initialization zone 22 are disclosed in WO 2021 / 052538 A1, the entire disclosure of which is incorporated herein by reference.

[0073] Component 24 is used to read out one or more current spin states of one or more qubits. When one or more spin states have been read out, any one of the one or more current spin states before the readout is known. Component 24 is also referred to as the "readout region." Various aspects of readout region 24 are disclosed in WO 2021 / 052536 A1, the entire disclosure of which is incorporated herein by reference.

[0074] The quantum processor 10 is operated to execute an algorithm, such as a quantum algorithm. As described above, executing the algorithm includes performing a sequence of actions on one or more qubits. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cell 26.

[0075] Operating quantum processor 10 involves controlling at least one action performed by components 16, 18, 20, 22, and 24. In one aspect of the present disclosure, the at least one action is controlled by applying voltages to a plurality of gate electrodes 50. The voltages can be set and / or adjusted to improve the fidelity F of the at least one action and / or sequence of actions. Fidelity F is a measure of how reliably the at least one action or sequence of actions produces the expected result based on the design of quantum processor 10 and the voltages applied to the plurality of gate electrodes 50. To determine fidelity F, at least one action or sequence of actions is repeated; the proportion of repetitions in which the actual result equals the expected result is then determined. The actual result includes one or more current spin states that have been read out at readout region 24 after the at least one action or sequence of actions. The expected result includes one or more current spin states that are expected to be read out at readout region 24 after the at least one action or sequence of actions based on the known fidelity of components 16, 18, 20, 22, and 24 and / or the relaxation time of one or more qubits.

[0076] For example, at least one action may include moving (shuttling) one or more qubits along at least one path 45 of the shuttling channel 16. In this case, the fidelity F is the shuttling fidelity. Shuttling fidelity is understood as the probability that one or more current spin states of one or more qubits are preserved during shuttling. For example, the shuttling fidelity may be determined by repeatedly performing a sequence of actions: initializing one or more qubits, moving (shuttling) one or more qubits, and reading out one or more qubits; then determining whether the initialized spin state of the one or more qubits is equal to the one or more current spin states after shuttling and before reading out; and finally calculating the proportion of repetitions in which one or more current spin states are unchanged.

[0077] Another example is turning one or more qubits during the movement of one or more qubits. When one or more qubits approach the T-junction 18, moving the one or more qubits may include turning the one or more qubits at the junction 28. Turning means changing the direction in which the one or more qubits are moving. The T-junction 18 may be connected to the straight-line shuttle fidelity F ss During a straight-line shuttle, one or more qubits do not change the direction in which one or more qubits are moving (see below Figure 7 ). Linear shuttling fidelity is similar to the shuttling fidelity described above. However, linear shuttling involves moving one or more qubits through the junction 28. In addition, the T-junction 18 can be used with the off fidelity F To During the off period, one or more qubits change the direction in which one or more qubits are moving (see below Figure 7 Switching off involves changing the direction in which one or more qubits move at junction 28.

[0078] As explained above, determining the shuttle fidelity Fs involves an initialization step and a readout step. M In a manner similar to that described above, the shuttle fidelity F can be determined by determining the fidelity F (which is a combination, i.e., the product, of the initialization fidelity, the shuttle fidelity, and the readout fidelity) and then dividing the fidelity F by the initialization fidelity and the readout fidelity. s Similarly, the straight-line shuttle fidelity F ss Can be determined as: initialization fidelity, straight-line shuttle fidelity F ss The combined fidelity F is then divided by the initialization fidelity and the readout fidelity. Similarly, the shutdown fidelity F To Can be determined as: initialization fidelity, shutdown fidelity F To The combined fidelity F is calculated as the combined fidelity of the initialization fidelity and the readout fidelity, and the combined fidelity F is then divided by the initialization fidelity and the readout fidelity.

[0079] Fidelity F may also be gate fidelity. Gate fidelity F is a measure of how well the results of a gate operation (i.e., a sequence of actions performed by components 16, 18, 20, 22, 24 on one or more qubits associated with the gate that quantum processor 10 is designed to implement) match expected results (e.g., theoretical results) based on the design of quantum processor 10 and components 16, 18, 20, 22, 24. Gate fidelity F can be determined through randomized benchmark testing.

[0080] As an example, improving the shuttling fidelity F of a single qubit along the shuttling channel 16 will be described. Figure 3A 1 shows aspects of a shuttle channel 16. The shuttle channel 16 includes a shield gate 50a and a transfer gate 50b disposed on at least one surface 14 of the semiconductor heterostructure 12. Figure 3A In the illustrated aspect, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. Figure 3B In the aspect shown, top surface 141 may be the top surface of dielectric or insulating layer 66 (described further below).

[0081] The shield 50a is arranged to extend on either side of at least one path 45 as shields 50a-1 and 50a-2 (see also Figure 3C ). In one aspect, as Figure 3A-3C As shown, the shielding grids 50a-1 and 50a-2 may extend continuously along at least one path 45. Figure 6A-Figure 6B As shown, one of the shield gates 50a-1 and 50a-2 can be interrupted along at least one path 45, for example, where a branch 45' branches off from at least one path 45. Shield gates 50a-1 and 50a-2 can be separated by approximately 200 nm. Shield gate 50a can be made of metal and can be fabricated by embedding the metal into semiconductor heterostructure 12 or by localized implantation of the metal into semiconductor heterostructure 12. Shield gate 50a can be embedded in dielectric or insulating layer 66 and / or dielectric or insulating layer 60.

[0082] The dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60 can be provided as two separate portions (not shown) that surround the two shield gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extends into the gap (not shown) between the two portions along the lateral direction D3. Thus, the semiconductor heterostructure 12 can form a ridge (not shown) in the gap between the two portions of the dielectric or insulating layer 66 and / or the dielectric or insulating layer 60.

[0083] The transfer gate 50b is arranged to extend laterally across at least one path 45 (e.g. Figure 3A For example, the transfer gate 50b may extend in the lateral direction D3. The transfer gate or finger gate 50b may be arranged along at least one path 45.

[0084] In such Figure 3A In the aspect shown, transfer gates 50b are provided in the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 (in Figure 3AThe transfer gates in the transfer gate 50b belonging to one of the electrode subsets 50b-1, 50b-2, 50b-3, 50b-4 are indicated by indices 1, 2, 3, 4 above the transfer gates of the corresponding electrode subsets. Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B The tops of are marked with the same index, either 1, 2, 3, or 4. Figure 3A The number of electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 shown in FIG is four. However, the number of electrode subsets of the transfer gate 50b can be different from this example, for example, three or five. Any number of electrode subsets of the transfer gate 50b can be selected as long as one or more traveling potential wells can be generated for moving (shuttling) the qubit or one or more qubits (see below).

[0085] One or more traveling potential wells provide confinement for trapped electrons or holes, which are strong enough to overcome disorder during movement (shuttling) in the quantum well 69, and whose height provides a barrier between adjacent potential wells to inhibit tunneling. The trapped electron or holes adiabatically follow a sufficiently slow transition in potential. The disorder is due to one or more of defects at the layer boundaries of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and / or defects within the dielectric layers 60, 66, and / or 67. The defects at the layer boundaries of the semiconductor heterostructure 12 include charge defects at the interface between the layer made of semiconductor material and the dielectric or insulating layer 60 and / or 66. These charge defects are randomly distributed, for example at the interface. The density of the charge defects is set to 5E10 / cm 2 Transitions of electrons confined in one or more traveling potential wells to excited orbital states are disorder-induced. Quasi-static fluctuations of disorder in the moving frame of one or more traveling potential wells transform into dynamic noise at the coupled orbital level. Setting the shuttle velocity to v = 10 m / s results in a reduced orbital excitation rate and subthreshold phase errors.

[0086] In one aspect, the transfer gates 50b may be arranged at at least one path 45 in such a manner that juxtaposed ones of the transfer gates 50b extend different distances in the lateral (or transverse) direction D3 (eg, Figure 3A In another aspect, transfer gate 50b may extend equally far in lateral direction (or transverse direction) D3.

[0087] The transfer gates 50b can be arranged in a substantially equidistant manner with a substantially constant transfer gate gap between any two adjacent transfer gates 50b. If the transfer gate width of the transfer gates 50b, i.e., the extension of the transfer gates 50b in the longitudinal direction D3, is substantially constant, then the transfer gate pitch (the sum of the transfer gate gap and the transfer gate width) is substantially constant. In one aspect of the present disclosure, the transfer gate pitch can be approximately 80 nm. The transfer gates 50b can be arranged in a periodic manner. In one aspect, the transfer gates 50b of any one of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged in a substantially equidistant manner from one another based on the spatial period of the periodically arranged transfer gates. In another aspect, any two transfer gates 50b belonging to any selected electrode subset of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 have one transfer gate of each other unselected electrode subset of these electrode subsets arranged therebetween. The periodic arrangement of the transfer gates 50b facilitates industrial manufacturing of the shuttle channel 16.

[0088] like Figure 3A As shown, the transfer gates 50b belonging to one of the four electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically connected to each other by electrical connections (not shown). The element gates of any electrode subset selected from the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 are electrically disconnected (or not electrically connected) from the element gates of the corresponding unselected electrode subsets. The electrical connection can be provided by a metal strip arranged parallel to the shield gate 50a. The electrode subsets of the transfer gates 50b indexed 1 and 3 can be on one side of at least one path 45 (e.g., Figure 3A The subset of electrodes of the transfer gates 50b indexed 2 and 4 may have an electrical connection on the other side of at least one path 45 (as shown). Figure 3AAs shown, below at least one path 45). In one aspect of the present disclosure, the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be arranged at different levels in the stacking direction D1. For example, the metal strips connecting the transfer gates of the electrode subset 50b-1 can be arranged on one side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-3; and the metal strips connecting the transfer gates of the electrode subset 50b-2 can be arranged on the other side of at least one path 45, which are arranged at a higher level in the stacking direction D1 than the metal strips connecting the transfer gates of the electrode subset 50b-4. The electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can each be arranged at the level where the corresponding metal strips are arranged. On the other hand, the metal strips can all be arranged on one side of at least one path 45. In a further aspect, the metal strips in the metal strips connecting the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be electrically connected to the transfer gates of the corresponding electrode subsets through through-holes; and the transfer gates of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 can be basically arranged on one level in the stacking direction D1.

[0089] The electrical connection of the element gates of any of the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 enables a single voltage to be supplied to the corresponding electrode subset. In other words, the number of voltage signals applied to the transmission gate 50b is given by the number of selected electrode subsets. Thus, the number of voltage signals applied to the shielding gate 50a and the transmission gate 50b is independent of the length of the shuttle element 16. Figure 3A and Figure 3B In the example shown, the number of electrode subsets is four, but this number may be smaller or larger than four.

[0090] In a further aspect of the present disclosure, the shuttle path 16 may include a top gate 50d (see Figure 3D ). The top gate 50d can extend in the lateral (transverse) direction D3. The top gate can extend in the shuttling direction (or longitudinal direction) D2. The top gate 50d can cover at least a portion of the first path 451 and / or the second path 452. In one aspect, at least in the lateral (transverse) direction D3, the top gate 50d completely covers the first path 451 and / or the second path 452.

[0091] In another aspect of the present disclosure, a top gate electrode 50d may be disposed above the transfer gate 50b with a dielectric layer 67 disposed therebetween. The dielectric or insulating layer 67 may be partially disposed on the dielectric or insulating layer 60 (see FIG. Figure 3D). Portions of the dielectric or insulating layer 67 disposed between the transfer gates 50b may be disposed on the dielectric or insulating layer 60. The dielectric or insulating layer 67 may be structured in the shuttle direction D2, for example segmented or profiled (see Figure 3D ). Dielectric or insulating layer 67 insulates transfer gates 50b belonging to different subsets of subsets 50b-1, 50b-2, 50b-3, 50b-4 from each other. In one aspect of the present disclosure, dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67 in which transfer gates 50b are embedded.

[0092] A constant voltage can be applied to the top gate 50d. In a further aspect, the voltage applied to the top gate 50d can be modified to be used for one or more actions on one or more qubits. For example, the voltage applied to the top gate 50d can be modified to be used to shuttle one or more qubits, to initialize one or more qubits, to read out one or more qubits, or to manipulate one or more qubits. In another example, the voltage applied to the top gate 50d can be modified based on a sequence of actions on one or more qubits, for example as part of executing an algorithm. In a further aspect, the voltage applied to the top gate 50d can be modified periodically or non-periodically. Periodically modifying and / or non-periodically modifying the voltage applied to the top gate 50d can depend on the actions performed on the one or more qubits. Periodically modifying the voltage applied to the top gate 50d includes adding a superposition of a square wave, a sawtooth wave, or a sine wave. Periodically modifying the voltage applied to the top gate 50d includes adding stepwise increments to the voltage applied to the top gate 50d. The step increment may depend on one or more actions performed on one or more qubits.

[0093] In one aspect, the top gate can have a flat top surface (not shown). In another aspect of the present disclosure, the top gate 50d can be structured. An example of a structured top gate 50d is a segmented top gate 50d. Another example of a structured top gate 50d is a top gate with a surface profile (or a shaped top gate), such as Figure 3D In one aspect, the top gate 50d may be a segmented and shaped top gate. Figure 3D As shown, the top grid 50d can be constructed along the shuttle direction (or longitudinal direction) D2, such as segmented and / or profiled. As a supplement or alternative to the longitudinal structure, the top grid 50d can be constructed along the lateral direction (or transverse direction) D3, such as segmented and / or profiled.

[0094] The top gate 50d enables the spacing between the transfer gates 50b to be increased while maintaining the ability to shuttle one or more qubits along at least one path 45. In addition, Figure 3DThe structured (eg, segmented) top gate 50d shown in FIG. 5 enables tuning of the Rabi frequency of the EDSR generated by the magnetic field of the at least one magnet 35 and the applied AC electric field.

[0095] In aspects of the present disclosure, at least one surface 14 may further include a back surface 142. At least one back gate 50c may be disposed on the back surface 142 of the semiconductor heterostructure 12 opposite to the top surface 141 (see FIG. Figure 3D ).exist Figure 3D In the illustrated aspect, the back surface 142 is disposed at the bottom of the semiconductor heterostructure. The back surface 142 is disposed opposite the top surface 141. The back surface 142 may be a surface of the silicon dioxide layer 62 (described above).

[0096] exist Figure 3D In the illustrated aspect, the at least one back gate 50c extends along the shuttling direction or longitudinal direction D2 of the shuttle channel 16. The at least one back gate 50c can also extend laterally (or transversely to the at least one path 45). For example, the at least one back gate 50c can also extend along a lateral (or transverse) direction D3 of the shuttle channel 16 that is transverse to the at least one path 45. The at least one back gate 50c can overlap or intersect the shield gate 50a in the lateral direction D3. The at least one back gate 50c can be arranged opposite the shield gate 50a. A voltage can be applied to the at least one back gate 50c to provide an electric potential to modify the confinement at the quantum well 69.

[0097] In one aspect of the present disclosure, at least one back gate 50c can be configured along the shuttling direction (or longitudinal direction) D2, e.g., segmented and / or profiled. In another aspect of the present disclosure, at least one back gate 50c can be configured along the lateral direction D3 (i.e., transverse to at least one path 45), e.g., segmented and / or profiled. In a further aspect of the present disclosure, at least one back gate can be configured along the shuttling direction (or longitudinal direction) D2 and the lateral direction D3, e.g., segmented and / or profiled.

[0098] like Figure 3B As shown, shield gate 50a and transfer gate 50b are separated by an insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during fabrication before transfer gate 50b is disposed on the insulating or dielectric layer 60. The four electrode subsets of transfer gate 50b are separated by an additional insulating or dielectric layer or material (not shown). In addition, a dielectric or insulating layer 66 may be disposed on semiconductor heterostructure 12 (see FIG. Figure 3B and Figure 4B The shield gate 50a is separated from the semiconductor heterostructure 12 by an insulating or dielectric layer 66. The shield gate 50a may be disposed on the insulating layer 66.

[0099] The shuttle channel 16 is configured to move (shuttle) one or more qubits along at least one path 45. During operation of the quantum processor 10, the shuttle channel 16 will be used to move one or more qubits, for example, from the initialization region 22 to the manipulation region 20 and then to the readout region 24. During this sequence of actions on one or more qubits, in one aspect of the present disclosure, two shielding grids (or "gates") 50a-1, 50a-2 (see FIG. 1 ) of the shielding grids 50a of the shuttle channel 16 may be moved. Figure 3A and Figure 3C ) are provided with the same voltage, for example 0V. An AC voltage is provided to the transfer gate 50b to provide one or more traveling potential wells in which one or more qubits can be moved (shuttled). The AC voltage provided to the transfer gate 50b can be a sine wave voltage. The AC voltage provided to the transfer gate 50b can be phase-shifted between the electrode subsets of the transfer gates 50b-1, 50b-2, 50b-3, and 50b-4. The phase shifts of the transfer gates 50b-2, 50b-3, and 50b-4 relative to the transfer gate 50b-1 can be set to π / 2, π, and 3π / 2, respectively. However, other settings for the phase shift are also possible. The phase shift can deviate from being set to a multiple of π / 2.

[0100] One or more qubits are transmitted along at least one path 45 (along Figure 5 The x-axis extension of the trajectory 80 (see Figure 5 ) in the lateral direction D3 is determined by applying the two gate electrodes 50a-1, 50a-2 in the shielding grid 50a (see, for example, Figure 3C). If the voltage applied to gate 50a-1 is substantially equal to the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will be substantially in the middle of the two gates 50a-1, 50a-2. On the other hand, if the voltage applied to gate 50a-1 is different from the voltage applied to gate 50a-2, the lateral position or positions of the one or more potential wells generated (i.e., the one or more minima of the one or more potential wells) will deviate from the middle of the two gates 50a-1, 50a-2. The different voltages on gates 50a-1, 50a-2 may be the result of changing the voltage applied to gate 50a-1 or the voltage applied to gate 50a-2 by adding an adjustment voltage ΔV. In other words, the voltage applied to gate 50a-1 or gate 50a becomes V+ΔV. For example, in the case where heterostructure 12 is an undoped Si / SiGe heterostructure, if the voltage applied to gate 50a-1 is reduced relative to the voltage applied to the other gate 50a-2, one or more locations of the generated one or more potential wells (i.e., one or more minima of the one or more potential wells) will shift toward the other gate 50a-2. In the case where heterostructure 12 is doped, such as when GaAs / AlGaAs is used, increasing the voltage applied to gate 50a-1 will shift the one or more potential wells toward the other gate 50a-2. In this way, the trajectory 80 of one or more qubits along at least one path 45 can be shifted laterally (i.e., in a lateral or transverse direction D3 relative to the at least one path 45).

[0101] In one aspect of the present disclosure, the lateral shift of the trajectory 80 of one or more qubits may be transient (at Figure 5 The transient lateral shift is the result of the addition of the time-varying adjustment voltage ΔV(t) to the voltage applied to gate 50a-1 or to gate 50a-2. In other words, the track 80 only temporarily deviates from the lateral position initially set during calibration (i.e., at Figure 5 A y-position of 0 nm in the example shown). A temporal lateral shift results in e.g. Figure 5 Trajectory 80-1 is shown.

[0102] In one aspect, the time-varying adjustment voltage ΔV(t) can be an AC voltage, such as a square pulse or square wave. Figure 5If the qubits are spaced an average distance of 1000 nm (or 1 μm) from each other along the x-axis in FIG45 and the shuttle speed of one or more qubits along at least one path 45 is 10 nm / ns (or 10 m / s), then on average, it takes 100 ns for one or more qubits to travel a distance equal to this average distance. Therefore, the time-varying modulation voltage ΔV(t) can last for 100 ns. For example, half a period of the square wave can be selected to be equal to 100 ns. In other words, the square wave can be selected to have a frequency of 5 MHz.

[0103] In a further aspect of the present disclosure, the adjustment voltage comprises a DC voltage added to the AC voltage applied to the transfer gate 50b. This DC voltage may be applied to the transfer gate 50b in addition to or in lieu of the adjustment voltage ΔV(t) applied to the shield gate 50a. The further adjustment voltage may provide a modification to the confinement provided by the transfer gate 50b, for example, to enhance the confinement when one or more qubits are near a fidelity reduction site 70 (see below).

[0104] The lateral shifting of the lateral position of trajectory 80-1 enables bypassing of reduced fidelity sites 70 in shuttle channel 16. When one or more qubits pass through reduced fidelity sites 70 in shuttle channel 16, the shuttling fidelity F may be reduced. The reduced shuttling fidelity F results in lower shuttling reliability of the one or more qubits along shuttle channel 16. Reduced fidelity sites 70 may be the result of, for example, manufacturing impurities, manufacturing defects, charge defects, crystal defects, and / or locally reduced valley splitting. Figure 5 A grayscale-coded valley splitting distribution plot is shown for valley splitting energies between 0 μeV and 300 μeV (lighter shaded areas correspond to higher valley splitting energies; darker shaded areas correspond to lower valley splitting energies). Fidelity reduction sites 70 are located at valley splitting energies between 0 μeV and approximately 30-50 μeV (illustrated by light shaded areas within dark shaded areas). Figure 5 In the example shown, the trajectory 80-1 bypasses several fidelity degradation sites 70 located at y positions of 0 nm. The fidelity degradation sites 70-1, 70-2, 70-3, ..., 70-10 are indicated by arrows and, in some cases, by white dashed elliptical markers. In the example shown, the deviation Δy from the lateral position of the trajectory 80 initially set during calibration (i.e., the y position of 0 nm set during the calibration step described below) is Figure 5 The peak value of about 20 nm is reached in the lateral direction D3 along the positive y-axis. Figure 5In another embodiment, the maximum values ​​of the deviation Δy in the two lateral directions (along the positive and negative y axes, respectively) may be different from 20 nm and -20 nm, respectively.

[0105] The lateral displacement of the lateral position y of the track 80 - 1 is further enabled to continuously adjust the lateral position y of the track 80 - 1 by a time-varying adjustment voltage ΔV(t). The time-varying adjustment voltage ΔV(t) results in a time-varying deviation Δy(t). Continuous adjustment may be required in the case of voltage fluctuations applied to the plurality of gate electrodes 50 .

[0106] In one aspect of the present disclosure, similar to the lateral shift described above, one or more vertical positions of one or more potential wells can be vertically shifted, i.e., in the stacking direction D1 (as described below). As a result, the vertical position of the track 80-3 (the position along the stacking direction D1) can be changed. When the voltage applied to at least one back gate 50c is changed, the confinement of the one or more potential wells changes. The voltage applied to at least one back gate 50c can be changed relative to the voltage applied to the shield gate 50a. According to at least one fidelity reduction site 70 (at Figure 3D The vertical position of the track 80 can be changed upward or downward in the stacking direction D1 by the position indicated by the asterisk in the figure. As a result, at least one fidelity reduction point 70 can be bypassed and the reliability (ie, fidelity) of the shuttle channel 16 can be improved.

[0107] Determination of the shuttle fidelity F enables identification of the location of the fidelity degradation site 70 at (e.g., along and / or near) the track 80-1 or 80-3. During identification of the location of the fidelity degradation site 70, the applied voltage V is iteratively adjusted. Thus, the lateral position of the track 80-1 and / or the vertical position of the track 80-3 are iteratively adjusted. Identification of the location of the fidelity degradation site 70 results in a method for controlling the shuttle channel 16.

[0108] In one aspect of the present disclosure, lateral and / or vertical shifting of trajectory 80 may be used in manipulation region 20 to move one or more qubits to a manipulation position that is inconsistent with a fidelity reduction site 70 .

[0109] Figure 6A The illustrated T-junction 18 includes a shuttling element 16 along at least one path 45 .

[0110] The T-junction 18 further includes a second shuttle element 16' (referred to as the "second shuttle element") in the shuttle element 16 along the branch 45'. Figure 6AAs shown, the second shuttle element 16' has two screens 50a'-1 and 50a'-2 extending in a second longitudinal (or shuttle) direction D2'. The second shuttle element 16' further includes a shuttle grid (or finger grid) 50b'. The shuttle grid 50b' extends in a second transverse (or lateral) direction D3'.

[0111] The at least one path 45 and the at least one branch 45' are arranged substantially perpendicular to each other. The second longitudinal direction D2' is perpendicular to the longitudinal direction D2. The second lateral direction D3' is perpendicular to the lateral direction D3.

[0112] Shuttle element 16 (referred to as "first shuttle element") and second shuttle element 16' are joined at junction 28. At least one path 45 and branch 45' meet at junction 28. Two shielding gates 50a'-1 and 50a'-2 terminate at junction 28. Transfer gate 50b' terminates at junction 28.

[0113] The screen 50a-1 of the first shuttle element 16 is interrupted in the longitudinal direction D2 at the junction 28. The screen 50a-1 is interrupted where the screens 50a'-1 and 50a'-2 of the second shuttle element 16' end. The screen 50a-1 is interrupted where the first shuttle element 16 and the second shuttle element 16' are joined to each other at the junction 28. The interruption can extend along the lateral direction D3' between at least the screens 50a'-1 and 50a'-2.

[0114] The shield grid 50a'-1 of the second shuttle element 16' can be connected to a portion of the shield grid 50a-1 of the first shuttle element 16. The shield grid 50a'-2 of the second shuttle element 16' can be connected to another portion of the shield grid 50a-1 of the first shuttle element 16. The shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be electrically connected in such a way that the shield grids 50a-1 and 50a'-1 (50a-2 and 50a'-2) effectively form a single continuous shield grid. In another aspect, the shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be designed as a single continuous shield grid. In another aspect, the shield grids 50a-1 and 50a'-1 (50a-1 and 50a'-2) can be separated by a dielectric or insulating layer.

[0115] The transfer gates 50b' of the second shuttle element 16' can be arranged at the junction 28 in the second longitudinal direction D2' (or the lateral direction D3 of the first transfer gate 16) such that at least one of the transfer gates 50b' contacts or overlaps the shield gate 50a-1 of the first shuttle element 16 along the second longitudinal direction D2' (or the first lateral direction D3). Some of the transfer gates 50b' can have curved or angled ends in the lateral direction D3'. Some of the transfer gates 50b' can be arranged adjacent to the junction 28.

[0116] exist Figure 6A In the illustrated aspect, the transfer grid of the electrode subset 50b'-1 of the second shuttle element 16' closest to the junction 28 ("the last transfer grid 50b'") overlaps the shield grid 50a-1. The last transfer grid 50b' extends in the lateral direction D3' at least between the shield grids 50b'-1 and 50b'-2. The last transfer grid 50b is arranged adjacent to the lower edge of the shield grid 50a-1 along the lateral direction D3 (as shown in FIG. Figure 6A (as shown). This arrangement of the last transfer gate 50b' enables a shielding potential to be provided by applying a voltage to the last transfer gate 50b' to provide sufficient confinement for one or more qubits. The voltage applied to provide confinement can be fixed. Providing a shielding potential enables compensation for interruptions in the shield gate 50a-1 while shuttling one or more qubits along the shuttling element 16 at the junction 28.

[0117] The transfer gate 50b of the first shuttle element 16 is arranged at the junction 28 so that the transfer gate 50b does not contact the transfer gate 50b' of the second shuttle element 16'. Figure 6A As shown, the transfer gate 50b of the first shuttle element 50b at the junction is arranged below the last transfer gate 50b' of the second transfer element 16' along the lateral direction D3 (or the second longitudinal direction D2') (as shown in FIG. Figure 6A ).

[0118] As the one or more qubits move along branch 45' toward junction 28, a voltage can be applied to transfer gate 50b of first shuttle element 16 to provide a quasi-stable potential well, into the minimum of which the one or more qubits can adiabatically move by traveling the potential well along second shuttle element 16'. The quasi-stable potential well is generated by applying a static voltage to transfer gate 50b of first shuttle element 16. Once the one or more qubits are moved to the minimum of the quasi-stable potential well provided by transfer gate 50b of first shuttle element 16, the voltage applied to transfer gate 50b can be changed to an AC voltage to move (shuttle) the one or more qubits along at least one path 45 through first shuttle element 16.

[0119] To reverse the movement, the voltage applied to the transfer gates 50b and 50b' can be adjusted. Thus, the difference in confinement strength between the first shuttling element 16 and the branch 16' can be managed.

[0120] When one or more qubits are located at junction 28, the one or more qubits can be moved along longitudinal direction D3 or along second longitudinal direction D3'. One or more qubits can be shuttled along at least one path 45 without turning into branch 45'. One or more qubits can be shuttled along at least one path 45 and turned along branch 45' (or vice versa). Thus, T-junction 18 enables movement of one or more qubits on quantum chip 10.

[0121] Figure 7 A simulation of the orbital splitting between the ground state and the first excited state of one or more qubits during movement of the one or more qubits in a straight line along the first shuttle element 16 (left panel) is shown. The simulation shows that the orbital splitting is above 1 meV throughout the simulated movement. For a shuttle speed of about 10 m / s, decoherence can be prevented if the orbital splitting remains above about 1 meV, which is Figure 7 The left panel shows the case of linear shuttling.

[0122] During the movement of one or more qubits, one or more qubits are transferred from the second shuttle element 16' to the first shuttle element 16 (see Figure 7 The orbital splitting drops below 1 meV (right panel of the figure). The orbital splitting can be improved by dynamically adjusting the offset between the transfer gates 50b and 50b' to increase the confinement at the junction 28. Another option is to adjust the shuttle speed.

[0123] Figure 8 A simulation of a quasi-stable potential well located at junction 28 and a traveling potential well moving along the second shuttle element 16' is shown (as described above). The results show that one or more qubits trapped in the traveling potential well moving along the second shuttle element 16' can be adiabatically transferred to the quasi-stable potential well. Tunneling of the one or more qubits can be prevented.

[0124] The method of adjusting the voltages applied to the plurality of gate electrodes 50 according to the present disclosure implements a method of controlling the quantum processor 10 .

[0125] Based on determining the density of the fidelity reduction sites 70 in a portion of the quantum processor 10, such as along one of the shuttle channels 16, at the T-junction 18, or throughout the quantum processor 10, the elevated density may point to characteristics of the quantum processor 10 fabrication process or materials used in the fabrication process. In this case, the quantum processor 10 may be fabricated such that the shielding grids 50a-1 and 50a-2 disposed thereon (see FIG. Figure 3A and Figure 3B ) is segmented.

[0126] In one aspect, the shield 50a-1 and / or the shield 50a-2 of the shuttle channel 16 can be segmented into electrically disconnected shield segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively. Figure 4A and Figure 4B shown.

[0127] exist Figure 4A and Figure 4B In the illustrated aspect, dielectric or insulating layer 60 includes a first dielectric or insulating layer 60a and a second dielectric or insulating layer 60b. Shield gates 50a-1 and 50a-2 and transfer gate 50b are separated by first insulating or dielectric layer 60a and / or by second insulating or dielectric layer 60b.

[0128] A dielectric or insulating layer 66 separates shield gates 50a-1 and 50a-2 from semiconductor heterostructure 12. Figure 4A and Figure 4B In the illustrated aspect, the shield segments 50a-11, 50a-21 may be disposed on the insulating layer 66. Figure 4A and Figure 4B In the illustrated aspect, a portion of the first dielectric and insulating layer 60 a is disposed between the shield fence segments 50 a - 12 , 50 a - 22 and the dielectric or insulating layer 66 .

[0129] For example, if an average of two fidelity degradation sites 70 are found per 1 μm along at least one path 45 of the shuttle channel 16, the shield segments 50a-11, 50a-12, 50a-21, and 50a-22 of the shield 50a can be designed to be no longer than approximately 500 nm. In one aspect, the shield 50a can be subdivided into four shield segments each approximately 250 nm in length.

[0130] The electrically disconnected shield fence segments 50a-11, 50a-12, 50a-21, 50a-22 are disconnected at a segmentation point (or disconnection point) 55. The shield fence segments 50a-11, 50a-12, 50a-21, 50a-22 of the shield fence 50a may be disconnected by a first dielectric or insulating layer 60a at the segmentation point 55. At the segmentation point 55, the first dielectric or insulating layer 60a may be disposed between the shield fence segments 50a-11 and 50a-12 and / or between the segments 50a-21 and 50a-22, respectively.

[0131] The shield gate 50a can be separated from the transfer gate 50b by a dielectric or insulating layer 60. In one aspect, the first dielectric or insulating layer 60a can at least partially separate the shield gate 50a from the transfer gate 50b. In this aspect, the second dielectric or insulating layer 60b can at least partially separate the shield gate 50a from the transfer gate 50b. For example, in Figure 4B In the aspect shown, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a are separated from the transfer gate 50b by a second dielectric or insulating layer 60b. In this aspect, the first dielectric or insulating layer 60a and the second dielectric or insulating layer 60b can be partially arranged on each other. The first portion 60a1 of the first dielectric or insulating layer 60a can be arranged on the shielding gate segments 50a-11, 50a-21 of the shielding gate 50a. In addition, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a can be at least partially arranged on the second portion 60a2 of the first dielectric or insulating layer 60a. Therefore, the shielding gate segments 50a-12, 50a-22 of the shielding gate 50a can be arranged at a higher level relative to the segments 50a-11, 50a-21 of the shielding gate 50a along the stacking direction D1 (see Figure 4B ).

[0132] The first dielectric or insulating layer 60a may form a step 60as at the segmentation point 55. The step 60as may be a portion of the first dielectric or insulating layer 60a. The first portion 60a1 and the second portion 60a2 may be connected by the step 60as. The step 60as may extend in the stacking direction D1. Furthermore, the step 60as may extend in the longitudinal direction D2.

[0133] In another aspect, the shuttle channel 16 may include a protrusion 161. The protrusion may be located at the segmentation point 55. At the protrusion 161, the protruding transfer gate 50bp of the transfer gate 50b, the protruding portion 60bp of the second dielectric or insulating layer 60b, the protruding portion 50a-12p of the segment 50a-12 of the shield gate 50a, and / or the protruding portion 50a-22p of the segment 50a-22 of the shield gate 50a may protrude relative to at least one surface 14 in the stacking direction D1 (see FIG. Figure 4B). The protruding transfer gate 50bp of the transfer gate 50b, the protruding portion 60bp of the second dielectric or insulating layer 60b, the protruding portion 50a-12p of the shield gate segment 50a-12 of the shield gate 50a, and / or the protruding portion 50a-22p of the shield gate segment 50a-22 of the shield gate 50a can protrude relative to the transfer gate 50b, the second dielectric or insulating layer 60b, the shield gate segment 50a-12, and / or the shield gate segment 50a-22, respectively. Therefore, the transfer gate 50bp, the portion 60bp, the portion 50a-12p, and the portion 50a-22p can be arranged at a higher level along the stacking direction D1 relative to the transfer gate 50b, the second dielectric or insulating layer 60b, the shield gate segment 50a-12, and the shield gate segment 50a-22, respectively. The protruding portion 60bp of the second dielectric or insulating layer 60b can have a portion extending in the stacking direction D1. The raised portion 60bp of the second dielectric or insulating layer may cover the raised portion 50-12p of the shield gate segment 50a-12 and / or the raised portion 50-22p of the shield gate segment 50a-22. The protrusion 161 may extend through the shield gate 50a-1 and / or the shield gate 50a-2 in the lateral (transverse) direction D3.

[0134] In another aspect, the protruding portions 50a-12p of the shield fence segments 50a-12 and / or the protruding portions 50a-22p of the shield fence segments 50a-22 of the shield fence 50a may be arranged to contact or intersect the line L extending along the stacking direction D1 along the longitudinal direction D2 (see FIG. Figure 4B ). Line L may also contact the shielding fence segment 50a-11 and / or the shielding fence segment 50a-21 of the shielding fence 50a along the longitudinal direction D2. On the other hand, the shielding fence segment 50a-12 and / or the shielding fence segment 50a-22 may intersect with the line L or overlap with the line L. In a further aspect, the shielding fence segment 50a-11 and / or the shielding fence segment 50a-21 may intersect with the line L or overlap with the line L along the longitudinal direction D2. In other words, through the protrusions 50a-12p and / or 50a-22p, the shielding fence segments 50a-11 and / or 50a-21 may overlap with the shielding fence segments 50a-12 and / or 50a-22, respectively, in the shuttling direction (or longitudinal direction) D2 (see Figure 4B ) without contacting each other. The shield fence segment 50a-11 and / or the shield fence segment 50a-21 are arranged to overlap with the shield fence segment 50a-12 and / or 50a-22, respectively, in a contactless manner in the shuttling direction (or longitudinal direction) D2, so that a continuous electric potential can be provided by the voltage applied to the shield fence segments 50a-11, 50a-12 of the shield fence 50a-1 and / or the voltage applied to the shield fence segments 50a-21, 50a-22 of the shield fence 50a-2.

[0135] Alternatively, the shuttle channel 16 does not have the protrusion 161. In this case, the second dielectric or insulating layer 60b can have a flat surface. In this case, the transfer gates 50b will be arranged at the same level along the stacking direction D1; or the electrode subsets 50b-1, 50b-2, 50b-3, and 50b-4 will be arranged at different levels along the stacking direction D1 (see above) without any transfer gate 50b protruding.

[0136] In another aspect, a gap in the shield grids 50a-1 and / or 50a-2 can be provided at segmentation points 55 along the shuttling direction (or longitudinal direction) D2, wherein the shield grids 50a-1 and / or 50b-2 are segmented. A gap can be provided along the shuttling direction (or longitudinal direction) D2 between the shield grid segments 50a-11, 50a-12 of the shield grid 50a-1 and / or between the shield grid segments 50a-21, 50a-22 of the shield grid 50a-2. A step 60as can be provided in the gap. In this aspect, no transfer gate 50b can be arranged above the gap in the stacking direction D1. Arranging the transfer gate 50b (which provides a potential well for moving (shuttling) one or more qubits) without any overlap between the transfer gate 50b and the gap prevents the transfer gate 50b from generating a potential that would interfere with the potential provided by the shield grids (or path-defining grids) 50a-1, 50a-2 that define the trajectory 80.

[0137] The shielding grid 50a is segmented into shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22 so that a voltage can be applied to the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively. The voltage applied to the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-22, respectively, can be a DC voltage, in which case, given a corresponding duration of the DC voltage, the trajectory 80-2 will remain constant along the shielding grid segments 50a-11, 50a-12 and / or 50a-21, 50a-2, as shown in FIG. Figure 5 As shown. Figure 5 In the example shown, the shield grid 50a is segmented into three sections, to which individual DC voltages are applied, as can be seen from the position of the trace 80-2 relative to the line of y=0 nm.

[0138] Based on the determined density of the fidelity degradation sites 70, one or more segmentation points (or disconnection points) 55 may be arranged in the quantum processor 10. The segmentation points 55 may be arranged in the quantum processor 10 based on the distribution of the fidelity degradation sites 70 derived from the locations of the identified fidelity degradation sites 70. For example, assuming that the distances between the fidelity degradation sites 70 are Gaussian distributed with a mean distance d and a standard deviation σ d, then the segmentation points 55 can be arranged in the quantum processor 10, wherein the distance between any two segmentation points 55 is, for example, approximately d-2xσ d .

[0139] In one aspect of the present disclosure, the shielding grid 50a-1 and the shielding grid 50a-2 are segmented into shielding grid segments 50a-11, 50a-12 and 50a-21, 50a-22, respectively. Alternatively, one of the shielding grid 50a-1 and the shielding grid 50a-2 is segmented. In this case, the shielding grid 50a-1 is segmented into shielding grid segments 50a-11, 50a-12, or the shielding grid 50a-2 is segmented into shielding grid segments 50a-21, 50a-22.

[0140] Figure 9 An aspect of the present disclosure is shown wherein the shuttle channel 16 has two segmentation points 55. The screen 50a-1 is segmented into three segments 50a-11, 50a-12, 50a-13, and / or the screen 50a-2 is segmented into three segments 50a-21, 50a-22, 50a-23.

[0141] As described above, the shuttle channel 16 may include two protrusions 161. Similarly, as described above, the transfer gate 50b may include two protruding transfer gates 50bp. Similarly, as described above, the second dielectric or insulating layer 60b may include two protruding portions 60bp. Figure 9 As shown, the two protrusions 60bp can belong to a single dielectric or insulating layer 60b. Similarly, the shield 50a-1 can include two protrusions 50a-12p, as described above; and / or the shield 50a-12 can include two protrusions 50a-22p, as described above. The two protrusions 50a-12p can belong to a single shield portion 50a-12, as described above. Figure 9 The two protruding portions 50a-22p may belong to a single shielding grid portion 50a-22, as shown. Figure 9 As shown. The first dielectric or insulating layer 60a may include two steps 60as. Figure 9 As shown, the two steps 60as may belong to a single first dielectric or insulating layer 60a.

[0142] Figure 10A and Figure 10B Shows the Figure 9 The aspects of the present disclosure shown are applied to Figure 6A The shielding grid 50a-2 of the first shuttle element 16 of the shielding grid 18 is divided into three sections, as shown in FIG. Figure 9 As shown. Figure 10A and Figure 10BAs shown, the segments 50a-22 can be arranged at the junction 28. This arrangement enables adjustment of the voltage applied to the shield segments 50a-22 in the presence of a fidelity degradation site 70 at the junction 70. The adjustment voltage ΔV can be added to the voltage applied to the shield segments 50a-22 to bypass the fidelity degradation site 70 at the junction 28 by changing the trajectory 80, or to offset the effect of the fidelity degradation site 70 at the junction 28 by adding restrictions created by the shield segments 50a-22 (which may be combined with the last transfer gate 50b' of the second shuttle element 16'). The shield segments 50a-22 have contact points 50a-22c for applying the adjustment voltage ΔV.

Claims

1. A T-junction (18) for a quantum processor (10), comprising a plurality of gate electrodes arranged on a semiconductor heterostructure (12), wherein The plurality of gate electrodes (50) include a transfer gate (50b) arranged at at least one path (45) and a transfer gate (50b') arranged at a branch (45'), The branch (45') and the at least one path (45) are arranged substantially perpendicular to each other and meet at a junction (28); The transfer gate (50b) and the transfer gate (50b') are configured to be provided with at least one voltage V to move at least one quantum bit arranged in the semiconductor heterostructure (12) along the at least one path (45) and / or along the branch (45'), and to divert the at least one quantum bit from the at least one path (45) to the branch (45') or from the branch (45') to the at least one path (45).

2. A T-junction (18) according to claim 1, wherein the transfer gate (50b) is further configured to generate at least one traveling potential well for moving the at least one quantum bit along the at least one path (45) or to generate a static potential well at the junction (28); and / or wherein the transfer gate (50b') is further configured to generate the traveling potential well for moving the at least one quantum bit along the branch (45') or to generate a confining potential at the junction (28).

3. A T-junction (18) according to claim 1 or 2, wherein the transfer gate (50b) includes electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) that are electrically disconnected from each other, and the transfer gates (50b) of any one of the electrode subsets (50b-1, 50b-2, 50b-3, 50b-4) are electrically connected to each other.

4. The T-junction (18) according to any one of claims 1 to 3, further comprising a shielding grid (50a-1, 50a-2) arranged along the at least one path (45) and / or a shielding grid (50a'-1, 50a'-2) arranged along the branch (45').

5. A T-junction (18) according to any one of claims 1 to 4, wherein the shielding gates (50a'-1, 50a'-2) arranged along the branch (45') are connected to the shielding gate (50a-1) arranged along the at least one path (45) at the junction (28), and the shielding gate (50a-10) is interrupted between the shielding gate (50a'-1) and the shielding gate (50a'-2).

6. The T-junction (18) according to any one of claims 1 to 5, wherein at least one of the transfer gates (50b') overlaps a shield gate (50a) arranged along the at least one path (45) at the junction (28).

7. The T-junction (18) according to any one of claims 1 to 6, wherein the transfer gate (50b) is arranged on a planarized dielectric or insulating layer (60).

8. The T-junction (18) according to any one of claims 1 to 7, further comprising a top gate (50d) arranged above the transfer gate (50b) and / or the transfer gate (50b').

9. The T-junction (18) according to any one of claims 1 to 8, further comprising a back gate (50c) arranged on the semiconductor heterostructure (12) and opposite to the transfer gate (50b) and the transfer gate (50b').

10. A system comprising a T-junction (18) according to any one of claims 1 to 9 and an external magnet for providing an external magnetic field B0.

11. A method for moving at least one quantum bit, the at least one quantum bit being located at a junction (28) of at least one path (45) and a branch (45') in a semiconductor heterostructure (12), the semiconductor heterostructure (12) comprising a plurality of gate electrodes (50) arranged thereon, the at least one path (45) and the branch (45') being perpendicular to each other and meeting at the junction (28), the method comprising: Provide an external magnetic field B0; A confinement is provided at the junction (28) for moving the at least one qubit along the at least one path (45), or a quasi-static potential well is provided at the junction (28), the quasi-static potential well being used to adiabatically transfer the at least one qubit moving along the branch (45) into the quasi-static potential well.

12. The method of claim 11 , wherein providing the restriction comprises: A static voltage is provided to at least some of the transfer gates (50b').

13. The method according to claim 11 or 12, wherein providing the quasi-static potential well comprises: A static voltage is provided to at least some of the transfer gates (50b).

14. The method according to any one of claims 11 to 13, further comprising: The at least one qubit is moved from the junction (28) along the at least one path (45) or the branch (45').

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