Driving method of display device, display device and electronic equipment

Abstract

A method for driving a display device (100), a display device (100), and an electronic apparatus (1). The driving method includes: applying a frame start signal (STV) and a plurality of clock signals (CLK1, CLK2,... CLK8) to a gate driving circuit (10) (S401) so that the gate driving circuit (10) outputs a plurality of gate driving signals (G1, G2,... GN); scanning the array of sub-pixels (P) row by row or multiple rows by using a plurality of gate drive signals (G1, G2,... GN) to turn on each row of scanned sub-pixels (P), so that the duration of the two adjacent rows of sub-pixels (P) in the turn-on state at the same time is greater than or equal to 2 times of the unit scanning time (H) (S402); and applying data signals (D11, D12,... D1M, D21, D22,... D2M) to at least two rows of sub-pixels (P) in an on state at the same time, so that the duration of applying the data signals (D11, D12,... D1M, D21, D22,... D2M) to at least part of the rows of sub-pixels (P) is greater than the unit scanning time (H) (S403). The rising edge of the frame start signal (STV) is earlier than the rising edge of the first-stage clock signal (CLK1), the falling edge of the frame start signal (STV) is not later than the falling edge of the first-stage clock signal (CLK1), and the phase difference between the falling edge of the frame start signal (STV) and the falling edge of the first-stage clock signal (CLK1) is larger than or equal to 0.2 times of unit scanning time (H) and smaller than or equal to 0.6 times of unit scanning time (H).

Description

Display device driving method, display device, and electronic equipment Technical Field

[0001] Embodiments of the present disclosure relate to a method for driving a display device, a display device, and an electronic device. Background Art

[0002] With technological advancements, display devices are moving towards larger sizes and higher resolutions. However, as the size of display devices increases and the resolution improves, the charging time provided to each row of pixels becomes shorter and shorter, making it impossible to meet the required pixel charging rate, thus affecting the display.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a method for driving a display device, comprising: wherein the display device includes a timing controller, a gate driving circuit, and a source driving circuit, and the method includes: the timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit; the gate driving circuit outputs a plurality of gate driving signals to a sub-pixel array based on the frame start signal and the plurality of clock signals, and utilizes the plurality of gate driving signals to scan the sub-pixel array one row or multiple rows one by one, so as to turn on each scanned row of sub-pixels, so that the time length during which two adjacent rows of sub-pixels are simultaneously in an on state is greater than or equal to 2 times a unit scanning time, and the unit scanning time is the time required to scan a row of sub-pixels, wherein the sub-pixel array includes a plurality of sub-pixels arranged in an N×M array, where N and M are both integers greater than 1; and the source driving circuit outputs a plurality of gate driving signals to the sub-pixel array that are simultaneously in an on state. Data signals are applied to at least two rows of sub-pixels in the state, so that the time duration for which data signals are applied to at least some rows of sub-pixels is greater than the unit scan time; wherein, the gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, and the N shift register units include a first-stage shift register unit connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal; wherein, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is no later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0005] For example, in the driving method provided in at least one embodiment of the present disclosure, the first-stage shift register unit to the P-th stage shift register unit among the N shift register units are connected to the frame start signal; the multiple clock signals also include a P-th clock signal for driving the P-th stage shift register unit to output a gate drive signal; the duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured so that the falling edge of the frame start signal is aligned with the rising edge of the P-th clock signal.

[0006] For example, in the driving method provided in at least one embodiment of the present disclosure, the phase difference between the rising edges of every two adjacent clock signals in the multiple clock signals is the unit scan time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each of the clock signals is 40%.

[0007] For example, in the driving method provided by at least one embodiment of the present disclosure, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the length of the charging period is equal to 2 times the unit scanning time, and the length of the pre-charging period is greater than or equal to the unit scanning time.

[0008] For example, in the driving method provided in at least one embodiment of the present disclosure, the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time, the duration of the pre-charging period is 1.2 times the unit scan time, and the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time; the multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive the 8 clock signals respectively; the first-level shift register unit to the fourth-level shift register unit in the N shift register units are connected to the frame start signal.

[0009] For example, in the driving method provided in at least one embodiment of the present disclosure, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels in two adjacent rows are in the on state differ by a unit scanning time. Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state includes: applying the 2k-1 row data signal and the 2k row data signal to the 2k-1 row sub-pixel in the charging period of the 2k-1 row sub-pixel; applying the 2k-1 row data signal and the 2k row data signal to the 2k row sub-pixel in the first pre-charging period of the 2k row sub-pixel and the first half of the charging period of the 2k row sub-pixel, and applying the 2k+1 row data signal and the 2(k+1) row data signal to the 2k row sub-pixel in the second half of the charging period of the 2k row sub-pixel; and applying the 2k-1 row data signal and the 2k row data signal to the 2k+1 row sub-pixel in the first pre-charging period of the 2k+1 row sub-pixel; wherein k=1, 2, 3, ...

[0010] For example, in the driving method provided by at least one embodiment of the present disclosure, the pre-charging period of each row of sub-pixels includes a first pre-charging period, the first pre-charging period is the last unit scan time in the pre-charging period, and the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time. Applying data signals to at least two rows of sub-pixels that are simultaneously in the on state includes: applying one of the 2k-1 row data signal and the 2k row data signal to the 2k-1 row sub-pixels in the second half of the charging period of the 2k-1 row sub-pixels; applying one of the 2k-1 row data signal and the 2k row data signal to the 2k row sub-pixels in the charging period of the 2k row sub-pixels; applying the 2k-1 row data signal and the 2k row data signal to the 2k+1 row sub-pixels in the first half of the first pre-charging period of the 2k+1 row sub-pixels and the 2k+1 row data signal to the 2k+1 row sub-pixels. One of the signals, in the second half of the charging period of the 2k+1th row sub-pixel, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2k+1th row sub-pixel; and in the first pre-charging period of the 2(k+1)th row sub-pixel, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row sub-pixel, and in the charging period of the 2(k+1)th row sub-pixel, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row sub-pixel; wherein, k=1,2,3,…….

[0011] For example, in the driving method provided in at least one embodiment of the present disclosure, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels in two adjacent rows are in the on state differ by a unit scanning time. Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state, including: applying the 6k-5 row data signal to the 6k-5 row sub-pixels in the charging period of the 6k-5 row sub-pixels; applying the 6k-5 row data signal to the 6k-4 row sub-pixels in the first pre-charging period and the first half of the charging period of the 6k-4 row sub-pixels, and applying the 6k-3 row data signal to the 6k-4 row sub-pixels in the second half of the charging period of the 6k-4 row sub-pixels; applying the 6k-5 row data signal to the 6k-3 row sub-pixels in the first pre-charging period of the 6k-3 row sub-pixels, and applying the 6k-3 row data signal to the 6k-3 row sub-pixels in the charging period of the 6k-3 row sub-pixels; applying the 6k-5 row data signal to the 6k-3 row sub-pixels in the first pre-charging period of the 6k-2 row sub-pixels and and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels; in the first pre-charging period of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels; in the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels; wherein, k=1,2,3,….

[0012] For example, in the driving method provided in at least one embodiment of the present disclosure, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scanning time in the pre-charging period, and the start and end times of the periods in which the sub-pixels in two adjacent rows are in the on state differ by a unit scanning time. Applying data signals to at least two rows of sub-pixels that are simultaneously in an on state, including: applying the 6k-4 row data signal to the 6k-5 row sub-pixels in the second half of the charging period of the 6k-5 row sub-pixels; applying the 6k-4 row data signal to the 6k-4 row sub-pixels in the charging period of the 6k-4 row sub-pixels; applying the 6k-4 row data signal to the 6k-3 row sub-pixels in the first pre-charging period and the first half of the charging period of the 6k-3 row sub-pixels, applying the 6k-4 row data signal to the 6k-3 row sub-pixels in the second half of the charging period of the 6k-3 row sub-pixels; applying the 6k-2 row data signal to the 6k-3 row sub-pixels in the first pre-charging period of the 6k-2 row sub-pixels The pixel applies the 6k-4 row data signal, and in the charging period of the 6k-2 row sub-pixel, the 6k-2 row data signal is applied to the 6k-2 row sub-pixel; in the first pre-charging period of the 6k-1 row sub-pixel and the first half of the charging period of the 6k-1 row sub-pixel, the 6k-2 row data signal is applied to the 6k-1 row sub-pixel, and in the second half of the charging period of the 6k-1 row sub-pixel, the 6k row data signal is applied to the 6k-1 row sub-pixel; in the first pre-charging period of the 6k row sub-pixel, the 6k-2 row data signal is applied to the 6k row sub-pixel, and in the charging period of the 6k row sub-pixel, the 6k row data signal is applied to the 6k row sub-pixel; wherein, k=1, 2, 3,….

[0013] For example, the driving method provided by at least one embodiment of the present disclosure also includes: dividing each of a plurality of initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes odd-numbered row data of the initial data frame, and the other includes even-numbered row data of the initial data frame; the plurality of initial data frames include adjacent first initial data frames and second initial data frames; in the first frame, applying the first target data frame corresponding to the first initial data frame to the sub-pixel array; in the second frame, applying the second target data frame corresponding to the first initial data frame to the sub-pixel array; in the third frame, applying the first target data frame corresponding to the second initial data frame to the sub-pixel array; and in the fourth frame, applying the second target data frame corresponding to the second initial data frame to the sub-pixel array.

[0014] For example, the driving method provided by at least one embodiment of the present disclosure also includes: dividing each of a plurality of initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes odd-numbered row data of the initial data frame, and the other includes even-numbered row data of the initial data frame; the plurality of initial data frames include adjacent first initial data frames and second initial data frames; in the first frame, applying the data of the first target data frame corresponding to the first initial data frame to the sub-pixel array; in the second frame, applying the data of the second target data frame corresponding to the first initial data frame to the sub-pixel array; in the third frame, applying the data of the second target data frame corresponding to the second initial data frame to the sub-pixel array; and in the fourth frame, applying the data of the first target data frame corresponding to the second initial data frame to the sub-pixel array.

[0015] For example, the driving method provided by at least one embodiment of the present disclosure also includes: dividing each of the multiple initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes odd-numbered row data of the initial data frame, and the other includes even-numbered row data of the initial data frame; the multiple initial data frames include adjacent first initial data frames and second initial data frames; in the first frame, applying the data of the first target data frame corresponding to the first initial data frame to the sub-pixel array; in the second frame, applying the data of the first target data frame corresponding to the second initial data frame to the sub-pixel array; in the third frame, applying the data of the second target data frame corresponding to the first initial data frame to the sub-pixel array; in the fourth frame, applying the data of the second target data frame corresponding to the second initial data frame to the sub-pixel array.

[0016] For example, in the driving method provided by at least one embodiment of the present disclosure, in the first time period, the nth row of sub-pixels and the n+1th row of sub-pixels are turned on in sequence, where n is an integer and 1≤n≤N-3; in the second time period, the n+2th row of sub-pixels and the n+3th row of sub-pixels are turned on in sequence, and one of the nth row of data signals and the n+1th row of data signals is applied to the nth row of sub-pixels and the n+1th row of sub-pixels, and the length of the second time period is greater than or equal to 2 times the unit scanning time; in the third time period, the nth row of sub-pixels is turned off, and one of the n+2th row of data signals and the n+3th row of data signals is applied to the n+1th row of sub-pixels, the n+2th row of sub-pixels and the n+3th row of sub-pixels.

[0017] For example, in the driving method provided in at least one embodiment of the present disclosure, the duration for which data signals are applied to each row of sub-pixels is greater than the unit scanning time; or, the duration for which data signals are applied to the first row of sub-pixels is equal to the unit scanning time, and the duration for which data signals are applied to each row of sub-pixels except the first row of sub-pixels is greater than the unit scanning time.

[0018] At least one embodiment of the present disclosure further provides a display device, comprising: a sub-pixel array, a gate driving circuit, a source driving circuit, and a timing controller, wherein the sub-pixel array comprises a plurality of sub-pixels arranged in an N×M array, wherein N and M are both integers greater than 1; the gate driving circuit is connected to the sub-pixel array and configured to output a plurality of gate driving signals to the sub-pixel array based on a frame start signal and a plurality of clock signals, and utilize the plurality of gate driving signals to scan the plurality of sub-pixels row by row or at least one row apart, so as to turn on each scanned row of sub-pixels, so that the time length during which the two rows of sub-pixels turned on in sequence are simultaneously in the turned-on state is greater than or equal to 2 times the unit scanning time, wherein the unit scanning time is the time required to scan a row of sub-pixels; the source driving circuit is connected to the plurality of sub-pixels and configured to apply data signals to at least two rows of sub-pixels that are simultaneously in the turned-on state, so that at least some rows of sub-pixels are applied with data signals. The duration of the data signal is greater than the unit scan time; the timing controller is configured to apply the frame start signal and the multiple clock signals to the gate drive circuit; wherein the gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, and the first-level shift register unit in the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-level shift register unit to output a gate drive signal; wherein the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0019] At least one embodiment of the present disclosure further provides an electronic device, comprising the display device described in at least one embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0021] FIG1 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0022] 2A and 2B show exemplary structural diagrams of a gate driving circuit provided by at least one embodiment of the present disclosure;

[0023] FIG3A shows a signal timing diagram of a driving method;

[0024] FIG3B shows a signal timing diagram of another driving method;

[0025] FIG4 shows a flow chart of a driving method according to an embodiment of the present disclosure;

[0026] FIG5 shows a timing diagram of a driving method according to an embodiment of the present disclosure;

[0027] FIG6 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure;

[0028] FIG7 shows a schematic diagram of a frame start signal line and a clock signal line according to an embodiment of the present disclosure;

[0029] FIG8A is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0030] FIG8B is a schematic diagram of extracting odd-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0031] FIG9 is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0032] FIG10 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure;

[0033] FIG11 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure;

[0034] 12A and 12B show exemplary structural diagrams of another gate driving circuit provided by at least one embodiment of the present disclosure;

[0035] FIG13 shows another timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure;

[0036] FIG14 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure;

[0037] FIG15 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure; and

[0038] FIG16 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which the invention belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] FIG1 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure.

[0042] As shown in FIG. 1 , the display device 100 includes a sub-pixel array, which includes a plurality of sub-pixels P arranged in an N×M array, where N and M are both integers greater than 1.

[0043] The display device 100 may further include a gate driver circuit 10, which is connected to a plurality of sub-pixels P. The gate driver circuit 10 may be connected to N rows of sub-pixels via a plurality of gate signal lines extending along a first direction (the x direction in FIG. 1 ), respectively. For example, the gate driver circuit 10 may be connected to the first row of sub-pixels P via a first gate signal line to provide a first gate driver signal G1 to the first row of sub-pixels P, and then connected to the second row of sub-pixels P via a second gate signal line to provide a second gate driver signal G2 to the second row of sub-pixels P, and so on. The first row of sub-pixels P are turned on in response to receiving the first gate driver signal G1, the second row of sub-pixels P are turned on in response to receiving the second gate driver signal G2, and so on.

[0044] In some embodiments, the gate drive circuit 10 can scan N rows of sub-pixels P one by one or more rows. For example, the gate drive circuit 10 can scan one row of sub-pixels at a time, for example, generating N gate drive signals G1, G2, ... GN in sequence to turn on the first row of sub-pixels P, the second row of sub-pixels P ... the Nth row of sub-pixels P in sequence. The gate drive circuit 10 can also scan two or more rows of sub-pixels P at a time. For example, the gate drive circuit 10 can simultaneously generate the first gate drive signal G1 and the second gate drive signal G2 to turn on the first row of sub-pixels P and the second row of sub-pixels P at the same time, then the gate drive circuit 10 can simultaneously generate the third gate drive signal G3 and the fourth gate drive signal G4 to turn on the third row of sub-pixels P and the fourth row of sub-pixels P at the same time, and so on. In some embodiments, the gate drive circuit 10 can scan the N rows of sub-pixels P with at least one row between them to turn on the sub-pixels P in some rows in sequence. For example, the gate driving circuit 10 can turn on the odd-numbered rows of sub-pixels P in sequence (for example, turn on the first row of sub-pixels P, the third row of sub-pixels P, the fifth row of sub-pixels P, and so on), or turn on the even-numbered rows of sub-pixels P in sequence (for example, turn on the second row of sub-pixels P, the fourth row of sub-pixels P, the sixth row of sub-pixels P, and so on).

[0045] The display device 100 may further include a source driver circuit 20, which is connected to a plurality of sub-pixels P. For example, the source driver circuit 20 may be connected to M columns of sub-pixels P via a plurality of data lines extending along a second direction (the y direction in FIG. 1 ). For example, the source driver circuit 20 may be connected to a first column of sub-pixels P via a first data line to provide a first data signal D1 to the first column of sub-pixels P, and may be connected to a second column of sub-pixels P via a second data line to provide a second data signal D2 to the second column of sub-pixels P, and so on.

[0046] For example, when the first row of sub-pixels P is turned on, the source driver circuit 20 can provide M data signals D11, D12, ..., D1M for the first row of sub-pixels P through M data lines; when the second row of sub-pixels P is turned on, the source driver circuit 20 can provide M data signals D21, D22, ..., D2M for the second row of sub-pixels P through multiple data lines, and so on. Of course, the embodiments of the present disclosure are not limited to this, and this will be further described in detail below.

[0047] In some embodiments, the display device 100 may further include a timing controller 30, which is connected to the gate drive circuit 10 and the source drive circuit 20 and may provide relevant control signals to the gate drive circuit 10 and the source drive circuit 20. For example, the timing controller 30 may provide a data control signal TP to the source drive circuit 20, and the source drive circuit 20 may output a data signal for each row under the control of the data control signal TP. The timing controller 30 may also provide other control signals to the source drive circuit 20, including but not limited to a row data start signal, a data synchronization signal, a data inversion signal, and the like. The timing controller 30 may also provide various control signals to the gate drive circuit 10, including but not limited to a frame start signal, a clock signal, and the like required by the gate drive circuit 10.

[0048] 2A and 2B show example structural diagrams of a gate driving circuit provided by at least one embodiment of the present disclosure.

[0049] As shown in Figures 2A and 2B, the gate drive circuit includes multiple stages of cascaded shift register units GOA1, GOA2, ..., GOAN. For example, for a 4K2K (resolution 3840×2160) display panel, the number of horizontal pixels is 3840 and the number of vertical pixels is 2160. If each pixel includes multiple sub-pixels arranged horizontally, the display panel includes 2160 rows of sub-pixels. If the display panel includes 2160 rows of sub-pixels and each shift register unit corresponds to a row of sub-pixels, the gate drive circuit can include 2160 shift register units.

[0050] Figure 2A shows the first through ninth shift register units GOA1 through GOA9. As shown in Figure 2A, STV1 is a frame start signal. When the gate drive circuit is connected to 8 CLKs, the input terminals "Input" of the first through fourth shift register units GOA1 through GOA4 can be connected to the frame start signal terminal STV1. Following the fourth shift register unit GOA4, the input terminal "Input" of the nth shift register unit GOAn is connected to the output terminal of the n-4th shift register unit GOA(n-4), where 5 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of G3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal RST of the nth shift register unit GOAn is connected to the output terminal OUT of the n+4th shift register unit GOA(n+4), where 1 ≤ n ≤ N-4. Figure 2B shows the final shift register unit, GOA2160, and the dummy GOA unit (Dummy GOA). As shown in Figure 2B, the last four rows of GOAs can be reset using four rows of Dummy GOAs. For example, Dummy GOA1 (Dum1) resets GOA2157, Dummy GOA 2 (Dum2) resets GOA2158, and so on. Each Dummy GOA can be reset using STV1. STV0 is the total reset signal, connected to GOA9 and subsequent units. The waveforms of STV0 and STV1 are identical, so they can be connected together externally.

[0051] The gate drive circuit shown in Figures 2A and 2B uses eight clock signals CLK1 to CLK8, wherein the clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth-stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar manner, the ninth to sixteenth-stage shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0052] Each stage of shift register units GOA1, GOA2, ..., GOAN can generate an output signal at its output terminal OUT as a gate drive signal (or gate scan signal) under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first stage of shift register unit GOA1 generates a first gate drive signal G1, the second stage of shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one stage of shift register unit can be shifted relative to the gate drive signal generated by another stage of shift register unit.

[0053] The above is merely an example of a display device according to an embodiment of the present disclosure. The structure of the display device according to the embodiment of the present disclosure is not limited thereto and may have other structures as needed. For example, the display device may be a display device based on liquid crystal display (LCD) technology or a display device based on organic light emitting diode (OLED) display technology. The gate drive circuit of the display device may adopt a cascade method different from that shown in Figures 2A and 2B. For example, 10 or 12 clock signals may be cascaded in a different manner.

[0054] Fig. 3A shows a signal timing diagram of a driving method. The signal timing diagram of Fig. 3A is explained below by taking the display device of Fig. 1, Fig. 2A and Fig. 2B as an example.

[0055] As shown in FIG3A , in each frame, the gate drive circuit 10 sequentially generates a first gate drive signal G1, a second gate drive signal G2, a third gate drive signal G3, a fourth gate drive signal G4, and so on, at predetermined time intervals. This time interval is referred to as a unit scan time H, which is the time required to scan a row of sub-pixels, i.e., the time interval between generating gate drive signals for one row of sub-pixels and generating gate drive signals for the next row of sub-pixels. In FIG3A , the active level duration of each gate drive signal is, for example, 4 hours.

[0056] For the first row of sub-pixels, during periods T1 to T4, the first gate drive signal G1 is at a high level, causing the first row of sub-pixels to be in the on state. The lengths of periods T1 to T4 are all H, meaning the first sub-pixels are on for 4 hours. During period T4, the first high-level pulse of the data control signal TP arrives, thereby controlling the source driver circuit 20 to apply the data signal DATA1 for the first row of sub-pixels (also referred to as the first row data signal) to the first row of sub-pixels in the on state. The first row data signal DATA1 may include M data signals D11, D12, ..., D1M, respectively, for the M sub-pixels in the first row, where data signal D11 is provided to the first row, first column sub-pixel, data signal D12 is provided to the second row, ..., and data signal D1M is provided to the Mth column sub-pixel in the first row.

[0057] Similarly, for the second row of sub-pixels, during periods T2 to T5, the second gate drive signal G2 is at a high level, turning on the second row of sub-pixels. During period T5, a second high-level pulse of the data control signal TP arrives, thereby controlling the source driver circuit 20 to apply data signals (also referred to as second-row data signals) DATA2 for the second row of sub-pixels to the turned-on second row of sub-pixels. The second-row data signals DATA2 may include M data signals D21, D22, ..., D2M, respectively, for the M sub-pixels in the second row, where data signal D21 is provided to the sub-pixel in the first column of the second row, data signal D22 is provided to the sub-pixel in the second column of the second row, ..., and data signal D2M is provided to the sub-pixel in the Mth column of the second row. The same applies to the sub-pixels in other rows.

[0058] Figure 3B shows a signal timing diagram of another driving method. As shown in Figure 3B, the effective level duration of each gate drive signal is, for example, 3.2 hours, so that each row of sub-pixels is in the on state for 3.2 hours, but the time for writing data signals to each row of sub-pixels is 1 hour, that is, the actual charging time is 1 hour.

[0059] From the above two examples, it can be seen that for each row of sub-pixels, although the duration of each row of sub-pixels being turned on is multiple times the unit scan time, the length of time that the data signal is written to each row of sub-pixels (also known as the actual charging duration) is only one time the unit scan time H. Taking an 8K display device with a resolution of 7680×4320 as an example, when the refresh rate is 60Hz, the scan time for one frame is 1 / 60 second, that is, the time it takes to scan 4320 rows of sub-pixels is 1 / 60 second, then the time it takes to scan each row of sub-pixels (i.e., the unit scan time) H = 1 / 60 ÷ 4320 ≈ 3.7us. When the refresh rate is 120Hz, the unit scan time H is 1.85us, which is too short to fully charge the sub-pixels, thus affecting the display.

[0060] In addition, in some embodiments, the frame start signal line STV1, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5 and the sixth clock signal line CLK6 are arranged in sequence in a first direction (e.g., horizontally). Due to the long distance between these signal lines, capacitance may be formed between adjacent signal lines. A capacitance may be formed between the start pulse signal line STV1 and the first clock signal line CLK1; similarly, a capacitance may be formed between the first clock signal line CLK1 and the second clock signal line CLK2, and a capacitance may be formed between the second clock signal line CLK2 and the third clock signal line CLK3, and so on. A CLK signal may cause adjacent CLK signals to be disturbed during the process of pulling up or pulling down. For example, the falling edge of the clock signal CLK1 may cause a pull-down disturbance to the clock signal CLK2. Accordingly, the gate drive signal G2 corresponding to the clock signal CLK2 is also subjected to a pull-down disturbance during the charging cycle, resulting in the charging time of the second row of sub-pixels being affected.

[0061] When the falling edge of the frame start signal STV1 is aligned with the falling edge of the clock signal CLK1, or when the falling edge of the frame start signal STV1 is earlier than the falling edge of the clock signal CLK1 and the phase difference between the two falling edges is large, the output signal (gate drive signal) corresponding to the first clock signal line CLK1 will not be disturbed by the frame start signal line STV1 during the charging cycle, or the disturbance is very small. In addition, the falling edges of other clock signals are later than the falling edge of the clock signal CLK1. Therefore, the output signal corresponding to the first clock signal line CLK1 will not be disturbed by other clock signals during the charging cycle. Since the output signal corresponding to the first clock signal line CLK1 is not disturbed by other signals during the charging cycle, the charging rate of the pixels in the corresponding row is normal. However, the output signals corresponding to the second clock signal line CLK2 to the eighth clock signal line CLK8 are disturbed during the charging cycle, so the charging rate of the pixels in the corresponding row is low. The waveforms of the gate drive signals corresponding to clock signal CLK1 and clock signals CLK2-CLK8 differ. From a macroscopic perspective, this can cause periodic horizontal fine lines to appear on the display panel, with eight rows of sub-pixels forming one cycle. Consequently, the display screen exhibits horizontal lines. Therefore, balancing the disturbances experienced by each clock signal is a critical issue.

[0062] At least one embodiment of the present disclosure provides a method for driving a display device, comprising: applying a frame start signal and a plurality of clock signals to a gate drive circuit so that the gate drive circuit outputs a plurality of gate drive signals to a sub-pixel array based on the frame start signal and the plurality of clock signals, wherein the sub-pixel array includes a plurality of sub-pixels arranged in an N×M array; scanning the sub-pixel array one row or multiple rows by one using the plurality of gate drive signals so as to turn on the sub-pixels in each scanned row, such that the time duration during which two adjacent rows of sub-pixels are simultaneously in an on state is greater than or equal to twice a unit scan time, where the unit scan time is the time required to scan a row of sub-pixels, wherein N and M are both integers greater than 1; and applying a data signal to at least two rows of sub-pixels that are simultaneously in an on state, such that The duration for which data signals are applied to at least some rows of sub-pixels is greater than the unit scan time; wherein, the gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, and the first shift register unit among the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first shift register unit to output a gate drive signal; wherein, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is no later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0063] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned driving method.

[0064] The driving method provided by the embodiments of the present disclosure applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, ensuring that the duration of the data signal applied to each row of sub-pixels is greater than the unit scanning time. Furthermore, this method can balance the interference experienced by the clock signal CLK1 and subsequent clock signals, improve the phenomenon of horizontal stripes, and achieve better display effects.

[0065] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0066] Fig. 4 shows a flow chart of a method for driving a display device according to an embodiment of the present disclosure. As shown in Fig. 4 , the method includes steps S401 to S403.

[0067] Step S401: the timing controller applies a frame start signal and multiple clock signals to the gate driving circuit;

[0068] Step S402: The gate drive circuit outputs multiple gate drive signals to the subpixel array based on the frame start signal and multiple clock signals. The gate drive circuit uses the multiple gate drive signals to scan the subpixel array row by row or multiple rows, turning on the subpixels in each scanned row, such that the duration that two adjacent rows of subpixels are simultaneously turned on is greater than or equal to twice the unit scan time. For example, the unit scan time is the time required to scan a row of subpixels. The subpixel array includes multiple subpixels arranged in an N×M array, where N and M are both integers greater than 1.

[0069] Step S403: the source driving circuit applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, so that the duration for which the data signals are applied to at least some rows of sub-pixels is greater than the unit scanning time.

[0070] For example, the multiple clock signals may include 8 clock signals. The N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive 8 clock signals respectively. For example, the gate drive circuit, frame start signal, clock signal, gate drive signal, data signal, etc. can be referred to Figures 1, 2A and 2B for the above-mentioned related description, and will not be repeated here.

[0071] For example, in the first time period, the nth row of sub-pixels and the n+1th row of sub-pixels are turned on in sequence, where n is an integer and 1≤n≤N-3; in the second time period, the n+2th row of sub-pixels and the n+3th row of sub-pixels are turned on in sequence, and one of the nth row of data signals and the n+1th row of data signals is applied to the nth row of sub-pixels and the n+1th row of sub-pixels, and the length of the second time period is greater than or equal to 2 times the unit scanning time; in the third time period, the nth row of sub-pixels is turned off, and one of the n+2th row of data signals and the n+3th row of data signals is applied to the n+1th row of sub-pixels, the n+2th row of sub-pixels and the n+3th row of sub-pixels.

[0072] FIG5 shows a timing diagram of a driving method according to an embodiment of the present disclosure.

[0073] During time period T1 (first time period), the first row of sub-pixels and the second row of sub-pixels are sequentially turned on. For example, during a first sub-period T11 of the first time period T1, the first gate drive signal G1 is at a high level, thereby turning on the first row of sub-pixels; and during a second sub-period T12 of the first time period T1, the second gate drive signal G2 is at a high level, thereby turning on the second row of sub-pixels.

[0074] In period T2 (second period), the third row of sub-pixels and the fourth row of sub-pixels are sequentially turned on, and data signals are applied to the first row of sub-pixels and the second row of sub-pixels. For example, upon the arrival of the first high-level pulse of the data control signal TP, the source driver circuit 20 applies one of the first row of data signals DATA1 and the second row of data signals DATA2 (in this embodiment, the first row of data signals DATA1) to the first row of sub-pixels and the second row of sub-pixels.

[0075] In period T3 (third period), the first row of sub-pixels is turned off, and data signals are applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels. For example, upon the arrival of the second high-level pulse of the data control signal TP, one of the third row of data signal DATA3 and the fourth row of data signal DATA4 is applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels that are in the turned-on state.

[0076] Similarly, for the third and fourth rows of sub-pixels, the first period is period T2 in FIG. 5 , the second period is periods T3 and T4 in FIG. 5 , and the third period is period T5 in FIG. During period T2, the third and fourth rows of sub-pixels are sequentially turned on. For example, during the first sub-period T21 of period T2, the third gate drive signal G3 is at a high level, thereby turning on the third row of sub-pixels. During the second sub-period T22 of period T2, the fourth gate drive signal G4 is at a high level, thereby turning on the fourth row of sub-pixels. During periods T3 and T4, the fifth and sixth rows of sub-pixels are sequentially turned on, and one of the third row data signal DATA3 and the fourth row data signal DATA4 is applied to the third and fourth rows of sub-pixels. During period T5, the third row of sub-pixels is turned off, and one of the fifth row data signal DATA5 and the sixth row data signal DATA6 is applied to the fourth, fifth, and sixth rows of sub-pixels.

[0077] The length of the second time period can be set to be greater than or equal to 2H, so that the length of time that the data signal is applied to each row of sub-pixels is greater than or equal to 2H. For example, in the example of Figure 5, the time period in which the data signal is applied to the sub-pixels in the first row is time period T2, and the time period in which the data signal is applied to the sub-pixels in the second row is time periods T2 and T3. The lengths of time periods T1 and T2 can be set to 2H, and the length of time period T3 can be set to H. In this case, the actual charging time of the sub-pixels in the first row is 2H (the length of time period T2), and the actual charging time of the sub-pixels in the second row is 3H (the sum of the lengths of time periods T2 and T3). Similarly, the actual charging time of the sub-pixels in the third row is 2H, and the actual charging time of the sub-pixels in the fourth row is 3H.

[0078] In the embodiments of the present disclosure, by sequentially turning on two rows of sub-pixels and applying data signals to the two rows of sub-pixels that are simultaneously turned on, the actual charging time of some sub-pixels (e.g., the sub-pixels in the odd rows) can be 2 hours or longer, while the actual charging time of another portion of sub-pixels (e.g., the sub-pixels in the even rows) can be 3 hours or longer. For example, the data written to the sub-pixels in the even rows may be the data of the two adjacent pixels in the odd rows.

[0079] For example, the gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, wherein the N shift register units include a first-stage shift register unit (e.g., GOA1) connected to the first row of sub-pixels in the sub-pixel array. The multiple clock signals include a first clock signal (e.g., CLK1) for driving the first-stage shift register unit to output a gate drive signal. For example, in the disclosed embodiment, the shift register unit connected to the first row of sub-pixels is referred to as the first-stage shift register unit.

[0080] FIG6 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0081] As shown in Figure 6, the rising edge of the frame start signal STV is earlier than the rising edge of the first clock signal CLK1, and the falling edge of the frame start signal STV is no later than the falling edge of the first clock signal CLK1. The phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time. Based on this setting, display defects can be improved and a better display effect can be achieved.

[0082] FIG7 shows a schematic diagram of a frame start signal line and a clock signal line according to an embodiment of the present disclosure.

[0083] As shown in Figures 6 and 7, if the falling edge of the frame start signal line STV is aligned with the falling edge of the clock signal line CLK1, then the frame start signal line STV will not cause pull-down interference to the clock signal CLK1 when it is pulled down. The width of the frame start signal line STV is greater than the width of the clock signal line CLK, so the resistance of the frame start signal line STV is greater than the resistance of the clock signal line CLK. When the falling edge of the frame start signal line STV is earlier than the falling edge of the clock signal line CLK1, and the phase difference between the falling edge of the frame start signal line STV and the falling edge of the clock signal line CLK1 is, for example, 1 hour or greater, the falling edge of the frame start signal STV when it is pulled down is relatively slow, thereby having a smaller impact on the clock signal line CLK1 and not being balanced with the interference to the clock signals CLK2 and subsequent thereto. In the embodiment of the present disclosure, the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is set to 0.2H~0.6H. In this way, the frame start signal STV can have a greater pull-down effect on the clock signal CLK1, thereby balancing the interference of the clock signal CLK1 and the clock signals thereafter, improving the phenomenon of poor horizontal stripes, and achieving a better display effect.

[0084] For example, the first-stage shift register unit to the P-th-stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals also include the P-th clock signal for driving the P-th-stage shift register unit to output a gate drive signal; the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and the phase difference and duty cycle are configured so that the falling edge of the frame start signal is aligned with the rising edge of the P-th clock signal, and P is an integer greater than 1.

[0085] For example, the value of P is related to the number of clock signals connected to the gate drive circuit. When the gate drive circuit is connected to an 8CLK signal, P is 4; when the gate drive circuit is connected to a 12CLK signal, P is 6.

[0086] For example, if the frame revelation signal STV is connected to the first through fourth shift register units, the P-th shift register unit is the fourth shift register unit. Setting the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 to 0.2H to 0.6H, setting the duty cycle of the clock signal to 40% to 45%, and coordinating the phase difference and duty cycle so that the falling edge of the frame start signal is aligned with the rising edge of the fourth clock signal CLK4 can further improve display defects and achieve a better display effect.

[0087] For example, in some embodiments, the phase difference between the rising edges of each two adjacent clock signals in the plurality of clock signals is a unit scan time H, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%. For example, as shown in FIG6 , the high-level duration t1 of the frame start signal STV is 8 hours, the high-level duration t3 of each clock signal CLK is 3.2 hours, and the cycle time t4 of the clock signal CLK is 8 hours, so the duty cycle of the clock signal is 3.2 / 8 = 40%. The phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the clock signal CLK1 is 5 hours, the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2 hours, and the start and end times of the clock signals CLK differ by t5 by 1 hour. The rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. That is to say, when the phase difference between the clock signals is 1H, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2H and the duty cycle of the clock signal is 40%, the rising edge of the clock signal CLK4 can be aligned with the falling edge of the frame start signal STV.

[0088] For example, in some other embodiments, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.3H, the duty cycle of the clock signal is set to 3.3 / 8=41.25%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.4H, the duty cycle of the clock signal is set to 3.4 / 8=42.5%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.6H, the duty cycle of the clock signal is set to 3.6 / 8=45%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV.

[0089] For example, when the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV, when the frame start signal STV ends, the clock signal CLK4 immediately starts to rise, generating a second-order PU, fully controlling the GOA output, and avoiding leakage of the PU point in the shift register unit, so that each sub-pixel can achieve a better charging effect.

[0090] For example, setting the clock signal's duty cycle to 40% to 45% can also improve poor display in some situations. The clock signal's duty cycle is typically 50%, but when the duty cycle is 50%, poor display may occur due to in-plane coupling and other factors. The disclosed embodiments set the duty cycle to 40% to 45%, which can address poor display in this situation.

[0091] For example, each of the multiple initial data frames can be divided into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any initial data frame includes odd-numbered row data of the initial data frame, and the other includes even-numbered row data of the initial data frame.

[0092] Figure 8A is a schematic diagram of extracting even-numbered rows of data from an initial data frame provided by at least one embodiment of the present disclosure. Figure 8B is a schematic diagram of extracting odd-numbered rows of data from an initial data frame provided by at least one embodiment of the present disclosure. As shown in Figures 8A and 8B, the odd-numbered rows of data from an initial data frame can be extracted to form a first target data frame, and the even-numbered rows of data from the initial data frame can be extracted to form a second target data frame. Alternatively, the odd-numbered rows of data from an initial data frame can be extracted to form a second target data frame, and the even-numbered rows of data from the initial data frame can be extracted to form a first target data frame. By decomposing a data frame into odd frames and even frames, and using the time originally used to display one frame of data to display two frames of data, the refresh rate of the display panel can be increased, thereby improving the display effect. For ease of description, in some of the following embodiments, odd frames and even frames are used to represent the first target data frame and the second target data frame.

[0093] For example, the multiple initial data frames include a first initial data frame and a second adjacent initial data frame. In the first frame, a first target data frame corresponding to the first initial data frame is applied to the subpixel array; in the second frame, a second target data frame corresponding to the first initial data frame is applied to the subpixel array; in the third frame, the first target data frame corresponding to the second initial data frame is applied to the subpixel array; and in the fourth frame, the second target data frame corresponding to the second initial data frame is applied to the subpixel array. In this manner, the first target data frame and the second target data frame are displayed alternately.

[0094] Figure 9 is a schematic diagram of extracting even-numbered row data of an initial data frame provided by at least one embodiment of the present disclosure. As shown in Figure 9, in Mode 1 and Mode 2, the first target data frame and the second target data frame are displayed alternately. The first initial data frame is an odd frame b1 and an even frame c1, the second initial data frame is an odd frame b2 and an even frame c2, the third initial data frame is an odd frame b3 and an even frame c3, and so on. In Mode 1, the odd frame b can be displayed first, and then the even frame c can be displayed, for example, in the order of b1~c1~b2~c2~b3~c3... In Mode 2, the even frame c can be displayed first, and then the odd frame b can be displayed, for example, in the order of c1~b1~c2~b2~c3~b3...

[0095] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the fourth frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0096] For example, as shown in FIG9 , in modes 3 and 4, the odd and even frames corresponding to each initial data frame are displayed continuously, and two adjacent odd frames are displayed continuously, and two adjacent even frames are displayed continuously. In mode 3, they are displayed in the order of b1 to c1 to c2 to b2 to b3 to c3… In mode 4, they are displayed in the order of c1 to b1 to b2 to c2 to c3 to b3… The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0097] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the fourth frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0098] For example, as shown in FIG9 , in modes 5 and 6, the odd frames of two adjacent initial data frames are displayed continuously, and the even frames of two adjacent initial data frames are displayed continuously, and the odd and even frames corresponding to each initial data frame are separated. In mode 5, the sequence of b1 to b2 to c1 to c2 to b3 to b4… is displayed. In mode 6, the sequence of c1 to c2 to b1 to b2 to c3 to c4… is displayed. The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0099] For example, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the length of the charging period is equal to 2 times the unit scanning time, and the length of the pre-charging period is greater than or equal to the unit scanning time.

[0100] For example, the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time, the duration of the pre-charging period is 1.2 times the unit scan time, and the start and end times of the periods of sub-pixels in the on state in two adjacent rows differ by a unit scan time.

[0101] FIG10 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure. In FIG10 , the period during which each row of sub-pixels is in an on state (the corresponding gate drive signals, such as G1-G6, are at a high level) includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in FIG10 , the duration during which each row of sub-pixels is in an on state is 3.2H, wherein the first 1.2H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0102] For example, in some embodiments, as shown in FIG10 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be: in the charging period of the 2k-1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k-1 row sub-pixel; in the first pre-charging period of the 2k row sub-pixel and the first half of the charging period of the 2k row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k row sub-pixel, and in the second half of the charging period of the 2k row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k row sub-pixel; and in the first pre-charging period (or the entire pre-charging period) of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; where k=1, 2, 3,…

[0103] For example, as shown in Figure 10, when displaying odd frames, in the charging period of the 1st row of sub-pixels, the 1st row of data signals are applied to the 1st row of sub-pixels; in the first pre-charging period and the first half of the charging period of the 2nd row of sub-pixels, the 1st row of data signals are applied to the 2nd row of sub-pixels, and in the second half of the charging period of the 2nd row of sub-pixels, the 3rd row of data signals are applied to the 2nd row of sub-pixels; in the first pre-charging period (or the entire pre-charging period) of the 3rd row of sub-pixels, the 1st row of data signals are applied to the 3rd row of sub-pixels, and in the charging period of the 3rd row of sub-pixels, the 3rd row of data signals are applied to the 3rd row of sub-pixels; and so on.

[0104] For example, in a specific embodiment, as shown in FIG10 , the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time H (i.e., 3.2H), of which the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging period of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging period of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving mode can be:

[0105] In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels;

[0106] In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels;

[0107] In the first pre-charging period (or the entire pre-charging period) of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charging period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels;

[0108] In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels;

[0109] In the first pre-charging period (or the entire pre-charging period) of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels;

[0110] In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels;

[0111] Among them, k = 1, 2, 3, ...

[0112] Figure 11 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure. In Figure 11, the period in which each row of sub-pixels is in the on state 1 includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 11, the duration of each row of sub-pixels in the on state is 3.2H, wherein the first 1.2H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H.

[0113] For example, in some embodiments, as shown in FIG11 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0114] In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0115] In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels;

[0116] In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels;

[0117] In the first pre-charging period (or the entire pre-charging period) of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charging period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels;

[0118] Among them, k = 1, 2, 3, ...

[0119] For example, in some examples, as shown in Figure 11, when displaying an even frame, in the second half of the charging period of the first row of sub-pixels, the second row of data signals are applied to the first row of sub-pixels; in the charging period of the second row of sub-pixels, the second row of data signals are applied to the second row of sub-pixels; in the first pre-charging period and the first half of the charging period of the third row of sub-pixels, the second row of data signals are applied to the third row of sub-pixels, and in the second half of the charging period of the third row of sub-pixels, the fourth row of data signals are applied to the third row of sub-pixels; in the first pre-charging period (or the entire pre-charging period) of the fourth row of sub-pixels, the second row of data signals are applied to the fourth row of sub-pixels, and in the charging period of the fourth row of sub-pixels, the fourth row of data signals are applied to the fourth row of sub-pixels; and so on.

[0120] For example, in a specific embodiment, as shown in FIG11 , the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time H (i.e., 3.2H), of which the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scan time H; accordingly, the start and end times of the pre-charging period of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging period of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving mode can be:

[0121] In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels;

[0122] In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels;

[0123] In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels;

[0124] In the first pre-charging period (or the entire pre-charging period) of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels;

[0125] In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels;

[0126] In the first pre-charging period (or the entire pre-charging period) of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels;

[0127] Among them, k = 1, 2, 3, ...

[0128] In the above embodiment, pre-charging can achieve charging boost because the data signal hardly needs to consider the rising delay and the difference between the data signals of two adjacent rows is small, so the image quality of the display device is good.

[0129] For example, in the above embodiment, the duration for which the data signal is applied to each row of sub-pixels is greater than the unit scan time; or, the duration for which the data signal is applied to the first row of sub-pixels is equal to the unit scan time, and the duration for which the data signal is applied to each row of sub-pixels except the first row of sub-pixels is greater than the unit scan time.

[0130] It should be understood that in the embodiments of the present disclosure, the charging period and the pre-charging period are intended to distinguish between two different (sub) periods in the period when each row of sub-pixels is in the on state. Part or all of the pre-charging period of a row or several rows of sub-pixels may not undergo pre-charging operations, and the first half of the charging period of the first row of sub-pixels may not undergo charging operations.

[0131] The embodiments of the present disclosure turn on each row of sub-pixels in sequence and apply data signals to each row of sub-pixels that are in the turned-on state at the same time, so that the actual charging time of some sub-pixels (the total time of the pre-charging period and the charging period) can reach 2H or more.

[0132] In some embodiments, a portion of sub-pixels and another portion of sub-pixels may be driven in different ways in different frames, so that the actual charging time of each sub-pixel in at least one frame is greater than the unit scanning time.

[0133] In the above embodiments, the gate driving circuit is described as being connected to 8 CLK signals. In other embodiments, the gate driving circuit may be connected to 12 CLK signals. This case will be described below.

[0134] 12A and 12B show example structural diagrams of another gate driving circuit provided by at least one embodiment of the present disclosure.

[0135] FIG12A shows the first through thirteenth shift register units GOA1 through GOA13. As shown in FIG12A , STV1 is a frame start signal. When the gate drive circuit is connected to 12 CLKs, the input terminals "Input" of the first through sixth shift register units GOA1 through GOA6 can be connected to the frame start signal terminal STV1. Following the sixth shift register unit GOA4, the input terminal "Input" of the nth shift register unit GOAn is connected to the output terminal of the n-6th shift register unit GOA(n-4), where 7 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA7, the output of GOA2 is connected to the input of GOA8, the output of G3 is connected to the input of GOA9, the output of G4 is connected to the input of GOA10, the output of G5 is connected to the input of GOA11, and so on. The reset terminal RST of the nth shift register unit GOAn is connected to the output terminal OUT of the n+6th shift register unit GOA(n+6), where 1 ≤ n ≤ N-6. FIG12B shows the last stage of shift register unit GOA4320 and dummy shift register unit (Dummy GOA). As shown in FIG12B , the last six rows of GOAs can be reset by six rows of Dummy GOAs, for example, Dummy GOA1 (Dum1) resets GOA4315, Dummy GOA 2 (Dum2) resets GOA4316, and so on, and each Dummy GOA can be reset by STV1.

[0136] The gate drive circuit shown in Figures 12A and 12B uses 12 clock signals CLK1 to CLK8, wherein the clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the 12th-stage shift register unit GOA12 is connected to receive the 12th clock signal CLK12. In a similar manner, the 13th to 24th-stage shift register units GOA13 to GOA24 are connected to receive the first to twelfth clock signals CLK1 to CLK12, respectively.

[0137] Each stage of shift register units GOA1, GOA2, ..., GOAN can generate an output signal at its output terminal OUT as a gate drive signal (or gate scan signal) under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first stage of shift register unit GOA1 generates a first gate drive signal G1, the second stage of shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one stage of shift register unit can be shifted relative to the gate drive signal generated by another stage of shift register unit.

[0138] For example, the GOA cascade relationship with a period of 12CLK can be applied to 8K4K products, referred to as 8K.

[0139] FIG13 shows another timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0140] As shown in Figure 13, the high-level duration t1 of the frame start signal STV is 9 hours, the high-level duration t3 of the clock signal CLK is 5 hours, the cycle time t4 of the clock signal CLK is 12 hours, the phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is 4 hours, the phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0 hours, and the phase difference T5 of each clock signal CLK is 1 hour. The duty cycle of the clock signal CLK is 41.6%, which is mainly selected to consider in-plane signal coupling or display defects. The phase difference between the falling edge of STV and the falling edge of CLK1 is 0 hours. Because STV is connected to the first 6 CLKs and generates a first-order PU level, the falling edge of STV is aligned with the rising edge of CLK6. That is, after STV ends, CLK immediately starts to rise, generating a second-order PU, fully controlling the GOA output and avoiding leakage at the PU point.

[0141] Figure 14 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 14, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 14, the duration of each row of sub-pixels in the on state is 5H, wherein the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0142] For example, in some embodiments, as shown in FIG14 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0143] In a charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0144] In the first precharge period of the 2kth row of sub-pixels and the first half of the charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels, and in the second half of the charging period of the 2kth row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2kth row of sub-pixels;

[0145] In the first precharge period of the 2k+1th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2k+1th row of sub-pixels; wherein k=1, 2, 3, . . .

[0146] For example, in a specific embodiment, as shown in FIG14 , the driving mode may be:

[0147] In a charging period of the 6k-5th row of sub-pixels, applying the 6k-5th row of data signals to the 6k-5th row of sub-pixels;

[0148] In the first pre-charging period of the 6k-4th row of sub-pixels and the first half of the charging period of the 6k-4th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-4th row of sub-pixels, and in the second half of the charging period of the 6k-4th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-4th row of sub-pixels;

[0149] In the first pre-charging period of the 6k-3th row of sub-pixels, the 6k-5th row of data signals are applied to the 6k-3th row of sub-pixels, and in the charging period of the 6k-3th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-3th row of sub-pixels;

[0150] In the first pre-charging period of the 6k-2th row of sub-pixels and the first half of the charging period of the 6k-2th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-2th row of sub-pixels, and in the second half of the charging period of the 6k-2th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-2th row of sub-pixels;

[0151] In the first pre-charging period of the 6k-1th row of sub-pixels, the 6k-3th row of data signals are applied to the 6k-1th row of sub-pixels, and in the charging period of the 6k-1th row of sub-pixels, the 6k-1th row of data signals are applied to the 6k-1th row of sub-pixels;

[0152] In the first pre-charging period of the 6kth row of sub-pixels and the first half of the charging period of the 6kth row of sub-pixels, the 6k-1th row of data signals are applied to the 6kth row of sub-pixels, and in the second half of the charging period of the 6kth row of sub-pixels, the 6k+1th row of data signals are applied to the 6kth row of sub-pixels;

[0153] Among them, k = 1, 2, 3, ...

[0154] Figure 15 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 15, the period in which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to 2 times the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 15, the duration of each row of sub-pixels in the on state is 5H, wherein the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, and the duration of the first pre-charging period is equal to the unit scan time H. For example, the first pre-charging period is a period before the charging period and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0155] For example, in some embodiments, as shown in FIG15 , the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H. In this case, the driving mode may be:

[0156] In the second half of the charging period of the 2k-1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k-1th row of sub-pixels;

[0157] In a charging period of the 2kth row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row of sub-pixels;

[0158] In the first precharge period of the 2k+1th row of sub-pixels and the first half of the charging period of the 2k+1th row of sub-pixels, one of the 2k-1th row of data signals and the 2kth row of data signals is applied to the 2k+1th row of sub-pixels, and in the second half of the charging period of the 2k+1th row of sub-pixels, one of the 2k+1th row of data signals and the 2(k+1)th row of data signals is applied to the 2k+1th row of sub-pixels;

[0159] In the first pre-charging period (or the entire pre-charging period) of the 2(k+1)th row of sub-pixels, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2(k+1)th row of sub-pixels, and in the charging period of the 2(k+1)th row of sub-pixels, one of the 2k+1th row data signal and the 2(k+1)th row data signal is applied to the 2(k+1)th row of sub-pixels;

[0160] Among them, k = 1, 2, 3, ...

[0161] For example, in a specific embodiment, as shown in FIG15 , the driving mode may be:

[0162] In the second half of the charging period of the 6k-5th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-5th row of sub-pixels;

[0163] In a charging period of the 6k-4th row of sub-pixels, applying the 6k-4th row of data signals to the 6k-4th row of sub-pixels;

[0164] In the first pre-charging period of the 6k-3th row of sub-pixels and the first half of the charging period of the 6k-3th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-3th row of sub-pixels, and in the second half of the charging period of the 6k-3th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-3th row of sub-pixels;

[0165] In the first pre-charging period (or the entire pre-charging period) of the 6k-2th row of sub-pixels, the 6k-4th row of data signals are applied to the 6k-2th row of sub-pixels, and in the charging period of the 6k-2th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-2th row of sub-pixels;

[0166] In the first pre-charging period of the 6k-1th row of sub-pixels and the first half of the charging period of the 6k-1th row of sub-pixels, the 6k-2th row of data signals are applied to the 6k-1th row of sub-pixels, and in the second half of the charging period of the 6k-1th row of sub-pixels, the 6kth row of data signals are applied to the 6k-1th row of sub-pixels;

[0167] In the first pre-charging period (or the entire pre-charging period) of the 6kth row of sub-pixels, the 6k-2th row of data signals are applied to the 6kth row of sub-pixels, and in the charging period of the 6kth row of sub-pixels, the 6kth row of data signals are applied to the 6kth row of sub-pixels;

[0168] Among them, k = 1, 2, 3, ...

[0169] In the above embodiment, pre-charging can achieve charging boost because the data signal hardly needs to consider the rising delay and the difference between the data signals of two adjacent rows is small, so the image quality of the display device is good.

[0170] At least one embodiment of the present disclosure further provides a display device. Referring to FIG1 , the display device includes a sub-pixel array, a gate driving circuit, a source driving circuit, and a timing controller.

[0171] The sub-pixel array includes a plurality of sub-pixels arranged in an N×M array, where N and M are both integers greater than 1.

[0172] The timing controller is configured to apply the frame start signal and the plurality of clock signals to the gate driving circuit.

[0173] The gate drive circuit is connected to the sub-pixel array and is configured to output multiple gate drive signals to the sub-pixel array based on a frame start signal and multiple clock signals, and use the multiple gate drive signals to scan multiple sub-pixels row by row or with at least one row interval to turn on each scanned row of sub-pixels, so that the time length during which two rows of sub-pixels turned on in sequence are simultaneously in the on state is greater than or equal to 2 times the unit scan time, where the unit scan time is the time required to scan a row of sub-pixels.

[0174] The source driving circuit is connected to multiple sub-pixels and is configured to apply data signals to at least two rows of sub-pixels that are simultaneously in an on state, so that the time duration for which the data signals are applied to at least some rows of sub-pixels is greater than the unit scanning time.

[0175] The gate drive circuit includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, and the first-stage shift register unit among the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal; the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is no later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0176] Regarding the display device, please refer to the above related description, which will not be repeated here.

[0177] At least one embodiment of the present disclosure further provides an electronic device. Figure 16 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. As shown in Figure 16, the electronic device 1 may include a display device 100. In addition, the electronic device 1 may also include components such as a processor. The display device 100 can refer to the display device in the above embodiment and will not be described in detail here.

[0178] For example, the electronic device 1 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or a combination of any electronic device and hardware, which is not limited in the embodiments of the present disclosure.

[0179] It should be noted that for the sake of clarity and brevity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art may provide and configure other components not shown according to specific needs, and the embodiments of the present disclosure are not limited thereto.

[0180] For the relevant description and technical effects of the electronic device 1 , reference may be made to the relevant description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be repeated here.

[0181] There are a few points to note:

[0182] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0183] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0184] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A driving method of a display device, wherein, The display device includes a timing controller, a gate driving circuit, and a source driving circuit. The method includes: The timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit; The gate driving circuit outputs a plurality of gate driving signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and uses the plurality of gate driving signals to scan the sub-pixel array row by row or multiple rows by multiple rows to turn on the sub-pixels in each scanned row, so that the duration for which adjacent two rows of sub-pixels are simultaneously in the on state is greater than or equal to 2 times the unit scanning time, where the unit scanning time is the time required to scan one row of sub-pixels. Herein, the sub-pixel array includes a plurality of sub-pixels arranged in an N×M array, and both N and M are integers greater than 1; and The source driving circuit applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, so that the duration for which at least some rows of sub-pixels are applied with data signals is greater than the unit scanning time; Wherein, the gate driving circuit includes N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, and the N shift register units include a first-stage shift register unit connected to the first row of sub-pixels in the sub-pixel array; the plurality of clock signals include a first clock signal for driving the first-stage shift register unit to output a gate driving signal; Wherein, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scanning time and less than or equal to 0.6 times the unit scanning time.

2. The driving method according to claim 1, wherein, The first-stage shift register unit to the P-stage shift register unit among the N shift register units are connected to the frame start signal; the plurality of clock signals further include a Pth clock signal for driving the P-stage shift register unit to output a gate driving signal; The duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured such that the falling edge of the frame start signal is aligned with the rising edge of the Pth clock signal, where P is an integer greater than 1.

3. The driving method according to claim 2, wherein, The phase difference between the rising edges of every two adjacent clock signals among the plurality of clock signals is the unit scanning time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scanning time, and the duty cycle of each of the clock signals is 40%.

4. The driving method according to any one of claims 1-3, wherein, The period during which each row of sub-pixels is in the on state includes a charging period and a pre-charging period before the charging period, where the duration of the charging period is equal to 2 times the unit scanning time, and the duration of the pre-charging period is greater than or equal to the unit scanning time.

5. The driving method according to claim 4, wherein, The duration for each row of sub-pixels to be in the on state is 3.2 times the unit scanning time, the duration of the pre-charge period is 1.2 times the unit scanning time, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by the unit scanning time; The multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups in the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group respectively receive the 8 clock signals; The first-stage shift register unit to the 4th-stage shift register unit among the N shift register units are connected to the frame start signal.

6. The driving method according to claim 4 or 5, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, the first pre-charge period is the last unit scanning time in the pre-charge period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by the unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in the on state includes: During the charging period of the (2k - 1)-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the (2k - 1)-th row of sub-pixels; During the first pre-charge period of the 2k-th row of sub-pixels and the first half of the charging period of the 2k-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the 2k-th row of sub-pixels, and during the second half of the charging period of the 2k-th row of sub-pixels, applying one of the (2k + 1)-th row data signal and the 2(k + 1)-th row data signal to the 2k-th row of sub-pixels; and During the first pre-charge period of the (2k + 1)-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the (2k + 1)-th row of sub-pixels; where k = 1, 2, 3, …….

7. The driving method according to claim 4 or 5, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, the first pre-charge period is the last unit scanning time in the pre-charge period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by the unit scanning time; Applying data signals to at least two rows of sub-pixels that are simultaneously in the on state includes: During the second half of the charging period of the (2k - 1)-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the (2k - 1)-th row of sub-pixels; During the charging period of the 2k-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the 2k-th row of sub-pixels; During the first pre-charge period of the (2k + 1)-th row of sub-pixels and the first half of the charging period of the (2k + 1)-th row of sub-pixels, applying one of the (2k - 1)-th row data signal and the 2k-th row data signal to the (2k + 1)-th row of sub-pixels, and during the second half of the charging period of the (2k + 1)-th row of sub-pixels, applying one of the (2k + 1)-th row data signal and the 2(k + 1)-th row data signal to the (2k + 1)-th row of sub-pixels; and During the first pre-charge period of the sub-pixels in the 2(k + 1)-th row, one of the data signals of the (2k - 1)-th row and the 2k-th row is applied to the sub-pixels in the 2(k + 1)-th row. During the charge period of the sub-pixels in the 2(k + 1)-th row, one of the data signals of the (2k + 1)-th row and the 2(k + 1)-th row is applied to the sub-pixels in the 2(k + 1)-th row; where k = 1, 2, 3,....

8. The driving method according to claim 4 or 5, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, and the first pre-charge period is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time; Applying data signals to at least two rows of sub-pixels that are simultaneously in the on state includes: During the charge period of the sub-pixels in the (6k - 5)-th row, the data signal of the (6k - 5)-th row is applied to the sub-pixels in the (6k - 5)-th row; During the first pre-charge period of the sub-pixels in the (6k - 4)-th row and the first half of the charge period of the sub-pixels in the (6k - 4)-th row, the data signal of the (6k - 5)-th row is applied to the sub-pixels in the (6k - 4)-th row. During the second half of the charge period of the sub-pixels in the (6k - 4)-th row, the data signal of the (6k - 3)-th row is applied to the sub-pixels in the (6k - 4)-th row; During the first pre-charge period of the sub-pixels in the (6k - 3)-th row, the data signal of the (6k - 5)-th row is applied to the sub-pixels in the (6k - 3)-th row. During the charge period of the sub-pixels in the (6k - 3)-th row, the data signal of the (6k - 3)-th row is applied to the sub-pixels in the (6k - 3)-th row; During the first pre-charge period of the sub-pixels in the (6k - 2)-th row and the first half of the charge period of the sub-pixels in the (6k - 2)-th row, the data signal of the (6k - 3)-th row is applied to the sub-pixels in the (6k - 2)-th row. During the second half of the charge period of the sub-pixels in the (6k - 2)-th row, the data signal of the (6k - 1)-th row is applied to the sub-pixels in the (6k - 2)-th row; During the first pre-charge period of the sub-pixels in the (6k - 1)-th row, the data signal of the (6k - 3)-th row is applied to the sub-pixels in the (6k - 1)-th row. During the charge period of the sub-pixels in the (6k - 1)-th row, the data signal of the (6k - 1)-th row is applied to the sub-pixels in the (6k - 1)-th row; During the first pre-charge period of the sub-pixels in the 6k-th row and the first half of the charge period of the sub-pixels in the 6k-th row, the data signal of the (6k - 1)-th row is applied to the sub-pixels in the 6k-th row. During the second half of the charge period of the sub-pixels in the 6k-th row, the data signal of the (6k + 1)-th row is applied to the sub-pixels in the 6k-th row; where k = 1, 2, 3,....

9. The driving method according to claim 4 or 5, wherein The pre-charge period of each row of sub-pixels includes a first pre-charge period, and the first pre-charge period is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time; Applying data signals to at least two rows of sub-pixels that are simultaneously in the on state includes: During the second half of the charge period of the sub-pixels in the (6k - 5)-th row, the data signal of the (6k - 4)-th row is applied to the sub-pixels in the (6k - 5)-th row; During the charge period of the sub-pixels in the (6k - 4)-th row, the data signal of the (6k - 4)-th row is applied to the sub-pixels in the (6k - 4)-th row; During the first pre-charging period of the sub-pixels in the (6k - 3)-th row and the first half of the charging period of the sub-pixels in the (6k - 3)-th row, apply the data signal of the (6k - 4)-th row to the sub-pixels in the (6k - 3)-th row. During the second half of the charging period of the sub-pixels in the (6k - 3)-th row, apply the data signal of the (6k - 2)-th row to the sub-pixels in the (6k - 3)-th row; During the first pre-charging period of the sub-pixels in the (6k - 2)-th row, apply the data signal of the (6k - 4)-th row to the sub-pixels in the (6k - 2)-th row. During the charging period of the sub-pixels in the (6k - 2)-th row, apply the data signal of the (6k - 2)-th row to the sub-pixels in the (6k - 2)-th row; During the first pre-charging period of the sub-pixels in the (6k - 1)-th row and the first half of the charging period of the sub-pixels in the (6k - 1)-th row, apply the data signal of the (6k - 2)-th row to the sub-pixels in the (6k - 1)-th row. During the second half of the charging period of the sub-pixels in the (6k - 1)-th row, apply the data signal of the 6k-th row to the sub-pixels in the (6k - 1)-th row; During the first pre-charging period of the sub-pixels in the 6k-th row, apply the data signal of the (6k - 2)-th row to the sub-pixels in the 6k-th row. During the charging period of the sub-pixels in the 6k-th row, apply the data signal of the 6k-th row to the sub-pixels in the 6k-th row; where k = 1, 2, 3,......

10. The driving method according to any one of claims 6 - 9, further comprising: Dividing each of the plurality of initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes the odd-row data of the initial data frame, and the other includes the even-row data of the initial data frame; the plurality of initial data frames includes adjacent first initial data frame and second initial data frame; In the first frame, apply the first target data frame corresponding to the first initial data frame to the sub-pixel array; In the second frame, apply the second target data frame corresponding to the first initial data frame to the sub-pixel array; In the third frame, apply the first target data frame corresponding to the second initial data frame to the sub-pixel array; In the fourth frame, apply the second target data frame corresponding to the second initial data frame to the sub-pixel array.

11. The driving method according to any one of claims 6 - 9, further comprising: Dividing each of the plurality of initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes the odd-row data of the initial data frame, and the other includes the even-row data of the initial data frame; the plurality of initial data frames includes adjacent first initial data frame and second initial data frame; In the first frame, apply the data of the first target data frame corresponding to the first initial data frame to the sub-pixel array; In the second frame, apply the data of the second target data frame corresponding to the first initial data frame to the sub-pixel array; In the third frame, apply the data of the second target data frame corresponding to the second initial data frame to the sub-pixel array; In the fourth frame, apply the data of the first target data frame corresponding to the second initial data frame to the sub-pixel array.

12. The driving method according to any one of claims 6-9 further includes: Dividing each of the multiple initial data frames into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any one of the initial data frames includes the odd-row data of the initial data frame, and the other includes the even-row data of the initial data frame; the multiple initial data frames include adjacent first initial data frame and second initial data frame; In the first frame, apply the data of the first target data frame corresponding to the first initial data frame to the sub-pixel array; In the second frame, apply the data of the first target data frame corresponding to the second initial data frame to the sub-pixel array; In the third frame, apply the data of the second target data frame corresponding to the first initial data frame to the sub-pixel array; In the fourth frame, apply the data of the second target data frame corresponding to the second initial data frame to the sub-pixel array.

13. The driving method according to any one of claims 1 to 12, wherein In the first period, turn on the nth row of sub-pixels and the (n + 1)th row of sub-pixels in sequence, where n is an integer and 1 ≤ n ≤ N - 3; In the second period, turn on the (n + 2)th row of sub-pixels and the (n + 3)th row of sub-pixels in sequence, and apply one of the nth row data signal and the (n + 1)th row data signal to the nth row of sub-pixels and the (n + 1)th row of sub-pixels, and the length of the second period is greater than or equal to 2 times the unit scanning time; In the third period, turn off the nth row of sub-pixels, and apply one of the (n + 2)th row data signal and the (n + 3)th row data signal to the (n + 1)th row of sub-pixels, the (n + 2)th row of sub-pixels and the (n + 3)th row of sub-pixels.

14. The driving method according to any one of claims 1 to 12, wherein, The duration for which each row of sub-pixels is applied with a data signal is greater than the unit scanning time; Or, The duration for which the first row of sub-pixels is applied with a data signal is equal to the unit scanning time, and the duration for which each row of sub-pixels other than the first row of sub-pixels is applied with a data signal is greater than the unit scanning time.

15. A display device, comprising: A sub-pixel array including a plurality of sub-pixels arranged in an N×M array, where N and M are both integers greater than 1; A gate driving circuit connected to the sub-pixel array, configured to output a plurality of gate driving signals to the sub-pixel array based on a frame start signal and a plurality of clock signals, and scan the plurality of sub-pixels row by row or with at least one row interval by using the plurality of gate driving signals to turn on the scanned rows of sub-pixels, so that the duration for which two consecutive rows of sub-pixels that are turned on simultaneously are in the on state is greater than or equal to 2 times the unit scanning time, and the unit scanning time is the time required to scan one row of sub-pixels; And A source driving circuit connected to the plurality of sub-pixels, configured to apply a data signal to at least two rows of sub-pixels that are simultaneously in the on state such that the duration for which at least some rows of sub-pixels are applied with a data signal is greater than the unit scanning time; A timing controller configured to apply the frame start signal and the plurality of clock signals to the gate driving circuit; Among them, the gate driving circuit includes N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, and the first-stage shift register unit among the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first-stage shift register unit to output a gate driving signal. Among them, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

16. An electronic device, comprising the display device as described in claim 15.

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