Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a display area, the display area comprises a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, and the conventional display area comprises a first area, a second area and a third area; at least one circuit unit of a first area (100A) in the conventional display area is connected with a light-emitting device in the light-transmitting display area (10), at least one circuit unit of a third area (100C) in the conventional display area comprises a data connecting line (70), and the second high-voltage power line comprises a first sub high-voltage power line (VLB1) and a second sub high-voltage power line (VLB2) which are connected with each other. The second sub-high-voltage power line (VLB2) is located on the side, away from the substrate, of the first sub-high-voltage power line (VLB1), the first high-voltage power line (VLA) and the second sub-high-voltage power line (VLB2) are arranged on the same layer, and the third high-voltage power line (VLC) and the first sub-high-voltage power line (VLB1) are arranged on the same layer.

Description

Display panel and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display panel comprising: a display area, the display area comprising: a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, the conventional display area comprising a first area, a second area, and a third area, at least one circuit unit in the first area being connected to a light-emitting device in the light-transmitting display area, at least one circuit unit in the third area comprising a data connection line, a high-voltage power line located in the first area being a first high-voltage power line, a high-voltage power line located in the second area being a second high-voltage power line, and a high-voltage power line located in the third area being a third high-voltage power line;

[0006] The second high-voltage power line includes: a first sub-high-voltage power line and a second sub-high-voltage power line connected to each other, the second sub-high-voltage power line is located on the side of the first sub-high-voltage power line away from the substrate, the first high-voltage power line and the second sub-high-voltage power line are arranged on the same layer, and the third high-voltage power line and the first sub-high-voltage power line are arranged on the same layer.

[0007] In an exemplary embodiment, the data connection line includes: a first connection line connected to each other and a second connection line extending along the second direction, the first connection line is located on a side of the third high-voltage power line close to the substrate, and the second connection line is arranged on the same layer as the first high-voltage power line;

[0008] The orthographic projection of the first connecting line on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the third high-voltage power line on the substrate.

[0009] In an exemplary embodiment, the first connection line includes: a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, the first data connection portion being connected to the second data connection portion and the second connection line, respectively, and the first direction and the second direction intersect;

[0010] An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the data signal line on the substrate.

[0011] In an exemplary embodiment, the length of the second sub-high-voltage power line along the first direction is less than the length of the first sub-high-voltage power line along the first direction, and the orthographic projection of the second sub-high-voltage power line on the substrate at least partially overlaps with the orthographic projection of the first sub-high-voltage power line on the substrate.

[0012] In an exemplary embodiment, the length of the first high-voltage power line along the first direction, the length of the first sub-high-voltage power line along the first direction, and the third high-voltage power line are approximately equal, and the shape of the first high-voltage power line, the shape of the first sub-high-voltage power line, and the shape of the third high-voltage power line are substantially the same.

[0013] In an exemplary embodiment, the length of the second sub-high-voltage power line along the first direction is approximately equal to the length of the second connecting line along the first direction, and the shape of the second sub-high-voltage power line is substantially the same as the shape of the second connecting line.

[0014] In an exemplary embodiment, the area of ​​the overlapping region of the orthographic projection of the second sub-high-voltage power line on the substrate and the orthographic projection of the first sub-high-voltage power line on the substrate is greater than the area of ​​the overlapping region of the orthographic projection of the second connecting line on the substrate and the orthographic projection of the third high-voltage power line on the substrate.

[0015] In an exemplary embodiment, the light-emitting device includes: an anode, an organic light-emitting layer and a cathode, and the display panel further includes: a plurality of first anode connecting lines extending along a first direction, the first anode connecting lines being arranged on the same layer as the third high-voltage power line and being configured to connect at least one circuit unit in the first area and the anode of the light-emitting device located in the light-transmitting display area.

[0016] In an exemplary embodiment, the light-transmitting display area includes: a central area and an edge area surrounding the central area; the display panel further includes: a second anode connection line, the second anode connection line being located on a side of the first high-voltage power line away from the substrate;

[0017] The first anode connection line is configured to connect at least one circuit unit in the first area and the anode of the light emitting device located in the edge area, and the second anode connection line is configured to connect at least one circuit unit in the first area and the anode of the light emitting device located in the central area.

[0018] In an exemplary embodiment, the first anode connection line includes a metal signal line, and the second anode connection line includes a transparent conductive signal line.

[0019] In an exemplary embodiment, the light emitting structure layer includes: a plurality of light emitting units, at least one light emitting unit includes: a first light emitting device, a second light emitting device, and a third light emitting device, different light emitting devices emit light of different colors, the first light emitting device and the second light emitting device emit red or blue light, and the third light emitting device emits green light;

[0020] For a light emitting unit located in the edge area, the length of the first anode connection line connected to the third light emitting device of the same light emitting unit along the first direction is shorter than the length of the first anode connection line connected to the first light emitting device and the second light emitting device of the same light emitting unit along the first direction.

[0021] In an exemplary embodiment, the length of the first anode connecting line connected to any third light emitting device located in the edge area along the first direction is less than the length of the first anode connecting line connected to any first light emitting device located in the edge area and the first anode connecting line connected to any second light emitting device located in the edge area along the first direction.

[0022] In an exemplary embodiment, the edge region occupies approximately 3% to 8% of the area of ​​the light-transmitting display region, or the number of light-emitting units included in the edge region is 5% to 10% of the number of light-emitting units in the light-transmitting display region.

[0023] In an exemplary embodiment, the pixel circuit includes at least a capacitor and a plurality of transistors, the capacitor including: a first electrode plate and a second electrode plate; the display panel includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planar layer, and a fifth conductive layer sequentially arranged on a substrate;

[0024] The semiconductor layer includes at least an active layer of multiple transistors; the first conductive layer includes at least gate electrodes of multiple transistors and a first plate of a capacitor; the second conductive layer includes at least a second plate of a capacitor; the third conductive layer includes at least the first and second electrodes of multiple transistors and a first connecting line; the fourth conductive layer includes at least a first anode connecting line, a first sub-high-voltage power line and a third high-voltage power line; the fifth conductive layer includes at least: a data signal line, a first high-voltage power line, a second sub-high-voltage power line and a second connecting line.

[0025] In an exemplary embodiment, the pixel circuit includes: a write transistor, which is connected to a data signal line; the second plate of the capacitor located in the third region includes: a capacitor main body and an auxiliary capacitor part that are connected to each other, the capacitor main body and the second plate of the capacitor located in the first region and the second region have substantially the same shape; the orthographic projection of the auxiliary capacitor part on the substrate at least partially overlaps with the orthographic projection of the active layer of the write transistor on the substrate.

[0026] In an exemplary embodiment, the third conductive layer further includes: a data connection block, an orthographic projection of the data connection block on the substrate at least partially overlapping with an orthographic projection of the auxiliary capacitor portion and the second connection line on the substrate;

[0027] The data connection blocks are connected to the first connection line and the second connection line respectively.

[0028] In an exemplary embodiment, the data connection block and the second data connection portion are located on the same side of the first data connection portion and are electrically connected to the first data connection portion;

[0029] An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the second plate of the capacitor on the substrate.

[0030] In an exemplary embodiment, the pixel circuit further includes: a first light-emitting transistor and a second light-emitting transistor, the first light-emitting transistor being connected to a high-voltage power line, and the second light-emitting transistor being connected to an anode of the light-emitting device, and the fourth conductive layer further includes: a first connection electrode, a second connection electrode, a third connection electrode, and a fourth connection electrode;

[0031] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the write transistor of at least one circuit unit located in the first area to the third area, and is electrically connected to the first electrode of the write transistor of at least one circuit unit located in the first area to the third area. The orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area, and is connected to the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area. The orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area, and is connected to the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area. The orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the data connection block on the substrate, and at least partially overlaps with the orthographic projection of the data connection block on the substrate.

[0032] In an exemplary embodiment, the fifth conductive layer further includes a fifth connecting electrode, the orthographic projection of the fifth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode on the substrate, and the fifth connecting electrode is connected to the second connecting electrode.

[0033] In an exemplary embodiment, orthographic projections of the plurality of first anode connection lines on the substrate may at least partially overlap with orthographic projections of the second plate of the capacitor and the anodes of the connected light emitting devices on the substrate.

[0034] In an exemplary embodiment, the orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate and is connected to the first connection electrode, the orthographic projection of the first high-voltage power line on the substrate at least partially overlaps with the orthographic projection of the third connection electrode on the substrate and is connected to the third connection electrode, and the orthographic projection of the second connection line on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode on the substrate and is connected to the fourth connection electrode.

[0035] In an exemplary embodiment, a transparent conductive layer is further included on a side of the second planar layer away from the substrate, the transparent conductive layer including a second anode connecting line, the second anode connecting line at least partially overlaps with the orthographic projection of the fifth connecting electrode on the substrate, and is connected to the fifth connecting electrode.

[0036] In a second aspect, the present disclosure further provides a display device comprising: the above-mentioned display panel and a light-sensitive sensor, wherein the light-sensitive sensor is located in a light-transmitting display area of ​​the display panel.

[0037] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0039] FIG1 is a schematic structural diagram of a display device;

[0040] FIG2 is a schematic structural diagram of a display panel;

[0041] FIG3 is a schematic diagram of a planar structure of a display area in a display panel;

[0042] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit;

[0043] FIG4B is a timing diagram of an operation of a pixel circuit;

[0044] FIG5A is a schematic diagram of a planar structure of a display panel according to an exemplary embodiment of the present disclosure;

[0045] FIG5B is a cross-sectional view of FIG5A taken along line AA;

[0046] FIG5C is a schematic diagram of an arrangement of data connection lines according to an exemplary embodiment of the present disclosure;

[0047] FIG6 is a schematic diagram of partitioning of a display area according to an exemplary embodiment of the present disclosure;

[0048] FIG7A is a schematic structural diagram of the E0 region, the E1 region, and the E2 region in FIG6 according to an embodiment of the present disclosure;

[0049] FIG7B is a schematic structural diagram of the E0 region in FIG6 according to an embodiment of the present disclosure;

[0050] FIG7C is a schematic structural diagram of the E1 region in FIG6 according to an embodiment of the present disclosure;

[0051] FIG7D is a schematic structural diagram of the E2 region in FIG6 according to an embodiment of the present disclosure;

[0052] FIG8A is a schematic diagram showing the wiring of a first anode connection line of a display panel;

[0053] FIG8B is a schematic diagram showing the connection of a first anode connection line of a display panel;

[0054] FIG8C is a schematic diagram of a partial wiring diagram of a first anode connection line of a display panel;

[0055] FIG8D is a second schematic diagram of partial wiring of a first anode connection line of a display panel;

[0056] FIG8E is another schematic structural diagram of the E0 region in FIG6 ;

[0057] FIG9 is a schematic diagram of regions E0, E1, and E2 after semiconductor patterns are formed;

[0058] FIG10 is a schematic diagram of the first conductive layer patterns in the E0 region, the E1 region, and the E2 region;

[0059] FIG11 is a schematic diagram of regions E0, E1, and E2 after a first conductive layer pattern is formed;

[0060] FIG12 is a schematic diagram of the first conductive layer pattern in the E0 region and the E1 region;

[0061] FIG13 is a schematic diagram of regions E0 and E1 after forming a first conductive layer pattern;

[0062] FIG14 is a schematic diagram of a first conductive layer pattern in region E2;

[0063] FIG15 is a schematic diagram of the E2 region after the first conductive layer pattern is formed;

[0064] FIG16 is a schematic diagram showing a region E0 and a region E1 after a third insulating layer pattern is formed;

[0065] FIG17 is a schematic diagram of a region E2 after a third insulating layer pattern is formed;

[0066] FIG18 is a schematic diagram of the third conductive layer pattern in the E0 region and the E1 region;

[0067] FIG19 is a schematic diagram showing the formation of a third conductive layer pattern in the E0 region and the E1 region;

[0068] FIG20 is a schematic diagram of a third conductive layer pattern in region E2;

[0069] FIG21 is a schematic diagram of the E2 region after the third conductive layer pattern is formed;

[0070] FIG22 is a schematic diagram showing a fourth insulating layer pattern formed in the E0 region and the E1 region;

[0071] FIG23 is a schematic diagram of a region E2 after a fourth insulating layer pattern is formed;

[0072] FIG24A is a first schematic diagram of a pattern of the fourth conductive layer in the E0 region;

[0073] FIG24B is a first schematic diagram of a region E0 after a fourth conductive layer pattern is formed;

[0074] FIG25A is a second schematic diagram of the fourth conductive layer pattern in the E0 region;

[0075] FIG25B is a second schematic diagram of the formation of the fourth conductive layer pattern in the E0 region;

[0076] FIG26 is a schematic diagram of a fourth conductive layer pattern in region E1;

[0077] FIG27 is a schematic diagram of the E1 region after the fourth conductive layer pattern is formed;

[0078] FIG28 is a schematic diagram of a fourth conductive layer pattern in region E2;

[0079] FIG29 is a schematic diagram of the E2 region after the fourth conductive layer pattern is formed;

[0080] FIG30 is a schematic diagram of the E0 region after the first planar layer pattern is formed;

[0081] FIG31 is a schematic diagram of the E1 region after the first planar layer pattern is formed;

[0082] FIG32 is a schematic diagram of the E2 region after the first planar layer pattern is formed;

[0083] FIG33 is a schematic diagram of a fifth conductive layer pattern in the E0 region;

[0084] FIG34 is a schematic diagram of the E0 region after the fifth conductive layer pattern is formed;

[0085] FIG35 is a schematic diagram of a fifth conductive layer pattern in region E1;

[0086] FIG36 is a schematic diagram of the E1 region after the fifth conductive layer pattern is formed;

[0087] FIG37 is a schematic diagram of the fifth conductive layer pattern in the E2 region;

[0088] FIG38 is a schematic diagram of the E2 region after the fifth conductive layer pattern is formed;

[0089] FIG39 is a schematic diagram of the E0 region after forming a second planar layer pattern;

[0090] FIG40 is a schematic diagram of the E1 region after the second planarization layer pattern is formed;

[0091] FIG41 is a schematic diagram of the E2 region after the second planarization layer pattern is formed;

[0092] FIG42 is a schematic diagram of an anode conductive layer pattern;

[0093] FIG43 is a schematic diagram of the E0 region after forming an anode conductive layer pattern;

[0094] FIG44 is a schematic diagram of the E1 region after the anode conductive layer pattern is formed;

[0095] FIG45 is a schematic diagram of the E2 region after the anode conductive layer pattern is formed;

[0096] FIG46 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.

[0097] Details

[0098] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0099] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0100] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0101] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0102] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0103] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0104] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0105] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0106] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0107] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0108] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" means that the values ​​differ by less than 10%.

[0109] Figure 1 is a schematic structural diagram of a display device. As shown in Figure 1, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver and a pixel array. The timing controller is connected to the data driver, the scan driver and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (for example, D1 to Dn), the scan driver is connected to a plurality of scan signal lines (for example, S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (for example, E1 to Eo). Wherein, n, m and o can be natural numbers. The pixel array may include a plurality of sub-pixels Pxij, and i and j can be natural numbers. At least one sub-pixel Pxij may include: a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least a pixel circuit, and the pixel circuit may be connected to the scan signal line, the light-emitting signal line and the data signal line respectively.

[0110] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel row basis. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next-stage circuit under the control of a clock signal. The light-emitting driver can generate a light-emitting control signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be constructed in the form of a shift register and can generate a light-emitting control signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal.

[0111] Figure 2 is a schematic diagram of the structure of a display panel. As shown in Figure 2, the display panel may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In some examples, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij may be configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In some examples, the display panel may utilize a flexible substrate, allowing the display panel to be deformable, such as being curled, bent, folded, or rolled up.

[0112] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The fan-out area is connected to the display area 100, and the fan-out area introduces the signal lines of the integrated circuit and the binding pads in the binding area to the wider display area in a fan-out routing manner. The fan-out area includes at least a data fan-out line, and a plurality of data fan-out lines are configured to connect the data signal lines of the display area 100 in a fan-out routing manner and extend to the bending area. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the driver chip area and the binding pin area to the back side of the display area 100. The driver chip area may be provided with an integrated circuit (IC), which may be configured to be connected to the plurality of data fan-out lines. The binding pin area may include a bonding pad, which may be configured to be bonded to an external flexible printed circuit (FPC). In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line, reset signal line, and light-emitting signal line connected to the pixel circuit in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display panel are prepared, the cutting equipment can cut along the cutting groove respectively.

[0113] In an exemplary embodiment, the fan-out region in the binding region 200 and the power line region in the frame region 300 may be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display region to form a ring structure surrounding the display region 100. The edge of the display region is the edge of the display region 100 on a side close to the binding region 200 or the frame region 300.

[0114] FIG3 is a schematic diagram of a planar structure of a display area in a display panel. As shown in FIG3 , the display panel may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 that emit a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel circuit. The pixel circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel circuit may be configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0115] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In some examples, the shape of the light-emitting devices of the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal, and the light-emitting devices of the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the light-emitting devices of the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in this disclosure.

[0116] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the light-emitting devices of the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or triangular pattern, which is not limited in the present disclosure.

[0117] In an exemplary embodiment, in a direction perpendicular to the display panel, the display panel may include: a substrate, a driving circuit layer, a light-emitting structure layer, and an encapsulation structure layer sequentially disposed on the substrate. In some possible implementations, the display panel may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0118] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The driving circuit layer of each sub-pixel may include a pixel circuit composed of a plurality of transistors and capacitors. The light-emitting structure layer of each sub-pixel may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0119] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EL) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer that is connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0120] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit. In an exemplary embodiment, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited to this.

[0121] In an exemplary embodiment, as shown in FIG4A , the pixel circuit of this example may include seven transistors (i.e., first to seventh transistors T1 to T7) and a capacitor C. The pixel circuit is respectively connected to eight signal lines (e.g., including: a data signal line DL, a scan signal line GL, a reset signal line RL, a light emitting signal line EL, a first initial signal line INIL1, a second initial signal line INIL2, a high-voltage power line VDD, and a low-voltage power line VSS).

[0122] In an exemplary embodiment, the seven transistors of the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the seven transistors of the pixel circuit may include P-type transistors and N-type transistors.

[0123] In an exemplary embodiment, the seven transistors of the pixel circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, i.e., an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0124] In an exemplary embodiment, the high-voltage power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, and the low-voltage power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the second voltage signal. The scan signal line GL can be configured to provide a scan signal to the pixel circuit, the data signal line DL can be configured to provide a data signal to the pixel circuit, and the light-emitting signal line EL can be configured to provide a light-emitting control signal to the pixel circuit. In some examples, in the n-th row of pixel circuits, the reset signal line RL can be electrically connected to the scan signal line GL of the n-1-th row of pixel circuits to be input with a scan signal. Wherein, n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced, and a narrow-frame design of the display panel can be achieved. However, this embodiment is not limited to this.

[0125] In an exemplary embodiment, the first initial signal line INIL1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIL2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal provided by the high-voltage power line VDD and the second voltage signal provided by the low-voltage power line VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0126] In an exemplary embodiment, as shown in FIG4A , the gate of the first transistor T1 is electrically connected to the reset signal line RL, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIL1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan signal line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The gate of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3. The third transistor T3 can be referred to as a drive transistor. The amount of drive current flowing between the high-voltage power supply line VDD and the low-voltage power supply line VSS is determined by the potential difference between the gate and the first electrode of the third transistor T3. The gate of the fourth transistor T4 is electrically connected to the scan signal line GL, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor can be referred to as a write transistor. The gate of the fifth transistor T5 is electrically connected to the light-emitting signal line EL, the first electrode of the fifth transistor T5 is electrically connected to the high-voltage power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The fifth transistor can be referred to as a first light-emitting transistor. The gate of the sixth transistor T6 is electrically connected to the light-emitting signal line EL, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device L. The sixth transistor T6 can be referred to as a second light-emitting transistor. The gate of the seventh transistor T7 is electrically connected to the reset signal line RL, the first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line INIL2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device L. The first plate of the capacitor C is electrically connected to the gate of the third transistor T3, and the second plate of the capacitor C is electrically connected to the high-voltage power supply line VDD.

[0127] In this example, the first node N1 is a connection point between the capacitor C, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is a connection point between the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is a connection point between the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is a connection point between the sixth transistor T6, the seventh transistor T7, and the light-emitting device L.

[0128] In an exemplary embodiment, the light-emitting device L may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The second electrode of the light-emitting device is connected to a low-voltage power line VSS, where the signal of the low-voltage power line VSS is a continuously provided low-level signal, and the signal of the high-voltage power line VDD is a continuously provided high-level signal.

[0129] In an exemplary embodiment, FIG4B is an operation timing diagram of a pixel circuit. As shown in FIG4A and FIG4B , taking the example that the first transistor T1 to the seventh transistor T7 included in the pixel circuit are all P-type transistors, the operation process of the pixel circuit may include the following stages.

[0130] The first phase A1 is called the reset phase. A low-level signal provided by the reset signal line RL turns on the first transistor T1. The first initial signal provided by the first initial signal line INIL1 is supplied to the first node N1, initializing the first node N1 and clearing the original data voltage in the capacitor C. The scan signal line GL provides a high-level signal, and the light-emitting signal line EL provides a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting device L does not emit light.

[0131] The second phase A2 is called the data writing phase or the threshold compensation phase. The scan signal line GL provides a low-level signal, the reset signal line RL and the light-emitting signal line EL both provide high-level signals, and the data signal line DL outputs the data signal DATA. During this phase, since the first plate of capacitor C is at a low level, the third transistor T3 is turned on. The scan signal line GL provides a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data signal line DL and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage of the first plate of capacitor C (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIL2 is provided to the anode of the light-emitting device L, initializing (resetting) the anode of the light-emitting device L, clearing the pre-stored voltage therein, completing the initialization, and ensuring that the light-emitting device L does not emit light. The reset signal line RL provides a high-level signal, turning off the first transistor T1. The light-emitting signal line EL provides a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0132] The third phase A3 is called the light-emitting phase. The light-emitting signal line EL provides a low-level signal, while the scan signal line GL and the reset signal line RL both provide high-level signals. The low-level signal provided by the light-emitting signal line EL turns on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output by the high-voltage power supply line VDD then passes through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to provide a driving voltage to the anode of the light-emitting device L, driving the light-emitting device L to emit light.

[0133] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0134] I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0135] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line DL, and Vdd is the first voltage signal output by the high-voltage power line VDD.

[0136] It can be seen from the above formula that the current flowing through the light emitting device L has nothing to do with the threshold voltage of the third transistor T3. The pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0137] With the development of OLED display technology, consumers have higher and higher requirements for the display effects of display products, and extremely narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of the bezel or even the design of no bezel has received more and more attention in the design of OLED display products. In a display panel, the binding area usually includes a fan-out area, a bending area, a driver chip area and a binding pin area arranged in sequence along the direction away from the display area. Since the width of the binding area is smaller than the width of the display area, the signal lines of the integrated circuit and the binding pad in the binding area need to pass through the fan-out area in a fan-out routing manner to be introduced into the wider display area. The greater the difference in width between the display area and the binding area, the more oblique fan-out lines there are in the fan-shaped area, and the greater the distance between the driver chip area and the display area. Therefore, the fan-shaped area occupies a larger space, which makes the narrowing design of the lower bezel more difficult. The lower bezel has been maintained at around 2.0 mm.

[0138] Furthermore, the concept of full-screen phones has garnered widespread attention in the mobile phone market and is a key trend in future phone development. Full-screen phones employ a Full Display with Camera (FDC) architecture, where the camera area is also displayed. This FDC structure allows the front viewable area to be almost entirely screen, providing users with an optimal display experience.

[0139] The exemplary embodiments of the present disclosure provide a display panel that utilizes a fanout in AA (FIAA) structure. Multiple data lines connect to multiple data signal lines in the display area at one end, while the other ends extend to a bonding area and connect to integrated circuits in the bonding area. Because fan-shaped diagonal lines are not required in the bonding area, the width of the fanout area is reduced, effectively reducing the width of the bottom bezel.

[0140] An exemplary embodiment of the present disclosure provides a display panel, comprising: a display area, the display area comprising: a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, the conventional display area comprising a first area, a second area, and a third area, at least one circuit unit in the first area being connected to a light-emitting device in the light-transmitting display area, at least one circuit unit in the third area comprising a data connection line, a high-voltage power line located in the first area being a first high-voltage power line, a high-voltage power line located in the second area being a second high-voltage power line, and a high-voltage power line located in the third area being a third high-voltage power line;

[0141] The second high-voltage power line includes: a first sub-high-voltage power line and a second sub-high-voltage power line connected to each other, the second sub-high-voltage power line is located on the side of the first sub-high-voltage power line away from the substrate, the first high-voltage power line and the second sub-high-voltage power line are arranged on the same layer, and the third high-voltage power line and the first sub-high-voltage power line are arranged on the same layer.

[0142] In an exemplary embodiment, the display area includes: a substrate, and a driving circuit layer and a light-emitting structure layer stacked in sequence on the substrate, the driving circuit layer including a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, and a plurality of high-voltage power lines; the light-emitting structure layer includes a plurality of light-emitting devices, the circuit unit includes a pixel circuit, the data signal line is configured to provide a data signal to the pixel circuit, the high-voltage power line is configured to provide a high power supply voltage signal to the pixel circuit, and the data connection line is connected to the data signal line.

[0143] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0144] In an exemplary embodiment, the light-emitting structure layer may include: a plurality of light-emitting devices, at least one of which includes: an anode, an organic light-emitting layer, and a cathode. The shape of the light-emitting device can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons, and is not limited in this disclosure.

[0145] The display panel provided by the embodiment of the present disclosure includes: a display area, the display area includes: a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, the conventional display area includes a first area, a second area, and a third area, at least one circuit unit in the first area is connected to the light-emitting device in the light-transmitting display area, at least one circuit unit in the third area includes a data connection line, the high-voltage power line located in the first area is a first high-voltage power line, the high-voltage power line located in the second area is a second high-voltage power line, and the high-voltage power line located in the third area is a third high-voltage power line; the second high-voltage power line includes: a first sub-high-voltage power line and a second sub-high-voltage power line connected to each other, the second sub-high-voltage power line is located on a side of the first sub-high-voltage power line away from the substrate, the first high-voltage power line and the second sub-high-voltage power line are arranged on the same layer, and the third high-voltage power line and the first sub-high-voltage power line are arranged on the same layer. The embodiment of the present disclosure arranges different high-voltage power lines in different areas of the conventional display area, thereby ensuring the display effect while also achieving compatibility between the FIAA structure and the FDC structure.

[0146] In an exemplary embodiment, the data connection line includes: a first connection line connected to each other and a second connection line extending along the second direction, the first connection line is located on a side of the third high-voltage power line close to the substrate, and the second connection line is arranged on the same layer as the first high-voltage power line;

[0147] The orthographic projection of the first connecting line on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the third high-voltage power line on the substrate.

[0148] In an exemplary embodiment, the first connection line includes: a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, the first data connection portion being connected to the second data connection portion and the second connection line, respectively, and the first direction and the second direction intersect;

[0149] An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the data signal line on the substrate.

[0150] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.

[0151] FIG5A is a schematic diagram of a planar structure of a display panel according to an exemplary embodiment of the present disclosure, and FIG5B is a cross-sectional view of FIG5A along the AA direction. As shown in FIG5A and FIG5B , on a plane perpendicular to the display panel, the display panel may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate. On a plane parallel to the display panel, the display panel may include at least a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the driving circuit layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel circuit, which is configured to output a corresponding current to the light-emitting device to which it is connected. The light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array, and at least one sub-pixel may include a light-emitting device connected to a pixel circuit of a corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to a current output by the connected pixel circuit.

[0152] In an exemplary embodiment, the driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel circuit. FIG5B illustrates only one transistor 210 and one storage capacitor 220. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the transistor 210 via a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. Driven by the anode 301 and cathode 304, the organic light-emitting layer 303 emits light of a corresponding color. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting structure layer 103.

[0153] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. In an exemplary embodiment, the rigid substrate may be made of a material such as glass or quartz, and the flexible substrate may be made of a material such as polyimide (PI). The flexible substrate may have a single-layer structure or a laminated structure composed of an inorganic material layer and a flexible material layer, which is not limited in this disclosure.

[0154] In an exemplary embodiment, as shown in Figure 5A, the driving circuit layer of the display area 100 may also include multiple data signal lines 60 and multiple data connection lines 70, at least one data signal line 60 is connected to multiple pixel circuits in a unit column, the data signal line 60 is configured to provide a data signal to the connected pixel circuit, at least one data connection line 70 is connected to the data signal line 60 accordingly, and the data connection line 70 is configured to connect the data signal line 60 to the lead line 210 in the binding area 200 through the data connection line 70.

[0155] In exemplary embodiments, the term "sub-pixel" in this disclosure refers to a region divided according to a light-emitting device, and the term "circuit unit" in this disclosure refers to a region divided according to a pixel circuit. In exemplary embodiments, the position of the orthographic projection of the sub-pixel on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the sub-pixel on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0156] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects the second direction Y. In an exemplary embodiment, the second direction Y may be an extending direction of a data signal line (a vertical direction), and the first direction X may be perpendicular to the second direction Y (a horizontal direction).

[0157] In an exemplary embodiment, the circuit units located in the first, second, and third regions may include a driving circuit unit and a dummy circuit unit. The pixel circuits in the driving circuit unit may be configured to drive the light-emitting device to emit light, while the pixel circuits in the dummy circuit unit may not be configured to drive the light-emitting device to emit light, thereby ensuring display uniformity of the display panel. The dummy circuit unit may be provided between the driving circuit units.

[0158] In an exemplary embodiment, the binding area 200 may include at least a lead area 201, a bend area, and a driver chip area, arranged in sequence away from the display area. The lead area 201 is connected to the display area 100, the bend area is connected to the lead area 201, and the driver chip area is connected to the bend area. The lead area 201 may be provided with multiple lead wires 210, which may extend along a second direction Y. The first ends of the multiple lead wires 210 are connected to the integrated circuit of the composite circuit area, and the second ends of the multiple lead wires 210 extend across the bend area to the lead area 201 and then connect to the corresponding data connection lines 70, so that the integrated circuit applies data signals to the data signal lines via the lead wires and data connection lines. Since the data connection lines are arranged in the display area, the length of the lead area in the second direction Y can be effectively reduced, significantly reducing the width of the lower frame, increasing the screen-to-body ratio, and facilitating the realization of a full-screen display.

[0159] In an exemplary embodiment, the plurality of data signal lines provided in the display area 100 may be in the shape of lines extending along the second direction Y. The plurality of data connection lines 70 provided in the display area 100 may be in the shape of zigzag lines. The data connection lines 70 may include first connection lines extending partially along the first direction X and second connection lines extending along the second direction Y. The first ends of the plurality of first connection lines (the first ends of the data connection lines 70) are connected to the plurality of data signal lines 60 via connection holes. The second ends of the plurality of first connection lines extend along the first direction X or a direction opposite to the first direction X and are connected to the first ends of the second connection lines. The second ends of the plurality of second connection lines (the second ends of the data connection lines 70) extend toward the binding area 200 and cross the display area boundary B to connect to the plurality of lead lines 210 of the lead area 201. In an exemplary embodiment, the display area boundary B may be the junction of the display area 100 and the binding area 200.

[0160] In an exemplary embodiment, the data connection line 70 and the lead-out line 210 may be directly connected or may be connected through a via hole, which is not limited in the present disclosure.

[0161] In an exemplary embodiment, a plurality of second connection lines may be disposed in parallel with the data signal line 60 .

[0162] In an exemplary embodiment, the intervals between adjacent second connection lines in the first direction X may be substantially the same, and the intervals between adjacent first connection lines in the second direction Y may be substantially the same, which is not limited in the present disclosure.

[0163] In an exemplary embodiment, the display area 100 may have a center line O, and the multiple data signal lines 60, the multiple data connection lines 70 and the multiple lead lines 210 in the lead area 201 in the display area 100 may be symmetrically arranged relative to the center line O. The center line O may be a straight line that bisects the multiple unit columns of the display area 100 and extends along the second direction Y.

[0164] Figure 5C is a schematic diagram illustrating the arrangement of data connection lines according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 5A and illustrates the structure of seven data signal lines, seven data connection lines, and seven lead lines. As shown in Figure 5C, in an exemplary embodiment, the multiple data signal lines in the display area 100 may include first to seventh data signal lines 60-1 to 60-7, the multiple data connection lines in the display area 100 may include first to seventh data connection lines 70-1 to 70-7, and the multiple lead lines in the lead area 201 may include first to seventh lead lines 210-1 to 210-7.

[0165] In an exemplary embodiment, the first data signal line 60-1 to the seventh data signal line 60-7, the first data connection line 70-1 to the seventh data connection line 70-7, and the first lead line 210-1 to the seventh lead line 210-7 can all be arranged sequentially along the first direction X, the first end of the i-th data connection line 70-i is connected to the i-th data signal line 60-i through a connection hole in the display area 100, and the second end of the i-th data connection line 70-i extends to the lead area 201 and is connected to the i-th lead line 210-i, i=1 to 7.

[0166] In an exemplary embodiment, the distances between the multiple connection holes correspondingly connecting the data connection lines 70 and the data signal lines 60 and the edge B of the display area may be different. For example, the distance between the connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the edge B of the display area may be smaller than the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the edge B of the display area. For another example, the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the edge B of the display area may be larger than the distance between the connection hole connecting the third data connection line 70-3 and the third data signal line 60-3 and the edge B of the display area.

[0167] Figure 6 is a schematic diagram of a display area according to an exemplary embodiment of the present disclosure. As shown in Figure 6, the display area includes a light-transmitting display area 10 and a normal display area. The normal display area includes a first area 100A, a second area 100B, and a third area 100C.

[0168] In an exemplary embodiment, at least one circuit unit of the first region 100A is connected to the light emitting device in the light-transmitting display area. The second region 100C is all regions of the normal display area except the first region and the third region.

[0169] In an exemplary embodiment, at least one circuit unit of the third region 100C includes a data connection line. The third region 100C may include a plurality of circuit units, and the orthographic projections of the pixel circuits in the plurality of circuit units of the third region 100C on the display panel plane overlap with the orthographic projections of the data connection line 70 on the display panel plane.

[0170] In an exemplary embodiment, the filled area in FIG. 6 refers to the third region 100C where the data connection line is located. The portion of the data connection line 70 located in the third region 100C is located in a different film layer than the data signal line 60 and is located on the side of the data signal line closer to the substrate. Another portion of the data connection line 70 is located in the same film layer as the data signal line. The portion of the data connection line 70 located in a different film layer than the data signal line is connected to the data signal line 60. The portion of the data connection line 70 located in the same layer as the data signal line extends along the second direction Y to the bonding region 201.

[0171] In an exemplary embodiment, as shown in Figures 5A, 5C, and 6, the data connection line 70 may include a first connection line 71 extending partially along the first direction X and a second connection line 72 extending along the second direction Y. The first connection line 71 and the second connection line 72 form a zigzag-shaped data connection line 70. The first end of the first connection line 71 is connected to the data signal line 60 through a first connection hole. The second end of the first connection line 71 extends along the first direction X or the opposite direction of the first direction X and is directly connected to the first end of the second connection line 72. The second end of the second connection line 72 extends along the second direction Y toward the lead area 201 and is connected to the lead line 210.

[0172] In an exemplary embodiment, the first connection line 71 and the data signal line 60 may be disposed in different conductive layers, and the second connection line 72 and the data signal line 60 may be located in the same conductive layer.

[0173] In an exemplary embodiment, the first connection line includes a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, the first data connection portion is connected to the second data connection portion and the second connection line, respectively, and the first direction and the second direction intersect.

[0174] In the exemplary embodiment, the division of the various regions shown in FIG6 is merely an exemplary illustration. The first region 100A and the second region 100B do not have data connection lines, while the third region 100C does have data connection lines. The circuit units in the first region 100A are connected to the light-emitting devices in the light-transmitting display area, while the circuit units in the second region 100B are not connected to the light-emitting devices in the light-transmitting display area. As a basis for division, the shapes of the three regions can be regular polygons or irregular polygons. The display area can be divided into one or more first regions 100A, one or more second regions 100B, and one or more third regions 100C, but this is not limited in this disclosure.

[0175] In an exemplary embodiment, the shape of the light-transmitting display area in a plane parallel to the display panel can be any one or more of the following: rectangular, polygonal, circular, and elliptical. Figures 5A and 6 illustrate this using a circular shape as an example. For example, when the light-transmitting display area is circular, the diameter of the circle can be approximately 3 mm to 5 mm. For another example, when the light-transmitting display area is rectangular, the side length of the rectangle can be approximately 3 mm to 5 mm.

[0176] In an exemplary embodiment, in a plane parallel to the display panel, the shape of the first area may be any one or more of the following: a rectangle, a polygon, a circle, and an ellipse.

[0177] In an exemplary embodiment, the area of ​​the light-transmitting display area may be larger than the area of ​​the first area, or the area of ​​the light-transmitting display area may be equal to the area of ​​the first area, or the area of ​​the light-transmitting display area may be smaller than the area of ​​the first area. Figures 5A and 6 are illustrated by taking the example that the area of ​​the light-transmitting display area is smaller than the area of ​​the second display area.

[0178] In an exemplary embodiment, the resolution of the light-transmitting display area and the first area may be the same or different. Pixels Per Inch (PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates a higher density of images displayed by the display panel, resulting in richer details.

[0179] In an exemplary embodiment, the resolution of the first area may be greater than the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is greater than the number of light-emitting devices included in the light-transmitting display area, or the resolution of the first area may be less than the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is less than the number of light-emitting devices included in the light-transmitting display area, or the resolution of the first area may be equal to the resolution of the light-transmitting display area, that is, the number of light-emitting devices included in the first area per unit area is equal to the number of light-emitting devices included in the light-transmitting display area.

[0180] In an exemplary embodiment, the display area may be in the shape of a rounded polygon or a circle. When the display area is in the shape of a rounded polygon, the display area may further include a straight display border. FIG5A and FIG6 illustrate the display area as a rounded rectangle as an example.

[0181] Figure 7A is a schematic diagram of the structures of the E0 region, E1 region, and E2 region in Figure 6 according to an embodiment of the present disclosure, Figure 7B is a schematic diagram of the structure of the E0 region in Figure 6 according to an embodiment of the present disclosure, Figure 7C is a schematic diagram of the structure of the E1 region in Figure 6 according to an embodiment of the present disclosure, and Figure 7D is a schematic diagram of the structure of the E2 region in Figure 6 according to an embodiment of the present disclosure. The E0 region is located in the first region, the E1 region is located in the second region, and the E3 region is located in the third region. The high-voltage power line located in the first region is the first high-voltage power line, the high-voltage power line located in the second region is the second high-voltage power line, and the high-voltage power line located in the third region is the third high-voltage power line.

[0182] In an exemplary embodiment, as shown in Figures 7A to 7D, the second high-voltage power line may include: a first sub-high-voltage power line VLB1 and a second sub-high-voltage power line VLB2 connected to each other, the second sub-high-voltage power line VLB2 is located on a side of the first sub-high-voltage power line VLB1 away from the substrate, the first high-voltage power line VLA and the second sub-high-voltage power line VLB2 are arranged on the same layer, and the third high-voltage power line VLC is arranged on the same layer as the first sub-high-voltage power line VLB1.

[0183] In an exemplary embodiment, as shown in FIG. 7A to FIG. 7D , the data signal lines in the first, second, and third regions may be the same data signal line, and the data signal line DL is provided on the same layer as the first high-voltage power line.

[0184] As shown in Figures 7A and 7C, the length of the second sub-high-voltage power line VLB2 along the first direction X can be less than the length of the first sub-high-voltage power line VLB1 along the first direction X, and the orthographic projection of the second sub-high-voltage power line VLB2 on the substrate at least partially overlaps with the orthographic projection of the first sub-high-voltage power line VLB1 on the substrate.

[0185] In an exemplary embodiment, as shown in Figures 7A to 7C , the length of the first high-voltage power line VLA along the first direction X, the length of the first sub-high-voltage power line VLB1 along the first direction X, and the length of the third high-voltage power line VLC along the first direction X are approximately equal, and the shapes of the first high-voltage power line VLA, the first sub-high-voltage power line VLB1, and the third high-voltage power line VLC are substantially the same. The shapes of the first high-voltage power line VLA and the third high-voltage power line VLC being substantially the same as the shape of the first sub-high-voltage power line VLB1 can eliminate afterimages caused by metal lines when the display panel is off, thereby ensuring the display quality of the display panel.

[0186] In an exemplary embodiment, as shown in Figures 7A and 7D, the data connection line may include: a first connection line 71 connected to each other and a second connection line 72 extending along the second direction, the first connection line 71 is located on a side of the third high-voltage power line VLC close to the substrate, and the second connection line 72 is arranged on the same layer as the first high-voltage power line VLA.

[0187] In an exemplary embodiment, the second connection line 72 and the first high-voltage power line VLA are disposed on the same layer to achieve low load and high refresh rate.

[0188] In an exemplary embodiment, as shown in Figures 7A and 7D, the length of the second sub-high-voltage power line VLB2 along the first direction X may be approximately equal to the length of the second connection line 72 along the first direction X, and the shape of the second sub-high-voltage power line VLB2 is substantially the same as the shape of the second connection line 72.

[0189] In an exemplary embodiment, as shown in Figures 7A and 7D, the orthographic projection of the first connection line 71 on the substrate at least partially overlaps with the orthographic projection of the data signal line DL on the substrate, and the orthographic projection of the second connection line 72 on the substrate at least partially overlaps with the orthographic projection of the third high-voltage power line VLC on the substrate.

[0190] In an exemplary embodiment, as shown in FIG7A , the area of ​​the overlapping region between the orthographic projection of the second sub-high-voltage power line VLB2 on the substrate and the orthographic projection of the first sub-high-voltage power line VLB1 on the substrate is greater than the area of ​​the overlapping region between the orthographic projection of the second connection line 72 on the substrate and the orthographic projection of the third high-voltage power line VLC on the substrate.

[0191] In an exemplary embodiment, Figure 8A is a schematic diagram illustrating the wiring of a first anode connecting line of a display panel, Figure 8B is a schematic diagram illustrating the connection of a first anode connecting line and a second anode connecting line of a display panel, Figure 8C is a first schematic diagram illustrating a partial wiring of a first anode connecting line of a display panel, Figure 8D is a second schematic diagram illustrating a partial wiring of a first anode connecting line of a display panel, and Figure 8E is another schematic diagram illustrating the structure of region E0 in Figure 6 . As shown in Figures 8A to 8E , a light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The display panel may further include a plurality of first anode connecting lines AL1 extending along a first direction. The first anode connecting lines AL1 are disposed on the same layer as the third high-voltage power line VLC and are configured to connect at least one circuit unit in the first region 100A to the anode of the light-emitting device located in the light-transmitting display area 10.

[0192] As shown in FIG8B , the circuit units of the first region 100A may include a plurality of circuit units, and the circuit units connected to the light-emitting devices in the light-transmitting display area may be located between the circuit units connected to the light-emitting devices in the normal display area.

[0193] In an exemplary embodiment, as shown in FIG. 8A , the light-transmitting display area 10 includes a central area 10A and an edge area 10B disposed outside the central area 10A.

[0194] In an exemplary embodiment, as shown in FIG8B , the display panel may further include a second anode connection line AL2. The second anode connection line AL2 may be located on a side of the first high-voltage power line away from the substrate. The first anode connection line AL1 is configured to connect at least one circuit unit in the first region and the anode of the light-emitting device located in the edge region, and the second anode connection line AL2 is configured to connect at least one circuit unit in the first region and the anode of the light-emitting device located in the center region.

[0195] In an exemplary embodiment, the first anode connection line may include a metal signal line. The first anode connection line and the third high-voltage power line are arranged on the same layer, which can simplify the manufacturing process of the display panel, save costs, and improve yield and production capacity.

[0196] In an exemplary embodiment, the second anode connection line includes a transparent conductive signal line, which can ensure the light transmittance of the light-transmitting display area.

[0197] In an exemplary embodiment, since the aperture size of the light-transmitting display area is approximately 2.5 mm, if the display panel utilizes all second anode connecting lines, at least three transparent conductive layers and a planar layer or insulating layer between the transparent conductive layers are required. In this case, the display panel requires a large number of reticles. However, by providing multiple first anode connecting lines AL1 on the same layer as the third high-voltage power line VLC, the present disclosure alleviates the wiring pressure on the second anode connecting lines, reduces the number of reticles used in display panel manufacturing, and helps save costs and improve yield and production capacity.

[0198] In an exemplary embodiment, the light emitting structure layer may include: a plurality of light emitting units, at least one light emitting unit includes: a first light emitting device, a second light emitting device and a third light emitting device, different light emitting devices emit light of different colors, the first light emitting device and the second light emitting device emit red or blue light, and the third light emitting device emits green light.

[0199] In an exemplary embodiment, as shown in FIG8C and FIG8D , the area of ​​the first light-emitting device in the light-emitting cell located in the light-transmitting display area is smaller than the area of ​​the first light-emitting device in the light-emitting cell located in the conventional display area. The area of ​​the second light-emitting device in the light-transmitting display area is smaller than the area of ​​the second light-emitting device in the light-emitting cell located in the conventional display area. The area of ​​the third light-emitting device in the light-transmitting display area is smaller than the area of ​​the third light-emitting device in the light-emitting cell located in the conventional display area.

[0200] In an exemplary embodiment, as shown in Figures 8C and 8D , for a light-emitting unit located in an edge region, the length of the first anode connection line AL1 connected to the third light-emitting device of the same light-emitting unit along the first direction is shorter than the length of the first anode connection line AL1 connected to the first and second light-emitting devices of the same light-emitting unit along the first direction. Having the length of the first anode connection line AL1 connected to the third light-emitting device of the same light-emitting unit along the first direction shorter than the length of the first anode connection line AL1 connected to the first and second light-emitting devices of the same light-emitting unit along the first direction can reduce the load of the sub-pixel in which the third light-emitting device is located, thereby improving the display effect of the light-emitting devices in the light-transmitting display area.

[0201] In an exemplary embodiment, as shown in Figures 8C and 8D , the length of the first anode connecting line AL1 connected to any third light-emitting device located in the edge region along the first direction X is shorter than the length of the first anode connecting line AL1 connected to any first light-emitting device located in the edge region and the length of the first anode connecting line AL1 connected to any second light-emitting device located in the edge region along the first direction X. The shorter length of the first anode connecting line connected to any third light-emitting device located in the edge region along the first direction X can improve the display effect of the light-emitting device in the light-transmitting display area.

[0202] In an exemplary embodiment, the edge region 10B occupies approximately 3% to 8% of the area of ​​the light-transmitting display region 10, or the number of light-emitting units included in the edge region 10B is 5% to 10% of the number of light-emitting units in the light-transmitting display region. The edge region 10B occupies approximately 3% to 8% of the area of ​​the light-transmitting display region 10, or the number of light-emitting units included in the edge region 10B is 5% to 10% of the number of light-emitting units in the light-transmitting display region, which can ensure the transmittance of the light-transmitting display region.

[0203] In an exemplary embodiment, on a plane perpendicular to the substrate, the display panel may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planar layer, and a fifth conductive layer sequentially disposed on the substrate;

[0204] The semiconductor layer includes at least an active layer of multiple transistors; the first conductive layer includes at least gate electrodes of multiple transistors and a first plate of a capacitor; the second conductive layer includes at least a second plate of the capacitor; the third conductive layer includes at least the first and second poles of multiple transistors and a first connecting line; the fourth conductive layer includes at least a first anode connecting line, a first sub-high-voltage power line and a third high-voltage power line; the fifth conductive layer includes at least: a data signal line, a first high-voltage power line, a second sub-high-voltage power line and a second connecting line.

[0205] In an exemplary embodiment, the pixel circuit includes: a write transistor, the write transistor is connected to the data signal line, the second plate of the capacitor located in the third area includes: a capacitor main body and an auxiliary capacitor part connected to each other, the capacitor main body and the second plate of the capacitor located in the first area and the second area have substantially the same shape; the orthographic projection of the auxiliary capacitor part on the substrate at least partially overlaps with the orthographic projection of the active layer of the write transistor on the substrate.

[0206] In an exemplary embodiment, the third conductive layer further includes: a data connection block, the orthographic projection of the data connection block on the substrate at least partially overlaps with the orthographic projections of the auxiliary capacitor portion and the second connection line on the substrate, and the data connection block is respectively connected to the first connection line and the second connection line.

[0207] In an exemplary embodiment, the data connection block and the second data connection portion are located on the same side of the first data connection portion and are electrically connected to the first data connection portion;

[0208] An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the second plate of the capacitor on the substrate.

[0209] In an exemplary embodiment, the pixel circuit further includes: a first light emitting transistor and a second light emitting transistor, the first light emitting transistor being connected to a high voltage power line, the second light emitting transistor being connected to an anode of the light emitting device, and the fourth conductive layer further includes: a first connection electrode, a second connection electrode, a third connection electrode, and a fourth connection electrode;

[0210] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the write transistor of at least one circuit unit located in the first area to the third area, and is electrically connected to the first electrode of the write transistor of at least one circuit unit located in the first area to the third area. The orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area, and is connected to the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area. The orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area, and is connected to the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area. The orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the data connection block on the substrate, and at least partially overlaps with the orthographic projection of the data connection block on the substrate.

[0211] In an exemplary embodiment, the fifth conductive layer further includes a fifth connection electrode, an orthographic projection of the fifth connection electrode on the substrate at least partially overlapping with an orthographic projection of the second connection electrode on the substrate, and connected to the second connection electrode.

[0212] In an exemplary embodiment, orthographic projections of the plurality of first anode connection lines on the substrate may at least partially overlap with orthographic projections of the second plate of the capacitor and the anodes of the connected light emitting devices on the substrate.

[0213] In an exemplary embodiment, an orthographic projection of the data signal line on the substrate at least partially overlaps with an orthographic projection of the first connection electrode on the substrate and is connected to the first connection electrode. An orthographic projection of the first high-voltage power line on the substrate at least partially overlaps with an orthographic projection of the third connection electrode on the substrate and is connected to the third connection electrode. An orthographic projection of the second connection line on the substrate at least partially overlaps with an orthographic projection of the fourth connection electrode on the substrate and is connected to the fourth connection electrode.

[0214] In an exemplary embodiment, the display panel may further include a transparent conductive layer located on a side of the second planar layer away from the substrate, the transparent conductive layer including a second anode connecting line, the second anode connecting line at least partially overlapping with an orthographic projection of the fifth connecting electrode on the substrate, and connected to the fifth connecting electrode.

[0215] The following is an illustrative explanation through the preparation process of the display panel. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display panel. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0216] In an exemplary embodiment, taking 6 circuit units (2 unit rows and 3 unit columns) in the E0 region, the E1 region, and the E2 region, where the circuit units in the Nth column and the N+1th column are driving circuit units and the circuit units in the N+2th column are virtual circuit units as an example, the preparation process of the display panel may include the following steps.

[0217] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG9 , which is a schematic diagram of forming semiconductor patterns in the E0 region, the E1 region, and the E2 region.

[0218] In an exemplary embodiment, as shown in FIG. 9 , the semiconductor layer patterns located in the E0 region, the E1 region, and the E2 region each include an active layer T11 of the first transistor to an active layer T71 of the seventh transistor.

[0219] In an exemplary embodiment, as shown in FIG. 9 , the active layer T11 of the first transistor to the active layer T61 of the sixth transistor are an integral structure connected to each other.

[0220] In an exemplary embodiment, as shown in FIG9 , in a first direction X, the active layer T21 of the second transistor and the active layer T61 of the sixth transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel, and the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the subpixel. In a second direction Y, the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor may be located on the same layer as the active layer T31 of the third transistor in the subpixel, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on the other side of the active layer T31 of the third transistor in the subpixel.

[0221] In an exemplary embodiment, as shown in FIG9 , the active layer T11 of the first transistor may have an “n” shape, the active layer T21 of the second transistor may have an “L” shape, the active layer T31 of the third transistor may have an “Ω” shape, and the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may have an “I” shape.

[0222] In an exemplary embodiment, as shown in FIG9 , the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor may serve as the first region T21_1 of the active layer T21 of the second transistor, the first region T31_1 of the active layer T31 of the third transistor may serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor, and the second region T31_2 of the active layer T31 of the third transistor may serve as the second region T21 of the active layer T21 of the second transistor. T21_2 and the first region T61_1 of the active layer T61 of the sixth transistor, the second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor, the first region T11_1 of the active layer T11 of the first transistor, the first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51_1 of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor can be set separately.

[0223] In an exemplary embodiment, as shown in FIG9 , the shape of the first region T31_1 of the active layer T31 of the third transistor (also the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) may be a strip structure extending along the second direction Y, and the length along the first direction X may be greater than the length of the first region T41_1 of the active layer T41 of the fourth transistor and the first region T51_1 of the active layer T51 of the fifth transistor.

[0224] In exemplary embodiments, the semiconductor patterns of the E1 and E2 regions in FIG. 9 are substantially the same as the semiconductor pattern of the E0 region.

[0225] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as shown in Figures 10 and 11, wherein Figure 10 is a schematic diagram of the first conductive layer pattern in the E0 region, the E1 region, and the E2 region, and Figure 11 is a schematic diagram of the E0 region, the E1 region, and the E2 region after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0226] In an exemplary embodiment, as shown in FIG. 10 and FIG. 11 , the first conductive layer patterns in the E0 region, the E1 region, and the E2 region may each include a scan signal line GL, a reset signal line RL, a light emitting signal line EL, and a first plate C1 of a capacitor.

[0227] In an exemplary embodiment, as shown in Figures 10 and 11 , the first plate C1 of the capacitor may be rectangular, with chamfered corners. The orthographic projection of the first plate C1 of the capacitor on the substrate at least partially overlaps the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first plate C1 of the capacitor may also serve as the control electrode T32 of the third transistor.

[0228] In an exemplary embodiment, as shown in Figures 10 and 11, the reset signal line RL can be shaped like a line extending along a first direction X. The reset signal line RL can be located on the side of the first plate C1 of the capacitor away from the light-emitting signal line EL. The area where the reset signal line RL overlaps with the active layer of the first transistor serves as the control electrode T12 of the first transistor, and the area where the reset signal line RL overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor. Because the active layer T11 of the first transistor can be shaped like an "n," there are two areas where the reset signal line RL overlaps with the active layer of the first transistor. In other words, the first transistor has two control electrodes T12, indicating that the first transistor has a dual-gate structure.

[0229] In an exemplary embodiment, as shown in Figures 10 and 11, the scan signal line GL may be in the shape of a line extending along a first direction X. The scan signal line GL may be located between the first plate C1 of the capacitor and the reset signal line RL. The region where the scan signal line GL overlaps with the active layer of the second transistor serves as the control electrode T22 of the second transistor, and the region where the scan signal line GL overlaps with the active layer of the fourth transistor serves as the control electrode T42 of the fourth transistor. The control electrode T22 of the second transistor overlaps with the active layer T21 of the second transistor in two regions, meaning that the second transistor has two control electrodes T22, and the second transistor has a dual-gate structure.

[0230] In an exemplary embodiment, as shown in Figures 10 and 11, the shape of the light-emitting signal line EL can be a line shape extending along the first direction X, and the area where the light-emitting signal line EL overlaps with the active layer of the fifth transistor serves as the control electrode T52 of the fifth transistor, and the area where the light-emitting signal line EL overlaps with the active layer of the sixth transistor serves as the control electrode T62 of the sixth transistor.

[0231] In an exemplary embodiment, as shown in Figures 10 and 11, the scanning signal line GL, the reset signal line RL and the light-emitting signal line EL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0232] In an exemplary embodiment, as shown in FIG11 , after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first to seventh transistors T1 to T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductively processed. That is, the first and second areas of the active layers of the first to seventh transistors are both conductively processed, and the first area of ​​the active layer of the third transistor (which is also the second area of ​​the active layer of the fourth transistor and the second area of ​​the active layer of the fifth transistor) after conductive processing can simultaneously serve as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, and the second electrode T54 of the fifth transistor. The second area of ​​the active layer of the third transistor (which is also the second area of ​​the active layer of the second transistor and the first area T61_1 of the active layer of the sixth transistor) after conductive processing also simultaneously serves as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor.

[0233] In exemplary embodiments, the first conductive layer patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the first conductive layer pattern of the E0 region.

[0234] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer. As shown in Figures 12 to 15, Figure 12 is a schematic diagram of the first conductive layer pattern of the E0 region and the E1 region, Figure 13 is a schematic diagram of the E0 region and the E1 region after the first conductive layer pattern is formed, Figure 14 is a schematic diagram of the first conductive layer pattern of the E2 region, and Figure 15 is a schematic diagram of the E2 region after the first conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0235] In exemplary embodiments, as shown in FIG. 12 to FIG. 15 , the second conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include a first initial signal line INIL1 , a second initial signal line INIL2 , and a second plate C2 of a capacitor.

[0236] In an exemplary embodiment, as shown in FIG12 to FIG15 , the first initial signal line INIL1 and the second initial signal line INIL2 may have a line shape whose main portion may extend along the first direction X. The first initial signal line INIL1 in the M-th row of circuit units may be located between the reset signal line RL and the scan signal line GL of the circuit unit, and the second initial signal line INIL2 may be located on a side of the reset signal line RL of the circuit unit away from the scan signal line GL.

[0237] In an exemplary embodiment, as shown in Figures 12 to 15, the outline shape of the second electrode plate C2 can be rectangular, and the corners of the rectangle can be chamfered. There is an overlapping area between the orthographic projection of the second electrode plate C2 on the substrate and the orthographic projection of the first electrode plate C1 on the substrate. The second electrode plate C2 serves as another electrode plate of the capacitor and is located between the scanning signal line GL and the light-emitting signal line EL of this circuit unit. The first electrode plate C1 and the second electrode plate C2 constitute the capacitor of the pixel circuit.

[0238] In an exemplary embodiment, the second plates C2 of adjacent circuit units are interconnected. This interconnection of the second plates C2 of adjacent circuit units allows the second plates of multiple circuit units in a unit row to form an interconnected integrated structure. The second plates of the integrated structure can be reused as power signal connection lines, ensuring that the multiple second plates in a unit row have the same potential, which helps improve the uniformity of the display panel, avoid display defects on the display panel, and ensure the display quality of the display panel.

[0239] In an exemplary embodiment, an opening V is provided on the second plate C2, which may be located in the middle of the second plate C2. The opening V may be rectangular, forming a ring-shaped structure. The opening V exposes the second insulating layer covering the first plate C1, and the orthographic projection of the first plate C1 on the substrate includes the orthographic projection of the opening V on the substrate. In an exemplary embodiment, the opening V is configured to accommodate a seventh via hole, which is formed later. The seventh via hole is located within the opening V and exposes the first plate C1, thereby connecting the second electrode of the first transistor T1 formed later to the first plate C1.

[0240] In an exemplary embodiment, as shown in FIG. 12 and FIG. 13 , the second conductive layer pattern of the E1 region is substantially the same as the second conductive layer pattern of the E0 region.

[0241] In an exemplary embodiment, the second electrode plate in the second conductive layer pattern of the E2 region differs from the second electrode plate in the second conductive layer pattern of the E0 region. As shown in Figures 14 and 15, the second electrode plate in the second conductive layer pattern of the E2 region may include: an integrally formed capacitor main portion C_main and an auxiliary capacitor portion C0.

[0242] In an exemplary embodiment, as shown in Figures 14 and 15, the shape of the capacitor main portion C_main is the same as the shape of the second electrode C2 in the second conductive layer pattern of the E0 region and the E1 region. The orthographic projection of the auxiliary capacitor portion C0 on the substrate at least partially overlaps the orthographic projection of the active layer of the fourth transistor on the substrate.

[0243] In an exemplary embodiment, the auxiliary capacitor portion can play a role in leveling the data connection block, thereby improving the display effect of the display panel.

[0244] In an exemplary embodiment, as shown in Figures 12 to 15, the first initial signal line INIL1 and the second initial signal line INIL2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0245] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG16 and FIG17 , wherein FIG16 is a schematic diagram of forming the third insulating layer pattern in the E0 region and the E1 region, and FIG17 is a schematic diagram of forming the third insulating layer pattern in the E2 region.

[0246] In an exemplary embodiment, as shown in Figures 16 and 17, the multiple vias in the third insulating layer of the E0 region, the E1 region, and the E2 region may each include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0247] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor T1 on the substrate. The first insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first transistor T1. The first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the active layer of the first transistor T1 through the via hole.

[0248] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor T1 (also the first region of the active layer of the second transistor T2) on the substrate, the first insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active layer of the first transistor T1 (also the first region of the active layer of the second transistor T2), and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to the first region of the active layer of the first transistor T1 (also the first region of the active layer of the second transistor T2) through the via.

[0249] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fourth transistor T4 on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the surface of the first region of the active layer of the fourth transistor T4, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fourth transistor to the first region of the active layer of the fourth transistor T4 through the via hole.

[0250] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth transistor T5 on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the first region of the active layer of the fifth transistor T5, and the fourth via hole V4 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the first region of the active layer of the fifth transistor T5 through the via hole.

[0251] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the sixth transistor T6 (also the second region of the active layer of the seventh transistor T7) on the substrate, the first insulating layer and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the active layer of the sixth transistor T6 (also the second region of the active layer of the seventh transistor T7), and the fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) to the second region of the active layer of the sixth transistor T6 (also the second region of the active layer of the seventh transistor T7) through the via.

[0252] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the seventh transistor T7 on the substrate, the first insulating layer and the second insulating layer within the sixth via hole V6 are etched away, exposing the surface of the first region of the active layer of the seventh transistor T7, and the sixth via hole V6 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the first region of the active layer of the seventh transistor T7 through the via hole.

[0253] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the opening on the substrate, the second insulating layer in the seventh via V7 is etched away, exposing the surface of the first plate of the first capacitor (also the control electrode of the third transistor), and the seventh via V7 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to the first plate of the first capacitor (also the control electrode of the third transistor T3) through the via.

[0254] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first initial signal line INIL1 on the substrate, the eighth via V8 exposes the surface of the first initial signal line INIL1, and the eighth via V8 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line INIL1 through the via.

[0255] In an exemplary embodiment, as shown in Figures 16 and 17, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second initial signal line INIL2 on the substrate, the ninth via V9 exposes the surface of the second initial signal line INIL2, and the ninth via V9 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line INIL2 through the via.

[0256] In an exemplary embodiment, as shown in Figures 16 and 17 , the orthographic projection of the tenth via V10 on the substrate is within the orthographic projection of the second plate of the capacitor on the substrate. The tenth via V10 exposes the surface of the second plate of the capacitor. The tenth via V10 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the second plate of the capacitor through the via. In an exemplary embodiment, there may be multiple tenth vias V10, and the multiple tenth vias V10 may be arranged sequentially along the second direction Y to improve connection reliability.

[0257] In an exemplary embodiment, as shown in FIG. 16 and FIG. 17 , the via hole pattern of the third insulating layer of the E1 region and the E2 region is substantially the same as the via hole pattern of the third insulating layer of the E0 region.

[0258] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in Figures 18 to 21. Figure 18 is a schematic diagram of the third conductive layer pattern in the E0 region and the E1 region, Figure 19 is a schematic diagram after the third conductive layer pattern is formed in the E0 region and the E1 region, Figure 20 is a schematic diagram of the third conductive layer pattern in the E2 region, and Figure 21 is a schematic diagram after the third conductive layer pattern is formed in the E2 region. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0259] In an exemplary embodiment, as shown in FIG18 to FIG21, the third conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include: a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, and a first electrode T73 and a second electrode T74 of a seventh transistor.

[0260] In an exemplary embodiment, as shown in Figures 18 to 21, the second electrode T14 of the first transistor can simultaneously serve as the first electrode T23 of the second transistor, the second electrode T64 of the sixth transistor can simultaneously serve as the second electrode T74 of the seventh transistor, and the first electrode T13 of the first transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor can be set separately.

[0261] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the third conductive layer pattern of the E2 region may further include a data connection block 73 and a first connection line 71 .

[0262] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the orthographic projection of the data connection block 73 on the substrate at least partially overlaps with the orthographic projection of the auxiliary capacitor portion on the substrate.

[0263] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the first connection line 71 is connected to the data connection block 73 and is an integrally formed structure.

[0264] In an exemplary embodiment, as shown in Figures 20 and 21, the first connection line 71 may include a first data connection portion 71A and a second data connection portion 71B. The first data connection portion 71A is connected to a data connection block 73 and a second data connection portion 71B, respectively. The data connection block 73 and the second data connection portion 71B are located on the same side of the first data connection portion 71A. The orthographic projection of the first data connection portion 71A on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate.

[0265] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the main portion of the first data connection portion 71A may be a line extending in the second direction Y, and the main portion of the second data connection portion 71B may be a line extending in the first direction X.

[0266] In an exemplary embodiment, as shown in Figures 18 to 21, the first electrode T13 of the first transistor may be in the shape of a line having a main portion extending along a first direction X. The first electrode T13 of the first transistor may be located between the scan signal line GL and the reset signal line RL. The orthographic projection of the first electrode T13 of the first transistor on the substrate may partially overlap with the orthographic projection of the first via and the first initial signal line INIL1 on the substrate. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor via the first via and is connected to the first initial signal line INIL1 via the eighth via.

[0267] In an exemplary embodiment, as shown in Figures 18 to 21, the second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) can be shaped like a line extending along the second direction Y, and the second electrode T14 of the first transistor (also the first electrode T13 of the second transistor) can be located on a side of the first initial signal line INIL1 away from the reset signal line RL. The orthographic projection of the second electrode T14 of the first transistor (also the first electrode T13 of the second transistor) on the substrate can at least partially overlap with the orthographic projections of the second via, the seventh via, the first plate of the first capacitor, and the second plate of the first capacitor on the substrate. The second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) is connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through the second via, and is connected to the first plate of the first capacitor through the seventh via.

[0268] In an exemplary embodiment, as shown in Figures 18 to 21, the first electrode T43 of the fourth transistor may be in a block-like structure and may be located between the first initial signal line INIL1 and the scan signal line GL. An orthographic projection of the first electrode T43 of the fourth transistor on the substrate at least partially overlaps with the third via. The first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the third via.

[0269] In an exemplary embodiment, as shown in FIG. 18 to FIG. 21 , the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) and the first electrode T53 of the fifth transistor are respectively located on both sides of the second electrode T14 of the first transistor (also the first electrode T23 of the second transistor).

[0270] In an exemplary embodiment, as shown in Figures 18 to 21, the shape of the first electrode T53 of the fifth transistor can be linear and extend along the second direction Y. The first electrode T53 of the fifth transistor in the M-th row of circuit units can be located between the scan signal line GL of the M-th row of circuit units and the second initial signal line INIL2 of the M+1-th row of circuit units. The orthographic projection of the first electrode T53 of the fifth transistor on the substrate can at least partially overlap with the orthographic projection of the fourth via, the tenth via, the light-emitting signal line, and the second plate of the capacitor on the substrate. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the fourth via, and is connected to the orthographic projection of the second plate of the capacitor on the substrate through the tenth via.

[0271] In an exemplary embodiment, as shown in Figures 18 to 21, the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) can be a block structure. The second pole T64 of the sixth transistor of the M-th row circuit unit (the second pole T74 of the seventh transistor) can be located between the scan signal line GL of the M-th row circuit unit and the second initial signal line INIL2 of the M+1-th row circuit unit. The orthographic projection of the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) on the substrate can at least partially overlap with the orthographic projection of the fifth via on the substrate. The second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor) through the fifth via.

[0272] In an exemplary embodiment, as shown in Figures 18 to 21, the orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) of the dummy pixel circuit on the substrate does not overlap with the orthographic projection of the light emitting signal line on the substrate. The orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) of the pixel circuit on the substrate at least partially overlaps with the orthographic projection of the light emitting signal line on the substrate.

[0273] In an exemplary embodiment, as shown in Figures 18 to 21, the first electrode T73 of the seventh transistor can be linear and extend along the second direction Y. The first electrode T73 of the seventh transistor is located on a side of the first initial signal line INIL1 away from the scan signal line GL. The orthographic projection of the first electrode T73 of the seventh transistor on the substrate at least partially overlaps with the orthographic projections of the sixth via, the ninth via, the reset signal line RL, and the second initial signal line INIL2 on the substrate. The first electrode of the seventh transistor is connected to the first region of the active layer of the seventh transistor via the sixth via and is connected to the second initial signal line via the ninth via.

[0274] In an exemplary embodiment, as shown in FIG. 18 and FIG. 19 , the third conductive layer pattern of the E1 region is substantially the same as the third conductive layer pattern of the E0 region.

[0275] (6) Forming a fourth insulating layer. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG22 and FIG23 , wherein FIG22 is a schematic diagram of forming the fourth insulating layer pattern in the E0 region and the E1 region, and FIG23 is a schematic diagram of forming the fourth insulating layer pattern in the E2 region.

[0276] In an exemplary embodiment, as shown in FIG. 22 and FIG. 23 , the plurality of via holes of the fourth insulation layer pattern of the E0 region, the E1 region, and the E2 region may each include an eleventh via hole V11 , a twelfth via hole V12 , and a thirteenth via hole V13 .

[0277] In an exemplary embodiment, as shown in FIG. 23 , the plurality of via holes of the fourth insulation layer pattern of the E2 region may further include a fourteenth via hole V14 .

[0278] In an exemplary embodiment, as shown in Figures 22 and 23, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor in the driving circuit unit in the E0 region and the E1 region and the driving circuit unit and the dummy circuit unit in the E2 region on the substrate, the eleventh via V11 exposes the first electrode of the fourth transistor in the driving circuit unit in the E0 region and the E1 region and the driving circuit unit and the dummy circuit unit in the E2 region, and the eleventh via V11 is configured to connect a subsequently formed first connecting electrode to the first electrode of the fourth transistor in the driving circuit unit in the E0 region and the E1 region and the driving circuit unit and the dummy circuit unit in the E2 region through the via.

[0279] In an exemplary embodiment, as shown in Figures 22 and 23, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, and the twelfth via V12 exposes the first electrode of the fifth transistor. The twelfth via V12 in the E0 region is configured to connect the subsequently formed third connection electrode to the first electrode of the fifth transistor through the via. The twelfth via V12 in the E1 region is configured to connect the subsequently formed first sub-high-voltage power line to the first electrode of the fifth transistor through the via. The twelfth via V12 in the E2 region is configured to connect the subsequently formed third high-voltage power line to the first electrode of the fifth transistor through the via.

[0280] In an exemplary embodiment, as shown in Figures 22 and 23, the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the second electrode of the sixth transistor (the second electrode of the seventh transistor) in the driving circuit units located in the E0 region, the E1 region, and the E2 region on the substrate. The thirteenth via hole V13 exposes the second electrode of the sixth transistor (the second electrode T74 of the seventh transistor) in the driving circuit units in the E0 region, the E1 region, and the E2 region. The thirteenth via hole V13 is configured to connect a subsequently formed second connection electrode to the second electrode of the sixth transistor (the second electrode of the seventh transistor) in the driving circuit units in the E0 region, the E1 region, and the E2 region through the via hole.

[0281] In an exemplary embodiment, as shown in FIG23 , the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the data connection block on the substrate, the fourteenth via hole V14 exposes the data connection block, and the fourteenth via hole V14 is configured to connect a subsequently formed fourth connection electrode to the data connection block through the via hole.

[0282] In an exemplary embodiment, as shown in FIG. 22 , the fourth insulation layer pattern of the E1 region is substantially the same as the fourth insulation layer pattern of the E0 region.

[0283] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer, as shown in Figures 24A, 24B, 25A, 25B, and 26 to 29, wherein Figure 24A is a schematic diagram of the fourth conductive layer pattern in the E0 region, Figure 24B is a schematic diagram of the fourth conductive layer pattern in the E0 region, Figure 25A is a schematic diagram of the fourth conductive layer pattern in the E0 region, Figure 25B is a schematic diagram of the fourth conductive layer pattern in the E0 region, Figure 26 is a schematic diagram of the fourth conductive layer pattern in the E1 region, Figure 27 is a schematic diagram of the fourth conductive layer pattern in the E1 region, Figure 28 is a schematic diagram of the fourth conductive layer pattern in the E2 region, and Figure 29 is a schematic diagram of the fourth conductive layer pattern in the E2 region. In an exemplary embodiment, the fourth conductive layer may be referred to as an intermediate source-drain metal (SDM) layer. 24A and 24B are described by taking an example in which the fourth conductive layer does not include the first anode connecting line, and FIG. 25A and 25B are described by taking an example in which the fourth conductive layer includes the first anode connecting line.

[0284] In exemplary embodiments, as shown in FIG. 24A to FIG. 29 , the fourth conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include a first connection electrode VL1 and a second connection electrode VL2 .

[0285] In exemplary embodiments, as shown in FIG. 24A and FIG. 24B , the fourth conductive layer pattern of the E0 region may further include a third connection electrode VL3 .

[0286] In an exemplary embodiment, as shown in FIG. 25A and FIG. 25B , the fourth conductive layer pattern of the E0 region may further include a third link electrode VL3 and a plurality of first anode link lines AL1 .

[0287] In an exemplary embodiment, as shown in FIG. 26 and FIG. 27 , the fourth conductive layer pattern of the E1 region may further include a first sub-high-voltage power line VLB1 in the second high-voltage power line.

[0288] In an exemplary embodiment, as shown in FIG. 28 and FIG. 29 , the fourth conductive layer pattern of the E2 region may further include a third high-voltage power line VLC and a fourth connection electrode VL4 .

[0289] In an exemplary embodiment, as shown in Figures 24A to 29, the first connection electrode VL1 may be in the form of a block structure. The orthographic projection of the first connection electrode VL1 on the substrate may partially overlap with the orthographic projection of the eleventh via hole on the substrate. The first connection electrode VL1 is connected to the first electrode of the fourth transistor in the drive circuit unit in the E0 region and the E1 region, as well as the drive circuit unit and the dummy circuit unit in the E2 region through the eleventh via hole.

[0290] In an exemplary embodiment, the first connection electrode serves to connect the data signal line and the first electrode of the fourth transistor, thereby avoiding unreliable connection caused by a deep via hole, thereby improving the reliability of the display panel.

[0291] In an exemplary embodiment, as shown in Figures 24A to 29, the second connection electrode VL2 may be in the shape of a block structure. The orthographic projection of the second connection electrode VL2 on the substrate may partially overlap with the orthographic projection of the thirteenth via hole on the substrate. The second connection electrode VL2 is connected to the second electrode of the sixth transistor (the second electrode of the seventh transistor) in the driving circuit unit of the E0 region, the E1 region, and the E2 region through the thirteenth via hole.

[0292] In an exemplary embodiment, the second connection electrode serves to connect the fifth connection electrode and the second electrode of the sixth transistor (the second electrode of the seventh transistor), thereby improving the reliability of the display panel by avoiding unreliable connection caused by opening a deeper via hole.

[0293] In an exemplary embodiment, as shown in Figures 24A, 24B, 25A, and 25B, the third connection electrode VL3 may be in a block-like structure. The orthographic projection of the third connection electrode VL3 on the substrate may partially overlap with the orthographic projection of the twelfth via hole on the substrate. The third connection electrode VL3 is connected to the first electrode of the fifth transistor through the twelfth via hole.

[0294] In an exemplary embodiment, the third connection electrode serves to connect the first high-voltage power line and the first electrode of the fifth transistor, thereby improving the reliability of the display panel by avoiding unreliable connection caused by opening a deep via hole.

[0295] In an exemplary embodiment, as shown in Figures 25A and 25B, the shape of the first anode connection line AL1 can be a line extending along the first direction X. The orthographic projections of the plurality of first anode connection lines AL1 on the substrate can overlap with the orthographic projections of the first electrode of the seventh transistor and the second electrode plate of the capacitor in the E0 region on the substrate. The first anode connection line AL1 is configured to be connected to the anode of a subsequently formed light-emitting device.

[0296] In an exemplary embodiment, as shown in Figures 26 and 27 , the first sub-high-voltage power line VLB1 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first sub-high-voltage power line VLB1 is configured to provide a high power supply voltage signal to the first electrode of the fifth transistor. The orthographic projection of the first sub-high-voltage power line VLB1 on the substrate overlaps with the twelfth via and the orthographic projection of the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate. The first sub-high-voltage power line VLB1 is connected to the first electrode of the fifth transistor through the twelfth via.

[0297] In an exemplary embodiment, as shown in Figures 28 and 29, the third high-voltage power line VLC may be shaped like a zigzag line with a main portion extending along the second direction Y. The third high-voltage power line VLC is configured to provide a high power supply voltage signal to the first electrode of the fifth transistor in region E2. The orthographic projection of the third high-voltage power line VLC on the substrate overlaps with the orthographic projection of the twelfth via and the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate. The third high-voltage power line VLC is connected to the first electrode of the fifth transistor through the twelfth via.

[0298] In an exemplary embodiment, the pattern of the third high-voltage power line VLC is substantially the same as that of the first sub-high-voltage power line VLB1 and they are connected to each other. The third high-voltage power line VLC and the first sub-high-voltage power line VLB1 are integrally formed.

[0299] In an exemplary embodiment, the length of the third high voltage power line along the first direction X may be approximately equal to the length of the first sub high voltage power line VLB1 along the first direction X.

[0300] In an exemplary embodiment, as shown in Figures 28 and 29, the fourth connection electrode VL4 may be in a block-like structure. The orthographic projection of the fourth connection electrode VL4 on the substrate may at least partially overlap with the orthographic projection of the data connection block on the substrate. The fourth connection electrode VL4 is connected to the data connection block through a fourteenth via hole.

[0301] In an exemplary embodiment, the fourth connection electrode plays a role in connecting the data connection block and the second connection line, thereby avoiding unreliable connection caused by opening a deep via hole, thereby improving the reliability of the display panel.

[0302] (8) Forming a first flat layer pattern. In an exemplary embodiment, forming the first flat layer pattern may include: coating a first flat film on the substrate on which the aforementioned pattern is formed, patterning the first flat film using a patterning process to form a first flat layer covering the fourth conductive layer, wherein a plurality of vias are provided on the first flat layer, as shown in FIG30 to FIG32 , wherein FIG30 is a schematic diagram of the E0 region after the first flat layer pattern is formed, FIG31 is a schematic diagram of the E1 region after the first flat layer pattern is formed, and FIG32 is a schematic diagram of the E2 region after the first flat layer pattern is formed.

[0303] In an exemplary embodiment, as shown in FIG. 30 to FIG. 32 , the plurality of via holes of the first planarization layer pattern of the E0 region, the E1 region, and the E2 region may each include a fifteenth via hole V15 and a sixteenth via hole V16 .

[0304] In an exemplary embodiment, as shown in FIG. 30 , the plurality of via holes of the first planar layer pattern of the E0 region may further include a seventeenth via hole V17 .

[0305] In an exemplary embodiment, as shown in FIG. 31 , the plurality of via holes of the first planar layer pattern of the E1 region may further include an eighteenth via hole V18 .

[0306] In an exemplary embodiment, as shown in FIG. 32 , the plurality of via holes of the first planar layer pattern of the E2 region may further include a nineteenth via hole V19 .

[0307] In an exemplary embodiment, as shown in Figures 30 to 32, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first connection electrode on the substrate, the fifteenth via hole V15 exposes the first connection electrode, and the fifteenth via hole V15 is configured to connect a subsequently formed data signal line to the first connection electrode through the via hole.

[0308] In an exemplary embodiment, as shown in Figures 30 to 32, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second connecting electrode on the substrate, the sixteenth via hole V16 exposes the second connecting electrode, and the sixteenth via hole V16 is configured to connect the subsequently formed fifth connecting electrode to the second connecting electrode through the via hole.

[0309] In an exemplary embodiment, as shown in FIG30 , the orthographic projection of the seventeenth via hole V17 on the substrate is within the range of the orthographic projection of the third connection electrode on the substrate, and the seventeenth via hole V17 exposes the third connection electrode. The seventeenth via hole V17 is configured to connect a subsequently formed first high-voltage power line to the third connection electrode through the via hole.

[0310] In an exemplary embodiment, as shown in FIG31 , the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the first sub-high-voltage power line of the second high-voltage power line on the substrate, and the eighteenth via V18 exposes the first sub-high-voltage power line. The eighteenth via V18 is configured to connect the subsequently formed second sub-high-voltage power line of the second high-voltage power line to the first sub-high-voltage power line of the second high-voltage power line through the via.

[0311] In an exemplary embodiment, as shown in FIG32 , the orthographic projection of the nineteenth via hole V19 on the substrate is within the range of the orthographic projection of the fourth connection electrode on the substrate, and the nineteenth via hole V19 exposes the fourth connection electrode. The nineteenth via hole V19 is configured to allow a subsequently formed second connection line to be connected to the fourth connection electrode through the via hole.

[0312] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer. FIG33 is a schematic diagram of the fifth conductive layer pattern in the E0 region, FIG34 is a schematic diagram after the fifth conductive layer pattern is formed in the E0 region, FIG35 is a schematic diagram of the fifth conductive layer pattern in the E1 region, FIG36 is a schematic diagram after the fifth conductive layer pattern is formed in the E1 region, FIG37 is a schematic diagram of the fifth conductive layer pattern in the E2 region, and FIG38 is a schematic diagram after the fifth conductive layer pattern is formed in the E2 region. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0313] In exemplary embodiments, as shown in FIG. 33 to FIG. 38 , the fifth conductive layer patterns of the E0 region, the E1 region, and the E2 region may each include a data signal line DL and a fifth link electrode VL5 .

[0314] In an exemplary embodiment, as shown in FIG. 33 and FIG. 34 , the fifth conductive layer pattern of the E0 region may further include a first high-voltage power line VLA.

[0315] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 , the fifth conductive layer pattern of the E1 region may further include a second sub-high-voltage power line VLB2 .

[0316] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38 , the fifth conductive layer pattern of the E2 region may further include a second connection line 72 .

[0317] In an exemplary embodiment, as shown in Figures 33 to 38, the data signal lines DL located in regions E0 to E2 and connected to the driving circuit units in the same column are interconnected and are the same data signal line. The data signal lines DL located in region E2 and connected to the dummy driving circuit units in the same column are interconnected and are the same data signal line. The data signal lines DL located in regions E0 and E1 and connected to adjacent circuit units are spaced apart.

[0318] In an exemplary embodiment, as shown in Figures 33 to 38, the shape of the data signal line DL may be a line extending along the second direction Y. The orthographic projection of the data signal line DL on the substrate at least partially overlaps with the orthographic projection of the fifteenth via hole on the substrate. The data signal line DL is connected to the first connection electrode through the fifteenth via hole.

[0319] In an exemplary embodiment, as shown in Figures 33 to 38, the fifth connection electrode VL5 may be in a block-like shape. The orthographic projection of the fifth connection electrode VL5 on the substrate partially overlaps the orthographic projection of the sixteenth via hole on the substrate. The fifth connection electrode VL5 is connected to the second connection electrode through the sixteenth via hole.

[0320] In an exemplary embodiment, the fifth connection electrode plays the role of receiving the anode of the light emitting device and the second connection line, thereby avoiding the unreliable connection caused by opening a deep via hole, thereby improving the reliability of the display panel.

[0321] In an exemplary embodiment, as shown in Figures 33 and 34 , the first high-voltage power line VLA may be shaped like a zigzag line with a main portion extending along the second direction Y. The first high-voltage power line VLA is configured to provide a high power supply voltage signal to the first electrode of the fifth transistor in the E0 region. The first high-voltage power line VLA is located between the data line DL and the fifth connection electrode VL5. The orthographic projection of the first high-voltage power line VLA on the substrate overlaps with the seventeenth via and the orthographic projection of the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate, respectively. The first high-voltage power line VLA is connected to the third connection electrode through the seventeenth via.

[0322] In an exemplary embodiment, as shown in FIG. 33 and FIG. 34 , the length of the data signal line DL along the first direction is shorter than the length of the first high-voltage power line VLA along the first direction.

[0323] In an exemplary embodiment, the first high voltage power line VLA may have substantially the same pattern as the third high voltage power line and the first sub high voltage power line, respectively.

[0324] In an exemplary embodiment, the length of the first high voltage power line VLA along the first direction may be substantially the same as the lengths of the third high voltage power line and the first sub high voltage power line along the first direction.

[0325] In an exemplary embodiment, as shown in Figures 35 and 36 , the second sub-high-voltage power line VLB2 may be shaped like a zigzag line with a main portion extending along the second direction Y. The second sub-high-voltage power line VLB2 is configured to provide a high power supply voltage signal to the first electrode of the fifth transistor in region E1. The second sub-high-voltage power line VLB2 is located between the data line DL and the fifth connection electrode VL5. The orthographic projections of the second sub-high-voltage power line VLB2 on the substrate overlap with the orthographic projections of the eighteenth via holes on the substrate. The second sub-high-voltage power line VLB2 is connected to the first sub-high-voltage power line VLB2 through the eighteenth via holes.

[0326] In an exemplary embodiment, the second sub high-voltage power line VLB2 is connected to the first high-voltage power line.

[0327] In an exemplary embodiment, as shown in FIG. 35 and FIG. 36 , the length of the data signal line DL along the first direction is substantially the same as the length of the second sub high-voltage power line VLB2 along the first direction.

[0328] In an exemplary embodiment, as shown in Figures 37 and 38, the second connection line 72 may be in the shape of a line with a main portion extending along the second direction Y. The second connection line 72 is located between the data signal line DL and the fifth connection electrode VL5. The orthographic projection of the second connection line 72 on the substrate overlaps with the nineteenth via hole and the orthographic projection of the first connection line on the substrate. The second connection line 72 is connected to the fourth connection electrode through the nineteenth via hole.

[0329] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38 , the pattern of the second connection line 72 may be substantially the same as the pattern of the second sub-high-voltage power line.

[0330] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38 , the second connection line 72 at least partially overlaps with an orthographic projection of the third high-voltage power line on the substrate.

[0331] In an exemplary embodiment, as shown in FIG. 37 and FIG. 38 , the length of the data signal line DL along the first direction may be substantially the same as the length of the second connection line 72 along the first direction.

[0332] (10) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the fifth conductive layer, wherein a plurality of vias are provided on the second flat layer, as shown in FIG39 to FIG41 , wherein FIG39 is a schematic diagram of the E0 region after the second flat layer pattern is formed, FIG40 is a schematic diagram of the E1 region after the second flat layer pattern is formed, and FIG41 is a schematic diagram of the E2 region after the second flat layer pattern is formed.

[0333] In an exemplary embodiment, as shown in FIG. 39 to FIG. 41 , the plurality of via holes of the second planarization layer pattern of the E0 region, the E1 region, and the E2 region may each include a twentieth via hole V20 .

[0334] In an exemplary embodiment, as shown in Figures 39 to 41, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the fifth connection electrode on the substrate, and the twentieth via hole V20 exposes the fifth connection electrode. The twentieth via hole V20 is configured to connect the anode of the subsequently formed light-emitting device to the fifth connection electrode through the via hole. To accommodate the connection with the subsequently formed anode, the position of the twentieth via hole V20 in multiple circuit units may be different.

[0335] In exemplary embodiments, the via hole patterns of the second planarization layer patterns of the E0 region, the E1 region, and the E2 region are substantially the same.

[0336] (11) Forming a third flat layer pattern. In an exemplary embodiment, forming the third flat layer pattern may include: coating a transparent conductive film on the substrate having the aforementioned pattern formed thereon, patterning the transparent conductive film using a patterning process to form a transparent conductive layer covering the second flat layer; coating a third flat film on the substrate having the transparent conductive layer pattern formed thereon, patterning the third flat film using a patterning process to form a third flat layer covering the transparent conductive layer, wherein the third flat layer is provided with a via hole exposing the fifth connection electrode. The transparent conductive layer may include: a second anode connection line.

[0337] At this point, the drive circuit layer is prepared on the substrate. On a plane parallel to the display panel, the drive circuit layer may include multiple circuit units, each circuit unit may include a pixel circuit, and a scan signal line, a reset signal line, a light-emitting signal line, a data signal line, a high-voltage power line, a low-voltage power line, a first initial signal line, and a second initial signal line connected to the pixel circuit. On a plane perpendicular to the display panel, the drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a transparent conductive layer, and a third flat layer stacked in sequence on the substrate.

[0338] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0339] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0340] In an exemplary embodiment, the transparent conductive layer may be made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a multi-layer composite structure, such as ITO / Ag / ITO.

[0341] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer, the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer. The first flat layer, the second flat layer and the third flat layer may be made of an organic material, such as a resin. The semiconductor layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, and the like. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0342] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0343] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer pattern disposed on the third flat layer, as shown in FIG42 to FIG45 , FIG42 is a schematic diagram of the anode conductive layer pattern, FIG43 is a schematic diagram of the anode conductive layer pattern formed in the E0 region, FIG44 is a schematic diagram of the anode conductive layer pattern formed in the E1 region, and FIG45 is a schematic diagram of the anode conductive layer pattern formed in the E2 region.

[0344] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0345] In an exemplary embodiment, the anode conductive layer pattern may include a first anode 301R of a red light-emitting device, a second anode 301B of a blue light-emitting device, a third anode 301G1 of a first green light-emitting device, and a fourth anode 301G2 of a second green light-emitting device. The area where the first anode 301R is located can form a red sub-pixel R that emits red light, the area where the second anode 301B is located can form a blue sub-pixel B that emits blue light, the area where the third anode 301G1 is located can form a first green sub-pixel G1 that emits green light, and the area where the fourth anode 301G2 is located can form a second green sub-pixel G2 that emits green light.

[0346] In an exemplary embodiment, the first anode 301A and the second anode 301B may be sequentially arranged along the second direction Y, the third anode 301C and the fourth anode 301D may be sequentially arranged along the second direction Y, and the third anode 301C and the fourth anode 301D may be arranged on one side of the first anode 301A and the second anode 301B in the first direction X. Alternatively, the first anode 301A and the second anode 301B may be sequentially arranged along the first direction X, the third anode 301C and the fourth anode 301D may be sequentially arranged along the first direction X, and the third anode 301C and the fourth anode 301D may be arranged on one side of the first anode 301A and the second anode 301B in the second direction Y.

[0347] In an exemplary embodiment, the first anode 301R, the second anode 301B, the third anode 301G1, and the fourth anode 301G2 can be connected to the fifth connection electrode in the corresponding circuit unit through the twentieth via hole V20. Since each anode is connected to the second electrode of the sixth transistor (also the second electrode of the seventh active layer) through the fifth connection electrode and the second connection electrode in a circuit unit, the four anodes in a light-emitting unit are respectively connected to the pixel circuits of the four circuit units, thereby enabling the pixel circuits to drive the light-emitting device to emit light.

[0348] In an exemplary embodiment, the shape and area of ​​the anodes of the four sub-pixels in a light-emitting unit may be the same or different, the positional relationship between the four sub-pixels of a light-emitting unit and the four circuit units in a circuit unit group may be the same or different, and the shapes and positions of the first anode 301R, the second anode 301B, the third anode 301G1 and the fourth anode 301G2 in different light-emitting units may be the same or different, and the present disclosure is not limited thereto.

[0349] In an exemplary embodiment, at least one of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D may include a main body portion and a connecting portion connected to each other, the main body portion may be rectangular in shape, the corners of the rectangle may be provided with arc-shaped chamfers, the connecting portion may be shaped like a strip extending in a direction away from the main body portion, and the connecting portion is connected to the fifth connecting electrode through twenty vias V20.

[0350] As shown in FIG. 45 , in region E2 , the orthographic projections of the main portions of the first anode 301A, the second anode 301B, the third anode 301C, and the fourth anode 301D on the substrate at least partially overlap with the orthographic projections of the second connection line and the data signal line on the substrate.

[0351] As shown in FIG44 , in the E1 region, the orthographic projections of the main bodies of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D on the substrate at least partially overlap with the orthographic projections of the second sub-high-voltage power line and the data signal line on the substrate.

[0352] As shown in FIG43 , in the E0 region, the orthographic projections of the main bodies of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D on the substrate at least partially overlap with the orthographic projections of the first high-voltage power line and the data signal line on the substrate.

[0353] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0354] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0355] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0356] In an exemplary embodiment, the display panel of the present disclosure can be applied to a display device having a pixel circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and the present disclosure is not limited here.

[0357] Figure 46 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Figure 46, an embodiment of the present disclosure further provides a display device comprising a display panel 1 provided by any of the aforementioned embodiments and a light sensor 2, the light sensor being located within the light-transmitting display area 10 of the display panel 1.

[0358] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the present disclosure is not limited thereto.

[0359] In an exemplary embodiment, when the light-transmitting display area 10 is rectangular, the orthographic projection area of ​​the light-sensitive sensor 2 on the substrate is smaller than or equal to the area of ​​the inscribed circle of the light-transmitting display area 10 .

[0360] In an exemplary embodiment, the photosensitive sensor 2 may include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0361] In an exemplary embodiment, the front-facing camera module is typically activated when a user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained from the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, and an image processing chip. The optical image of the scene generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS), converted into an electrical signal, and then converted into a digital image signal through analog-to-digital conversion by the image processing chip. The digital image signal is then sent to the processor for processing and output on the display screen.

[0362] In an exemplary embodiment, a 3D structured light sensor and a time of flight (ToF) sensor may be used for face recognition to unlock the display device.

[0363] The display device provided by the embodiment of the present disclosure can display images in the light-transmitting display area to maintain the display integrity of the entire display device.

[0364] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0365] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0366] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display panel, comprising: a display area, the display area comprising: a light-transmitting display area and a conventional display area located on at least one side of the light-transmitting display area, the conventional display area comprising a first area, a second area, and a third area, at least one circuit unit in the first area being connected to the light-emitting device in the light-transmitting display area, at least one circuit unit in the third area comprising a data connection line, the high-voltage power line located in the first area being a first high-voltage power line, the high-voltage power line located in the second area being a second high-voltage power line, and the high-voltage power line located in the third area being a third high-voltage power line; The second high-voltage power line includes: a first sub-high-voltage power line and a second sub-high-voltage power line connected to each other, the second sub-high-voltage power line is located on the side of the first sub-high-voltage power line away from the substrate, the first high-voltage power line and the second sub-high-voltage power line are arranged on the same layer, and the third high-voltage power line and the first sub-high-voltage power line are arranged on the same layer.

2. The display panel according to claim 1, wherein: The data connection line includes: a first connection line connected to each other and a second connection line extending along the second direction, the first connection line is located on a side of the third high-voltage power line close to the substrate, and the second connection line is arranged on the same layer as the first high-voltage power line; The orthographic projection of the first connecting line on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the third high-voltage power line on the substrate.

3. The display panel according to claim 2, wherein: The first connection line includes: a first data connection portion extending along the second direction and a second data connection portion extending along the first direction, the first data connection portion is connected to the second data connection portion and the second connection line respectively, and the first direction and the second direction intersect; An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the data signal line on the substrate.

4. The display panel according to claim 1 or 2, wherein: The length of the second sub-high-voltage power line along the first direction is less than the length of the first sub-high-voltage power line along the first direction, and the orthographic projection of the second sub-high-voltage power line on the substrate at least partially overlaps with the orthographic projection of the first sub-high-voltage power line on the substrate.

5. The display panel according to claim 4, wherein: The length of the first high-voltage power line along the first direction, the length of the first sub-high-voltage power line along the first direction and the third high-voltage power line are approximately equal, and the shape of the first high-voltage power line, the shape of the first sub-high-voltage power line and the shape of the third high-voltage power line are roughly the same. The display panel according to claim 4 , wherein: The length of the second sub-high-voltage power line along the first direction is approximately equal to the length of the second connecting line along the first direction, and the shape of the second sub-high-voltage power line is substantially the same as the shape of the second connecting line.

7. The display panel according to claim 6, wherein: The area of ​​the overlapping area between the orthographic projection of the second sub-high-voltage power line on the substrate and the orthographic projection of the first sub-high-voltage power line on the substrate is greater than the area of ​​the overlapping area between the orthographic projection of the second connecting line on the substrate and the orthographic projection of the third high-voltage power line on the substrate.

8. The display panel according to claim 1, wherein: The light-emitting device includes: an anode, an organic light-emitting layer and a cathode, and the display panel also includes: a plurality of first anode connecting lines extending along a first direction, the first anode connecting lines are arranged on the same layer as the third high-voltage power line, and are configured to connect at least one circuit unit in the first area and the anode of the light-emitting device located in the light-transmitting display area.

9. The display panel according to claim 8, wherein: The light-transmitting display area includes: a central area and an edge area surrounding the central area; the display panel further includes: a second anode connecting line, the second anode connecting line is located on a side of the first high-voltage power line away from the substrate; The first anode connection line is configured to connect at least one circuit unit in the first area and the anode of the light emitting device located in the edge area, and the second anode connection line is configured to connect at least one circuit unit in the first area and the anode of the light emitting device located in the central area.

10. The display panel according to claim 9, wherein: The first anode connection line includes a metal signal line, and the second anode connection line includes a transparent conductive signal line.

11. The display panel according to claim 9, wherein: The display area includes: a plurality of light-emitting units, at least one light-emitting unit includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, different light-emitting devices emit light of different colors, the first light-emitting device and the second light-emitting device emit red or blue light, and the third light-emitting device emits green light; For a light emitting unit located in the edge area, the length of the first anode connection line connected to the third light emitting device of the same light emitting unit along the first direction is shorter than the length of the first anode connection line connected to the first light emitting device and the second light emitting device of the same light emitting unit along the first direction.

12. The display panel according to claim 11, wherein: The length of the first anode connecting line connected to any third light-emitting device located in the edge area along the first direction is shorter than the length of the first anode connecting line connected to any first light-emitting device located in the edge area and the length of the first anode connecting line connected to any second light-emitting device located in the edge area along the first direction.

13. The display panel according to claim 9, wherein: The edge region occupies about 3% to 8% of the area of ​​the light-transmitting display region, or the number of light-emitting units included in the edge region is 5% to 10% of the number of light-emitting units in the light-transmitting display region.

14. The display panel according to any one of claims 2 to 13, wherein: The pixel circuit includes at least a capacitor and a plurality of transistors, wherein the capacitor includes: a first electrode plate and a second electrode plate; the display panel includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planar layer, and a fifth conductive layer, which are sequentially arranged on a substrate; The semiconductor layer includes at least an active layer of multiple transistors; the first conductive layer includes at least gate electrodes of multiple transistors and a first plate of a capacitor; the second conductive layer includes at least a second plate of a capacitor; the third conductive layer includes at least the first and second electrodes of multiple transistors and a first connecting line; the fourth conductive layer includes at least a first anode connecting line, a first sub-high-voltage power line and a third high-voltage power line; the fifth conductive layer includes at least: a data signal line, a first high-voltage power line, a second sub-high-voltage power line and a second connecting line.

15. The display panel according to claim 14, wherein: The pixel circuit includes: a write transistor, which is connected to a data signal line; the second plate of the capacitor located in the third area includes: a capacitor main body and an auxiliary capacitor part that are connected to each other; the capacitor main body has a shape roughly the same as the second plate of the capacitor located in the first area and the second area; the orthographic projection of the auxiliary capacitor part on the substrate at least partially overlaps with the orthographic projection of the active layer of the write transistor on the substrate.

16. The display panel according to claim 14, wherein: The third conductive layer further includes: a data connection block, wherein an orthographic projection of the data connection block on the substrate at least partially overlaps with an orthographic projection of the auxiliary capacitor portion and the second connection line on the substrate; The data connection blocks are connected to the first connection line and the second connection line respectively.

17. The display panel according to claim 16, wherein: The data connection block and the second data connection portion are located on the same side of the first data connection portion and are electrically connected to the first data connection portion; An orthographic projection of the first data connection portion on the substrate at least partially overlaps with an orthographic projection of the second plate of the capacitor on the substrate.

18. The display panel according to claim 14, wherein: The pixel circuit further includes: a first light emitting transistor and a second light emitting transistor, the first light emitting transistor is connected to the high voltage power line, the second light emitting transistor is connected to the anode of the light emitting device, and the fourth conductive layer further includes: a first connecting electrode, a second connecting electrode, a third connecting electrode and a fourth connecting electrode; The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the write transistor of at least one circuit unit located in the first area to the third area, and is electrically connected to the first electrode of the write transistor of at least one circuit unit located in the first area to the third area. The orthographic projection of the second connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area, and is connected to the second electrode of the second light-emitting transistor in at least one circuit unit located in the first area to the third area. The orthographic projection of the third connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area, and is connected to the first electrode of the first light-emitting transistor in at least one circuit unit located in the first area. The orthographic projection of the fourth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the data connection block on the substrate, and at least partially overlaps with the orthographic projection of the data connection block on the substrate.

19. The display panel according to claim 18, wherein: The fifth conductive layer further includes a fifth connecting electrode, the orthographic projection of the fifth connecting electrode on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode on the substrate, and the fifth connecting electrode is connected to the second connecting electrode.

20. The display panel according to claim 19, wherein The orthographic projections of the plurality of first anode connection lines on the substrate at least partially overlap with the orthographic projections of the fifth connection electrode and the anode of the connected light-emitting device on the substrate.

21. The display panel according to claim 18, wherein The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate and is connected to the first connecting electrode, the orthographic projection of the first high-voltage power line on the substrate at least partially overlaps with the orthographic projection of the third connecting electrode on the substrate and is connected to the third connecting electrode, and the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the fourth connecting electrode on the substrate and is connected to the fourth connecting electrode.

22. The display panel according to claim 19 further includes a transparent conductive layer located on a side of the second flat layer away from the substrate, the transparent conductive layer includes a second anode connecting line, the second anode connecting line at least partially overlaps with the positive projection of the fifth connecting electrode on the substrate, and is connected to the fifth connecting electrode.

23. A display device comprising: The display panel and photosensor according to any one of claims 1 to 22, wherein the photosensor is located in a light-transmitting display area of ​​the display panel.

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