LDO circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of circuits, and discloses an LDO circuit, a chip and electronic equipment. In the LDO circuit, the first end of a first current source unit is used for being connected with the first end of a reference circuit, the first end of a driving circuit, the first end of a power tube unit and a power supply end, and the second end of the first current source unit is connected with the first end of a first capacitor unit and the first end of a third switch circuit; the second end of the reference circuit is connected with the second end of the driving circuit, and the third end of the reference circuit is grounded; the third end of the driving circuit is connected with the second end of the power tube unit, and the fourth end of the driving circuit is connected with the second end of the third switching circuit; the third end of the power tube unit is used for being connected with the third end of the reference circuit, the second end of the first capacitor unit, the third end of the third switching circuit and the output end of the LDO circuit; therefore, through controlling the conduction state of the third switch circuit, the damage of the surge current to a post-stage circuit is reduced.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an LDO circuit, chip, and electronic device. Background Art

[0002] In integrated circuit applications, circuits with a low-dropout linear regulator (LDO) structure (hereinafter referred to as LDO circuits) are widely used in power management chips to power subsequent circuits due to their low cost, simple structure, and ease of integration. During stable operation, the LDO circuit, through components such as op amps and power dissipators, ensures a stable output voltage (VOUT) as the power supply voltage for subsequent circuits when the power supply voltage (VDD) varies within a certain range, thereby ensuring the stability of the subsequent circuits. Therefore, a high-quality LDO circuit should have a high power supply rejection ratio (PSRR) and high stability.

[0003] When the LDO circuit receives a start signal, it starts up quickly. At the moment of startup, the voltage at the output of the LDO circuit rises rapidly, causing a large inrush current in the LDO circuit, which can easily damage the downstream circuits connected to the LDO circuit. Summary of the Invention

[0004] The present application provides an LDO circuit, a chip, and an electronic device.

[0005] In a first aspect, the present application provides an LDO circuit, which includes a reference circuit, a drive circuit, a power tube unit, and a soft start circuit. The soft start circuit includes a first current source unit, a first capacitor unit, and a third switch circuit. The first end of the first current source unit is used to connect to the first end of the reference circuit, the first end of the drive circuit, the first end of the power tube unit, and the power supply end, and the second end of the first current source unit is respectively connected to the first end of the first capacitor unit and the first end of the third switch circuit. The second end of the reference circuit is connected to the second end of the drive circuit, and the third end of the reference circuit is grounded. The third end of the drive circuit is connected to the second end of the power tube unit, and the fourth end of the drive circuit is connected to the second end of the third switch circuit. The third end of the power tube unit is used to connect to the third end of the reference circuit, the second end of the first capacitor unit, the third end of the third switch circuit, and the output end of the LDO circuit. At a first moment after the LDO circuit is started, the reference circuit outputs a reference current, the drive circuit is in an on state, the third switch circuit is in an off state, the power tube unit is in an off state, and the first current source unit charges the first capacitor unit. At a second moment after the LDO circuit is started, the third switch circuit is in an on state, and the power tube unit is in an on state.

[0006] It can be understood that at the first moment after the LDO circuit is started, the reference circuit provides a reference current. The voltage at the fourth terminal of the reference circuit is zero, that is, the feedback voltage VFB is zero, causing the voltage V1 at the third terminal of the driver circuit to gradually increase, thereby disconnecting the third switch circuit and the power tube unit. As a result, the output voltage VOUT of the LDO circuit does not rise rapidly at the first moment after the LDO circuit is started. As a result, a large inrush current is not generated in the LDO circuit, effectively reducing the damage caused by the inrush current to the subsequent circuit.

[0007] During this process, the first current source unit continuously charges the first capacitor unit, causing a linearly increasing ramp voltage VSLOP to be generated at the first end of the first capacitor unit. Consequently, at the second moment after the LDO circuit is activated, the third switch circuit gradually turns on as the ramp voltage VSLOP increases, causing the third switch circuit and the power transistor unit to be in the on state. Consequently, the output voltage VOUT of the LDO circuit increases as the power transistor unit turns on. In this way, by controlling the on-state of the third switch circuit, and thereby controlling the rate of increase of the output voltage VOUT of the LDO circuit, the output voltage VOUT of the LDO circuit does not rise rapidly at the first moment after the LDO circuit is activated, effectively reducing the inrush current generated in the LDO circuit and minimizing the damage caused by the inrush current to subsequent circuits.

[0008] In a possible implementation of the first aspect above, the LDO circuit further includes a voltage divider sampling circuit, a first switching circuit, and a second switching circuit; the first end of the voltage divider sampling circuit is respectively connected to the third end of the power tube unit and the output end of the LDO circuit; the second end of the voltage divider sampling circuit is connected to the fourth end of the reference circuit; the third end of the voltage divider sampling circuit is respectively connected to the third end of the reference circuit, the second end of the first capacitor unit, and the third end of the third switching circuit; the first end of the first switching circuit is respectively connected to the first end of the drive circuit, the first end of the power tube unit, the first end of the second switching circuit, the first end of the first current source unit, and the power supply end; the second end of the first switching circuit is connected to the first end of the reference circuit; and the second end of the second switching circuit is respectively connected to the third end of the drive circuit and the second end of the power tube unit.

[0009] In a possible implementation of the first aspect above, the first current source unit includes a current source, the first capacitor unit includes a first capacitor, and the third switching circuit includes a first switching tube; the first end of the current source is respectively connected to the first end of the driving circuit, the first end of the power tube unit, the first end of the first switching circuit, the first end of the second switching circuit, and the power supply end; the second end of the current source is respectively connected to the first end of the first capacitor and the gate of the first switching tube; the second end of the first capacitor is respectively connected to the third end of the reference circuit, the third end of the voltage divider sampling circuit, and the source of the first switching tube; the drain of the first switching tube is connected to the fourth end of the driving circuit.

[0010] In a possible implementation of the first aspect above, the reference circuit includes an N-type power transistor and a second N-type enhancement transistor, the drive circuit includes a second P-type enhancement transistor and a third N-type enhancement transistor, the power tube unit includes a first P-type power transistor, the voltage divider sampling circuit includes a second resistor and a third resistor, the first switch circuit includes a second switch tube, and the second switch circuit includes a third switch tube; the drain of the N-type power transistor is connected to the drain of the second switch tube, the gate of the N-type power transistor is connected to the source of the N-type power transistor, and the source of the N-type power transistor is respectively connected to the drain of the second N-type enhancement transistor and the gate of the third N-type enhancement transistor; the source of the second N-type enhancement transistor is grounded, and the gate of the second N-type enhancement transistor is respectively connected to the second end of the second resistor and the first end of the third resistor; the source of the second P-type enhancement transistor is respectively connected to the power supply end and the second switch The source of the transistor, the source of the third switching transistor, the source of the first P-type power transistor, and the first end of the current source are connected; the drain of the second P-type enhancement transistor is respectively connected to the gate of the second P-type enhancement transistor and the drain of the third N-type enhancement transistor, and the gate of the second P-type enhancement transistor is respectively connected to the drain of the third switching transistor and the gate of the first P-type power transistor; the source of the third N-type enhancement transistor is connected to the drain of the first switching transistor; the drain of the first P-type power transistor is respectively connected to the output end of the LDO circuit and the first end of the second resistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is respectively connected to the source of the second N-type enhancement transistor, the source of the first switching transistor, and the second end of the first capacitor; the gate of the second switching transistor is used to receive the first enable signal; and the gate of the third switching transistor is used to receive the second enable signal.

[0011] In a possible implementation of the first aspect above, the LDO circuit includes an operational amplifier circuit; a first end of the operational amplifier circuit is connected to a first end of the third switching circuit, a second end of the operational amplifier circuit is connected to a second end of the voltage divider sampling circuit, and a third end of the operational amplifier circuit is respectively connected to the second end of the first current source unit and the first end of the first capacitor unit.

[0012] In a possible implementation of the first aspect above, the operational amplifier circuit includes an operational amplifier; the output end of the operational amplifier is connected to the gate of the first switching tube, the negative input end of the operational amplifier is respectively connected to the second end of the second resistor and the first end of the third resistor, and the positive input end of the operational amplifier is respectively connected to the second end of the current source and the first end of the first capacitor.

[0013] In a possible implementation of the first aspect above, the LDO circuit includes a zero-pole compensation circuit; a first end of the zero-pole compensation circuit is respectively connected to a first end of the third switching circuit and a first end of the operational amplifier circuit; and a second end of the zero-pole compensation circuit is respectively connected to a third end of the reference circuit, a third end of the third switching circuit, a second end of the first capacitor unit, and a third end of the voltage divider sampling circuit.

[0014] In a possible implementation of the first aspect above, the pole-zero compensation circuit includes a first resistor and a second capacitor;

[0015] The first end of the first resistor is respectively connected to the gate of the first switching tube and the output end of the operational amplifier; the second end of the first resistor is connected to the first end of the second capacitor; the second end of the second capacitor is respectively connected to the source of the second N-type enhancement tube, the source of the first switching tube, the second end of the first capacitor C1, and the second end of the third resistor.

[0016] In a possible implementation of the first aspect above, the LDO circuit includes a power circuit, a control circuit, and an inverter circuit; a first end of the power circuit is used to connect to a power supply end; a second end of the power circuit is respectively connected to the first end of the third switch circuit, the first end of the operational amplifier circuit, and the first end of the zero-pole compensation circuit; a third end of the power circuit is connected to the first end of the inverter circuit; a first end of the control circuit is connected to the second end of the operational amplifier circuit, and the second end of the control circuit is connected to the second end of the voltage divider sampling circuit; a third end of the control circuit is respectively connected to the third end of the reference circuit, the third end of the third switch circuit, the second end of the first capacitor unit, the third end of the voltage divider sampling circuit, and the second end of the zero-pole compensation circuit; a fourth end of the control circuit is connected to the second end of the inverter circuit; a fifth end of the control circuit is connected to the first end of the inverter circuit; a first end of the inverter circuit is respectively connected to the third end of the power circuit and the fifth end of the control circuit, a second end of the inverter circuit is connected to the fourth end of the control circuit, and a third end of the inverter circuit is respectively connected to the second end of the first current source unit, the first end of the first capacitor unit, and the third end of the operational amplifier circuit.

[0017] In a possible implementation of the first aspect above, the power circuit includes a first P-type enhancement tube, the control circuit includes a first N-type enhancement tube and a second N-type enhancement tube, and the inverter circuit includes a first inverter and a second inverter; the source of the first P-type enhancement tube is used to be connected to the power supply terminal; the drain of the first P-type enhancement tube is respectively connected to the gate of the first switching tube, the output terminal of the operational amplifier, and the first end of the first resistor; the gate of the first P-type enhancement tube is used to receive the first logic signal; the drain of the first N-type enhancement tube is respectively connected to the drain of the second N-type enhancement tube and the negative input terminal of the operational amplifier; the gate of the first N-type enhancement tube is used to be connected to the The first inverter is configured to receive a second logic signal; the source of the first N-type enhancement tube is respectively connected to the source of the second N-type enhancement tube, the second end of the first capacitor, the source of the first switch tube, the second end of the third resistor, and the second end of the second capacitor; the source of the second N-type enhancement tube is respectively connected to the second end of the second resistor and the first end of the third resistor, and the gate of the second N-type enhancement tube is used to receive the first logic signal; the input end of the first inverter is used to receive the ramp voltage signal, the output end of the first inverter is connected to the input end of the second inverter, the output end of the first inverter is used to output the first logic signal, and the output end of the second inverter is used to output the second logic signal.

[0018] In a second aspect, the present application provides a chip, which includes the LDO circuit mentioned in the first aspect.

[0019] In a third aspect, the present application provides an electronic device comprising the chip mentioned in the second aspect.

[0020] The beneficial effects of the present application are: by controlling the conduction state of the third switch circuit, the output voltage rise speed of the LDO circuit is controlled, the surge current generated in the LDO circuit is effectively reduced, and the damage caused by the surge current to the subsequent circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 According to the prior art, a structural diagram of an LDO circuit 10 is shown;

[0022] Figure 2A According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0023] Figure 2B According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0024] Figure 2C According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0025] Figure 3A According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0026] Figure 3B According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0027] Figure 4 According to some embodiments of the present application, a schematic diagram of the temporal relationship between the slope voltage VSLOP and the feedback voltage VFB in an LDO circuit 10 is shown;

[0028] Figure 5 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0029] Figure 6 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0030] Figure 7 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown;

[0031] Figure 8 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit 10 is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0033] Figure 1 The schematic diagram of the structure of an LDO circuit is shown. The LDO circuit 10 may include: a second resistor R1, a third resistor R2, a first P-type power transistor MP1, a second P-type enhancement transistor MP2, a third switch transistor MP3, a second switch transistor MP4, an N-type power transistor DN1, a second N-type enhancement transistor MN1, and a third N-type enhancement transistor MN2.

[0034] In some optional embodiments, the LDO circuit 10 has a power supply terminal that can be connected to a battery, and the battery provides a power supply voltage VDD to the LDO circuit 10. The LDO circuit 10 has an output terminal that is connected to the input terminal of a subsequent circuit, and the output voltage VOUT of the LDO circuit 10 is used as the input voltage of the subsequent circuit to power the subsequent circuit.

[0035] In some optional embodiments, the source of the second switch tube MP4 is respectively connected to the power supply end, the source of the second P-type enhancement tube MP2, the source of the third switch tube MP3, and the source of the first P-type power tube MP1; the drain of the second switch tube MP4 is connected to the drain of the N-type consumption tube DN1; and the gate of the second switch tube MP4 is used to receive the first enable signal ENB.

[0036] The drain of the second P-type enhancement transistor MP2 and the gate of the second P-type enhancement transistor MP2 form a diode connection, which can improve the stability of the LDO circuit 10. The drain of the second P-type enhancement transistor MP2 is connected to the drain of the third N-type enhancement transistor MN2, and the gate of the second P-type enhancement transistor MP2 is connected to the gate of the first P-type power transistor MP1 and the drain of the third switching transistor MP3.

[0037] The gate of the third switch tube MP3 is used to receive the second enable signal EN.

[0038] The drain of the first P-type power transistor MP1 is connected to the first end of the second resistor R1 and the output end of the LDO circuit respectively.

[0039] The gate and source of the N-type power transistor DN1 are short-circuited to provide a reference current to the LDO circuit 10. The source of the N-type power transistor DN1 is connected to the drain of the second N-type enhancement transistor MN1 and the gate of the third N-type enhancement transistor MN2.

[0040] The source of the second N-type enhancement transistor MN1 is grounded, and the gate of the second N-type enhancement transistor MN1 is connected to the second end of the second resistor R1.

[0041] The source of the third N-type enhancement transistor MN2 is connected to the source of the second N-type enhancement transistor MN1 and the second end of the third resistor R2 respectively.

[0042] The second end of the second resistor R1 is connected to the first end of the third resistor R2 , and the second end of the third resistor R2 is connected to the source of the second N-type enhancement transistor MN1 .

[0043] In some optional embodiments, the voltage at the second end of the second resistor R1 can be recorded as the feedback voltage VFB. Therefore, in the LDO circuit 10, the output voltage VOUT and the feedback voltage VFB satisfy VOUT=VFB×(R1+R2) / R2.

[0044] In some optional embodiments, when the second enable signal EN received by the gate of the third switch transistor MP3 is at a high level and the first enable signal ENB received by the gate of the second switch transistor MP4 is at a low level, the LDO circuit 10 is turned on. When the second enable signal EN received by the gate of the third switch transistor MP3 is at a low level and the first enable signal ENB received by the gate of the second switch transistor MP4 is at a high level, the LDO circuit 10 is turned off.

[0045] The working principle of the LDO circuit provided in the embodiment of the present application is described below with reference to the accompanying drawings.

[0046] In some optional embodiments, the operating principle of the LDO circuit 10 may include: when the second enable signal EN received at the gate of the third switch MP3 is at a high level, and the first enable signal ENB received at the gate of the second switch MP4 is at a low level, the LDO circuit 10 is activated. The gate and source of the N-type power transistor DN1 are shorted, providing a reference current to the LDO circuit 10. At this time, the feedback voltage VFB is zero, the current flowing through the second N-type power transistor MN1 is zero, and the gate voltage V1 of the third N-type power transistor MN2 gradually increases, causing the third N-type power transistor MN2 to fully conduct, thereby reducing the gate voltage V2 of the first P-type power transistor MP1. This causes the first P-type power transistor MP1 to be in the conducting state, and the output voltage VOUT gradually increases to a steady-state value. The feedback voltage VFB at the gate of the second N-type power transistor MN1 also gradually increases, and the reference current begins to flow through the second N-type power transistor MN1, causing the gate voltage V1 of the third N-type power transistor MN2 to gradually decrease to a steady-state value, and the LDO circuit 10 is in normal operation. At this time, the feedback voltage VFB is stable, and the current flowing through the second N-type enhancement transistor MN1 is equal to the reference current. In the LDO circuit 10, the second N-type enhancement transistor MN1, the N-type consumption transistor DN1, the third N-type enhancement transistor MN2, the first P-type power transistor MP1, the second resistor R1, and the third resistor R2 form a loop. The LDO circuit 10 can provide a stable output voltage VOUT to the subsequent circuit.

[0047] It can be understood that the LDO circuit 10 is a power supply circuit that is used to output a stable output voltage VOUT after the input power supply voltage VDD passes through the LDO circuit 10. Therefore, if the output voltage VOUT output by the LDO circuit 10 to the subsequent circuit fluctuates significantly, it is very likely to cause damage to the subsequent circuit.

[0048] Specifically, at the moment the LDO circuit 10 starts up, the output voltage VOUT of the LDO circuit 10 rises rapidly, generating a large surge current at the output of the LDO circuit 10, which can easily damage subsequent circuits. Furthermore, the rise time of the output voltage VOUT is uncontrollable, making it impossible to guarantee the widespread application of mass-produced products.

[0049] Therefore, in order to solve the above problems, the present application provides an LDO circuit. Figure 2AAs shown, the LDO circuit 10 includes a reference circuit 101, a drive circuit 102, a power tube unit 103 and a soft start circuit 104. The soft start circuit 104 includes a first current source unit 1041, a first capacitor unit 1042 and a third switch circuit 1043. The first end of the first current source unit 1041 is used to connect to the first end of the reference circuit 101, the first end of the drive circuit 102, the first end of the power tube unit 103 and the power supply end, and the second end of the first current source unit 1041 is respectively connected to the first end of the first capacitor unit 1042. The first terminal of the reference circuit 101 is connected to the second terminal of the driving circuit 102, and the third terminal of the reference circuit 101 is grounded; the third terminal of the driving circuit 102 is connected to the second terminal of the power tube unit 103, and the fourth terminal of the driving circuit 102 is connected to the second terminal of the third switching circuit 1043; the third terminal of the power tube unit 103 is used to be connected to the third terminal of the reference circuit 101, the second terminal of the first capacitor unit 1042, the third terminal of the third switching circuit 1043, and the output terminal of the LDO circuit.

[0050] Among them, at the first moment after the LDO circuit is started, the reference circuit 101 outputs the reference current, the driving circuit 102 is in the on state, the third switch circuit 1043 is in the off state, the power tube unit 103 is in the off state, and the first current source unit 1041 charges the first capacitor unit 1042; at the second moment after the LDO circuit is started, the third switch circuit 1043 is in the on state, and the power tube unit 103 is in the on state.

[0051] It will be appreciated that at the moment the LDO circuit 10 starts up (e.g., the first moment after the LDO circuit starts up), the reference circuit 101 provides a reference current, and the voltage at the fourth terminal of the reference circuit 101 is zero, that is, the feedback voltage VFB is zero, causing the voltage V1 at the third terminal of the driver circuit 102 to gradually increase, thereby disconnecting the third switch circuit 1043 and the power transistor unit 103. As such, the output voltage VOUT of the LDO circuit 10 does not rise rapidly at the moment the LDO circuit 10 starts up. Consequently, a large inrush current is not generated in the LDO circuit 10 at the moment the LDO circuit 10 starts up, effectively reducing damage to subsequent circuits caused by the inrush current.

[0052] It can be understood that during this process, the first current source unit 1041 continuously charges the first capacitor unit 1042, causing a linearly increasing ramp voltage VSLOP to be generated at the first end of the first capacitor unit 1042. Consequently, at the second moment after the LDO circuit 10 is started, the third switch circuit 1043 gradually turns on as the ramp voltage VSLOP increases, causing the third switch circuit 1043 to be in an on state, and the power transistor unit 103 to be in an on state. Consequently, the output voltage VOUT of the LDO circuit 10 increases as the power transistor unit 103 turns on. In this way, by controlling the on-state of the third switch circuit 1043 and thereby controlling the rate of increase of the output voltage VOUT of the LDO circuit 10, the output voltage VOUT of the LDO circuit 10 does not rise rapidly at the moment of startup of the LDO circuit 10, effectively reducing the inrush current generated in the LDO circuit 10 and minimizing the damage caused by the inrush current to subsequent circuits.

[0053] Figure 2B A schematic diagram of the structure of an LDO circuit 10 is shown. It can be understood that Figure 2B As shown, the LDO circuit 10 may further include a first switch circuit 106, a second switch circuit 107, and a voltage-dividing sampling circuit 105. The first end of the voltage-dividing sampling circuit 105 is respectively connected to the third end of the power tube unit 103 and the output end of the LDO circuit; the second end of the voltage-dividing sampling circuit 105 is respectively connected to the fourth end of the reference circuit 101; the third end of the voltage-dividing sampling circuit 105 is respectively connected to the third end of the reference circuit 101, the second end of the first capacitor unit 1042, and the third end of the third switch circuit 1043; the first end of the first switch circuit 106 is respectively connected to the first end of the drive circuit 102, the first end of the power tube unit 103, the first end of the second switch circuit 107, the first end of the first current source unit 1041, and the power supply end; the second end of the first switch circuit 106 is connected to the first end of the reference circuit 101; and the second end of the second switch circuit 107 is respectively connected to the third end of the drive circuit 102 and the second end of the power tube unit 103.

[0054] The structure of the LDO circuit mentioned in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0055] Figure 2C Shows a Figure 2B A schematic diagram of a specific structure of the LDO circuit 10 is shown in FIG. Figure 2C As shown, the first current source unit 1041 of the soft start circuit 104 may include at least one current source S, and the first capacitor unit 1042 may include at least one first capacitor C1. For ease of description, the following description takes the example of the first current source unit 1041 including one current source S and the first capacitor unit 1042 including one first capacitor C1.

[0056] In some optional embodiments, the first current source unit 1041 includes a current source S, and the first capacitor unit 1042 includes a first capacitor C1. The first end of the current source S is the first end of the first current source unit 1041, and the second end of the current source S is the second end of the first current source unit 1041; the first end of the first capacitor C1 is the first end of the first capacitor unit 1042, and the second end of the first capacitor C1 is the second end of the first capacitor unit 1042.

[0057] The third switch circuit 1043 includes a first switch transistor MN3 , a gate of which is a first terminal of the third switch circuit 1043 , a drain of which is a second terminal of the third switch circuit 1043 , and a source of which is a third terminal of the third switch circuit 1043 .

[0058] Reference circuit 101 includes an N-type power transistor DN1 and a second N-type enhancement transistor MN1. The drain of N-type power transistor DN1 serves as a first terminal of reference circuit 101. The source of N-type power transistor DN1 and the drain of second N-type enhancement transistor MN1 together constitute a second terminal of reference circuit 101. The source of second N-type enhancement transistor MN1 serves as a third terminal of reference circuit 101. The gate of second N-type enhancement transistor MN1 serves as a fourth terminal of reference circuit 101.

[0059] The driving circuit 102 includes a second P-type enhancement transistor MP2 and a third N-type enhancement transistor MN2. The source of the second P-type enhancement transistor MP2 is a first terminal of the driving circuit 102, the gate of the second P-type enhancement transistor MP2 is a third terminal of the driving circuit 102, the gate of the third N-type enhancement transistor MN2 is a second terminal of the driving circuit 102, and the source of the third N-type enhancement transistor MN2 is a fourth terminal of the driving circuit 102.

[0060] The power tube unit 103 includes at least one first P-type power tube MP1. For ease of description, the following description assumes that the power tube unit 103 includes one first P-type power tube MP1. The source of the first P-type power tube MP1 is the first terminal of the power tube unit 103, the gate of the first P-type power tube MP1 is the second terminal of the power tube unit 103, and the drain of the first P-type power tube MP1 is the third terminal of the power tube unit 103.

[0061] The voltage-dividing sampling circuit 105 includes a second resistor R1 and a third resistor R2. The first end of the second resistor R1 serves as the first end of the voltage-dividing sampling circuit 105. The second end of the second resistor R1 and the first end of the third resistor R2 together serve as the second end of the voltage-dividing sampling circuit 105. The second end of the third resistor R2 serves as the third end of the voltage-dividing sampling circuit 105.

[0062] The first switch circuit 106 includes a second switch transistor MP4 , a source of which is a first terminal of the first switch circuit 106 , and a drain of which is a second terminal of the first switch circuit 106 .

[0063] The second switch circuit 107 includes a third switch transistor MP3 , wherein a source of the third switch transistor MP3 is a first terminal of the second switch circuit 107 , and a drain of the third switch transistor MP3 is a second terminal of the second switch circuit 107 .

[0064] In some optional embodiments, the drain of the N-type power transistor DN1 is connected to the drain of the second switching transistor MP4; the gate of the N-type power transistor DN1 is connected to the source of the N-type power transistor DN1; the source of the N-type power transistor DN1 is respectively connected to the drain of the second N-type enhancement transistor MN1 and the gate of the third N-type enhancement transistor MN2. The gate of the second N-type enhancement transistor MN1 is respectively connected to the second end of the second resistor R1 and the first end of the third resistor R2, and the source of the second N-type enhancement transistor MN1 is grounded.

[0065] The source of the second P-type enhancement transistor MP2 is connected to the source of the second switching transistor MP4, the source of the third switching transistor MP3, the source of the first P-type power transistor MP1, the first end of the current source S, and the power supply. The drain of the second P-type enhancement transistor MP2 is connected to the drain of the third N-type enhancement transistor MN2 and the gate of the second P-type enhancement transistor MP2. The gate of the second P-type enhancement transistor MP2 is connected to the drain of the third switching transistor MP3 and the gate of the first P-type power transistor MP1. The source of the third N-type enhancement transistor MN2 is connected to the drain of the first switching transistor MN3.

[0066] The drain of the first P-type power transistor MP1 is connected to the first end of the second resistor R1 and the output end of the LDO circuit 10 respectively.

[0067] The second end of the current source S is connected to the first end of the first capacitor C1 and the gate of the first switch tube MN3 respectively; the second end of the first capacitor C1 is connected to the source of the second N-type enhancement tube MN1, the source of the first switch tube MN3, and the second end of the third resistor R2 respectively.

[0068] The second end of the second resistor R1 is connected to the first end of the third resistor R2.

[0069] The gate of the second switch transistor MP4 is used to receive the first enable signal ENB. The gate of the third switch transistor MP3 is used to receive the second enable signal EN.

[0070] In some optional embodiments, the LDO circuit 10 starts operating when the second enable signal EN received by the gate of the third switch transistor MP3 is at a high level and the first enable signal ENB received by the gate of the second switch transistor MP4 is at a low level. The LDO circuit 10 stops operating when the second enable signal EN received by the gate of the third switch transistor MP3 is at a low level and the first enable signal ENB received by the gate of the second switch transistor MP4 is at a high level.

[0071] In some optional embodiments, based on Figure 2C As shown in the schematic diagram of the structure of the LDO circuit 10, in the LDO circuit 10, when the LDO circuit 10 starts operating, the third switch MP3 is turned on, and the output voltage VOUT of the LDO circuit 10 gradually rises until it reaches a stable value. When VOUT reaches a stable value, VOUT = VFB × (R1 + R2) / R2, where VFB is the feedback voltage in the LDO circuit 10.

[0072] Therefore, in the embodiment of the present application, a first switch tube MN3, a current source S, and a first capacitor C1 are added to the LDO circuit 10 to form the LDO circuit 10. By controlling the conduction state of the first switch tube MN3, a large surge current is not generated in the LDO circuit 10 at the moment when the LDO circuit 10 is started.

[0073] In some optional embodiments, the operating principle of the LDO circuit 10 may include the following: at the moment the LDO circuit 10 starts up, the N-type consumption transistor DN1 provides a reference current to the LDO circuit 10. Furthermore, at the moment the LDO circuit 10 starts up, the gate voltage of the second N-type enhancement transistor MN1 is zero, i.e., the feedback voltage VFB is zero, and the gate voltage V1 of the third N-type enhancement transistor MN2 gradually increases, thereby fully turning on the third N-type enhancement transistor MN2, turning off the first switch MN3, and turning off the first P-type power transistor MP1. In this way, the output voltage VOUT of the LDO circuit 10 does not rise rapidly at the moment the LDO circuit 10 starts up. Consequently, at the moment the LDO circuit 10 starts up, a large inrush current is not generated in the LDO circuit 10, effectively reducing damage to subsequent circuits caused by the inrush current. Furthermore, by adding the first switch MN3, the current source S, and the first capacitor C1 to the LDO circuit 10, the LDO circuit 10 has a simpler architecture.

[0074] It can be understood that during this process, the current source S continuously charges the first capacitor C1, causing a linearly increasing ramp voltage VSLOP to be generated at the first end of the first capacitor C1. Consequently, the first switch MN3 gradually turns on as the ramp voltage VSLOP increases. Furthermore, the gradual turning on of the first switch MN3 causes the gate voltage V2 of the first P-type power transistor MP1 to gradually decrease, causing the first P-type power transistor MP1 to gradually turn on. Consequently, the output voltage VOUT of the LDO circuit 10 increases as the first switch MN3 gradually turns on. In this way, by controlling the conduction state of the first switch MN3 and thereby controlling the rate of increase of the output voltage VOUT of the LDO circuit 10, the output voltage VOUT of the LDO circuit 10 does not rise rapidly at the moment of startup of the LDO circuit 10, effectively reducing the inrush current generated in the LDO circuit 10 and minimizing the damage caused by the inrush current to subsequent circuits.

[0075] However, in Figure 2C In the LDO circuit 10 shown, there is a situation where the surge current and the VOUT startup time are discrete, that is, the VOUT startup time is uncontrollable, which easily leads to limitations in the application of the LDO circuit 10. For example, the LDO circuit 10 cannot be applied to some products with higher processes.

[0076] Therefore, in order to solve the above problems, we can Figure 2B An operational amplifier circuit 108 is added to the LDO circuit 10 shown. Figure 3A A schematic diagram of the structure of an LDO10 circuit is shown. Figure 3A As shown, the LDO circuit 10 includes a first switch circuit 106, a second switch circuit 107, a reference circuit 101, a drive circuit 102, a power tube unit 103, an operational amplifier circuit 108, a voltage divider sampling circuit 105, and a soft start circuit 104. The soft start circuit 104 includes a first current source unit 1041, a first capacitor unit 1042, and a third switch circuit 1043.

[0077] In some optional embodiments, the first terminal of the operational amplifier circuit 108 is connected to the first terminal of the third switch circuit 1043, the second terminal of the operational amplifier circuit 108 is connected to the second terminal of the voltage divider sampling circuit 105, and the third terminal of the operational amplifier circuit 108 is connected to the second terminal of the first current source unit 1041. Figure 2B , I will not go into details here.

[0078] Figure 3B Shown Figure 3A A specific structural diagram of the LDO circuit 10 is shown in FIG. Figure 3BAs shown, the operational amplifier circuit 108 includes an operational amplifier AMP. The output terminal of the operational amplifier AMP is the first terminal of the operational amplifier circuit 108, the positive input terminal of the operational amplifier AMP is the third terminal of the operational amplifier circuit 108, and the negative input terminal of the operational amplifier AMP is the second terminal of the operational amplifier circuit 108.

[0079] The output terminal of the operational amplifier AMP is connected to the gate of the first switch MN3; the negative input terminal of the operational amplifier AMP is connected to the first terminal of the second resistor R1; and the positive input terminal of the operational amplifier AMP is connected to the second terminal of the current source S. For the structural description of the rest of the LDO circuit 10, please refer to Figure 2C , I will not go into details here.

[0080] The present application forms an LDO circuit 10 by adding an operational amplifier AMP to the LDO circuit 10. The conduction state of the first switch tube MN3 is controlled by the output voltage of the operational amplifier AMP. This can not only effectively reduce the surge current generated in the LDO circuit 10, but also make the startup time of the output voltage VOUT of the LDO circuit 10 controllable.

[0081] In some optional embodiments, the operating principle of the LDO circuit 10 may include: at the moment of startup of the LDO circuit 10, the N-type power transistor DN1 generates a reference current. At this time, the gate voltage of the second N-type enhancement transistor MN1 is zero, that is, the feedback voltage VFB is zero. The gate voltage V1 of the third N-type enhancement transistor MN2 gradually increases due to the reference current generated in the LDO circuit 10, causing the third N-type enhancement transistor MN2 to turn on and the first switch MN3 to turn off. At this time, the operational amplifier AMP, the first switch MN3, the first P-type power transistor MP1, the second resistor R1, and the third resistor R2 in the LDO circuit 10 form a loop (corresponding to the second loop mentioned below). Therefore, the output voltage VOUT of the LDO circuit 10 does not rise rapidly at the moment of startup of the LDO circuit 10. As a result, a large inrush current is not generated in the LDO circuit 10 at the moment of startup.

[0082] During operation based on the second loop, the current source S continuously charges the first capacitor C1, causing a linearly increasing ramp voltage VSLOP to be generated at the first end of the first capacitor C1. As the ramp voltage VSLOP increases, the voltage at the positive input of the operational amplifier AMP increases. Furthermore, the operational amplifier AMP outputs a voltage based on the voltage difference between the positive input voltage (ramp voltage VSLOP) and the negative input voltage (feedback voltage VFB). This output voltage is used to control the gate voltage of the first switch MN3, causing the first switch MN3 to gradually turn on. This gradually reduces the gate voltage V2 of the first P-type power transistor MP1, causing the first P-type power transistor MP1 to gradually turn on. Consequently, the output voltage VOUT of the LDO circuit 10 gradually increases, and the feedback voltage VFB also gradually increases to a steady-state value.

[0083] When the output voltage VOUT of the LDO circuit 10 rises to a steady-state value, the first switch tube MN3 in the second loop is gradually turned on. At this time, the LDO circuit 10 is in a normal working state. The second loop formed by the operational amplifier AMP, the first switch tube MN3, the first P-type power tube MP1, the second resistor R1, and the third resistor R2 in the LDO circuit 10 is converted into the first loop formed by the third N-type enhancement tube MN2, the N-type consumption tube DN1, the first P-type power tube MP1, the second N-type enhancement tube MN1, the second P-type enhancement tube MP2, the second resistor R1, and the third resistor R2, and the circuit operates normally based on the first loop.

[0084] In this way, the operational amplifier AMP controls the conduction state of the first switch MN3, thereby controlling the rising speed of the output voltage VOUT of the LDO circuit 10. This prevents the output voltage VOUT of the LDO circuit 10 from rising rapidly at the moment of startup, effectively reducing the inrush current generated in the LDO circuit 10 and minimizing damage to subsequent circuits caused by the inrush current.

[0085] In some optional embodiments, according to Figure 3B The LDO circuit 10 shown, Figure 4 FIG. 1 shows a relationship diagram of the slope voltage VSLOP and the feedback voltage VFB over time. Figure 4 As can be seen in the figure, after the LDO circuit 10 starts up, the ramp voltage VSLOP increases linearly as the current source S continuously charges the first capacitor C1. The feedback voltage VFB also increases linearly with the ramp voltage until, at time t1, the current flowing through the second N-type enhancement transistor MN1 equals the reference current provided by the N-type consumption transistor DN1, and the feedback voltage VFB rises to a steady-state value.

[0086] In some optional embodiments, during the startup of the LDO circuit 10, the operational amplifier AMP, the first switch MN3, the first P-type power transistor MP1, the second resistor R1, and the third resistor R2 form a second loop, which may affect the stability of the LDO circuit 10, that is, the stability of the output voltage VOUT of the LDO circuit 10. Therefore, to solve this problem, Figure 3A A zero-pole compensation circuit 109 is added to the LDO circuit 10 shown to perform zero-pole compensation on the second loop, thereby reducing the surge current generated in the LDO circuit 10 while ensuring the stability of the LDO circuit 10 .

[0087] Figure 5 Shows a Figure 3A The schematic diagram of the structure of the LDO circuit 10 in which the zero-pole compensation circuit 109 is added is shown in FIG. Figure 5 As shown, the LDO circuit 10 includes a first switch circuit 106, a second switch circuit 107, a reference circuit 101, a drive circuit 102, a power tube unit 103, an operational amplifier circuit 108, a voltage divider sampling circuit 105, a soft start circuit 104, and a zero-pole compensation circuit 109. The soft start circuit 104 includes a first current source unit 1041 (current source S), a first capacitor unit 1042 (first capacitor C1), and a third switch circuit 1043.

[0088] In some optional embodiments, the first end of the zero-pole compensation circuit 109 is respectively connected to the first end of the third switch circuit 1043 and the first end of the operational amplifier circuit 108; the second end of the zero-pole compensation circuit 109 is respectively connected to the third end of the reference circuit 101, the third end of the third switch circuit 1043, the second end of the first capacitor unit 1042, and the third end of the voltage divider sampling circuit 105.

[0089] Figure 6 Shown Figure 5 A specific structural diagram of the LDO circuit 10 is shown in FIG. Figure 6 As shown, the zero-pole compensation circuit 109 includes a first resistor R3 and a second capacitor C2 , wherein the first end of the first resistor R3 is the first end of the zero-pole compensation circuit 109 , and the second end of the second capacitor C2 is the second end of the zero-pole compensation circuit 109 .

[0090] The first end of the first resistor R3 is connected to the gate of the first switch MN3 and the output of the operational amplifier AMP, respectively. The second end of the first resistor R3 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 is connected to the source of the second N-type enhancement transistor MN1, the source of the first switch MN3, the second end of the first capacitor C1, and the second end of the third resistor R2, respectively. For a structural description of the rest of the LDO circuit 10, please refer to Figure 3B, I will not go into details here.

[0091] In some optional embodiments, the operating principle of using the zero-pole compensation circuit 109 to perform zero-pole compensation on the second loop may include: since the second loop in the LDO circuit 10 includes an operational amplifier AMP, a first switch tube MN3, a first P-type power tube MP1, a second resistor R1, and a third resistor R2, the phase margin of the second loop is improved by adding the first resistor R3 and the second capacitor C2, thereby improving the stability of the startup process of the LDO circuit 10.

[0092] It can be understood that the negative input voltage of the operational amplifier AMP is the feedback voltage VFB, and during the operation of the LDO circuit 10, the positive input voltage of the operational amplifier AMP continues to increase, and the negative input voltage is a steady-state value, causing the operational amplifier to continuously compare the ramp voltage VSLOP with the feedback voltage VFB, causing the feedback voltage VFB to be unable to exit the second loop, thereby affecting the power supply rejection ratio of the LDO circuit 10. Therefore, in order to solve this problem, by Figure 5 A power circuit 1010, a control circuit 1011 and an inverter circuit 1012 are added to the LDO circuit 10 shown, so that the operational amplifier AMP exits the LDO circuit 10, thereby reducing the impact on the power supply rejection ratio of the LDO circuit 10 and not affecting the stability of the LDO circuit 10.

[0093] Figure 7 Shows a Figure 5 The schematic diagram of the structure of the LDO circuit 10 shown in FIG1 is shown as follows: a power circuit 1010, a control circuit 1011 and an inverter circuit 1012 are added to the LDO circuit 10 shown in FIG1. Figure 7 As shown, the LDO circuit 10 includes a first switch circuit 106, a second switch circuit 107, a reference circuit 101, a drive circuit 102, a power tube unit 103, an operational amplifier circuit 108, a voltage divider sampling circuit 105, a soft start circuit 104, a zero-pole compensation circuit 109, a power circuit 1010, a control circuit 1011, and an inverter circuit 1012. The soft start circuit 104 includes a first current source unit 1041 (current source S), a first capacitor unit 1042 (first capacitor C1), and a third switch circuit 1043.

[0094] In some optional embodiments, a first terminal of the power circuit 1010 is connected to a power supply terminal; a second terminal of the power circuit 1010 is respectively connected to a first terminal of the third switch circuit 1043, a first terminal of the operational amplifier circuit 108, and a first terminal of the zero-pole compensation circuit 109; and a third terminal of the power circuit 1010 is configured to receive a first logic signal SSTL. The third terminal of the power circuit 1010 may be connected to a first terminal of the inverter circuit 1012.

[0095] A first end of the control circuit 1011 is connected to a second end of the operational amplifier circuit 108; a second end of the control circuit 1011 is connected to a second end of the voltage divider sampling circuit 105; a third end of the control circuit 1011 is respectively connected to a third end of the reference circuit 101, a third end of the third switch circuit 1043, a second end of the first capacitor unit 1042, a third end of the voltage divider sampling circuit 105, and a second end of the zero-pole compensation circuit 109; a fourth end of the control circuit 1011 is connected to a second end of the inverter circuit 1012, and a fifth end of the control circuit 1011 is connected to a first end of the inverter circuit 1012.

[0096] The third terminal of the inverter circuit 1012 is used to connect to the ramp voltage VSLOP, and the second terminal of the inverter circuit 1012 is used to output the second logic signal SSTH. The first terminal of the inverter circuit 1012 is used to output the first logic signal SSTL. Figure 5 , I will not go into details here.

[0097] Figure 8 Shown Figure 7 A specific structural diagram of the LDO circuit 10 is shown in FIG. Figure 8 As shown, the power circuit 1010 may include a first P-type enhancement transistor MP5, the control circuit 1011 may include a first N-type enhancement transistor MN4 and a second N-type enhancement transistor MN5, and the inverter circuit 1012 may include a first inverter SCHMIT and a second inverter INV.

[0098] Among them, the source of the first P-type enhancement transistor MP5 is the first end of the power circuit 1010, the drain of the first P-type enhancement transistor MP5 is the second end of the power circuit 1010, and the gate of the first P-type enhancement transistor MP5 power circuit 1010 is the third end of the power circuit 1010.

[0099] The drain of the first N-type enhancement transistor MN4 and the drain of the second N-type enhancement transistor MN5 together constitute the first end of the control circuit 1011, the source of the second N-type enhancement transistor MN5 is the second end of the control circuit 1011, the source of the first N-type enhancement transistor MN4 is the third end of the control circuit 1011, the gate of the first N-type enhancement transistor MN4 is the fourth end of the control circuit 1011, and the gate of the second N-type enhancement transistor MN5 is the fifth end of the control circuit 1011.

[0100] The output end of the first inverter SCHMIT and the input end of the second inverter INV together constitute a first end of the inverter circuit 1012 , the output end of the second inverter INV is a second end of the inverter circuit 1012 , and the input end of the first inverter SCHMIT is a third end of the inverter circuit 1012 .

[0101] In some optional embodiments, the source of the first P-type enhancement transistor MP5 is used to connect to the power supply end; the drain of the first P-type enhancement transistor MP5 is respectively connected to the gate of the first switch transistor MN3, the output end of the operational amplifier AMP, and the first end of the first resistor R3; the gate of the first P-type enhancement transistor MP5 is used to receive the first logic signal SSTL.

[0102] The drain of the first N-type enhancement transistor MN4 is connected to the drain of the second N-type enhancement transistor MN5 and the negative input terminal of the operational amplifier AMP. The gate of the first N-type enhancement transistor MN4 is used to receive the second logic signal SSTH.

[0103] The source of the first N-type enhancement tube MN4 is respectively connected to the source of the second N-type enhancement tube MN1, the second end of the first capacitor C1, the source of the first switch tube MN3, the second end of the third resistor R2, and the second end of the second capacitor C2.

[0104] The gate of the second N-type enhancement transistor MN5 is used to receive the first logic signal SSTL. The source of the second N-type enhancement transistor MN5 is connected to the first end of the third resistor R2.

[0105] An input terminal of the first inverter SCHMIT is used to connect to the ramp voltage signal VSLOP, an output terminal of the first inverter SCHMIT is used to output a first logic signal SSTL, and an output terminal of the second inverter INV is used to output a second logic signal SSTH.

[0106] In some optional embodiments, the gate of the first P-type enhancement transistor MP5 can be connected to the output end of the first inverter SCHMIT and the input end of the second inverter INV, respectively. The gate of the second N-type enhancement transistor MN5 can be connected to the output end of the first inverter SCHMIT and the input end of the second inverter INV, respectively. The gate of the first N-type enhancement transistor MN4 can be connected to the output end of the second inverter INV. The input end of the first inverter SCHMIT can be connected to the positive input end of the operational amplifier AMP, the second end of the current source S, and the first end of the first capacitor C1, respectively. The output end of the first inverter SCHMIT is connected to the input end of the second inverter INV. For a structural introduction of the rest of the LDO circuit 10, refer to Figure 6 , I will not go into details here.

[0107] In some optional embodiments, after the feedback voltage VFB rises to a steady-state value, the current source S continuously charges the first capacitor C1, causing the ramp voltage VSLOP to continue to rise linearly. When the ramp voltage VSLOP rises to a value greater than or equal to the threshold voltage of the first inverter SCHMIT, the first logic signal SSTL output by the first inverter SCHMIT changes from a high level to a low level, and the second logic signal SSTH output by the second inverter INV changes from a low level to a high level. Furthermore, the high level of the second logic signal SSTH fully turns on the first N-type transistor MN4, and the low level of the first logic signal SSTL fully turns off the second N-type transistor MN5. Consequently, the voltage at the negative input of the operational amplifier AMP decreases, and the voltage at the output of the operational amplifier AMP increases to the power supply voltage VDD. During this process, since the second N-type transistor MN5 is fully turned off, the feedback voltage VFB exits the second loop, effectively preventing the second loop from affecting the power supply rejection ratio of the LDO circuit 10. Furthermore, the output voltage of the operational amplifier AMP increases to the power supply voltage VDD, so that the operational amplifier AMP exits the LDO circuit 10 , without affecting the normal operation of the LDO circuit.

[0108] Thus, by adding the op amp circuit 108, the soft-start circuit 104, the zero-pole compensation circuit 109, the power circuit 1010, the control circuit 1011, and the inverter circuit 1012 to the LDO circuit 10, the impact of the surge current generated at the moment of LDO circuit startup on the LDO circuit can be effectively reduced, while simultaneously controlling the startup time of the output voltage VOUT. Furthermore, by adding the zero-pole compensation circuit 109, the stability of the output voltage VOUT during the LDO circuit startup process can be effectively guaranteed. Furthermore, after the output voltage VOUT rises to a stable state, the second loop quickly switches to the first loop, disconnecting the feedback voltage VFB from the op amp circuit 108, effectively preventing any impact on the power supply rejection ratio of the LDO circuit.

[0109] In some optional embodiments, based on the operation of the LDO circuit 10, the relationship between the ramp voltage VSLOP, the feedback voltage VFB, the first logic signal SSTL, and the second logic signal SSTH can be expressed as follows: After the LDO circuit 10 is started, the ramp voltage VSLOP rises linearly as the current source S continuously charges the first capacitor C1. The feedback voltage VFB also rises linearly with the ramp voltage until the current in the second N-type enhancement transistor MN1 equals the reference current provided by the N-type power transistor DN1, at which point the feedback voltage VFB reaches a steady-state value. After the feedback voltage VFB reaches the steady-state value, the ramp voltage VSLOP continues to rise linearly to the power supply voltage VDD. When the ramp voltage VSLOP is greater than or equal to the threshold voltage of the first inverter SCHMIT, the first logic signal SSTL output by the first inverter SCHMIT transitions from a high level to a low level, and the second logic signal SSTH output by the second inverter INV transitions from a low level to a high level. Furthermore, the high level of the second logic signal SSTH fully turns on the first N-type enhancement transistor MN4, while the low level of the first logic signal SSTL fully turns off the second N-type enhancement transistor MN5. Consequently, the voltage at the negative input of the operational amplifier AMP drops, while the voltage at the output rises to the power supply voltage VDD. During this process, since the second N-type enhancement transistor MN5 is fully turned off, the feedback voltage VFB exits the second loop, effectively preventing the second loop from affecting the power supply rejection ratio of the LDO circuit 10.

[0110] The embodiment of the present application provides a chip, wherein a Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3A 、 Figure 3B 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 Any circuit shown is an LDO circuit as described in the embodiment. This embodiment is a chip implementation corresponding to the aforementioned LDO circuit embodiment, and this embodiment can be implemented in conjunction with the LDO circuit implementation. The relevant technical details mentioned in the LDO circuit implementation are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the LDO circuit implementation.

[0111] An embodiment of the present application provides an electronic device, which may include the above-mentioned chip.

[0112] The electronic device mentioned in this application is introduced below. It is understood that the electronic device can be any electronic device including the above-mentioned LDO circuit. The scope of the present invention includes, but is not limited to: mobile phones (including foldable phones and candy-bar phones), tablet computers, desktop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), portable Android devices (PADs), personal digital assistants (PDAs), handheld devices, computing devices, vehicle-mounted devices or wearable devices with wireless communication capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and other mobile or fixed terminals, power banks and other electronic devices with data transmission synchronization requirements.

[0113] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0114] While the present application has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. An LDO circuit, characterized in that: The LDO circuit includes a reference circuit, a driving circuit, a power tube unit and a soft start circuit, and the soft start circuit includes a first current source unit, a first capacitor unit and a third switch circuit; The first end of the first current source unit is used to be connected to the first end of the reference circuit, the first end of the driving circuit, the first end of the power tube unit, and the power supply end, and the second end of the first current source unit is respectively connected to the first end of the first capacitor unit and the first end of the third switch circuit; The second end of the reference circuit is connected to the second end of the driving circuit, and the third end of the reference circuit is grounded; The third end of the driving circuit is connected to the second end of the power tube unit, and the fourth end of the driving circuit is connected to the second end of the third switch circuit; The third end of the power tube unit is used to connect to the third end of the reference circuit, the second end of the first capacitor unit, the third end of the third switch circuit, and the output end of the LDO circuit; Wherein, at the first moment after the LDO circuit is started, the reference circuit outputs a reference current, the driving circuit is in an on state, the third switch circuit is in an off state, the power tube unit is in an off state, and the first current source unit charges the first capacitor unit; At a second moment after the LDO circuit is started, the third switch circuit is in a conducting state, and the power tube unit is in a conducting state.

2. The LDO circuit according to claim 1, wherein: The LDO circuit further includes a voltage division sampling circuit, a first switching circuit, and a second switching circuit; The first end of the voltage-dividing sampling circuit is connected to the third end of the power tube unit and the output end of the LDO circuit respectively; The second end of the voltage-dividing sampling circuit is connected to the fourth end of the reference circuit; The third end of the voltage-dividing sampling circuit is respectively connected to the third end of the reference circuit, the second end of the first capacitor unit, and the third end of the third switch circuit; The first end of the first switch circuit is respectively connected to the first end of the drive circuit, the first end of the power tube unit, the first end of the second switch circuit, the first end of the first current source unit, and the power supply end; The second end of the first switch circuit is connected to the first end of the reference circuit; The second end of the second switch circuit is connected to the third end of the drive circuit and the second end of the power tube unit respectively.

3. The LDO circuit according to claim 2, wherein: The first current source unit includes a current source, the first capacitor unit includes a first capacitor, and the third switch circuit includes a first switch tube; The first end of the current source is respectively connected to the first end of the driving circuit, the first end of the power tube unit, the first end of the first switch circuit, the first end of the second switch circuit, and the power supply end; The second end of the current source is connected to the first end of the first capacitor and the gate of the first switch tube respectively; The second end of the first capacitor is connected to the third end of the reference circuit, the third end of the voltage-dividing sampling circuit, and the source of the first switch tube respectively; The drain of the first switch tube is connected to the fourth end of the drive circuit.

4. The LDO circuit according to claim 3, wherein: The reference circuit includes an N-type power transistor and a second N-type enhancement transistor, the driving circuit includes a second P-type enhancement transistor and a third N-type enhancement transistor, the power transistor unit includes a first P-type power transistor, the voltage divider sampling circuit includes a second resistor and a third resistor, the first switch circuit includes a second switch transistor, and the second switch circuit includes a third switch transistor; The drain of the N-type power transistor is connected to the drain of the second switching transistor, the gate of the N-type power transistor is connected to the source of the N-type power transistor, and the source of the N-type power transistor is connected to the drain of the second N-type enhancement transistor and the gate of the third N-type enhancement transistor respectively; The source of the second N-type enhancement transistor is grounded, and the gate of the second N-type enhancement transistor is connected to the second end of the second resistor and the first end of the third resistor respectively; The source of the second P-type enhancement tube is respectively connected to the power supply end, the source of the second switch tube, the source of the third switch tube, the source of the first P-type power tube, and the first end of the current source; the drain of the second P-type enhancement tube is respectively connected to the gate of the second P-type enhancement tube and the drain of the third N-type enhancement tube; the gate of the second P-type enhancement tube is respectively connected to the drain of the third switch tube and the gate of the first P-type power tube; The source of the third N-type enhancement tube is connected to the drain of the first switching tube; The drain of the first P-type power tube is connected to the output end of the LDO circuit and the first end of the second resistor respectively; The second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the source of the second N-type enhancement transistor, the source of the first switching transistor, and the second end of the first capacitor respectively; The gate of the second switch tube is used to receive a first enable signal; The gate of the third switch tube is used to receive a second enable signal.

5. The LDO circuit according to claim 4, wherein: The LDO circuit includes an operational amplifier circuit; The first end of the operational amplifier circuit is connected to the first end of the third switching circuit, the second end of the operational amplifier circuit is connected to the second end of the voltage divider sampling circuit, and the third end of the operational amplifier circuit is respectively connected to the second end of the first current source unit and the first end of the first capacitor unit.

6. The LDO circuit according to claim 5, wherein: The operational amplifier circuit includes an operational amplifier; The output end of the operational amplifier is connected to the gate of the first switching tube, the negative input end of the operational amplifier is connected to the second end of the second resistor and the first end of the third resistor respectively, and the positive input end of the operational amplifier is connected to the second end of the current source and the first end of the first capacitor respectively.

7. The LDO circuit according to claim 6, wherein: The LDO circuit includes a zero-pole compensation circuit; The first end of the zero-pole compensation circuit is connected to the first end of the third switch circuit and the first end of the operational amplifier circuit respectively; The second end of the zero-pole compensation circuit is respectively connected to the third end of the reference circuit, the third end of the third switch circuit, the second end of the first capacitor unit, and the third end of the voltage divider sampling circuit.

8. The LDO circuit according to claim 7, wherein: The zero-pole compensation circuit includes a first resistor and a second capacitor; The first end of the first resistor is connected to the gate of the first switch tube and the output end of the operational amplifier respectively; The second end of the first resistor is connected to the first end of the second capacitor; The second end of the second capacitor is respectively connected to the source of the second N-type enhancement tube, the source of the first switch tube, the second end of the first capacitor, and the second end of the third resistor.

9. The LDO circuit according to claim 8, wherein: The LDO circuit includes a power circuit, a control circuit and an inverter circuit; The first end of the power circuit is used to be connected to the power supply end; The second end of the power circuit is respectively connected to the first end of the third switch circuit, the first end of the operational amplifier circuit, and the first end of the zero-pole compensation circuit; The third terminal of the power circuit is connected to the first terminal of the inverter circuit; The first end of the control circuit is connected to the second end of the operational amplifier circuit, and the second end of the control circuit is connected to the second end of the voltage divider sampling circuit; The third end of the control circuit is respectively connected to the third end of the reference circuit, the third end of the third switch circuit, the second end of the first capacitor unit, the third end of the voltage divider sampling circuit, and the second end of the zero-pole compensation circuit; The fourth terminal of the control circuit is connected to the second terminal of the inverter circuit; The fifth terminal of the control circuit is connected to the first terminal of the inverter circuit; The first end of the inverter circuit is respectively connected to the third end of the power circuit and the fifth end of the control circuit, the second end of the inverter circuit is connected to the fourth end of the control circuit, and the third end of the inverter circuit is respectively connected to the second end of the first current source unit, the first end of the first capacitor unit, and the third end of the operational amplifier circuit.

10. The LDO circuit according to claim 9, wherein: The power circuit includes a first P-type enhancement tube, the control circuit includes a first N-type enhancement tube and a second N-type enhancement tube, and the inverter circuit includes a first inverter and a second inverter; The source electrode of the first P-type enhancement tube is used to be connected to the power supply end; The drain of the first P-type enhancement tube is connected to the gate of the first switch tube, the output end of the operational amplifier, and the first end of the first resistor respectively; The gate of the first P-type enhancement tube is used to receive a first logic signal; The drain of the first N-type enhancement tube is connected to the drain of the second N-type enhancement tube and the negative input terminal of the operational amplifier respectively; The gate of the first N-type enhancement transistor is used to receive a second logic signal; The source of the first N-type enhancement tube is respectively connected to the source of the second N-type enhancement tube, the second end of the first capacitor, the source of the first switch tube, the second end of the third resistor, and the second end of the second capacitor; The source of the second N-type enhancement transistor is connected to the second end of the second resistor and the first end of the third resistor respectively, and the gate of the second N-type enhancement transistor is used to receive the first logic signal; The input end of the first inverter is used to receive a ramp voltage signal, the output end of the first inverter is connected to the input end of the second inverter, the output end of the first inverter is used to output the first logic signal, and the output end of the second inverter is used to output the second logic signal.

11. A chip, characterized in that: The LDO circuit comprises the LDO circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: Comprising the chip according to claim 11.

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