Fine-grained security tracking model modeling method and system facing side channel attack

Abstract

The invention discloses a side channel attack-oriented fine-grained security tracking model modeling method and system. The method comprises the following steps of: defining a sensitive tag; constructing a side channel tracking logic formula of the basic logic gate according to the input and output signals and the truth table of the corresponding sensitive tag; logic information in a circuit to be modeled is extracted, and a time label is added to each signal in the logic information; adding the basic logic gate and side channel tracking logic formulas of other gate-level structures to a side channel tracking logic library; mapping the logic information of the circuit to be modeled to a side channel tracking logic library, adding a side channel tracking logic formula for each logic unit of the circuit to be modeled, and generating a safety tracking model; verifying whether all logic units of the security tracking model generate corresponding side channel tracking logic expressions or not; solving the safety tracking model by using a Z3 solver, and generating a leakage path; the method has the advantage that the information leakage path is accurately positioned.

Description

Technical Field

[0001] The present invention relates to the field of hardware security technology, and in particular to a method and system for modeling a fine-grained security tracing model for side-channel attacks. Background Art

[0002] As the theoretical security of cryptographic algorithms continues to improve, cryptographic chips based on application-specific integrated circuits (ASICs) have become widely used in the information security industry. As a crucial carrier of information security, the physical security of cryptographic chips requires thorough analysis. Because cryptographic chips inevitably leak physical information such as power consumption, electromagnetic fields, latency, sound, and photons during their physical interactions with the surrounding environment, side-channel attacks (SCA) have gradually become a core threat to hardware system security. These attacks, by collecting physical side-channel information from target devices and combining it with statistical analysis methods, can effectively crack encryption keys or steal sensitive data. Therefore, developing fine-grained risk assessment methods for side-channel attacks, which can accurately locate information leakage paths and provide a theoretical basis for designing targeted protection mechanisms, is of great practical significance.

[0003] Side-channel attacks are a type of non-invasive attack technique that exploits physical information leaks generated during the operation of cryptographic devices. Depending on the source of the leak, they are primarily categorized as power analysis attacks, electromagnetic radiation attacks, and timing analysis attacks. For example, differential power analysis (DPA) can recover the secret keys of algorithms like AES by statistically correlating key guesses with power consumption waveforms. Cache timing attacks exploit timing differences in shared caches to infer sensitive operations. Unlike traditional cryptanalysis, side-channel attacks do not require breaching the mathematical strength of the algorithm. Instead, they reverse-engineer the secret key from physical layer signals, resulting in a stealthy and highly successful attack. Chinese Patent Publication No. CN118784204A discloses a method for detecting side-channel attacks in quantum key distribution (QKD) based on federated deep learning. The method collects side-channel data from multiple QKD nodes; initializes a deep learning model for pattern recognition and anomaly detection on each node; and uses the collected side-channel data to train a deep learning model on each node to identify and classify side-channel attack patterns in QKD. However, this patent application only identifies side-channel attack patterns and cannot locate information leakage paths.

[0004] In summary, after extensive research, we have found that existing technologies still have limitations when constructing complete leakage paths in side-channel security analysis. Existing static analysis models lack dynamic timing correlation, making it difficult to capture the dynamic timing dependencies of leakage paths in multi-cycle operations, resulting in incomplete path coverage or misjudgments. To address this issue, there is currently a lack of effective fine-grained detection methods. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the existing side-channel attack detection method cannot accurately locate the information leakage path, resulting in incomplete path coverage or misjudgment, and thus unable to provide targeted protection.

[0006] The present invention solves the above technical problems by the following technical means: a method for modeling a fine-grained security tracking model for side-channel attacks, comprising:

[0007] S1. Define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 depending on whether the sensitive variable has a leakage risk.

[0008] S2. Define time tags;

[0009] S3. Construct the side channel tracking logic formula of the basic logic gate based on the truth table of the input and output signals and the corresponding sensitive labels;

[0010] S4. Extracting logic information from the circuit to be modeled and adding a time tag to each signal therein;

[0011] S5. Construct the side channel tracing logic of the basic logic gate according to the side channel tracing logic formula of the basic logic gate, add the corresponding side channel tracing logic formula after converting other gate-level structures into the form of basic logic gates, and then add the side channel tracing logic formulas of the basic logic gates and other gate-level structures to the side channel tracing logic library;

[0012] S6. Mapping the logic information of the circuit to be modeled to the side channel tracing logic library, adding a side channel tracing logic formula to each logic unit of the circuit to be modeled, and generating a security tracing model;

[0013] S7: Verify whether all logic units of the security tracking model have generated corresponding side channel tracking logic expressions. If so, proceed to S8; if not, construct side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions.

[0014] S8. Use the Z3 solver to solve the security tracking model and generate the leakage path.

[0015] Furthermore, S1 includes:

[0016] When a logic unit receives a sensitive variable and the sensitive variable undergoes state maintenance or state flipping, if the output state of the logic unit is consistent with the state change of the sensitive variable, the sensitive label of the logic unit is set to 1; otherwise, it is set to 0; state maintenance means that the state remains unchanged, and state flipping means that the state changes from 0 to 1 or from 1 to 0.

[0017] Furthermore, the basic logic gates include an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate and an XOR gate.

[0018] Furthermore, when the basic logic gate is an AND gate, its two input signals are A and B, the output signal is Y, and the corresponding sensitive labels are a, b, y. According to its truth table, the side channel tracking logic formula is:

[0019]

[0020] Where i is a time label, indicating the i-th clock cycle; represents the negation of signal A in the i-th clock cycle, A[i] represents signal A in the i-th clock cycle, and ⊙ represents the exclusive-or operator.

[0021] Furthermore, when adding a time tag, if the logic unit is a sequential logic unit, that is, the input signal and the output signal are in different clock cycles, the time tag of the input signal is set to i, and the time tag of the output signal is set to i+1; if the input signal and the output signal of the logic unit are in the same clock cycle, the time tags of the input signal and the output signal are consistent.

[0022] Furthermore, S7 includes:

[0023] The types of all logic units in the safety tracing model are displayed, and the results are compared with the logic gate library generated by the input of the safety tracing model into the Z3 parser. If any type of logic gate in the safety tracing model does not appear in the logic gate library, an error is reported, and the side channel tracing logic formula of the logic gate is constructed and added to the safety tracing model. If all types of logic gates in the safety tracing model appear in the logic gate library, then enter S8.

[0024] Furthermore, S8 includes:

[0025] The solution obtained by the Z3 solver displays the logical values ​​of all signals in the security tracking model and their sensitivity labels. The sensitive signal set is extracted from the solution. The sensitive signal set refers to signals with a sensitivity label of 1 and continuous time labels. The logic units corresponding to all signals with a sensitivity label of 1 are topologically sorted in ascending order of time labels to form a leakage path diagram across clock cycles.

[0026] The present invention also provides a fine-grained security tracking modeling system for side-channel attacks, including:

[0027] The first definition module is used to define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 according to whether there is a leakage risk of the sensitive variable;

[0028] The second definition module is used to define the time label;

[0029] A basic logic building module, used to construct the side channel tracking logic formula of the basic logic gate according to the truth table of the input and output signals and the corresponding sensitive labels;

[0030] A time label adding module is used to extract the logic information in the circuit to be modeled and add a time label to each signal therein;

[0031] a library construction module, configured to construct side channel tracing logic of basic logic gates according to the side channel tracing logic formulas of basic logic gates, add corresponding side channel tracing logic formulas after converting other gate-level structures into basic logic gate forms, and then add the side channel tracing logic formulas of the basic logic gates and other gate-level structures into the side channel tracing logic library;

[0032] A modeling module is used to map the logic information of the circuit to be modeled to the side channel tracing logic library, add the side channel tracing logic formula to each logic unit of the circuit to be modeled, and generate a security tracing model;

[0033] The integrity verification module is used to verify whether all logic units in the security tracking model have generated corresponding side channel tracking logic expressions. If so, it enters the result output module. If not, it constructs side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions;

[0034] The result output module is used to solve the safety tracking model using the Z3 solver and generate the leakage path.

[0035] Furthermore, the first definition module is further configured to:

[0036] When a logic unit receives a sensitive variable and the sensitive variable undergoes state maintenance or state flipping, if the output state of the logic unit is consistent with the state change of the sensitive variable, the sensitive label of the logic unit is set to 1; otherwise, it is set to 0; state maintenance means that the state remains unchanged, and state flipping means that the state changes from 0 to 1 or from 1 to 0.

[0037] Furthermore, the basic logic gates include an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate and an XOR gate.

[0038] Furthermore, when the basic logic gate is an AND gate, its two input signals are A and B, the output signal is Y, and the corresponding sensitive labels are a, b, y. According to its truth table, the side channel tracking logic formula is:

[0039]

[0040] Where i is a time label, indicating the i-th clock cycle; represents the negation of signal A in the i-th clock cycle, A[i] represents signal A in the i-th clock cycle, and ⊙ represents the exclusive-or operator.

[0041] Furthermore, when adding a time tag, if the logic unit is a sequential logic unit, that is, the input signal and the output signal are in different clock cycles, the time tag of the input signal is set to i, and the time tag of the output signal is set to i+1; if the input signal and the output signal of the logic unit are in the same clock cycle, the time tags of the input signal and the output signal are consistent.

[0042] Furthermore, the integrity verification module is also used to:

[0043] The types of all logic units in the safety tracing model are displayed, and the results are compared with the logic gate library generated by the Z3 parser when the safety tracing model is input. If any type of logic gate in the safety tracing model does not appear in the logic gate library, an error is reported, and the side channel tracking logic formula of the logic gate is constructed and added to the safety tracing model. If all types of logic gates in the safety tracing model appear in the logic gate library, the result output module is entered.

[0044] Furthermore, the result output module is also used to:

[0045] The solution obtained by the Z3 solver displays the logical values ​​of all signals in the security tracking model and their sensitivity labels. The sensitive signal set is extracted from the solution. The sensitive signal set refers to signals with a sensitivity label of 1 and continuous time labels. The logic units corresponding to all signals with a sensitivity label of 1 are topologically sorted in ascending order of time labels to form a leakage path diagram across clock cycles.

[0046] The advantages of the present invention are:

[0047] (1) The present invention extracts the logic information in the circuit to be modeled and adds a time tag to each signal therein, thereby being able to capture the dynamic timing dependency of the leakage path in multi-cycle operations. The logic information of the circuit to be modeled is mapped to the side channel tracing logic library, and a side channel tracing logic formula is added to each logic unit of the circuit to be modeled to generate a security tracing model. At the same time, the integrity of the logic unit in the security tracing model is also verified. Finally, the security tracing model is solved by the Z3 solver to generate the leakage path, accurately locate the information leakage path, and accurately characterize the dynamic propagation path of sensitive information in the timing circuit, which helps to carry out targeted protection.

[0048] (2) Compared with traditional static analysis methods, the present invention improves the side channel risk detection coverage across clock cycles, and through the separation of timing constraints of time tags, eliminates the interference of self-satisfied loops and self-contradictory loops, reduces the false alarm rate and missed alarm rate, and significantly improves the accuracy and reliability of hardware design side channel protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a flowchart of a method for modeling a fine-grained security tracking model for side-channel attacks disclosed in Example 1 of the present invention;

[0050] Figure 2 This is a schematic diagram of multiple clock cycles in a fine-grained security tracking model modeling method for side channel attacks disclosed in Example 1 of the present invention, wherein: Figure 2 (a) is the original design, Figure 2 (b) is the graph obtained by adding time labels to each signal based on the original design;

[0051] Figure 3 This is an example of adding a time tag to the fine-grained security tracking model modeling method for side-channel attacks disclosed in Example 1 of the present invention;

[0052] Figure 4 The pseudo code of the algorithm for constructing a fine-grained security tracking model for side-channel attacks disclosed in Example 1 of the present invention;

[0053] Figure 5 This is a schematic diagram of the process of constructing a side channel tracking logic library in a fine-grained security tracking model modeling method for side channel attacks disclosed in Example 1 of the present invention;

[0054] Figure 6 This is a schematic diagram of an AES circuit integrity detection report in a fine-grained security tracking model modeling method for side-channel attacks disclosed in Example 1 of the present invention. DETAILED DESCRIPTION

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] Example 1

[0057] like Figure 1 As shown, embodiment 1 of the present invention provides a method for modeling a fine-grained security tracking model for side channel attacks, comprising the following steps:

[0058] S1. Define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 depending on whether the sensitive variable has a leakage risk. The specific process is as follows:

[0059] Side-channel attack leakage model analysis. In a side-channel attack scenario, the attacker collects power consumption or electromagnetic radiation data leaked during circuit operation and, combined with known plaintext input, builds a side-channel information leakage model based on the Hamming weight model (e.g., the linear correlation between key bits and power consumption). The generation of information leakage paths stems from the propagation characteristics of logic units for sensitive variables. When a leakage path exists, the attacker can use statistical analysis methods such as the Pearson correlation coefficient to calculate the correlation trajectory between the leakage model and the actual side-channel waveform, thereby locating the key leakage point.

[0060] This paper defines the leakage sensitivity of a logic gate as the contribution of its output power distribution to the characteristics of the leakage path when the sensitive input variable undergoes a state flip or state retention. By introducing a time tagging mechanism, the dynamic propagation behavior of sensitive tags over multiple cycles is analyzed to accurately identify leakage paths that span clock cycles, thereby improving the timing coverage of side-channel risk detection.

[0061] Develop a sensitive label propagation strategy. Taking a specific logic unit as an example, when developing a propagation strategy, assume that the unit receives sensitive variables from a front-end source unit or intermediate unit. When the sensitive variable undergoes state retention (0→0 or 1→1) or state flipping (0→1 or 1→0), while the output state remains consistent, the unit is on the leakage path, and its power consumption distribution should reflect the leakage characteristics of the front-end unit. This phenomenon is defined as leakage attribute propagation. The sensitive variable refers to the input received by the current logic unit. In other words, as long as the output state remains unchanged due to the input state retention / flip (the two remain consistent), the side channel leakage risk is propagated. That is, if the output of the current logic unit is consistent with the input of the current logic unit that caused the output to change, the current unit is on the leakage path. A counterexample is when the input state flips but the output is not affected. If the output does not flip at this time, the input bit flip is not propagated, and the leakage risk is not propagated. If, after the sensitive variable is input into the current logic unit, the output state is maintained / flipped due to the input state maintenance / flip, the side channel leakage risk is propagated and the sensitivity label of the current logic unit is set to 1; otherwise, the sensitivity label is set to 0.

[0062] To simplify the complexity of the model, it is assumed that the power consumption difference between state maintenance (0→0 and 1→1) and state flipping (0→1 and 1→0) can be ignored (the error tolerance threshold is set based on the measured data). The intermediate unit only needs to track the impact of sensitive variable flipping on its output, and changes in non-sensitive inputs do not participate in the propagation calculation.

[0063] S2. Define the time tag; the specific process is as follows:

[0064] In order to solve the modeling problem of feedback loops in sequential circuits, a multi-cycle unfolding method for sequential circuits is proposed based on the bounded model checking theory. This method uses a timing tag mechanism to add time tags to the circuit and unfold the sequential logic circuit over multiple clock cycles to monitor and record the circuit's behavior. In order to distinguish the same signal at different times, each signal in the circuit is assigned a time tag. Figure 2 As shown, Figure 2 (a) is the original design, adding a time tag to each signal to obtain Figure 2 (b) For a combinational logic gate, the change of the input and the corresponding output are completed in the same clock cycle, so the time labels of the input and output of the combinational logic gate are consistent, that is, t out =t in For sequential logic, such as registers, the change of register data input and output occurs in different clock cycles, so the output time label is the input time label plus 1, that is, t out =t in +1. Figure 2 Taking FF1 in (b) as an example, its formal logic can be expressed as: B[i+1]=f(A[i],D[i]), which means that A and D in the i-th cycle are assigned to B in the i+1th clock cycle after a series of logical operations.

[0065] S3. Construct the side channel tracking logic formula of the basic logic gate based on the truth table of the input and output signals and the corresponding sensitive labels. The specific process is as follows:

[0066] Construct side-channel tracking logic formulas for basic logic gates. This paper defines the propagation mechanism of sensitive labels and time labels for basic logic gates through mathematical formulas. By constructing truth tables and Karnaugh maps, the relationship between the leakage sensitivity of the logic gate output and its input is studied, and specific label propagation expressions for each logic gate are derived. Taking a two-input AND gate as an example, the input and output signals are represented by capital letters A, B, and Y, respectively; the corresponding sensitive labels are represented by a, b, and y, respectively. A partial truth table for a two-input AND gate is as follows:

[0067]

[0068] The sensitive information propagation mechanism caused by state flip is as described above. If there is no state flip in the input and the output, the sensitive attributes remain consistent with the input.

[0069] The side channel tracking logic expression of the two-input AND gate is obtained as follows:

[0070]

[0071] Using the same method and basic properties of information flow, side channel security models can be established for other basic logic gates, such as OR gates, XOR gates, etc., and logical expressions can be constructed based on truth tables. Constructing logical expressions based on truth tables is a conventional technology in this field and will not be elaborated here.

[0072] Taking the AES encryption algorithm circuit as an example, information flow tracing technology was used to perform comprehensive optimization on the verification module. Information flow tracing is a port-based technology that detects the flow of information within a circuit. This feature is leveraged during the synthesis phase to perform sensitive attribute-driven logic pruning. Based on pre-set security boundaries (such as key-related signals), the Synopsys DesignCompiler (DC) tool is used to prune logic ports associated with non-sensitive paths, reducing verification complexity. The optimization process also ensures that the timing characteristics of the original circuit are not compromised, maintaining the validity of the multi-cycle unrolled model.

[0073] S4. Extract the logic information in the circuit to be modeled and add a time tag to each signal therein. The specific process is as follows:

[0074] Extract the logic information in the netlist (i.e. the circuit to be modeled) and add time tags. Use the multi-cycle expansion method described in S2 to expand the sequential circuit into multiple clock cycles. Use an automated script to traverse the netlist. When extracting the logic of the gate-level netlist, add time tags to each variable based on the timing characteristics of the standard cell to achieve complete verification of the behavior of the sequential circuit in different clock cycles. Figure 3 As shown, DFFRHQX1 is a register unit with a reset function. Because this unit is a sequential logic unit, its input and output signals are in different clock cycles. If the input signal of this register unit is in cycle i, then the input signal must be assigned to the register output in cycle i+1. Therefore, the output signal has a timestamp of i+1. AND2X2, as a combinational logic unit, completes its assignment operation within the same clock cycle, so the timestamps of its input and output ports are consistent.

[0075] S5. Construct the side channel tracing logic of the basic logic gate based on the side channel tracing logic formula of the basic logic gate. After converting other gate-level structures into the basic logic gate form, add the corresponding side channel tracing logic formula. Then, add the side channel tracing logic formula of the basic logic gate and other gate-level structures to the side channel tracing logic library. The specific process is as follows:

[0076] Use the construction algorithm to build a side channel tracking logic library. The pseudo code of the construction algorithm is as follows Figure 4As shown in the figure, in the logic netlist, the most basic logic gates for both combinational logic circuits and sequential logic circuits are AND gates, OR gates, and NOT gates. The elements of combinational logic can be composed of these basic gates, while sequential logic circuits add time tags on this basis. Figure 5 As shown, in order to build the side-channel tracing logic of all netlist elements, it is necessary to first build the side-channel tracing logic of the basic gates and expand the formal description of the basic gates into other gate-level structures and add them to the side-channel tracing logic library, and repeat this cycle until a complete side-channel tracing logic library is built. Figure 5 IFT (Information Flow Tracking) stands for information flow tracking.

[0077] S6. Map the logic information of the circuit to be modeled to the side channel tracing logic library, add the side channel tracing logic formula to each logic unit of the circuit to be modeled, complete the formal modeling, and generate a security tracing model; that is, map the logic information of the circuit to be modeled extracted by S4 to the side channel tracing logic library, and add the side channel tracing logic to each logic unit.

[0078] S7: Verify whether all logic units in the security tracking model have generated corresponding side channel tracking logic expressions. If so, proceed to S8. If not, construct side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions. The specific process is as follows:

[0079] To ensure the integrity of the model, the original logic expressions of all gate-level structures are generated with corresponding side channel tracing logic expressions. The types of logic gates that make up the netlist are displayed, and the results are compared with the logic gate library used in the netlist to Z3 parser code generation. If any type of logic gate in the netlist does not appear in the preset logic gate library, an error will be reported, and the side channel tracing logic formula for the logic gate will be added to the security tracing model to ensure the integrity of the model. Figure 6 As shown, taking the netlist of the AES circuit as an example, the integrity detection report is displayed. From this report, it can be concluded that the number of logic units in the netlist is the same as the number of logic units in its corresponding side channel tracking logic modeling, that is, the modeling is complete.

[0080] S8. Use the Z3 solver to solve the security tracking model and generate the leakage path. The specific process is as follows:

[0081] The Z3 solver is used for the solution. The Z3SMT (Satisfiability Modulo Theories) solver performs information flow reachability analysis, inputs the established security tracing model, generates leakage path constraint equations, and then performs a Boolean solution. The leakage risk is determined based on the sensitive label contamination constraint. Specifically, if the output signal sensitive label is true, the logic unit is at risk of leakage.

[0082] The solution obtained from the Z3 solver can display the logical values ​​of all signals and their labels. The sensitive signal set (i.e., signals with a sensitive label of 1 and continuous time labels) is extracted from the solution results. First, based on the sensitive signal nodes, the logical dependency relationship is reversed back to the sensitive source (such as the key register) to locate the starting point of the leakage path. Then, all the signal nodes involved are topologically sorted, and a leakage path diagram across clock cycles is constructed in ascending order of time labels, clearly showing the signal propagation path in the timing dimension. Finally, the complete side channel leakage path that meets the timing constraints is output.

[0083] Through the above technical solutions, compared with the existing technology, the present invention effectively solves the core problems of incomplete multi-cycle leakage path coverage, feedback loop false alarms, and missed reports caused by the lack of timing correlation in traditional side-channel analysis by introducing a time tag mechanism and a multi-cycle expansion method. Based on a fine-grained security tracking model, the dynamic propagation path of sensitive information in the timing circuit can be accurately characterized. Compared with traditional static analysis methods, the cross-clock cycle side channel risk detection coverage is improved, and through the separation of timing constraints of time tags, the interference of self-satisfied loops and self-contradictory loops is eliminated, the false alarm rate and missed report rate are reduced, and the accuracy and reliability of hardware design side channel protection are significantly improved.

[0084] Example 2

[0085] Based on Example 1, Example 2 of the present invention further provides a fine-grained security tracking modeling system for side-channel attacks, including:

[0086] The first definition module is used to define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 according to whether there is a leakage risk of the sensitive variable;

[0087] The second definition module is used to define the time label;

[0088] A basic logic building module, used to construct the side channel tracking logic formula of the basic logic gate according to the truth table of the input and output signals and the corresponding sensitive labels;

[0089] A time label adding module is used to extract the logic information in the circuit to be modeled and add a time label to each signal therein;

[0090] a library construction module, configured to construct side channel tracing logic of basic logic gates according to the side channel tracing logic formulas of basic logic gates, add corresponding side channel tracing logic formulas after converting other gate-level structures into basic logic gate forms, and then add the side channel tracing logic formulas of the basic logic gates and other gate-level structures into the side channel tracing logic library;

[0091] A modeling module is used to map the logic information of the circuit to be modeled to the side channel tracing logic library, add the side channel tracing logic formula to each logic unit of the circuit to be modeled, and generate a security tracing model;

[0092] The integrity verification module is used to verify whether all logic units in the security tracking model have generated corresponding side channel tracking logic expressions. If so, it enters the result output module. If not, it constructs side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions;

[0093] The result output module is used to solve the safety tracking model using the Z3 solver and generate the leakage path.

[0094] Specifically, the first definition module is further used to:

[0095] When a logic unit receives a sensitive variable and the sensitive variable undergoes state maintenance or state flipping, if the output state of the logic unit is consistent with the state change of the sensitive variable, the sensitive label of the logic unit is set to 1; otherwise, it is set to 0; state maintenance means that the state remains unchanged, and state flipping means that the state changes from 0 to 1 or from 1 to 0.

[0096] Specifically, the basic logic gates include an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, and an XOR gate.

[0097] Specifically, when the basic logic gate is an AND gate, its two input signals are A and B, the output signal is Y, and the corresponding sensitive labels are a, b, y. According to its truth table, the side channel tracking logic formula is:

[0098]

[0099] Where i is a time label, indicating the i-th clock cycle; represents the negation of signal A in the i-th clock cycle, A[i] represents signal A in the i-th clock cycle, and ⊙ represents the exclusive-or operator.

[0100] Specifically, when adding a time tag, if the logic unit is a sequential logic unit, that is, the input signal and output signal are in different clock cycles, the time tag of the input signal is set to i, and the time tag of the output signal is set to i+1; if the input signal and output signal of the logic unit are in the same clock cycle, the time tags of the input signal and the output signal are consistent.

[0101] Specifically, the integrity verification module is also used to:

[0102] The types of all logic units in the safety tracing model are displayed, and the results are compared with the logic gate library generated by the Z3 parser when the safety tracing model is input. If any type of logic gate in the safety tracing model does not appear in the logic gate library, an error is reported, and the side channel tracking logic formula of the logic gate is constructed and added to the safety tracing model. If all types of logic gates in the safety tracing model appear in the logic gate library, the result output module is entered.

[0103] Specifically, the result output module is also used to:

[0104] The solution obtained by the Z3 solver displays the logical values ​​of all signals in the security tracking model and their sensitivity labels. The sensitive signal set is extracted from the solution. The sensitive signal set refers to signals with a sensitivity label of 1 and continuous time labels. The logic units corresponding to all signals with a sensitivity label of 1 are topologically sorted in ascending order of time labels to form a leakage path diagram across clock cycles.

[0105] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A fine-grained security tracking model modeling method for side-channel attacks, characterized by: include: S1. Define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 depending on whether the sensitive variable has a leakage risk. S2. Define time tags; S3. Construct the side channel tracking logic formula of the basic logic gate based on the truth table of the input and output signals and the corresponding sensitive labels; S4. Extracting logic information from the circuit to be modeled and adding a time tag to each signal therein; S5. Construct the side channel tracing logic of the basic logic gate according to the side channel tracing logic formula of the basic logic gate, add the corresponding side channel tracing logic formula after converting other gate-level structures into the form of basic logic gates, and then add the side channel tracing logic formulas of the basic logic gates and other gate-level structures to the side channel tracing logic library; S6. Mapping the logic information of the circuit to be modeled to the side channel tracing logic library, adding a side channel tracing logic formula to each logic unit of the circuit to be modeled, and generating a security tracing model; S7: Verify whether all logic units of the security tracking model have generated corresponding side channel tracking logic expressions. If so, proceed to S8; if not, construct side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions. S8. Use the Z3 solver to solve the security tracking model and generate the leakage path.

2. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: S1 includes: When a logic unit receives a sensitive variable and the sensitive variable undergoes state maintenance or state flipping, if the output state of the logic unit is consistent with the state change of the sensitive variable, the sensitive label of the logic unit is set to 1; otherwise, it is set to 0; state maintenance means that the state remains unchanged, and state flipping means that the state changes from 0 to 1 or from 1 to 0.

3. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: The basic logic gates include an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, and an XOR gate.

4. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: When the basic logic gate is an AND gate, its two input signals are A and B, the output signal is Y, and the corresponding sensitive labels are a, b, and y. According to its truth table, the side channel tracking logic formula is: Where i is a time label, indicating the i-th clock cycle; represents the negation of signal A in the i-th clock cycle, A[i] represents signal A in the i-th clock cycle, and ⊙ represents the exclusive-or operator.

5. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: When adding time tags, if the logic unit is a sequential logic unit, that is, the input signal and output signal are in different clock cycles, the time tag of the input signal is set to i, and the time tag of the output signal is set to i+1; if the input signal and output signal of the logic unit are in the same clock cycle, the time tags of the input signal and output signal are consistent.

6. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: S7 includes: Display the types of all logic units in the safety tracing model and compare the results with the logic gate library that the safety tracing model is input into the Z3 parser generation; If any type of logic gate in the safety tracing model does not appear in the logic gate library, an error is reported and the side channel tracing logic formula for constructing that logic gate is added to the safety tracing model; If all types of logic gates in the safety tracking model appear in the logic gate library, then enter S8.

7. The method for modeling a fine-grained security tracking model for side-channel attacks according to claim 1 is characterized in that: The S8 includes: The solution obtained by the Z3 solver displays the logical values ​​of all signals in the security tracking model and their sensitivity labels. The sensitive signal set is extracted from the solution. The sensitive signal set refers to signals with a sensitivity label of 1 and continuous time labels. The logic units corresponding to all signals with a sensitivity label of 1 are topologically sorted in ascending order of time labels to form a leakage path diagram across clock cycles.

8. A fine-grained security tracking modeling system for side-channel attacks, characterized by: include: The first definition module is used to define a sensitive label. When the logic unit receives a sensitive variable, it sets its sensitive label to 1 or 0 according to whether there is a leakage risk of the sensitive variable; The second definition module is used to define the time label; A basic logic building module, used to construct the side channel tracking logic formula of the basic logic gate according to the truth table of the input and output signals and the corresponding sensitive labels; A time label adding module is used to extract the logic information in the circuit to be modeled and add a time label to each signal therein; a library construction module, configured to construct side channel tracing logic of basic logic gates according to the side channel tracing logic formulas of basic logic gates, add corresponding side channel tracing logic formulas after converting other gate-level structures into basic logic gate forms, and then add the side channel tracing logic formulas of the basic logic gates and other gate-level structures into the side channel tracing logic library; A modeling module is used to map the logic information of the circuit to be modeled to the side channel tracing logic library, add the side channel tracing logic formula to each logic unit of the circuit to be modeled, and generate a security tracing model; The integrity verification module is used to verify whether all logic units in the security tracking model have generated corresponding side channel tracking logic expressions. If so, it enters the result output module. If not, it constructs side channel tracking logic formulas for logic gates that have not generated side channel tracking logic expressions; The result output module is used to solve the safety tracking model using the Z3 solver and generate the leakage path.

9. The fine-grained security tracking modeling system for side-channel attacks according to claim 8 is characterized in that: The first definition module is also used to: When a logic unit receives a sensitive variable and the sensitive variable undergoes state maintenance or state flipping, if the output state of the logic unit is consistent with the state change of the sensitive variable, the sensitive label of the logic unit is set to 1; otherwise, it is set to 0; state maintenance means that the state remains unchanged, and state flipping means that the state changes from 0 to 1 or from 1 to 0.

10. The fine-grained security tracking modeling system for side channel attacks according to claim 8 is characterized in that: The basic logic gates include an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, and an XOR gate.

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