Display device and vehicle display device

Abstract

The invention discloses a display device which comprises a pulse width control circuit, a display circuit and a pulse amplitude control circuit. The pulse width control circuit comprises an oblique wave generation circuit and a light-emitting control circuit. The light-emitting control circuit comprises first to fifth switches, a first capacitor and a second capacitor. The display circuit comprises a light-emitting element and a sixth switch. The ramp generation circuit adjusts the voltage level of the first node according to the pulse width modulation signal. The control end of the first switch is coupled to the first node. The control end of the second switch is coupled to the first node. The control end of the third switch is coupled to the second node. The fourth switch resets the voltage level of the first node. The fifth switch resets the voltage level of the third node. The first end of the first capacitor is coupled to the first node. The first end of the second capacitor is coupled to the third node. The light-emitting element emits light according to the light-emitting control signal. The sixth switch controls light emission of the light-emitting element. The pulse amplitude control circuit provides a pulse amplitude control signal to the sixth switch.

Description

Technical Field

[0001] The present invention relates to a display technology, and more particularly to a display device and a vehicle display device. Background Art

[0002] When driving a light-emitting diode (LED) panel, the display device requires a ramp generator chip. The higher the number of components and the required voltage precision, the higher the cost and the larger the wiring area. Therefore, generating multiple pulse waveforms within the circuit using pulse-width modulation (PWM) circuits is a key issue in this field. Summary of the Invention

[0003] An embodiment of the present invention includes a display device. The display device includes a pulse width control circuit, a display circuit, and a pulse amplitude control circuit. The pulse width control circuit includes a ramp wave generation circuit and a light control circuit. The light control circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The display circuit includes a light-emitting element and a sixth switch. The ramp wave generation circuit is configured to adjust the voltage level of a first node based on a pulse width modulation signal. The first end of the first switch is coupled to a second node, and the control end of the first switch is coupled to the first node. The first end of the second switch is coupled to the second node, and the control end of the second switch is coupled to the first node. The first end of the third switch is configured to output a light control signal, and the control end of the third switch is coupled to the second node. The fourth switch is configured to reset the voltage level of the first node, and the first end of the fourth switch is coupled to the first node. The fifth switch is configured to reset the voltage level of the third node, and the first end of the fifth switch is coupled to the third node. The first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is grounded. The first end of the second capacitor is coupled to the third node. The light-emitting element is configured to emit light in response to a light-emitting control signal. A sixth switch is configured to control the light-emitting element. A first terminal of the sixth switch is coupled to the light-emitting element, and a control terminal of the sixth switch is coupled to the third node. A pulse amplitude control circuit is configured to provide a pulse amplitude control signal to the sixth switch. The pulse amplitude control circuit is coupled to a second terminal of the sixth switch.

[0004] An embodiment of the present invention includes a vehicle display device. The vehicle display device includes a pulse width control circuit, a display circuit, and a pulse amplitude control circuit. The pulse width control circuit includes a ramp wave generation circuit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The display circuit includes a light-emitting element and a sixth switch. The ramp wave generation circuit is configured to adjust the voltage level of a first node based on a pulse width modulation signal. The first end of the first switch is coupled to a second node, and the control end of the first switch is coupled to the first node. The first end of the second switch is coupled to the second node, and the control end of the second switch is coupled to the first node. The first end of the third switch is configured to output a light control signal, and the control end of the third switch is coupled to the second node. The fourth switch is configured to reset the voltage level of the first node, and the first end of the fourth switch is coupled to the first node. The fifth switch is configured to reset the voltage level of the third node, and the first end of the fifth switch is coupled to the third node. The first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is grounded. The first end of the second capacitor is coupled to the third node. A light-emitting element is placed on the vehicle body and is configured to emit light in response to a light-emitting control signal. A sixth switch is configured to control the light-emitting element. A first terminal of the sixth switch is coupled to the light-emitting element, and a control terminal of the sixth switch is coupled to the third node. A pulse amplitude control circuit is configured to provide a pulse amplitude control signal to the sixth switch. The pulse amplitude control circuit is coupled to a second terminal of the sixth switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of a display device according to some embodiments of the present invention.

[0006] Figure 2 FIG. 1 is a schematic diagram of a ramp wave generating circuit according to some embodiments of the present invention.

[0007] Figure 3 FIG. 1 is a schematic diagram of a timing diagram according to some embodiments of the present invention.

[0008] Figure 4 FIG. 1 is a schematic diagram of a timing diagram according to some embodiments of the present invention.

[0009] Figure 5 FIG. 1 is a schematic diagram of a ramp wave generating circuit according to some embodiments of the present invention.

[0010] Figure 6 FIG. 1 is a schematic diagram of a timing diagram according to some embodiments of the present invention.

[0011] Figure 7 FIG. 1 is a schematic diagram of a timing diagram according to some embodiments of the present invention.

[0012] Wherein, the reference numerals:

[0013] 100: Display device

[0014] 101: Pulse width control circuit

[0015] 110: Lighting control circuit

[0016] 120: Ramp wave generating circuit

[0017] 130: Pulse amplitude control circuit

[0018] 140: Display circuit

[0019] T11~T16, T21~T23, T51~T57: switch

[0020] C11~C12、C2、C5:capacitors

[0021] N11~N13, N21~N22, N51~N54: nodes

[0022] SS, DD: voltage signal

[0023] VGL, VGH: voltage level

[0024] RST: reset signal

[0025] PEM: light control signal

[0026] L1: Light-emitting element

[0027] PWCS: Pulse Width Control Signal

[0028] PACS: pulse amplitude control signal

[0029] 200, 500: Ramp generation circuit

[0030] PWM: Pulse Width Modulation Signal

[0031] SCN: Scan signal

[0032] EM: luminescent signal

[0033] 300, 400, 600, 700: Timing diagram

[0034] P31~P312、P41~P411、P61~P613、P71~P712: Period

[0035] VL, VH: reference voltage level

[0036] Vbp: bias signal

[0037] Vref: reference voltage signal

[0038] RD: Read signal DETAILED DESCRIPTION

[0039] In this document, when an element is referred to as being "connected" or "coupled," it may refer to being "electrically connected" or "electrically coupled." "Connected" or "coupled" may also refer to the coordinated operation or interaction between two or more elements. Furthermore, while terms such as "first," "second," and so on are used herein to describe different elements, these terms are used solely to distinguish between elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms are not intended to specifically designate or imply a sequence or order, nor are they intended to limit the present invention.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0041] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0042] The following diagrams illustrate various embodiments of the present invention. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details should not be construed as limiting the present invention. In other words, these practical details are not essential to some embodiments of the present disclosure. Furthermore, to simplify the diagrams, some commonly used structures and components are depicted in simplified schematic form.

[0043] Figure 1 FIG1 is a schematic diagram of a display device 100 according to some embodiments of the present invention. In some embodiments, the display device 100 can be placed on a vehicle body. Accordingly, the display device 100 can be referred to as a vehicle display device. Figure 1The display device 100 includes a pulse width control circuit 101, a display circuit 140, and a pulse amplitude control circuit 130. The pulse width control circuit 101 includes a ramp wave generating circuit 120 and a light emitting control circuit 110. In some embodiments, the display device 100 can be made of a glass substrate or a plastic substrate, but is not limited thereto.

[0044] In some embodiments, the ramp wave generation circuit 120 receives the pulse width modulation signal PWM and provides a pulse width control signal PWCS to the light control circuit 110. The light control circuit 110 receives the pulse width control signal PWCS and outputs a light control signal PEM to the display circuit 140. The pulse amplitude control circuit 130 provides a pulse amplitude control signal PACS to the display circuit 140 to control the light intensity of the light-emitting element L1. The display circuit 140 is configured to emit light based on the pulse amplitude control signal PACS and the light control signal PEM.

[0045] like Figure 1 As shown, the switch T11 is used to control the voltage level of the node N11. One terminal of the switch T11 is used to receive the pulse width control signal PWCS at the node N11, the control terminal of the switch T11 is used to receive the reset signal RST, and the other terminal of the switch T11 is used to receive the voltage signal SS with a voltage level VGL.

[0046] Capacitor C11 is charged according to the pulse width control signal PWCS. One end of capacitor C11 is coupled to node N11, and the other end of capacitor C11 is grounded. When switch T11 is turned on, switch T11 transmits voltage signal SS to node N11, causing node N11 to have a voltage level VGL.

[0047] Switches T12 and T13 are used to control the voltage level of node N12. One terminal of switch T12 and one terminal of switch T13 are coupled to node N12. The other terminal of switch T12 is used to receive a voltage signal DD having a voltage level VGH, and the other terminal of switch T13 is used to receive a voltage signal SS. The control terminals of switches T12 and T13 are each coupled to node N11.

[0048] In some embodiments, switches T12 and T13 have different conductivity types. For example, switches T12 and T13 can be implemented using P-type metal oxide semiconductor (PMOS) and N-type metal oxide semiconductor (NMOS) transistors, respectively. When node N11 has a voltage potential of VGH, switch T12 is turned off and switch T13 is turned on, causing node N12 to have a voltage potential of VGL.

[0049] like Figure 1As shown, switches T14 and T15 are used to control the voltage level of node N13. One end of switch T14 and one end of switch T15 are coupled to node N13. The other end of switch T14 is used to receive voltage signal DD, and the other end of switch T15 is used to receive voltage signal SS. The control end of switch T14 is coupled to node N12, and the control end of switch T15 is used to receive reset signal RST. When node N12 has a voltage level of VGL, switch T14 is turned on, causing node N13 to have a voltage level of VGH. When reset signal RST has a reference voltage level of VL, switch T15 is turned on, causing node N13 to have a voltage level of VGL.

[0050] The capacitor C12 is used to charge according to the voltage level of the node N13. One end of the capacitor C12 is coupled to the node N13, and the other end of the capacitor C12 is used to receive the voltage signal SS.

[0051] Switch T16 is used to control the light-emitting element L1. One terminal of switch T16 is coupled to the light-emitting element, a control terminal of switch T16 is coupled to node N13, and the other terminal of switch T16 is coupled to the pulse amplitude control circuit 130. When node N13 has a voltage level VGH, switch T16 is turned off, causing light-emitting element L1 to stop emitting light.

[0052] In some embodiments, switch T13 may be implemented using an N-type metal oxide semiconductor (NMOS) transistor, and switches T11, T12, and T14-T16 may be implemented using P-type metal oxide semiconductor (PMOS) transistors. In other words, switch T13 is turned on in response to a reference voltage level VH and turned off in response to a reference voltage level VL, while switches T11, T12, and T14-T16 are turned on in response to a reference voltage level VL and turned off in response to a reference voltage level VH.

[0053] In some implementations, the ramp wave generating circuit 120 needs to be operated in conjunction with a ramp wave generator chip, which increases the cost and wiring area.

[0054] Compared to the above approach, in the embodiment of the present invention, the display circuit 140 can adjust the light-emitting time length of the light-emitting element L1 through the light-emitting control signal PEM output by the light-emitting control circuit 110 .

[0055] Figure 2 FIG2 is a circuit diagram of a ramp wave generating circuit 200 according to some embodiments of the present invention. Figure 1 and Figure 2 The ramp wave generating circuit 200 is an embodiment of the ramp wave generating circuit 120 in the display device 100. The ramp wave generating circuit 200 includes switches T21, T22, T23 and a capacitor C2.

[0056] like Figure 2As shown, switch T21 is used to control the voltage level of node N21. One end of switch T21 is coupled to node N21, the other end of switch T21 is used to receive a pulse-width modulation signal PWM, and a control end of switch T21 is used to receive a scan signal SCN. When switch T21 is turned on, node N21 has the voltage level of the pulse-width modulation signal PWM.

[0057] One terminal of the capacitor C2 is coupled to the node N21 , and the other terminal of the capacitor C2 is used to receive the voltage signal DD.

[0058] The switch T22 is used to control the voltage level of the node N22 . One terminal of the switch T22 is coupled to the node N22 , the other terminal of the switch T22 is used to receive the voltage signal DD, and a control terminal of the switch T22 is coupled to the node N21 .

[0059] The switch T23 is turned on according to the luminescence signal EM to output the pulse width control signal PWCS to the luminescence control circuit 110. One terminal of the switch T23 is coupled to the luminescence control circuit 110, the other terminal of the switch T23 is coupled to the node N22, and the control terminal of the switch T23 is coupled to receive the luminescence signal EM.

[0060] In some embodiments, the switches T21 - T23 may be implemented by P-type metal oxide semiconductor (PMOS) transistors. In other words, the switches T21 - T23 are turned on in response to the reference voltage level VL and turned off in response to the reference voltage level VH.

[0061] Figure 3 A timing diagram 300 is shown illustrating a light emitting operation of the display device 100 according to some embodiments of the present invention.

[0062] like Figure 3 As shown, the horizontal axis of the timing diagram 300 corresponds to time, and the vertical axis of the timing diagram 300 corresponds to voltage level. The timing diagram 300 includes periods P31 to P312 arranged sequentially and continuously. In some embodiments, the timing diagram 300 corresponds to Figure 2 and Figure 1 The operations of various signals, such as the scan signal SCN, the reset signal RST, and the emission signal EM, are shown. During periods P31 to P312, each of the scan signal SCN, the reset signal RST, and the emission signal EM has a reference voltage level VL or a reference voltage level VH. Reference voltage level VL is less than reference voltage level VH. Reference voltage level VL is greater than or equal to voltage level VGL. Reference voltage level VH is greater than or equal to voltage level VGH.

[0063] During period P31 , the scan signal SCN has a reference voltage level VL, and the reset signal RST and the emitting signal EM each have a reference voltage level VH. The switch T21 is turned on according to the scan signal SCN, so that the node N21 has a voltage level of the pulse width modulation signal PWM.

[0064] During period P32, reset signal RST has a reference voltage level VL, and scan signal SCN and emission signal EM each have a reference voltage level VH. Switches T11 and T15 are turned on in response to reset signal RST, causing nodes N11 and N13 to each have a voltage level VGL. Correspondingly, switch T12 is turned on and switch T13 is turned off, causing node N12 to have a voltage level VGH. Switch T14 is turned off in response to the voltage level VGH at node N12.

[0065] On the other hand, the switch T16 is turned on according to the voltage level VGL of the node N13 , so that the light emitting element L1 starts to emit light.

[0066] During period P33, the emitting signal EM has a reference voltage level VL, and the scan signal SCN and the reset signal RST each have a reference voltage level VH. Switch T22 is turned on in response to the voltage level at node N21 to determine the voltage level at node N22. When switch T23 is turned on in response to the emitting signal EM, capacitor C11 is charged in response to the voltage level at node N22, gradually increasing the voltage level at node N11 to the reference voltage level VH. While capacitor C11 is charging, node N11 has the reference voltage level VH, turning off switch T12 and turning on switch T13, causing node N12 to have a voltage level VGL.

[0067] During period P33, when switch T14 is turned on according to the voltage level of node N12, capacitor C12 is charged, causing the voltage level of node N13 to gradually rise to voltage level VGH. During the charging period of capacitor C12, node N13 has a reference voltage level VH, turning off switch T16 and stopping light-emitting element L1 from emitting light.

[0068] In summary, during the period P33 , the light control circuit 110 adjusts the light emitting time length of the light emitting element L1 according to the pulse width modulation signal PWM.

[0069] During period P34, each of the scan signal SCN, the luminous signal EM, and the reset signal RST has a reference voltage level VH. When the switch T23 is turned off according to the luminous signal EM, the capacitor C11 maintains the voltage level of the node N11.

[0070] The operation of each of the periods P35, P38, and P311 is similar to the operation of the period P32. The operation of each of the periods P36, P39, and P312 is similar to the operation of the period P33. The operation of each of the periods P37 and P310 is similar to the operation of the period P34.

[0071] Figure 4 A timing diagram 400 is shown illustrating a light emitting operation of the display device 100 according to some embodiments of the present invention.

[0072] like Figure 4 As shown, the horizontal axis of the timing diagram 400 corresponds to time, and the vertical axis of the timing diagram 400 corresponds to voltage level. The timing diagram 400 includes periods P41 to P411 arranged sequentially and continuously. In some embodiments, the timing diagram 400 corresponds to Figure 2 and Figure 1 The operations of various signals, such as the scan signal SCN, the reset signal RST, and the emission signal EM, are shown. During periods P41 to P411, each of the scan signal SCN, the reset signal RST, and the emission signal EM has a reference voltage level VL or a reference voltage level VH. Reference voltage level VL is less than reference voltage level VH. Reference voltage level VL is greater than or equal to voltage level VGL. Reference voltage level VH is greater than or equal to voltage level VGH.

[0073] During the period P41 , when the scan signal SCN has the reference voltage level VL and the light-emitting signal EM has the reference voltage level VH, the switch T21 is turned on according to the scan signal SCN, so that the node N21 has the voltage level of the pulse width modulation signal PWM.

[0074] During period P41 , when the scan signal SCN and the reset signal RST have the reference voltage level VL and the light emitting signal EM has the reference voltage level VH, the switches T11 and T15 are turned on according to the reset signal RST, so that each of the nodes N11 and N13 has the voltage level VGL.

[0075] During period P42, the emitting signal EM has a reference voltage level VL, and the scan signal SCN and the reset signal RST each have a reference voltage level VH. Switch T22 is turned on in response to the voltage level of node N21 to determine the voltage level of node N22. When switch T23 is turned on in response to the emitting signal EM, capacitor C11 is charged in response to the voltage level of node N22, gradually increasing the voltage level of node N11 to the reference voltage level VH. While capacitor C11 is charging, node N11 has the reference voltage level VH, turning off switch T12 and turning on switch T13, causing node N12 to have a voltage level VGL.

[0076] During period P42, when switch T14 is turned on according to the voltage level of node N12, capacitor C12 is charged, causing the voltage level of node N13 to gradually rise to voltage level VGH. During the charging period of capacitor C12, node N13 has a reference voltage level VH, turning off switch T16 and stopping light-emitting element L1 from emitting light.

[0077] In summary, during the period P42 , the light control circuit 110 adjusts the light emitting time length of the light emitting element L1 according to the pulse width modulation signal PWM.

[0078] During period P43, each of the scan signal SCN, the reset signal RST, and the emitting signal EM has a reference voltage level VH. When the switch T23 is turned off according to the emitting signal EM, the capacitor C11 maintains the voltage level of the node N11.

[0079] During period P44, reset signal RST has a reference voltage level VL, and scan signal SCN and emission signal EM each have a reference voltage level VH. Switch T11 is turned on in response to reset signal RST, causing nodes N11 and N13 to each have a voltage level VGL. Correspondingly, switch T12 is turned on and switch T13 is turned off, causing node N12 to have a voltage level VGH. Switch T14 is turned off in response to the voltage level VGH at node N12.

[0080] On the other hand, the switch T16 is turned on according to the voltage level VGL of the node N13 , so that the light emitting element L1 starts to emit light.

[0081] The operation of each of the periods P47 and P410 is similar to the operation of the period P44. The operation of each of the periods P45, P48, and P411 is similar to the operation of the period P42. The operation of each of the periods P46 and P49 is similar to the operation of the period P43.

[0082] Figure 5 FIG2 is a block diagram of the ramp wave generating circuit 120 in the display device 100 according to some embodiments of the present invention. The ramp wave generating circuit 500 is an embodiment of the ramp wave generating circuit 120 in the display device 100. The ramp wave generating circuit 500 includes switches T51 to T57 and a capacitor C5.

[0083] like Figure 5 The switches T51, T56 and T57 shown can correspond to Figure 2 The switches T21, T22 and T23 are shown. The nodes N52 and N54 can correspond to Figure 2 Node N21 and node N22 are shown.

[0084] like Figure 5As shown, the switch T51 is used to control the voltage level of the node N51. One end of the switch T51 is coupled to the node N51, the other end of the switch T51 is used to receive the pulse width modulation signal PWM, and the control end of the switch T51 is used to receive the scan signal SCN.

[0085] The switch T52 is used to control the voltage level of the node N51. One terminal of the switch T52 is coupled to the node N51, the other terminal of the switch T52 is used to receive the bias signal Vbp, and the control terminal of the switch T52 is used to receive the luminous signal EM.

[0086] The capacitor C5 is used to couple the voltage level of the node N51 to the node N52. One end of the capacitor C5 is coupled to the node N51, and the other end of the capacitor C5 is coupled to the node N52.

[0087] Switches T53 and T55 are used to control the voltage levels of nodes N52 and N54, respectively. One end of switch T53 is coupled to node N52, the other end of switch T53 is used to receive a reference voltage signal Vref, and a control end of switch T53 is used to receive a scan signal SCN. One end of switch T55 is coupled to node N54, the other end of switch T55 is used to receive a reference voltage signal Vref, and a control end of switch T55 is used to receive a scan signal SCN.

[0088] The switch T54 is turned on according to the read signal RD. One terminal of the switch T54 is coupled to the node N53, the other terminal of the switch T54 is used to receive the reference voltage signal Vref, and the control terminal of the switch T54 is used to receive the read signal RD.

[0089] The switch T56 is used to control the voltage level of the node N54 , one terminal of the switch T56 is coupled to the node N54 , the other terminal of the switch T56 is used to receive the voltage signal DD, and a control terminal of the switch T56 is coupled to the node N52 .

[0090] One end of the switch T57 is coupled to the node N11 of the light emitting control circuit 110 , the other end of the switch T57 is coupled to the node N54 , and a control end of the switch T57 is used to receive the light emitting signal EM.

[0091] In some embodiments, the switches T51 - T57 can be implemented by P-type metal oxide semiconductor (PMOS) transistors. In other words, the switches T51 - T57 are turned on in response to the reference voltage level VL and turned off in response to the reference voltage level VH.

[0092] Figure 6 A timing diagram 600 is shown illustrating a light emitting operation of the display device 100 according to some embodiments of the present invention.

[0093] like Figure 6As shown, the horizontal axis of the timing diagram 600 corresponds to time, and the vertical axis of the timing diagram 600 corresponds to voltage level. The timing diagram 600 includes periods P61 to P613 arranged sequentially and continuously. In some embodiments, the timing diagram 600 corresponds to Figure 5 and Figure 1 The operations of various signals, such as the read signal RD, the scan signal SCN, the reset signal RST, and the emission signal EM, are shown. During periods P61 to P613, each of the read signal RD, the scan signal SCN, the reset signal RST, and the emission signal EM has a reference voltage level VL or VH. Reference voltage level VL is less than reference voltage level VH. Reference voltage level VL is greater than or equal to voltage level VGL. Reference voltage level VH is greater than or equal to voltage level VGH.

[0094] During period P61 , when the read signal RD has the reference voltage level VL and each of the reset signal RST and the emission signal EM has the reference voltage level VH, the switch T54 is turned on, so that the node N53 has the voltage level of the reference voltage signal Vref.

[0095] During period P61, when each of the read signal RD and the scan signal SCN has a reference voltage level VL and the reset signal RST and the emission signal EM have a reference voltage level VH, the switch T51 is turned on, causing the node N51 to have a voltage level of the pulse-width modulation signal PWM. The switches T53 and T55 are turned on, causing each of the nodes N52, N53, and N54 to have a voltage level of the reference voltage signal Vref.

[0096] During period P62, scan signal SCN has a reference voltage level VL, and each of read signal RD, reset signal RST, and emission signal EM has a reference voltage level VH. Switch T54 is turned off in response to read signal RD, causing the voltage levels of nodes N52, N53, and N54 to be charged to a voltage level VGH of voltage signal DD minus a threshold voltage of switch T56 via switch T56.

[0097] During period P63, reset signal RST has a reference voltage level VL, and each of read signal RD, scan signal SCN, and emission signal EM has a reference voltage level VH. When switches T11 and T15 are turned on in response to reset signal RST, each of node N11 and node N13 has a voltage level VGL. Correspondingly, switch T12 is turned on and switch T13 is turned off, causing node N12 to have a voltage level VGH. Switch T14 is turned off in response to the voltage level VGH at node N12.

[0098] On the other hand, the switch T16 is turned on according to the voltage level VGL of the node N13 , so that the light emitting element L1 starts to emit light.

[0099] During period P64, the emitting signal EM has a reference voltage level VL, and each of the read signal RD, the scan signal SCN, and the reset signal RST has a reference voltage level VH. Switch T56 is turned on in response to the voltage level of node N52 to determine the voltage level of node N54. When switch T52 is turned on in response to the emitting signal EM, node N51 has the voltage level of the bias signal Vbp and the pulse-width modulation signal PWM. When switch T57 is turned on in response to the emitting signal EM, the voltage level of node N54 gradually rises to the reference voltage level VH.

[0100] During period P64, when the switch T52 is turned on, the voltage level of the node N51 is adjusted from the voltage level of the pulse width modulation signal PWM to the voltage level of the bias signal Vbp, and the capacitor C5 couples the voltage level change of the node N51 to the node N52, so that the voltage level of the node N52 is adjusted from the voltage level VGH of the voltage signal DD minus the threshold voltage of the switch T56 to the voltage level VGH of the voltage signal DD minus the threshold voltage of the switch T56 and the sum of the voltage level change of the node N51.

[0101] During period P64, when nodes N51 and N54 have the voltage levels of bias signal Vbp and voltage signal DD, respectively, switch T56 is turned on, charging capacitor C11 based on the voltage level of node N54 and gradually increasing the voltage level of node N11 to reference voltage level VH. While capacitor C11 is charging, node N11 has reference voltage level VH, turning off switch T12 and turning on switch T13, causing node N12 to have voltage level VGL.

[0102] During period P64, when switch T14 is turned on according to the voltage level of node N12, capacitor C12 is charged, causing the voltage level of node N13 to gradually rise to voltage level VGH. During the charging period of capacitor C12, node N13 has a reference voltage level VH, turning off switch T16 and stopping light-emitting element L1 from emitting light.

[0103] In summary, during the period P64 , the light control circuit 110 adjusts the light emitting time length of the light emitting element L1 according to the pulse width modulation signal PWM.

[0104] During period P65 , each of the read signal RD, the scan signal SCN, the reset signal RST, and the emitting signal EM has a reference voltage level VH. When the switches T52 and T57 are turned off according to the emitting signal EM, the capacitor C11 maintains the voltage level of the node N11 .

[0105] The operation of each of the periods P66, P69, and P612 is similar to the operation of the period P63. The operation of each of the periods P67, P610, and P613 is similar to the operation of the period P64. The operation of each of the periods P68 and P611 is similar to the operation of the period P65.

[0106] Figure 7 A timing diagram 700 is shown illustrating a light emitting operation of the display device 100 according to some embodiments of the present invention.

[0107] like Figure 7 As shown, the horizontal axis of the timing diagram 700 corresponds to time, and the vertical axis of the timing diagram 700 corresponds to voltage level. The timing diagram 600 includes periods P71 to P712 arranged sequentially and continuously. In some embodiments, the timing diagram 700 corresponds to Figure 5 and Figure 1 The operations of various signals, such as the read signal RD, the scan signal SCN, the reset signal RST, and the emission signal EM, are shown. During periods P71 to P712, each of the read signal RD, the scan signal SCN, the reset signal RST, and the emission signal EM has a reference voltage level VL or VH. Reference voltage level VL is less than reference voltage level VH. Reference voltage level VL is greater than or equal to voltage level VGL. Reference voltage level VH is greater than or equal to voltage level VGH.

[0108] During period P71 , when the read signal RD has the reference voltage level VL and each of the reset signal RST and the emission signal EM has the reference voltage level VH, the switch T54 is turned on, so that the node N53 has the voltage level of the reference voltage signal Vref.

[0109] During period P71, when each of the read signal RD and the scan signal SCN has a reference voltage level VL and the reset signal RST and the emission signal EM have a reference voltage level VH, the switch T51 is turned on, causing the node N51 to have a voltage level of the pulse-width modulation signal PWM. The switches T53 and T55 are turned on, causing each of the nodes N52, N53, and N54 to have a voltage level of the reference voltage signal Vref.

[0110] During period P72, scan signal SCN and reset signal RST each have a reference voltage level VL, and read signal RD and emission signal EM each have a reference voltage level VH. When switch T54 is turned off in response to read signal RD, the voltage levels of nodes N52, N53, and N54 are charged via switch T56 to a voltage level VGH of voltage signal DD minus a threshold voltage of switch T56. When switches T11 and T15 are turned on in response to reset signal RST, nodes N11 and N13 each have a voltage level VGL.

[0111] During period P73, the emitting signal EM has a voltage signal SS at a voltage level VGL, and each of the read signal RD, the scan signal SCN, and the reset signal RST has a reference voltage level VH. Switch T56 is turned on in response to the voltage level of node N52 to determine the voltage level of node N54. When switch T52 is turned on in response to the emitting signal EM, node N51 has a voltage level of the bias signal Vbp and a pulse-width modulation signal PWM. When switch T57 is turned on in response to the emitting signal EM, the voltage level of node N54 gradually increases to the reference voltage level VH.

[0112] During period P73, when the switch T52 is turned on, the voltage level of the node N51 is adjusted from the voltage level of the pulse width modulation signal PWM to the voltage level of the bias signal Vbp, and the capacitor C5 couples the voltage level change of the node N51 to the node N52, so that the voltage level of the node N52 is adjusted from the voltage level of the voltage signal DD minus the threshold voltage of the switch T56 to the voltage level of the voltage signal DD minus the threshold voltage of the switch T56 and the sum of the voltage level change of the node N51.

[0113] During period P73, switch T56 is turned on, charging capacitor C11 based on the voltage level at node N54, and gradually increasing the voltage level at node N11 to a reference voltage level VH. During the charging period of capacitor C11, node N11 has a reference voltage level VH, turning off switch T12 and turning on switch T13, causing node N12 to have a voltage level VGL.

[0114] During period P73, when switch T14 is turned on according to the voltage level of node N12, capacitor C12 is charged, causing the voltage level of node N13 to gradually rise to voltage level VGH. During the charging period of capacitor C12, node N13 has a reference voltage level VH, turning off switch T16 and stopping light-emitting element L1 from emitting light.

[0115] In summary, during the period P73 , the light control circuit 110 adjusts the light emitting time length of the light emitting element L1 according to the pulse width modulation signal PWM.

[0116] During period P74, each of the read signal RD, the scan signal SCN, the reset signal RST, and the emitting signal EM has a reference voltage level VH. When the switches T52 and T57 are turned off according to the emitting signal EM, the capacitor C11 maintains the voltage level of the node N11.

[0117] During period P75, reset signal RST has a reference voltage level VL, and each of read signal RD, scan signal SCN, and emission signal EM has a reference voltage level VH. When switches T11 and T15 are turned on in response to reset signal RST, each of node N11 and node N13 has a voltage level VGL. Correspondingly, switch T12 is turned on and switch T13 is turned off, causing node N12 to have a voltage level VGH. Switch T14 is turned off in response to the voltage level VGH at node N12.

[0118] On the other hand, the switch T16 is turned on according to the voltage level VGL of the node N13 , so that the light emitting element L1 starts to emit light.

[0119] The operation of each of the periods P76, P79, and P712 is similar to the operation of the period P73. The operation of each of the periods P77 and P710 is similar to the operation of the period P74. The operation of each of the periods P78 and P711 is similar to the operation of the period P75.

[0120] The aforementioned various light-emitting operation modes in this case are for illustration only, and other various light-emitting operation modes are within the scope of this case.

[0121] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications.

Claims

1. A display device, characterized in that: include: A pulse width control circuit comprising: a ramp wave generating circuit for adjusting a voltage level of a first node according to a pulse width modulation signal; a first switch, wherein a first terminal of the first switch is coupled to a second node, and a control terminal of the first switch is coupled to the first node; a second switch, wherein a first terminal of the second switch is coupled to the second node, and a control terminal of the second switch is coupled to the first node; a third switch, wherein a first terminal of the third switch is configured to output a light-emitting control signal, and a control terminal of the third switch is coupled to the second node; a fourth switch for resetting the voltage level of the first node, wherein a first terminal of the fourth switch is coupled to the first node; a fifth switch for resetting a voltage level of a third node, wherein a first terminal of the fifth switch is coupled to the third node; a first capacitor, a first terminal of the first capacitor being coupled to the first node, and a second terminal of the first capacitor being grounded; and a second capacitor, a first terminal of the second capacitor coupled to the third node; a light-emitting element configured to emit light according to the light-emitting control signal; a sixth switch for controlling the light emitting element to emit light, wherein a first terminal of the sixth switch is coupled to the light emitting element, and a control terminal of the sixth switch is coupled to the third node; and A pulse amplitude control circuit is used to provide a pulse amplitude control signal to the sixth switch. The pulse amplitude control circuit is coupled to the second end of the sixth switch.

2. The display device according to claim 1, wherein When the fourth switch is turned on, the first switch is turned on and each of the second switch and the third switch is turned off.

3. The display device according to claim 1, wherein The second end of the first switch and the second end of the third switch are each used to receive a first reference voltage signal, and the second end of the second switch and the second end of the fourth switch are each used to receive a second reference voltage signal.

4. The display device according to claim 1, wherein The ramp wave generating circuit includes a seventh switch. A first terminal of the seventh switch is coupled to the first node. When the fourth switch is turned on, the seventh switch is turned off.

5. The display device according to claim 1, wherein Also includes: a seventh switch, a first terminal of the seventh switch coupled to the first node; an eighth switch, wherein a first terminal of the eighth switch is coupled to the second terminal of the seventh switch, and a second terminal of the eighth switch is used to receive a first reference voltage signal; a ninth switch, wherein a first terminal of the ninth switch is coupled to the control terminal of the eighth switch, and a second terminal of the ninth switch is used for receiving the pulse width modulation signal; and a third capacitor, wherein a first terminal of the third capacitor is coupled to the first terminal of the ninth switch, and a second terminal of the third capacitor is used for receiving the first reference voltage signal.

6. The display device according to claim 5, wherein When the fourth switch is turned on, the seventh switch is turned off.

7. The display device according to claim 1, wherein Also includes: a seventh switch, a first terminal of the seventh switch coupled to the first node; an eighth switch, wherein a first terminal of the eighth switch is coupled to the second terminal of the seventh switch, and a second terminal of the eighth switch is configured to receive a first reference voltage signal; a third capacitor, a first terminal of the third capacitor being coupled to the control terminal of the eighth switch; a ninth switch, wherein a first terminal of the ninth switch is coupled to the second terminal of the capacitor; and a tenth switch, wherein a first terminal of the tenth switch is coupled to the first terminal of the ninth switch, and a second terminal of the tenth switch is used for receiving the pulse width modulation signal.

8. The display device according to claim 7, wherein: When the fourth switch is turned on, the tenth switch is turned on.

9. The display device according to claim 1, wherein Also includes: a seventh switch, a first terminal of the seventh switch coupled to the first node; an eighth switch, wherein a first terminal of the eighth switch is coupled to a fourth node, and a second terminal of the eighth switch is coupled to the second terminal of the seventh switch; a ninth switch, wherein a first terminal of the ninth switch is coupled to the fourth node; and a tenth switch, wherein a first terminal of the tenth switch is coupled to the fourth node.

10. A vehicle display device, characterized in that: include: A pulse width control circuit comprising: a ramp wave generating circuit for adjusting a voltage level of a first node according to a pulse width modulation signal; a first switch, wherein a first terminal of the first switch is coupled to a second node, and a control terminal of the first switch is coupled to the first node; a second switch, wherein a first terminal of the second switch is coupled to the second node, and a control terminal of the second switch is coupled to the first node; a third switch, wherein a first terminal of the third switch is configured to output a light-emitting control signal, and a control terminal of the third switch is coupled to the second node; a fourth switch for resetting the voltage level of the first node, wherein a first terminal of the fourth switch is coupled to the first node; a fifth switch for resetting a voltage level of a third node, wherein a first terminal of the fifth switch is coupled to the third node; a first capacitor, a first terminal of the first capacitor being coupled to the first node, and a second terminal of the first capacitor being grounded; and a second capacitor, a first terminal of the second capacitor coupled to the third node; a light-emitting element, placed on the vehicle body and configured to emit light according to the light-emitting control signal; a sixth switch for controlling the light emitting element to emit light, wherein a first terminal of the sixth switch is coupled to the light emitting element, and a control terminal of the sixth switch is coupled to the third node; and A pulse amplitude control circuit is used to provide a pulse amplitude control signal to the sixth switch. The pulse amplitude control circuit is coupled to the second end of the sixth switch.

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