Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The manufacturing method of the electronic device comprises the following steps. A first electronic unit and a second electronic unit are provided on a carrier plate. An insulating layer is provided to surround the first electronic unit and the second electronic unit. Grinding the insulating layer until at least part of the first electronic units and at least part of the second electronic units are exposed; and performing offset confirmation on at least one of the first electronic unit and the second electronic unit. And providing a circuit structure on the insulating layer according to the offset. The circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer comprises a first wire and a second wire, and the first wire and the second wire are electrically connected through the second conductor layer.

Description

Technical Field

[0001] The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device with better electrical reliability and a manufacturing method thereof. Background Art

[0002] In packaging processes such as wafer-level packaging (WLP) and panel-level packaging (PLP), large-area packaging is affected by the die-bonding and molding processes, resulting in different chip offsets, which in turn leads to poor product electrical reliability. Conventional technology addresses chip offset by increasing the size of the annular ring (AR) while maintaining the same trace routing. However, this approach consumes more circuit design space, resulting in reduced product competitiveness. Summary of the Invention

[0003] The present disclosure is directed to an electronic device and a manufacturing method thereof, which can have better electrical reliability.

[0004] According to an embodiment of the present invention, a method for manufacturing an electronic device includes the following steps: providing a first electronic unit and a second electronic unit on a carrier board; providing an insulating layer to surround the first electronic unit and the second electronic unit; thinning the insulating layer until at least a portion of the first electronic unit and at least a portion of the second electronic unit are exposed; determining an offset of at least one of the first electronic unit and the second electronic unit; and providing a circuit structure on the insulating layer based on the offset. The circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer includes a first trace and a second trace, and the first trace and the second trace are electrically connected via the second conductor layer.

[0005] According to an embodiment of the present invention, an electronic device includes a first electronic unit and a second electronic unit, an insulating layer, and a circuit structure. The first electronic unit and the second electronic unit are adjacent to each other. The insulating layer surrounds the first and second electronic units. The circuit structure is disposed on the insulating layer. The circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer includes a first trace and a second trace. The first trace and the second trace are electrically connected via the second conductor layer.

[0006] Based on the above, in the disclosed embodiments, an algorithm is first used to calculate and confirm the position (e.g., offset) of the electronic unit. This positional information is then used to configure the circuit structure, whereby the second conductive layer can connect the first and second traces of the first conductive layer, resulting in improved electrical reliability for the electronic device. Furthermore, the configuration of the second conductive layer can be implemented without modifying the annular ring (AR) design, or, by slightly modifying the AR design, this allows for more flexible circuit design space utilization, thereby enhancing the competitiveness of the electronic device.

[0007] In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1E is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0009] Figure 1F for Figure 1E Schematic top view of

[0010] Figure 2 is a top perspective diagram of multiple electronic devices on a carrier board according to an embodiment of the present disclosure;

[0011] Figure 3 is a schematic top view of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 4 is a schematic top view of an electronic device according to another embodiment of the present disclosure;

[0013] 5A to 5D is a schematic diagram of a second conductive layer of a circuit structure according to various embodiments of the present disclosure;

[0014] Figure 6 is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 7A is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0016] Figure 7B FIG. 4 is a cross-sectional diagram of an electronic device according to another embodiment of the present disclosure.

[0017] Description of Reference Numerals

[0018] 10, 22, 32: adhesive layer;

[0019] 20: Temporary board;

[0020] 30: carrier board;

[0021] 100 ′, 100 a, 100 b, 100 c, 100 d, 100 e, 100 f: electronic devices;

[0022] 110, 110', 110c: first electronic unit;

[0023] 111: first active surface;

[0024] 112, 112': first input / output pad;

[0025] 113: first solder mask;

[0026] 113a, 123a, 135a, 157a: surface;

[0027] 120, 120', 120c: second electronic unit;

[0028] 121: Second active surface;

[0029] 122, 122': second input / output pads;

[0030] 123: second solder mask;

[0031] 130a, 130d: guide plates;

[0032] 131, 143: curved surface;

[0033] 133, 145: bottom surface;

[0034] 135, 135f: conductor column;

[0035] 137: Opening;

[0036] 138: groove;

[0037] 140, 140a, 140d: insulation layer;

[0038] 141: surrounding surface;

[0039] 150', 150a, 150h: circuit structure;

[0040] 151: first conductor layer;

[0041] 152, 152b, 152c, 152f: first trace;

[0042] 152a, 154a, 157b: side walls;

[0043] 154, 154b, 154f: second trace;

[0044] 155, 155', 155b, 155c, 155d, 155e, 155f, 155g, 155h, 155e, 155f: second conductor layer;

[0045] 157: connecting column;

[0046] 158: insulation layer;

[0047] 156b, 156c, 156d1, 156d2, 156d3, 156d4, 156d5, 156e, 156f, 156g, 156e: compensation pattern;

[0048] 159b, 159c, 159f, 159g, 159e: compensation routing;

[0049] 160: Connector;

[0050] BS1, BS2: dorsal;

[0051] CL: conductor layer;

[0052] SL: seed layer;

[0053] L1, L2, L3, L4: line layer;

[0054] O1, O2: opening;

[0055] P1: first spacing;

[0056] P2: second spacing;

[0057] W1: first width;

[0058] W2: second width;

[0059] W3: third width. DETAILED DESCRIPTION

[0060] The present disclosure will be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, many of the drawings in this disclosure depict only portions of electronic devices, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0061] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names.

[0062] In the following description and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0063] In addition, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It is understood that if the device in the drawings is turned upside down, the element described as being on the "below" side will become the element on the "above" side.

[0064] In some embodiments of the present disclosure, terms such as "connected" and "interconnected," unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct (or indirect) contact, with another structure disposed between the two structures. Furthermore, such terms may include situations where both structures are movable or both structures are fixed. Furthermore, the term "coupled" encompasses situations where energy is transferred between two structures by means of direct or indirect electrical connection, or where energy is transferred between two separate structures by means of mutual induction.

[0065] It should be understood that when an element or film layer is referred to as being “on” or “connected to” another element or film layer, it can be directly on or directly connected to the other element or film layer, or there may be intervening elements or film layers between the two (indirect case). Conversely, when an element is referred to as being “directly on” or “directly connected to” another element or film layer, there are no intervening elements or film layers between the two.

[0066] The terms "about," "equal to," "equal," or "same," "substantially," or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0067] In the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step thin film thickness profilometer, an ellipsometer, or other suitable methods may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and the area, width, thickness, or height of each component, or the distance or spacing between components, may be measured.

[0068] In this disclosure, roughness can be defined as observation by SEM. On a concave-convex surface, the peaks and valleys of the surface undulations can be observed to have a distance difference of 0.15 micrometers (μm) to 1 μm. Roughness measurement can include using an SEM, a transmission electron microscope (TEM), etc., to observe the surface undulations at an appropriate magnification. The undulations are then compared by taking a sample of a unit length (e.g., 10 μm) to determine the roughness range. Here, "appropriate magnification" means the roughness (Rz) or average roughness (Ra) of at least one surface where at least 10 peaks of undulations can be observed under this magnification.

[0069] As used herein, the terms "film" and / or "layer" may refer to any continuous or discontinuous structure and material (such as a material deposited by the methods disclosed herein). For example, a film and / or layer may include a two-dimensional material, a three-dimensional material, nanoparticles, or even a partial or complete molecular layer, or a partial or complete atomic layer, or clusters of atoms and / or molecules. A film or layer may include a material or layer having pinholes that may be at least partially continuous.

[0070] While the terms "first," "second," "third," etc. may be used to describe various components, these terms are not intended to be limiting. These terms are used solely to distinguish a single component from other components within the specification. Claims may not use the same terms, but may be replaced with "first," "second," "third," etc., according to the order in which the components are declared in the claims. Thus, in the following description, the first component may be referred to as the second component in a claim.

[0071] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with the background or context of the relevant art and this disclosure and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

[0072] It should be noted that the following embodiments may replace, reorganize, or mix the technical features of several different embodiments to implement other embodiments without departing from the spirit of the present disclosure.

[0073] The electronic devices disclosed herein may include power modules, semiconductor devices, semiconductor packaging devices, display devices, antenna devices, sensing devices, light-emitting devices, or splicing devices, but are not limited thereto. The electronic devices may include bendable or flexible electronic devices. The electronic devices may include electronic components. The electronic components may include passive components, active components, or a combination thereof, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical systems (MEMS), liquid crystal chips, etc., but are not limited thereto. The diodes may include light-emitting diodes or non-light-emitting diodes. The diodes include PN junction diodes, PIN diodes, or constant current diodes. The light-emitting diodes may, for example, include organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (mini LEDs), micro LEDs, quantum dot LEDs, fluorescence, phosphors, or other suitable materials, or a combination thereof, but are not limited thereto. The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but is not limited thereto. Below, a display device will be used as an electronic device to illustrate the present disclosure, but the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the manufacturing method of the provided electronic device may be applied, for example, to a wafer-level package (WLP) or a panel-level package (PLP) process, and may adopt a chip-first process or a chip-last / RDL-first process, which will be further described in detail below. The electronic device referred to in the present disclosure may include a system on package (SoC), a system in package (SiP), an antenna in package (AiP), a co-packaged optics (CPO), or a combination thereof, but is not limited thereto.

[0074] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0075] Figures 1A to 1E It is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 1F for Figure 1E Please refer to the top view of Figure 1A Regarding the manufacturing method of the electronic device of this embodiment, first, the first electronic unit 110, the second electronic unit 120, and the conductive post 135 are arranged on a temporary carrier (not shown) through a temporary adhesive layer (not shown). Next, an insulating layer 140a is provided to surround the first electronic unit 110, the second electronic unit 120, and the conductive post 135 to form a packaging structure. Next, a temporary carrier 20 is provided, and the temporary adhesive layer and the temporary carrier are removed. The packaging structure can be temporarily fixed to the temporary carrier 20 so that the back side BS1 of the first electronic unit 110, the back side BS2 of the second electronic unit 120, and one side of the conductive post 135 are away from the temporary carrier 20. Next, a guide plate 130a is provided, so that the guide plate 130a is arranged on the back side BS1 of the first electronic unit 110 and the back side BS2 of the second electronic unit 120 through the adhesive layer 10. The guide plate 130a can be, for example, a metal plate or a heat sink, but is not limited thereto. The conductive pillars 135 are suitable for electrical conduction, thermal conduction, or both, and are not limited thereto. In the method described above, the first electronic unit 110 is packaged on a temporary carrier with its first active surface 111 and the second electronic unit 120 is packaged on a temporary carrier with its second active surface 121 initially facing away from the temporary carrier. This can be referred to as a face-up process. According to some embodiments, the first electronic unit 110 can also be packaged on a temporary carrier with its first active surface 111 and the second electronic unit 120 with its second active surface 121 facing the temporary carrier. The back side BS1 of the first electronic unit 110 and the back side BS2 of the second electronic unit 120 are then exposed, and the guide plate 130a is disposed on the back side BS1 of the first electronic unit 110 and the back side BS2 of the second electronic unit 120 through the adhesive layer 10. This can be referred to as a face-down process.

[0076] According to some embodiments, when a chip-down process is adopted and a package structure is formed through a molding process, the package structure is then flipped over. The openings in the first solder mask layer 113 of the first electronic unit 110 can expose the first I / O pads 112, and the second solder mask layer 123 of the second electronic unit 120 can expose the second I / O pads 122. When a chip-up process is adopted, the insulating layer 140a overlaps the first I / O pads 112, or the insulating layer 140a and the first solder mask layer 113 overlap both the first I / O pads 112 and the second I / O pads 122. Subsequently, a patterning process is required to expose the first I / O pads 112 and the second I / O pads 122 to facilitate subsequent processes. The patterning step may include photolithography, etching, developing, laser, plasma cleaning, combinations thereof, or other suitable steps, without limitation.

[0077] Please refer to Figure 1B . Figure 1BIn another embodiment, the first electronic unit 110 and the second electronic unit 120 are disposed on a guide plate 130a via an adhesive layer 10. According to some embodiments, a conductive post 135 is also disposed on the guide plate 130a. Furthermore, the conductive post 135 and the guide plate 130a may be integrally formed. According to some embodiments, the conductive post 135 may be formed separately on the guide plate 130a. Forming the conductive post 135 may include, but is not limited to, chemical plating, electroplating, atomic deposition, chemical deposition, or other suitable process methods. Therefore, the difference between the thermal conductivity of the conductive post 135 and the thermal conductivity of the guide plate 130a ranges from 0% to 70% of the thermal conductivity of the guide plate 130a. Subsequently, an insulating layer 140a is provided surrounding the first electronic unit 110, the second electronic unit 120, and the conductive post 135. The insulating layer 140a directly contacts the adhesive layer 32 located on the temporary carrier 30. In one embodiment, the temporary carrier 30 may be, for example, a glass substrate, a printed circuit board, a fiberglass (FR4) substrate, a steel substrate, or other suitable substrates, without limitation thereto. In one embodiment, the insulating layer 140a may be, for example, a molding compound, an epoxy resin, other suitable packaging materials, or a combination thereof, without limitation thereto. The phrase "A surrounds B" disclosed herein means that, in a cross-sectional direction, component A contacts at least two mutually opposing sides of component B. According to some embodiments, the dissociation method of the adhesive layer 22 and the adhesive layer 32 may include photodissociation, thermal dissociation, other suitable methods, or a combination of any two of the above. For example, depending on the dissociation method, the adhesive layer 22 and the adhesive layer 32 may be used with different types of temporary carriers, for example, the photodissociation type adhesive layer 22 and the adhesive layer 32 may be used with a transparent glass substrate, while the thermal dissociation type adhesive layer 22 and the adhesive layer 32 may be used with a steel plate. Adhesive layers 22 and 32 may include, for example, UV-sensitive adhesive film, heat release tape (HRT), other suitable materials, or a combination thereof. By disposing adhesive layers 22 and 32 on a temporary carrier, the package structure can be effectively separated.

[0078] Next, please also refer to Figure 1B as well as Figure 1C , thinning the insulating layer 140a until at least a portion of the first electronic unit 110 and at least a portion of the second electronic unit 120 are exposed. That is, the thinning method includes removing a portion of the insulating layer 140a by grinding, sandblasting, laser or other suitable methods, wherein the insulating layer 140a exposes the surface 113a of the first solder mask 113, the surface 123a of the second solder mask 123 and the surface 135a of the conductor post 135. Next, please refer to Figure 1CBy means of a surface treatment process such as laser ablation, plasma treatment, or etching, the first solder resist layer 113 is removed to expose the first input / output pads 112, or the insulating layer 140a located within the opening O1 of the first solder resist layer 113 is removed to expose the first input / output pads 112. Furthermore, the second solder resist layer 123 is removed to expose the second input / output pads 122, or the insulating layer 140a located within the opening O2 of the second solder resist layer 123 is removed to expose the second input / output pads 122. Thus, the insulating layer 140 surrounding the first electronic unit 110 and the second electronic unit 120 is provided.

[0079] Next, please refer to Figure 1D , an offset is confirmed for at least one of the first electronic unit 110 and the second electronic unit 120. According to some embodiments, one of the first electronic unit 110 and the second electronic unit 120 can be designated as a master die by first confirming the size of the annular ring (AR). Generally speaking, an annular ring refers to a copper ring that is flat against the board surface around the wall of the via. According to some embodiments, one of the first electronic unit 110 and the second electronic unit 120 can be designated as a master die by first confirming the distance (pitch) between adjacent annular rings. Furthermore, when the distance between adjacent annular rings is smaller, it is the position with the smallest allowable variation in the process and can be defined as the master die. In other words, depending on different situations, only the position with the smallest allowable variation can be considered the master die.

[0080] In one embodiment, the first electronic unit 110 includes first I / O pads 112 having a first pitch P1, and the second electronic unit 120 includes second I / O pads 122 having a second pitch P2. When the first pitch P1 and the second pitch P2 are different, the chip having the smaller pitch is the primary chip. The following description uses the first electronic unit 110 as the primary chip as an example, but is not limited to this. Next, a position check is performed on the first electronic unit 110 using a detection device to obtain position information of the first electronic unit 110. In one embodiment, the position information includes the position of the first I / O pad 112 of the first electronic unit 110. Next, based on the position information, a first trace 152 is formed on the first electronic unit 110, wherein the first trace 152 is electrically connected to the first I / O pad 112 of the first electronic unit 110, and the orthographic projection of the first trace 152 on the first electronic unit 110 overlaps with the first electronic unit 110. Next, the position of the second electronic unit 120 is inspected using a detection device to obtain position information of the second electronic unit 120. Subsequently, based on the position information, a second trace 154 is formed on the second electronic unit 120. The second trace 154 is electrically connected to the second input / output pad 122 of the second electronic unit 120, and the orthographic projection of the second trace 154 on the second electronic unit 120 overlaps with the second electronic unit 120. Here, the first trace 152 and the second trace 154 can be defined as the first conductive layer 151, with the first trace 152 insulated from the second trace 154. In other words, this embodiment confirms the offset of the first electronic unit 110 and the second electronic unit 120, and measures the first spacing P1 and the second spacing P2 to determine the positions of the first trace 152 and the second trace 154, respectively. Next, the first trace 152 and the second trace 154 are calculated to determine the position of the second conductor layer 155, wherein the first trace 152 and the second trace 154 are electrically connected via the second conductor layer 155. Here, the second conductor layer 155 can be considered a compensation pattern that can meet the interconnection requirements between offset electronic units. In one embodiment, the first trace 152, the second trace 154, and the second conductor layer 155 are located on the same plane, but this is not limited to this. The first conductor layer 151 and the second conductor layer 155 can be defined as a circuit structure 150a. Thus, the circuit structure 150a has been provided on the insulating layer 140 based on the offset, wherein the circuit structure 150a may include the first conductor layer 151 and the second conductor layer 155. The first conductor layer 151 includes the first trace 152 and the second trace 154, and the first trace 152 and the second trace 154 are electrically connected via the second conductor layer 155.

[0081] Please continue to refer to Figure 1D. In detail, the method of forming the second conductor layer 155 includes, after determining the position of the second conductor layer 155, providing a seed layer SL to overlap the first trace 152 and the second trace 154, and then providing a conductor layer CL on the seed layer SL, removing part of the seed layer SL, so that the remaining part of the seed layer SL is arranged between the conductor layer CL, the insulating layer 140a, the first trace 152 and the second trace 154. In other words, the seed layer SL and the conductor layer CL define the second conductor layer 155. The method of forming the conductor layer CL and the seed layer SL includes electroplating, chemical plating, deposition, yellow light development process, etching process, thinning or other suitable processes, but is not limited thereto. The materials of the seed layer SL and the conductor layer CL may include titanium, copper, tantalum, nickel, tungsten, nitride, and combinations thereof, but are not limited thereto.

[0082] In this embodiment, the circuit structure 150a may be a redistribution layer (RDL) and includes at least one conductive layer and at least one dielectric layer ( Figure 1D Three conductive layers and two dielectric layers are schematically shown, but not limited to this). The redistribution layer can redistribute the circuits and / or further increase the circuit fan-out area. The redistribution layer can be used to electrically connect different electronic components. The redistribution layer can extend the connection to a wider spacing or redistribute the connection to another connection with a different spacing, and / or the redistribution layer can serve as a substrate for wiring the electrical interface between one connection and another connection. For example, the pitch of two adjacent contact pads at one end of the redistribution structure contacting the electronic component can be less than or equal to the pitch of two adjacent contact pads at one end of the redistribution structure away from the electronic component, so that the redistribution structure can adjust the circuit fan-out condition or electrically connect a circuit structure / electronic component with a first pitch to a circuit structure / electronic component with a second pitch, but not limited to this. Among them, the step of forming the redistribution layer may include providing a stack of at least one conductive layer and at least one dielectric layer, and the method of forming the redistribution layer may include processes such as yellow light, etching, surface treatment, laser, electroplating, chemical plating, deposition, and atomic-level deposition. The surface treatment may include roughening or activating the surface of the dielectric layer or the conductive layer to improve the adhesion of the dielectric layer or the conductive layer. For example, increasing the surface roughness may improve the bonding strength with subsequent film layers.

[0083] In another embodiment, only the position information of the master die can be checked, that is, only the position of the first input / output pad 112 of the first electronic unit 110 can be checked, and the circuit structure 150a can be formed based on this position information. In other words, in this embodiment, only the offset of the first electronic unit 110 can be confirmed, and only the first pitch P1 can be measured to determine the position of the first trace 152 and the second trace 154. The position of the second conductive layer 155 can also be determined by calculating at least one of the first trace 152 and the second trace 154.

[0084] Please refer to Figure 1D After forming the first conductive layer 151, connecting posts 157 may be formed on the first traces 152 and the second traces 154, where the connecting posts 157 electrically connect the first traces 152 and the second traces 154. Subsequently, an insulating layer 158 may be formed to cover the first conductive layer 151, the second conductive layer 155, and the connecting posts 157, exposing surfaces 157a of the connecting posts 157. Thus, the circuit structure 150a may include not only the first conductive layer 151 and the second conductive layer 155, but also the connecting posts 157 and the insulating layer 158.

[0085] Afterwards, please also refer to Figure 1D as well as Figure 1E , remove the carrier 30 and the adhesive layer 32 thereon, and perform a singulation process to cut at least the insulating layer 158 and the insulating layer 140. In one embodiment, the sidewall 157b of the connecting pillar 157 can be cut flush with the peripheral surface 141 of the insulating layer 140, but is not limited thereto. In one embodiment, a portion of the guide plate 130a can be removed to have a curved surface 131, but is not limited thereto. In one embodiment, a portion of the guide plate 130a can be removed to form a guide plate 130a having an opening 137 and / or a groove 138, wherein the opening 137 penetrates the guide plate 130a from the bottom surface 133 toward the insulating layer 140, and the groove 138 can be formed in the bottom surface 133. Because the guide plate 130a has a patterned design, i.e., having the opening 137 and / or the groove 138, it can prevent the first electronic unit 110 and the second electronic unit 120 from being cracked due to high stress. On the other hand, the guide plate 130a having the opening 137 and / or the groove 138 can enhance the subsequent bonding strength with the printed circuit board. In one embodiment, a connection layer (not shown) can be provided on the bottom surface 133 of the guide plate 130a. The connection layer can be made of tin, nickel, gold, silver, gallium, or other suitable metal materials. The connection layer can be used to bond with external components (such as a printed circuit board). Finally, a connector 160 can be formed on the connecting post 157. The connector 160 can extend to cover the sidewall 152a of the first trace 152 and the sidewall 154a of the second trace 154, but is not limited to this. At this point, the electronic device 100a is completed.

[0086] It should be noted that in this embodiment, only one electronic device 100a is schematically shown on the carrier 30, but this is not limiting. In one embodiment, multiple electronic devices may be mounted on the carrier 30, and the circuit structure may be configured by inspecting the position information of the master die in all electronic devices, or by inspecting only a few regions and taking the average displacement.

[0087] Figure 2 This is a top perspective diagram of multiple electronic devices on a carrier board according to an embodiment of the present disclosure. Figure 2 , the circuit structures 150a, 150' of two adjacent electronic devices 100a, 100' are different from each other. For example, the first input / output pad 112 of the first electronic unit 110 of the electronic device 100a and the first input / output pad 112' of the first electronic unit 110' of the electronic device 100' may be the same in size, position, and shape, but are not limited to this. The second input / output pad 122 of the second electronic unit 120 of the electronic device 100a and the second input / output pad 122' of the second electronic unit 120' of the electronic device 100' may be the same in size and shape, but the positions may be different, but are not limited to this. The second conductor layer 155 of the circuit structure 150a of the electronic device 100a and the second conductor layer 155' of the circuit structure 150' of the electronic device 100' may be different in size, position, and shape, but are not limited to this.

[0088] In terms of structure, please also refer to Figure 1E and Figure 1F In this embodiment, the electronic device 100a includes a first electronic unit 110 and a second electronic unit 120, an insulating layer 140 and a circuit structure 150a. The first electronic unit 110 and the second electronic unit 120 are arranged adjacent to each other or side by side. The insulating layer 140 surrounds the first electronic unit 110 and the second electronic unit 120, and exposes at least a portion of the first electronic unit 110 and at least a portion of the second electronic unit 120. The circuit structure 150a is configured on the insulating layer 140, and the circuit structure 150a includes a first conductor layer 151 and a second conductor layer 155. The first conductor layer 151 includes a first trace 152 and a second trace 154. The first trace 152 is insulated from the second trace 154, and the first trace 152 and the second trace 154 are electrically connected through the second conductor layer 155. As Figure 1F As shown, in this embodiment, each first trace 152 is electrically connected to each second trace 154 via a second conductive layer 155, but the present invention is not limited thereto. In one embodiment, the second conductive layer 155 is, for example, a compensation pattern.

[0089] Furthermore, the electronic device 100a of this embodiment further includes a guide plate 130a, on which the first electronic unit 110 and the second electronic unit 120 are disposed. In one embodiment, the first electronic unit 110 and the second electronic unit 120 share the same guide plate 130a, wherein the guide plate 130a may be, for example, a metal plate or a heat sink, but is not limited thereto. Furthermore, the electronic device 100a of this embodiment further includes a conductive post 135, which penetrates the insulating layer 140 and connects the first trace 152 to the guide plate 130a and the second trace 154 to the guide plate 130a. The conductive post 135 is suitable for electrical conductivity, thermal conductivity, or both, without limitation.

[0090] In addition, the circuit structure 150a of this embodiment may further include a connecting post 157 and an insulating layer 158. The connecting post 157 is disposed on the first trace 152 and the second trace 154, wherein the connecting post 157 electrically connects the first trace 152 and the second trace 154. The insulating layer 158 covers the first conductive layer 151, the second conductive layer 155, and the connecting post 157, and exposes a surface 157a of the connecting post 157. Furthermore, the circuit structure 100a of this embodiment may further include a connector 160 disposed on the surface 157a of the connecting post 157. The connector 160 may extend to cover the sidewall 152a of the first trace 152 and the sidewall 154a of the second trace 154, but is not limited thereto.

[0091] In short, in this embodiment, an algorithm is first used to calculate and confirm the position information of the master die, such as the position (e.g., offset) of the first electronic unit 110. This information is then used to arrange the first conductive layer 151. The calculations of the first conductive layer 151 are then used to determine the position of the second conductive layer 155, allowing the second conductive layer 155 to connect the first trace 152 and the second trace 154 of the first conductive layer 151. This allows the electronic device 100a to have greater electrical reliability. Furthermore, the arrangement of the second conductive layer 155 does not require changing the size of the annular ring (AR), allowing for more flexible space utilization in the circuit design and, consequently, enhancing the competitiveness of the electronic device 100a of this embodiment.

[0092] It should be noted that the following embodiments share the same component numbers and some of the contents as the previous embodiments, wherein the same reference numerals are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the previous embodiments, and the following embodiments will not repeat them.

[0093] Figure 3 This is a top view of an electronic device according to an embodiment of the present disclosure. Figure 1F and Figure 3 The electronic device 100b of this embodiment is Figure 1FThe electronic device 100a is similar to the electronic device 100a, but differs in that: in this embodiment, the second conductive layer 155b includes compensation patterns 156b and compensation traces 159b connected to each other. Each first trace 152b is electrically connected to each second trace 154b via two compensation patterns 156b and one compensation trace 159b, but the present invention is not limited thereto.

[0094] Figure 4 This is a top view of an electronic device according to another embodiment of the present disclosure. Figure 1F and Figure 4 The electronic device 100c of this embodiment is Figure 1F The electronic device 100a is similar to the electronic device 100a, with the difference being that in this embodiment, the first electronic unit 110c and the second electronic unit 120c are offset. The second conductive layer 155c includes interconnected compensation patterns 156c and compensation traces 159c. Each first trace 152c is electrically connected to each second trace 154c via two compensation patterns 156c and one compensation trace 159c, but this is not limiting.

[0095] It should be noted that the present disclosure does not limit the structural type of the second conductive layer, that is, it does not limit the configuration of the compensation patterns and compensation traces. 5A to 5D Schematic diagram of the second conductive layer of the circuit structure of multiple embodiments disclosed herein.

[0096] Please refer to Figure 5A The second conductive layer 155d includes a plurality of compensation patterns 156d1, 156d2, 156d3, 156d4, and 156d5. Compensation patterns 156d1, 156d2, 156d3, 156d4, and 156d5 are arranged at equal intervals, but are not limited to this arrangement. From a top view, compensation pattern 156d1 can be cross-shaped; compensation pattern 156d2 can be square-shaped; compensation pattern 156d3 can be diamond-shaped; compensation pattern 156d4 can be snowflake-shaped; and compensation pattern 156d5 can be circular-shaped, but is not limited to this arrangement.

[0097] Please refer to Figure 5B The second conductive layer 155e includes a plurality of compensation patterns 156e, wherein the compensation patterns 156e are arranged in a staggered manner, but the present invention is not limited thereto.

[0098] Please refer to Figure 5C The second conductive layer 155f includes a plurality of compensation patterns 156f and a plurality of compensation traces 159f, wherein a compensation trace 159f connecting two compensation patterns 156f can be regarded as a set of connection structures, and these connection structures can be arranged at equal intervals, but are not limited thereto.

[0099] Please refer to Figure 5DThe second conductor layer 155g includes a plurality of compensation patterns 156g and a plurality of compensation traces 159g, wherein some compensation patterns 156g can be set separately without being connected to the compensation traces 159g, and one compensation trace 159g can connect two compensation patterns 156g and can be regarded as a group of connection structures, and these connection structures can be arranged in non-arrays and non-equidistantly, but are not limited to this.

[0100] In short, in the present disclosure, the second conductive layer can have any shape. The second conductive layer can be arranged in a matrix, a non-matrix arrangement, an evenly spaced arrangement, or an unevenly spaced arrangement, without limitation. The position and size of the second conductive layer require calculation and software processing via an algorithm. The second conductive layer can be variable in both shape and position, variable in size, or both in size and position.

[0101] Figure 6 This is a cross-sectional diagram of an electronic device according to an embodiment of the present disclosure. Figure 1E and Figure 6 The electronic device 100d of this embodiment is Figure 1E The electronic device 100a is similar to the electronic device 100a, except that in this embodiment, the second conductive layer 155h of the circuit structure 150h is connected across the first trace 152 and the second trace 154. Specifically, the second conductive layer 155h is located on the first trace 152 and the second trace 154. The second conductive layer 155h has a first width W1, the overlap between the second conductive layer 155h and the first trace 152 has a second width W2, and the overlap between the second conductive layer 155h and the second trace 154 has a third width W3. The ratio of the second width W2 to the first width W1, or the ratio of the third width W3 to the first width W1, is between 0.3 and 0.7. Furthermore, in this embodiment, the first electronic unit 110 and the second electronic unit 120 are respectively disposed on two guide plates 130d, wherein the guide plates 130d are separated from each other and each has a curved surface 131, but this is not limiting. The insulating layer 140 d surrounds the first electronic unit 110 , the second electronic unit 120 and the conductive pillar 135 and has a curved surface 143 . The bottom surface 145 of the insulating layer 140 d exposes the bottom surface 133 of the guide plate 130 d to enhance heat dissipation.

[0102] Figure 7A This is a cross-sectional diagram of an electronic device according to another embodiment of the present disclosure. Figure 6 and Figure 7A The electronic device 100e of this embodiment is Figure 6d. The electronic device 100d is similar to the electronic device 100d, with the difference being that in this embodiment, the first trace 152f and the second trace 154f of the first conductive layer 151f each comprise multiple circuit layers. Specifically, in this embodiment, the first trace 152f includes a circuit layer L1 and a circuit layer L2, wherein the circuit layer L1 is electrically connected to the first input / output pad 112 of the first electronic unit 110, and the circuit layer L2 is located on the circuit layer L1 and electrically connected to the circuit layer L1. In one embodiment, the first trace 152f is, for example, a fan-out circuit, but is not limited thereto. The second trace 154f includes a circuit layer L3 and a circuit layer L4, wherein the circuit layer L3 is electrically connected to the second input / output pad 122 of the second electronic unit 120, and the circuit layer L4 is located on the circuit layer L3 and electrically connected to the circuit layer L3. In one embodiment, the second trace 154f is, for example, a fan-out circuit, but is not limited thereto. Furthermore, in this embodiment, the conductive post 135f connects the circuit layer L1 of the first trace 152f and the metal plate 130d, and connects the circuit layer L3 of the second trace 154f and the metal plate 130d. Furthermore, the second conductive layer 155e includes a compensation pattern 156e and a compensation trace 159e. The compensation trace 159e connects the circuit layer L2 of the first trace 152f and the circuit layer L4 of the second trace 154f. The compensation pattern 156e is located on and connected to the compensation trace 159e.

[0103] Figure 7B This is a cross-sectional diagram of an electronic device according to another embodiment of the present disclosure. Figure 7A and Figure 7B The electronic device 100f of this embodiment is Figure 7A The difference between the two is that: in this embodiment, the second conductive layer 155f connects the circuit layer L2 of the first trace 152f and the circuit layer L4 of the second trace 154f, and is located on the same plane as the circuit layer L2 and the circuit layer L4, but is not limited thereto.

[0104] It should be noted that in one embodiment, the electronic device may not include a guide plate, which means that the insulating layer directly covers the back surface of the electronic unit relative to the active surface, or the insulating layer may directly expose the back surface of the electronic unit, which still falls within the scope of protection of this disclosure.

[0105] In summary, an algorithm is first used to calculate and confirm the position of the electronic unit (e.g., offset). This positional information is then used to configure the circuit structure, where the second conductive layer connects the first and second traces of the first conductive layer. This ensures greater electrical reliability for the electronic device. Furthermore, the placement of the second conductive layer eliminates the need to change the size of the annular ring (AR), allowing for more flexible space utilization in circuit design and ultimately enhancing the competitiveness of the electronic device.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: Providing a first electronic unit and a second electronic unit on a carrier board; providing an insulating layer to surround the first electronic unit and the second electronic unit; Thinning the insulating layer until at least a portion of the first electronic unit and at least a portion of the second electronic unit are exposed; performing an offset confirmation on at least one of the first electronic unit and the second electronic unit; and A circuit structure is provided on the insulating layer according to the offset, wherein the circuit structure includes a first conductor layer and a second conductor layer, the first conductor layer includes a first trace and a second trace, and the first trace and the second trace are electrically connected through the second conductor layer.

2. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: At least one of the first routing line and the second routing line is calculated to determine a position of the second conductive layer.

3. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: The first electronic unit includes first input / output pads having a first pitch, and the second electronic unit includes second input / output pads having a second pitch. When the first pitch is different from the second pitch, at least the smaller of the first pitch and the second pitch is measured to determine the positions of the first trace and the second trace.

4. An electronic device, characterized in that: include: The first electronic unit and the second electronic unit are adjacent to each other; an insulating layer surrounding the first electronic unit and the second electronic unit; as well as The circuit structure is configured on the insulating layer, and the circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer includes a first trace and a second trace, and the first trace and the second trace are electrically connected through the second conductor layer.

5. The electronic device according to claim 4, wherein: The first wiring is insulated from the second wiring.

6. The electronic device according to claim 4, wherein: The second conductor layer is located on the first routing and the second routing, the second conductor layer has a first width, the overlapping portion of the second conductor layer and the first routing has a second width, the overlapping portion of the second conductor layer and the second routing has a third width, and the ratio of the second width to the first width or the ratio of the third width to the first width is between 0.3 and 0.

7.

7. The electronic device according to claim 4, wherein: The circuit structures of two adjacent electronic devices are different from each other.

8. The electronic device according to claim 4, wherein: Also includes: At least one guide plate, the first electronic unit and the second electronic unit are configured on the at least one guide plate.

9. The electronic device according to claim 8, wherein: Also includes: The conductor post penetrates the insulating layer and connects at least one of the first trace and the second trace to the at least one guide plate.

10. The electronic device according to claim 4, wherein: The circuit structure further includes a connecting column configured on the first trace and the second trace.

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