Display device

Abstract

The invention discloses a display device. A display device of an embodiment is divided into an active area, a wiring area disposed on at least one side of the active area, and a pad area adjacent to the wiring area, and includes: an element layer disposed on a circuit layer and including a light emitting element and a sensing element disposed in the active area; and a data line and a sensing line electrically connected to the light emitting element and the sensing element, respectively, and arranged so as to extend from the active area to the wiring area. The wiring region includes: a first region adjacent to the active region; a second region adjacent to the pad region; and an open region disposed between the first region and the second region in which the sensing line is disposed on an upper side of the data line, and the organic insulating layer is removed, in which the sensing line is disposed on a lower side of the data line, and sensing lines can be easily arranged in a defined wiring region irrespective of the arrangement of the data lines to enlarge the area of a sensing region, thereby exhibiting excellent sensing capability.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including a sensing element. Background Art

[0002] Display devices offer a variety of functions that allow for organic interaction with users, such as displaying images to provide information to users and sensing user input. Recent display devices also include functions for sensing user-provided information (e.g., biometric information). Methods for identifying user information include capacitive methods that sense changes in capacitance between electrodes, optical methods that use photosensors to sense incident light, and ultrasonic methods that use piezoelectric elements to sense vibrations.

[0003] In addition, with the recent introduction of a structure that minimizes a dead space of a display device, there is a problem that an arrangement area for wiring for driving a sensing element or the like for a sensing function is limited. Summary of the Invention

[0004] The present invention provides a display device including a display element and a sensing element, wherein the arrangement of sensing wirings connected to the sensing element is optimized within a limited area.

[0005] Another object of the present invention is to provide a display device that minimizes interference between a sensing wire connected to a sensing element and a data wire connected to a display element, while expanding a sensing area by arranging the sensing wires without increasing a dead zone.

[0006] One embodiment provides a display device as follows, which is divided into an active area, a wiring area arranged on at least one side of the active area, and a pad area adjacent to the wiring area, and includes: a base layer; a circuit layer including a buffer layer arranged on the base layer, multiple inorganic insulating layers arranged on the buffer layer, multiple organic insulating layers arranged on the inorganic insulating layers, and multiple conductive patterns; an element layer arranged on the circuit layer and including a light-emitting element and a sensing element arranged in the active area; a data line electrically connected to the light-emitting element and extending from the active area to the wiring area; and a sensing line electrically connected to the sensing element and extending from the active area to the wiring area, wherein the wiring area includes: a first area adjacent to the active area; a second area adjacent to the pad area; and an open area arranged between the first area and the second area, and the organic insulating layer is removed, wherein in the first area and the second area, the sensing line is arranged above the data line, and in the open area, the sensing line is arranged below the data line. The sensing line may include: a first sensing wiring portion, which is arranged on the upper side of the inorganic insulating layer in the first area; a second sensing wiring portion, which is arranged on the lower side of the inorganic insulating layer in the open area; a third sensing wiring portion, which is arranged on the upper side of the inorganic insulating layer in the second area; and a connecting wiring portion, which respectively connects the first sensing wiring portion and the second sensing wiring portion and the second sensing wiring portion and the third sensing wiring portion.

[0007] The first sensing wiring portion and the third sensing wiring portion may be respectively arranged on the same layer between the organic insulating layers, and the second sensing wiring portion may be arranged on a lower side of the buffer layer.

[0008] The circuit layer may further include a lower shielding pattern overlapping the second sensing wiring portion in the open region and disposed between the second sensing wiring portion and the data line.

[0009] The lower shield pattern may be disposed at a lower side of the inorganic insulating layer or between the inorganic insulating layers.

[0010] The circuit layer may further include an upper shielding pattern disposed between the sensing line and the data line in the first region and the second region.

[0011] The upper shield pattern may be disposed on a lower side of the organic insulating layer, or disposed on the same layer as an organic insulating layer adjacent to the inorganic insulating layer among the organic insulating layers.

[0012] The connection wiring portion may include a first connection portion disposed through at least one of the organic insulating layers; and a second connection portion disposed through the inorganic insulating layer.

[0013] The data line may be disposed between the inorganic insulating layers.

[0014] In the effective area, the conductive pattern may include a transistor, a capacitor, a back metal layer overlapping the transistor on the lower side of the transistor, and a plurality of connecting electrodes electrically connected to the light-emitting element or the sensing element and arranged between the organic insulating layers, wherein the conductive pattern in the wiring area may include the data line and the sensing line.

[0015] In the wiring region, the data line may be arranged on the same layer as any one of the electrodes constituting the transistor or any one of the electrodes constituting the capacitor.

[0016] In the wiring area, the data lines may include: a first layer of data lines, which are arranged on the same first inorganic insulating layer in the first area, the open area and the second area; and a second layer of data lines, which are arranged on the same second inorganic insulating layer in the first area, the open area and the second area, and the second inorganic insulating layer is arranged on the first inorganic insulating layer.

[0017] In the open area, the sensing line may be arranged on the same layer as the back metal layer.

[0018] In the first region and the second region, the sensing line may be arranged on the same layer as any one of the connection electrodes.

[0019] The display device further includes at least one dam portion disposed on the inorganic insulating layer in the open region, wherein the at least one dam portion may overlap with the sensing line.

[0020] The at least one dam may be arranged to extend in a second direction perpendicular to a first direction extending from the active area to the wiring area.

[0021] The display device may further include: a sensor layer arranged on the element layer, including a sensor conductive layer and a sensor insulating layer.

[0022] The wiring area may include: a first non-bending area adjacent to the effective area; a bending area bent with a virtual axis extending in one direction as a reference; and a second non-bending area separated from the first non-bending area and with the bending area positioned therebetween, wherein the open area is included in the first non-bending area.

[0023] A width of the second non-bending region in the one direction may be smaller than a width of the first non-bending region in the one direction.

[0024] In one embodiment, a display device is divided into an active area and a peripheral area adjacent to the active area, and includes: a base layer; a circuit layer, including a lower insulating layer arranged on the base layer, an upper insulating layer arranged on the lower insulating layer and including an organic matter, and a conductive pattern; a display layer, arranged on the circuit layer, including a pixel defining film defining an opening, a light-emitting element and a sensing element respectively arranged in the opening; a data line, electrically connected to the light-emitting element, and arranged to extend from the active area to the peripheral area; a sensing line, electrically connected to the sensing element, and arranged to extend from the active area to the peripheral area; and at least one shielding pattern, arranged between the data line and the sensing line in the peripheral area, wherein the peripheral area includes: an open area, in which the upper insulating layer is removed; a non-open area, adjacent to the open area, in which the upper insulating layer is not removed, wherein the sensing line is arranged on the upper side of the data line in the non-open area, and wherein the sensing line is arranged on the lower side of the data line in the open area.

[0025] The sensing line may include an upper sensing wiring portion arranged on an upper side of the lower insulating layer in the non-open region; and a lower sensing wiring portion arranged on a lower side of the lower insulating layer in the open region. The conductive pattern includes a transistor, a capacitor, a back metal layer overlapping with the transistor on the lower side of the transistor, and a plurality of connecting electrodes electrically connected to the light-emitting element or the sensing element and arranged on the upper insulating layer. In the peripheral area, the data line and any one of the electrodes constituting the transistor or any one of the electrodes constituting the capacitor can be arranged on the same layer.

[0026] In the open area, the sensing line may be arranged on the same layer as the back metal layer.

[0027] In the non-open area, the sensing line may be arranged on the same layer as any one of the connection electrodes.

[0028] The at least one shielding pattern may include a lower shielding pattern arranged at a lower side of the upper sensing wiring portion in the non-open region; and an upper shielding pattern arranged at an upper side of the lower sensing wiring portion in the open region.

[0029] The opening includes a first opening and a second opening that do not overlap with each other on a plane. The light-emitting element can be arranged on the upper insulating layer and include a first light-emitting electrode with an upper portion exposed from the first opening and a light-emitting layer arranged in the first opening. The sensing element is arranged on the upper insulating layer and can include a first sensing electrode with an upper portion exposed from the second opening and a photoelectric conversion layer arranged in the second opening.

[0030] A display device according to an embodiment of the present invention is provided, comprising: an active area and a peripheral area, wherein the peripheral area is arranged on one side of the active area and includes a curved area that is curved with respect to a virtual axis extending in one direction and is separated from the active area, and the display device includes: a base layer; a circuit layer comprising a plurality of inorganic insulating layers arranged on the base layer, a plurality of organic insulating layers arranged on the inorganic insulating layers, transistors, capacitors, a back metal layer overlapping with the transistors on the lower side of the transistors, and a plurality of connection electrodes arranged on the organic insulating layer; an element layer arranged on the circuit layer and including a light emitting diode arranged in the active area; A light-emitting element and a sensing element; a data line electrically connected to the light-emitting element and extending from the effective area to the bending area; and a sensing line electrically connected to the sensing element and extending from the effective area to the bending area, wherein the peripheral area includes an open area defined between the bending area and the effective area and from which the organic insulating layer is removed, in which the sensing line is arranged on the same layer as the back metal layer on the lower side of the data line, and between the effective area and the open area, the sensing line is arranged on the same layer as one of the multiple connecting electrodes on the upper side of the data line.

[0031] A display device according to an embodiment includes a sensing line of a layer different from that of a data line arranged in an open area where an organic insulating layer is removed. The sensing line can be easily arranged even in the open area regardless of the arrangement of the data line, thereby enabling sufficient arrangement of sensing elements and exhibiting excellent sensing capabilities.

[0032] In addition, the display device of one embodiment arranges the sensing lines as a conductive layer different from the data lines in the open area where the organic insulating layer is removed, so that the sensing lines are not restricted to areas other than the area where the data lines are arranged. Accordingly, the data lines and the sensing lines can be effectively arranged even in a reduced dead space. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0034] Figure 2is a block diagram of a display device according to an embodiment of the present invention.

[0035] Figure 3 FIG. 1 is a block diagram illustrating a display layer and a display driving unit according to an embodiment of the present invention.

[0036] Figure 4 FIG. 1 is a diagram illustrating a block diagram of a sensor layer and a sensor driving unit according to an embodiment of the present invention.

[0037] Figure 5 FIG. 4 is an equivalent circuit diagram of a pixel and a sensor according to an embodiment of the present invention.

[0038] Figure 6 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0039] Figure 7 FIG. 1 is a plan view illustrating a display panel according to an embodiment of the present invention.

[0040] Figure 8 FIG. 1 is an enlarged plan view illustrating a portion of a display panel according to an embodiment of the present invention.

[0041] Figure 9 FIG. 1 is an enlarged cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention.

[0042] Figure 10 FIG. 1 is an enlarged cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention.

[0043] Figure 11 FIG. 1 is an enlarged cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention.

[0044] Description of Reference Numerals DETAILED DESCRIPTION

[0045] The present invention is susceptible to various modifications and various forms, and specific embodiments will be illustrated in the accompanying drawings to provide a detailed description thereof. However, this does not limit the present invention to the specific disclosed forms, and the present invention should be understood to encompass all modifications, equivalents, and even alternatives encompassed by the concept and technical scope of the present invention.

[0046] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being "on", "connected to" or "bound to" another component (or region, layer, part, etc.), it means that it can be directly arranged on / connected to / bound to another component (or region, layer, part, etc.), or a third component (or region, layer, part, etc.) can be arranged between them.

[0047] The same reference numerals refer to the same components. Furthermore, in the drawings, the thicknesses, ratios, and sizes of the components are exaggerated to effectively illustrate the technical content. "And / or" includes one or more combinations of all relevant components that can be defined.

[0048] Terms such as first and second can be used when describing a variety of components, but the components are not limited to the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, the first component can be named as the second component, and similarly, the second component can also be named as the first component. Unless otherwise clearly stated in the context, a singular expression includes a plural expression.

[0049] Furthermore, terms such as “below,” “on the lower side,” “above,” and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0050] Terms such as "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding in advance the existence or additional possibilities of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0051] In this specification, "directly arranged" may mean that there is no additional layer, film, region, plate, etc. between a layer, film, region, plate, etc. and another part. For example, "directly arranged" may mean that two layers or two parts are arranged without using an additional part such as an adhesive part between them.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meanings as those commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with those in the context of the relevant art and should not be interpreted as having overly ideal or formal meanings unless expressly defined herein.

[0053] Hereinafter, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0055] The display device 1000 of one embodiment can be a device activated by an electrical signal. For example, it can be a small or medium-sized device such as a smartphone, a personal computer, a notebook computer, a personal digital assistant, a car navigation unit, a game console, a tablet computer, or a camera. Alternatively, the display device 1000 can be a large device such as a television, a monitor, or an external billboard. Furthermore, such a device is provided as an example only and can be used in other electronic devices without departing from the concepts of the present invention. Figure 1 exemplarily illustrates a case where the display device 1000 is a smart phone.

[0056] An active area 1000A and a peripheral area 1000NA may be defined in the display device 1000. The display device 1000 may display an image through the active area 1000A. The active area 1000A may include a surface defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may surround the periphery of the active area 1000A.

[0057] The thickness direction of the display device 1000 may be parallel to a third direction DR3 that intersects the first direction DR1 and the second direction DR2. Therefore, the front surface (or top surface) and the back surface (or bottom surface) of the components constituting the display device 1000 may be defined based on the third direction DR3.

[0058] Figure 2 is a block diagram of a display device according to an embodiment of the present invention.

[0059] Reference Figure 2 The display device 1000 may include a display panel DP, a display driver 100C, a sensor driver 200C, and a main driver 1000C. The display panel DP may include a display layer 100 and a sensor layer 200 disposed above the display layer 100. In one embodiment of the present invention, the sensor layer 200 may also be omitted.

[0060] The display layer 100 may be a structure that substantially generates an image. The display layer 100 may be a light-emitting display layer. For example, the display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer. Furthermore, the display layer 100 may include a sensor that senses light reflected by the user's fingerprint 2000fp or reacts to light.

[0061] The sensor layer 200 may be disposed above the display layer 100. The sensor layer 200 may sense external input 2000 applied from the outside. The external input 2000 may include any input unit capable of providing a change in capacitance. For example, the sensor layer 200 may sense input not only from passive input units such as the user's body, but also from active input units providing a driving signal.

[0062] The main driver 1000C can control the overall operation of the display device 1000. For example, the main driver 1000C can control the operation of the display driver 100C and the sensor driver 200C. The main driver 1000C can include at least one microprocessor and may also include a graphics controller. The main driver 1000C can be referred to as an application processor, a central processing unit, or a main processor.

[0063] The display driver 100C can drive the display layer 100. The display driver 100C can receive image data RGB and a control signal D-CS from the main driver 1000C. The control signal D-CS can include various signals. For example, the control signal D-CS can include an input vertical synchronization signal, an input horizontal synchronization signal, a master clock, and a data enable signal. The display driver 100C generates a vertical synchronization signal and a horizontal synchronization signal based on the control signal D-CS to control the timing of providing signals to the display layer 100.

[0064] The sensor driving part 200C may drive the sensor layer 200. The sensor driving part 200C may receive a control signal I-CS from the main driving part 1000C. The control signal I-CS may include a mode determination signal for determining a driving mode of the sensor driving part 200C and a clock signal.

[0065] The sensor driver 200C can calculate the input coordinate information based on the signal received from the sensor layer 200 and provide a coordinate signal I-SS containing the coordinate information to the main driver 1000C. The main driver 1000C performs an operation corresponding to the user input based on the coordinate signal I-SS. For example, the main driver 1000C can operate the display driver 100C to display a new application image on the display layer 100.

[0066] Figure 3 FIG. 1 is a block diagram illustrating a display layer and a display driving unit according to an embodiment of the present invention.

[0067] Reference Figure 2 and Figure 3 The display driving part 100C may include a driving controller 100C1 , a data driver 100C2 , a scan driver 100C3 , a light emitting driver 100C4 , a voltage generator 100C5 , and a sensor controller 100C6 .

[0068] The display layer 100 may include an active area 1000A ( Figure 1 ) corresponding to the active area DA (or display area) and the peripheral area 1000NA ( Figure 1 ) corresponds to the peripheral area NDA (or non-display area).

[0069] The display layer 100 may include a plurality of pixels PX arranged in an active area DA and a plurality of sensors FX arranged in the active area DA. The display layer 100 also includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and sensing lines (or, may be referred to as readout lines) RL1 to RLh.

[0070] Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn extend along the second direction DR2. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and emission control lines EML1 to EMLn are arranged spaced apart from one another in the first direction DR1. The data lines DL1 to DLm and the sensing lines RL1 to RLh extend along the first direction DR1 and are arranged spaced apart from one another in the second direction DR2.

[0071] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto and may vary.

[0072] Multiple sensors FX are electrically connected to sensing lines RL1 to RLh. One sensor FX can be electrically connected to one scan line (e.g., one write scan line among write scan lines SWL1 to SWLn). However, the present invention is not limited thereto. The number of scan lines connected to each sensor FX may vary.

[0073] As an example of the present invention, the number of sensing lines RL1 to RLh may be equal to 1 / 2 of the number of data lines DL1 to DLm. However, the present invention is not limited thereto. For example, in one embodiment, the number of sensing lines RL1 to RLh may be equal to 1 / 4 or 1 / 8 of the number of data lines DL1 to DLm, or the number of sensing lines RL1 to RLh may be the same as the number of data lines DL1 to DLm.

[0074] The driver controller 100C1 receives image data RGB and a control signal D-CS. It converts the data format of the image data RGB to generate an image data signal DATA that matches the interface specifications of the data driver 100C2. The driver controller 100C1 outputs a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal RCS.

[0075] The data driver 100C2 receives a third control signal DCS and an image data signal DATA from the drive controller 100C1. The data driver 100C2 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0076] The scan driver 100C3 receives a first control signal SCS from the drive controller 100C1. The scan driver 100C3 can output scan signals to the scan lines in response to the first control signal SCS. For example, the scan driver 100C3 can output initialization scan signals to the initialization scan lines SIL1 to SILn and compensation scan signals to the compensation scan lines SCL1 to SCLn in response to the first control signal SCS. Furthermore, the scan driver 100C3 can output write scan signals to the write scan lines SWL1 to SWLn and black scan signals to the black scan lines SBL1 to SBLn in response to the first control signal SCS.

[0077] The light emitting driver 100C4 receives the second control signal ECS from the driving controller 100C1. The light emitting driver 100C4 may output a light emitting control signal to the light emitting control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 100C3 may be connected to the light emitting control lines EML1 to EMLn. In this case, the light emitting driver 100C4 may be omitted, and the scan driver 100C3 may output a light emitting control signal to the light emitting control lines EML1 to EMLn.

[0078] The scan driver 100C3 and the light emitting driver 100C4 may be disposed in the peripheral area NDA of the display layer 100. However, the embodiment is not limited thereto. For example, at least a portion of each of the scan driver 100C3 and the light emitting driver 100C4 may also be disposed in the active area DA.

[0079] The voltage generator 100C5 generates voltages required for the operation of the display layer 100. In this embodiment, the voltage generator 100C5 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst.

[0080] The sensor controller 100C6 receives the fourth control signal RCS from the driving controller 100C1 .

[0081] The sensor controller 100C6 may receive sensing signals from the sensing lines RL1 to RLh in response to the fourth control signal RCS. The sensor controller 100C6 may process the sensing signals received from the sensing lines RL1 to RLh and provide the processed sensing signals S_FS to the driving controller 100C1.

[0082] Figure 4 FIG. 1 is a diagram illustrating a block diagram of a sensor layer and a sensor driving unit according to an embodiment of the present invention.

[0083] Reference Figure 4 The sensor layer 200 may include a plurality of first sensing electrodes 210 and a plurality of second sensing electrodes 220 arranged in the active area DA. Each of the plurality of second sensing electrodes 220 may cross the plurality of first sensing electrodes 210.

[0084] Each of the plurality of first sensing electrodes 210 may extend along the first direction DR1 and may be spaced apart in the second direction DR2. Each of the plurality of second sensing electrodes 220 may extend along the second direction DR2 and may be spaced apart in the first direction DR1.

[0085] Each of the plurality of first sensing electrodes 210 may include a sensing pattern 211 and a connection pattern 212. Two adjacent sensing patterns 211 may be electrically connected to each other via two connection patterns 212, but the present invention is not particularly limited thereto. The sensing patterns 211 and the connection patterns 212 may be arranged on different layers.

[0086] Each of the plurality of second sensing electrodes 220 may include a first portion 221 and a second portion 222. The first portion 221 and the second portion 222 may have a shape integral with each other and may be arranged on the same layer. For example, the first portion 221 and the second portion 222 may be arranged on the same layer as the sensing pattern 211. The two connection patterns 212 may be insulated and intersected with the second portion 222.

[0087] The sensor layer 200 may further include a plurality of first traces 231 electrically connected to the first sensing electrodes 210 and a plurality of second traces 232 electrically connected to the second sensing electrodes 220. Each of the first traces 231 and the second traces 232 may be arranged in the peripheral area NDA, but is not particularly limited thereto. For example, at least a portion of the first traces 231 and the second traces 232 may also be arranged to overlap with the active area DA.

[0088] The sensor driver 200C can be driven by the main driver 1000C ( Figure 2 ) receives the control signal I-CS. The sensor driver 200C can send a signal to the main driver 1000C ( Figure 2 ) provides coordinate signal I-SS.

[0089] The sensor driver 200C may be implemented as an integrated circuit (IC) and mounted directly on a predetermined area of ​​the sensor layer 200 , or mounted on a separate printed circuit board in a chip on film (COF) manner and electrically connected to the sensor layer 200 .

[0090] The sensor driving unit 200C may include a sensor control circuit 200C1, a signal generating circuit 200C2, and an input detection circuit 200C3. The sensor control circuit 200C1 may control the operations of the signal generating circuit 200C2 and the input detection circuit 200C3 according to a control signal I-CS.

[0091] The signal generating circuit 200C2 can output the transmission signal TX to the first sensing electrode 210 of the sensor layer 200. The input detection circuit 200C3 can receive the input signal RX from the sensor layer 200. For example, the input detection circuit 200C3 can receive the input signal RX from the second sensing electrode 220. In one embodiment of the present invention, the signal generating circuit 200C2 can output the transmission signal TX to the second sensing electrode 220 of the sensor layer 200, and the input detection circuit 200C3 can receive the input signal RX from the first sensing electrode 210.

[0092] The input detection circuit 200C3 may convert an analog signal into a digital signal. For example, the input detection circuit 200C3 amplifies and filters the received analog signal. That is, the input detection circuit 200C3 may convert the filtered signal into a digital signal.

[0093] Figure 5 FIG. 4 is an equivalent circuit diagram of a pixel and a sensor according to an embodiment of the present invention.

[0094] exist Figure 5 exemplarily illustrates a plurality of pixels PX ( Figure 3 ) is an equivalent circuit diagram of a pixel PXij in ). Each of the multiple pixels PX has the same circuit structure, so for Figure 5 The circuit structure of the pixel PXij in FIG is described and the detailed description of the remaining pixels PX is omitted. Figure 5 As shown in the figure Figure 3 The equivalent circuit diagram of one sensor FXdj among the multiple sensors FX is shown in FIG. Each of the multiple sensors FX has the same circuit structure, so Figure 5 The circuit structure of the sensor FXdj is described and the detailed description of the remaining sensors FX is omitted.

[0095] Reference Figure 3 and Figure 5 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0096] The pixel PXij includes a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto.

[0097] The pixel driving circuit PDC includes first to fifth transistors T1 to T5 , first and second emission control transistors ET1 and ET2 , and a capacitor Cst.

[0098] At least one of the first to fifth transistors T1 to T5 and the first and second emission control transistors ET1 and ET2 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to fifth transistors T1 to T5 and the first and second emission control transistors ET1 and ET2 may be a transistor having an oxide semiconductor layer. For example, the third and fourth transistors T3 and T4 may be oxide semiconductor transistors, and the first, second, and fifth transistors T1, T2, and first and second emission control transistors ET1 and ET2 may be LTPS transistors.

[0099] Specifically, it directly affects the display device 1000 ( Figure 1 ) is constructed to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. In addition, oxide semiconductors have high carrier mobility and low leakage current, so even when driven for a long time, the voltage drop is small. In other words, even when driven at a low frequency, the color change of the image due to the voltage drop is small, so low-frequency driving is possible. As described above, oxide semiconductors have the advantage of low leakage current. Therefore, using an oxide semiconductor to form at least one of the third transistor T3 and the fourth transistor T4 connected to the third electrode (or gate electrode) of the first transistor T1 can prevent leakage current that may flow to the gate electrode while reducing power consumption.

[0100] Some of the first to fifth transistors T1 to T5 and the first and second emission control transistors ET1 and ET2 may be P-type transistors, and the remaining portions may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the first and second emission control transistors ET1 and ET2 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors.

[0101] The configuration of the pixel driving circuit PDC according to the present invention is not limited to Figure 5 The embodiment shown. Figure 5 The pixel driving circuit PDC shown is only an example, and the structure of the pixel driving circuit PDC may be modified. For example, the first to fifth transistors T1 to T5 and the first and second emission control transistors ET1 and ET2 may all be P-type transistors or N-type transistors.

[0102] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can respectively transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device 1000 ( Figure 2 ) image data RGB ( Figure 2 ) corresponding to the voltage level.

[0103] The first driving voltage line VL1 and the second driving voltage line VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can transmit the first initialization voltage VINT1 and the second initialization voltage VINT2 to the pixel PXij, respectively.

[0104] The first transistor T1 is connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light-emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a first emission control transistor ET1, a second electrode connected to the light-emitting element ED via a second emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to one end of the capacitor Cst (e.g., a first node N1). The first transistor T1 can receive an i-th data signal Di transmitted by the i-th data line DLi based on the switching operation of the second transistor T2 and supply a driving current Id to the light-emitting element ED.

[0105] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 can be turned on in response to a write scan signal SWj received via the j-th write scan line SWLj and transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0106] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 can be turned on in response to the j-th compensation scan signal SCj received via the j-th compensation scan line SCLj, and connects the third electrode and the second electrode of the first transistor T1 to each other, thereby diode-connecting the first transistor T1.

[0107] The fourth transistor T4 is connected between the first initialization voltage line VL3, to which the first initialization voltage VINT1 is applied, and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3, which transmits the first initialization voltage VINT1; a second electrode connected to the first node N1; and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj received via the j-th initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT1 to the first node N1, thereby initializing the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0108] The first emission control transistor ET1 includes a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0109] The second light emission control transistor ET2 includes a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the j-th light emission control line EMLj.

[0110] The first and second emission control transistors ET1 and ET2 are simultaneously turned on according to the j-th emission control signal EMj received via the j-th emission control line EMLj. The first driving voltage ELVDD applied by the turned-on first emission control transistor ET1 is compensated by the diode-connected first transistor T1 and then transmitted to the light-emitting element ED.

[0111] The fifth transistor T5 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VINT2, a second electrode connected to a second electrode of the second light emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The second initialization voltage VINT2 may have a voltage level lower than or equal to the first initialization voltage VINT1.

[0112] As described above, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The second driving voltage ELVSS can have a voltage level lower than the first driving voltage ELVDD.

[0113] Sensor FXdj is connected to the dth sensing line RLd, the jth write scan line SWLj (or output control line), and the reset control line RCL among the sensing lines RL1 to RLh. Sensor FXdj includes a sensing element OPD (or light sensing element) and a sensor drive circuit O_SD.

[0114] The sensing element OPD may be a photodiode. As an example of the present invention, the sensing element OPD may be an organic photodiode including an organic substance as a photoelectric conversion layer. The first electrode AE-S ( Figure 6 ) is connected to the first sensing node SN1, the second electrode CE of the sensing element OPD ( Figure 6 ) is connected to a second driving voltage line VL2 that transmits a second driving voltage ELVSS. Figure 5 , the sensor FXdj includes an example of a single sensing element OPD, but the present invention is not particularly limited thereto. For example, the sensor FXdj may include z sensing elements connected in parallel to each other. z may be an integer greater than or equal to 2.

[0115] The sensor drive circuit O_SD includes three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 may be a reset transistor ST1, an amplifier transistor ST2, and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. As an example of the present invention, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifier transistor ST2 and the output transistor ST3 may be LTPS transistors. However, the present invention is not limited thereto, and the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifier transistor ST2 may be an LTPS transistor.

[0116] Furthermore, some of the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may be P-type transistors, while others may be N-type transistors. As an example of the present invention, the amplifier transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, the present invention is not limited thereto, and the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may all be N-type transistors or all be P-type transistors.

[0117] The circuit configuration of the sensor drive circuit O_SD according to the present invention is not limited to Figure 5 . Figure 5 The sensor driving circuit O_SD shown is merely an example, and the configuration of the sensor driving circuit O_SD may be modified for implementation.

[0118] Reset transistor ST1 includes a first electrode connected to third initialization voltage line VL5 and receiving reset voltage Vrst, a second electrode connected to first sensing node SN1, and a third electrode receiving reset control signal RST. Reset transistor ST1 can reset the potential of first sensing node SN1 to reset voltage Vrst in response to reset control signal RST. Reset control signal RST can be a signal provided by reset control line RCL.

[0119] The amplifier transistor ST2 includes a first electrode for receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on according to the potential of the first sensing node SN1, thereby applying the sensing drive voltage SLVD to the second sensing node SN2. As an example of the present invention, the sensing drive voltage SLVD can be one of the first driving voltage ELVDD, the first initialization voltage VINT1, and the second initialization voltage VINT2. When the sensing drive voltage SLVD is the first driving voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VL3. When the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VL4.

[0120] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth sensing line RLd, and a third electrode that receives an output control signal. The output transistor ST3 can transmit the sensing signal FSd to the dth sensing line RLd in response to the output control signal. The output control signal can be the jth write scan signal SWj (or, referred to as the jth output control signal) supplied via the jth write scan line SWLj. In other words, the output transistor ST3 can receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0121] The reset period can be defined as the period during which the reset control line RCL is active (i.e., a high-level period). If a high-level reset control signal RST is supplied via the reset control line RCL, the reset transistor ST1 is turned on. Alternatively, if the reset transistor ST1 is configured as a PMOS transistor, a low-level reset control signal RST can be supplied to the reset control line RCL during the reset period. During the reset period, the first sense node SN1 can be reset to a potential corresponding to the reset voltage Vrst. As an example of the present invention, the reset voltage Vrst can have a voltage level lower than the second drive voltage ELVSS.

[0122] The sensing element OPD of the sensor FXdj may be exposed to light during the light-emitting period of the light-emitting element ED. The voltage of the first sensing node SN1 may maintain the reset voltage Vrst during the reset period. When the sensing element OPD is exposed to light, the voltage of the first sensing node SN1 may gradually shift to the second drive voltage ELVSS. The amplification transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge input to the first sensing node SN1 to the third electrode.

[0123] In the output period, the output transistor ST3 is supplied with the j-th write scan signal SWj of a low level through the j-th write scan line SWLj. If the output transistor ST3 is turned on in response to the j-th write scan signal SWj of a low level, the sensing signal FSd corresponding to the current flowing through the amplifying transistor ST2 can be output to the d-th sensing line RLd.

[0124] Figure 6 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0125] Reference Figure 6 , the display layer 100 may include a base layer BL and a circuit layer DP_CL, a device layer DP_ED, and an encapsulation layer TFE sequentially arranged on the base layer BL.

[0126] The circuit layer DP_CL may include a plurality of insulating layers and a plurality of conductive patterns. In addition, the circuit layer DP_CL may include at least one inorganic layer disposed under the plurality of insulating layers. The at least one inorganic layer may include at least one of a buffer layer and a barrier layer.

[0127] The circuit layer DP_CL may include at least one inorganic layer disposed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. The multiple inorganic layers may constitute the barrier layers BR1, BR2, and / or the buffer layer BFL described later. The barrier layers BR1, BR2, and the buffer layer BFL may be selectively disposed.

[0128] The barrier layers BR1 and BR2 prevent foreign matter from flowing in from the outside. The barrier layers BR1 and BR2 may include at least one of a silicon oxide layer and a silicon nitride layer. They may be provided in plurality, and the silicon oxide layers and the silicon nitride layers may be alternately stacked.

[0129] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. A first back metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2.

[0130] Figure 6 The diagrams in FIG and FIG illustrate a situation where the first back metal layer BMC1 is arranged between the first barrier layer BR1 and the second barrier layer BR2, but the embodiments are not limited thereto. At least one of the first barrier layer BR1 and the second barrier layer BR2 may be omitted, or an additional barrier layer may be further arranged on the second barrier layer BR2.

[0131] The first back metal layer BMC1 may overlap with the first transistor T1. The first back metal layer BMC1 may be a shielding electrode. The first back metal layer BMC1 may block light incident from the lower portion of the display layer 100 toward the first transistor T1, etc., thereby protecting the semiconductor pattern or conductive pattern. The first back metal layer BMC1 may include a conductive material. In addition, in one embodiment, the sensing wiring may be located on the same layer as the first back metal layer BMC1 in a portion of the peripheral area. That is, the sensing wiring may be arranged on the same layer as the first back metal layer BMC1 in a portion of the peripheral area. The sensing wiring may be formed in the same process step as the first back metal layer BMC1. However, the embodiment is not limited thereto, and the sensing wiring may also be arranged on the same layer as the first back metal layer BMC1 and formed in different process steps.

[0132] In one embodiment, each of the first barrier layer BR1 and the second barrier layer BR2, disposed with the first back metal layer BMC1 interposed therebetween, may include multiple stacked sublayers. Each of the multiple sublayers may be an inorganic layer. For example, each of the multiple sublayers may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an amorphous silicon layer, or the like. Furthermore, in one embodiment, the circuit layer DP_CL may include, in addition to the inorganic layers such as the first barrier layer BR1 and the second barrier layer BR2, an organic layer disposed adjacent to the first barrier layer BR1 or the second barrier layer BR2.

[0133] In the case where the first barrier layer BR1 or the second barrier layer BR2 disposed adjacent to the first back metal layer BMC1 includes a plurality of sub-layers, coupling between the first back metal layer BMC1 and other conductive patterns may be more effectively prevented.

[0134] A buffer layer (BFL) may be disposed on the barrier layers BR1 and BR2. The buffer layer (BFL) improves the bonding strength between the base layer (BL) and the semiconductor pattern and / or conductive pattern. The buffer layer (BFL) may include at least one of a silicon oxide layer and a silicon nitride layer. For example, in one embodiment, the buffer layer (BFL) includes a silicon oxide layer and a silicon nitride layer, and the silicon oxide layers and the silicon nitride layers may be alternately stacked.

[0135] The first semiconductor pattern may be arranged above the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern may include low-temperature polycrystalline silicon.

[0136] Figure 6 Only a portion of the first semiconductor pattern arranged above the buffer layer BFL is shown, and another portion of the first semiconductor pattern may be further arranged in another region. The first semiconductor pattern may be arranged in a specific pattern across the pixel. The first semiconductor pattern may have different electrical characteristics depending on whether it is doped or not. The first semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or may be a region doped at a lower concentration than the first region.

[0137] The first region has a greater conductivity than the second region, and the first region can essentially function as an electrode or signal line. The second region can essentially correspond to the active region (or channel region) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion can be the source or drain of the transistor, and yet another portion can be a connecting electrode or signal line.

[0138] The first electrode S1 (or source), active region A1 (or channel region), and second electrode D1 (or drain) of the first transistor T1 are formed by the first semiconductor pattern. The first electrode S1 and second electrode D1 of the first transistor T1 extend from the active region A1 in opposite directions.

[0139] Figure 6 A portion of the connection signal line CSL formed from the first semiconductor pattern is shown. Although not separately shown, the connection signal line CSL may be aligned with the fifth transistor T5 ( Figure 5 ) is connected to the second electrode of the second light emitting control transistor ET2.

[0140] The circuit layer DP_CL may include a plurality of insulating layers arranged on the base layer BL. The circuit layer DP_CL may include a lower insulating layer IL-L ( Figure 9 ) and the upper insulating layer IL-U ( Figure 9 ). Upper insulation layer IL-U ( Figure 9 ) may be a layer including organic matter.

[0141] In one embodiment, the circuit layer DP_CL may include a plurality of inorganic insulating layers and a plurality of organic insulating layers. In addition, in this specification, the plurality of inorganic insulating layers may be referred to as a lower insulating layer IL-L ( Figure 9 ), the plurality of organic insulating layers may be referred to as an upper insulating layer IL-U ( Figure 9 In addition, the circuit layer DP_CL may further include a circuit layer disposed on the lower insulating layer IL-L ( Figure 9 )'s lower barrier layers BR1, BR2 and buffer layer BFL, etc.

[0142] Reference Figure 6 , the first insulating layer 10 can be arranged above the buffer layer BFL. The first insulating layer 10 can overlap with multiple pixels and can cover the first semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide. In this embodiment, the first insulating layer 10 can be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit layer DP_CL described later can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned substances, but is not limited thereto. For example, in one embodiment, the first insulating layer 10 may be an inorganic insulating layer.

[0143] The third electrode G1 (or gate) of the first transistor T1 is disposed above the first insulating layer 10. The third electrode G1 may be part of a metal pattern. The third electrode G1 of the first transistor T1 overlaps with the active area A1 of the first transistor T1. During the doping process of the first semiconductor pattern, the third electrode G1 of the first transistor T1 may function as a mask. The third electrode G1 may include, but is not particularly limited to, titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

[0144] The second insulating layer 20 may be arranged above the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer. For example, in one embodiment, the second insulating layer 20 may be an inorganic insulating layer.

[0145] The upper electrode UE and the second back metal layer BMC2 may be arranged above the second insulating layer 20. The upper electrode UE may overlap with the third electrode G1. The upper electrode UE may be part of the metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping therewith may define a capacitor Cst ( Figure 5 In one embodiment of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. In this case, the upper electrode UE may be arranged on the insulating pattern, and the upper electrode UE may serve as a mask for forming the insulating pattern from the second insulating layer 20.

[0146] The second back metal layer BMC2 may be disposed corresponding to a lower portion of the oxide thin film transistor (eg, the third transistor T3 ) and may receive a constant voltage or signal.

[0147] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second back metal layer BMC2. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer. In one embodiment, the third insulating layer 30 may be an inorganic insulating layer.

[0148] The second semiconductor pattern may be arranged above the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include multiple regions differentiated by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, the reduced region) has higher conductivity than the region where the metal oxide is not reduced (hereinafter, the non-reduced region). The reduced region essentially functions as the source / drain or signal line of the transistor. The non-reduced region essentially corresponds to the active region (or semiconductor region, channel region) of the transistor. In other words, a portion of the second semiconductor pattern may be the active region of the transistor, another portion may be the source / drain region of the transistor, and another portion may be the signal transmission region.

[0149] The first electrode S3 (or source), active area A3 (or channel area), and second electrode D3 (or drain) of the third transistor T3 are formed from the second semiconductor pattern. The first electrode S3 and the second electrode D3 include a metal reduced from a metal oxide semiconductor. The first electrode S3 and the second electrode D3 may extend in opposite directions from the active area A3 in cross-section.

[0150] The fourth insulating layer 40 may be disposed above the third insulating layer 30. The fourth insulating layer 40 may overlap with a plurality of pixels and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. For example, the fourth insulating layer 40 may be an inorganic insulating layer.

[0151] The third electrode G3 (or gate) of the third transistor T3 is disposed above the fourth insulating layer 40. The third electrode G3 may be part of a metal pattern. The third electrode G3 of the third transistor T3 overlaps with the active area A3 of the third transistor T3. The third electrode G3 may function as a mask during the process of restoring the second semiconductor pattern. In one embodiment of the present invention, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0152] The fifth insulating layer 50 may be disposed over the fourth insulating layer 40 and may cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0153] The first connection electrode CNE10 may be disposed above the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first insulating layer 10 to the fifth insulating layer 50.

[0154] The sixth insulating layer 60 may be disposed above the fifth insulating layer 50. The sixth insulating layer 60 may be an organic insulating layer. The organic insulating layer may include, but is not limited to, a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and blends thereof.

[0155] The second connection electrode CNE20 may be disposed above the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 via a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed above the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic insulating layer.

[0156] The third connection electrode CNE30 may be disposed above the seventh insulating layer 70. The third connection electrode CNE30 may be connected to the second connection electrode CNE20 via a third contact hole CH3 penetrating the seventh insulating layer 70. The eighth insulating layer 80 may be disposed above the seventh insulating layer 70 and may cover the third connection electrode CNE30. The eighth insulating layer 80 may be an organic insulating layer.

[0157] In one embodiment, the sixth insulating layer 60, the seventh insulating layer 70, and the eighth insulating layer 80 may be referred to as organic insulating layers. Furthermore, the sixth insulating layer 60, the seventh insulating layer 70, and the eighth insulating layer 80 stacked sequentially may be referred to as an upper insulating layer IL-U ( Figure 9 ).

[0158] The circuit layer DP_CL may further include a sensor driving circuit O_SD ( Figure 5 For ease of explanation, Figure 6 The diagram illustrates a reset transistor ST1 in the sensor drive circuit O_SD. The first electrode STS1, active area STA1, and second electrode STD1 of the reset transistor ST1 are formed using a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. A fourth insulating layer 40 is arranged to cover the first electrode STS1, active area STA1, and second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 is arranged on the fourth insulating layer 40. In this embodiment, the third electrode STG1 may be part of the metal pattern. The third electrode STG1 of the reset transistor ST1 overlaps with the active area STA1 of the reset transistor ST1.

[0159] As an example of the present invention, the reset transistor ST1 can be arranged on the same layer as the third transistor T3. That is, the first electrode STS1, active area STA1, and second electrode STD1 of the reset transistor ST1 can be formed using the same process as the first electrode S3, active area A3, and second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 can be formed simultaneously with the third electrode G3 of the third transistor T3 using the same process. Although not separately illustrated, the first and second electrodes of the amplifier transistor ST2 and the output transistor ST3 of the sensor drive circuit O_SD can be formed using the same process as the first electrode S1 and second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 can be formed using the same process on the same layer, eliminating the need for an additional process for forming the reset transistor ST1, thereby improving process efficiency and reducing costs.

[0160] The circuit layer DP_CL may include a buffer layer BFL, a plurality of inorganic insulating layers 10, 20, 30, 40, 50, a plurality of organic insulating layers 60, 70, 80, and a plurality of conductive patterns. Figure 3 ), the conductive pattern may include transistors T1, T3, ST1, capacitor Cst ( Figure 5 ), the back metal layer BMC1, BMC2 overlapping with the transistor on the lower side of the transistor, and a plurality of connection electrodes CNE10, CNE20, CNE30 electrically connected to the light emitting element ED or the sensing element OPD. In addition, in the peripheral area NDA ( Figure 3 ), the conductive pattern may include data lines DL1 to DLm ( Figure 3 ) and sensing lines RL1 to RLh ( Figure 3 ).

[0161] The element layer DP_ED may be arranged above the circuit layer DP_CL. The element layer DP_ED may include a pixel definition film PDL, a light emitting element ED, and a sensing element OPD. The element layer DP_ED may include a plurality of light emitting elements ED and a plurality of sensing elements OPD divided by the pixel definition film PDL. Figure 6 In FIG, one light emitting element ED and one sensing element OPD are representatively shown.

[0162] A light emitting region PXA may be defined corresponding to the light emitting element ED, and a sensing region SA may be defined corresponding to the sensing element OPD. The light emitting region PXA and the sensing region SA may be defined by a pixel definition layer PDL described later.

[0163] The light emitting element ED may include a first electrode AE, a first functional layer HFL, a light emitting layer EL, a second functional layer EFL, and a second electrode CE. The sensing element OPD may include a first electrode AE-S, a first functional layer HFL, a photoelectric conversion layer LRL, a second functional layer EFL, and a second electrode CE. The first functional layer HFL, the second functional layer EFL, and the second electrode CE may be provided together in the pixel PX (refer to Figure 3 ) and sensor FX (refer to Figure 3 In this specification, the first electrode AE ​​of the light emitting element ED may be referred to as a first light emitting portion electrode, and the first electrode AE-S of the sensing element OPD may be referred to as a first sensing portion electrode.

[0164] Reference Figure 6 The first electrode AE ​​of the light emitting element ED and the first electrode AE-S of the sensing element OPD are disposed on the eighth insulating layer 80. The first electrode AE ​​of the light emitting element ED may be connected to the third connection electrode CNE30 through a fourth contact hole CH4 penetrating the eighth insulating layer 80.

[0165] The light-emitting element ED may further include an auxiliary layer SL. The auxiliary layer SL may be disposed in both the light-emitting region PXA and the sensing region SA. The auxiliary layer SL may be disposed between the first functional layer HFL and the light-emitting layer EL, and between the first functional layer HFL and the photoelectric conversion layer LRL. In one embodiment of the present invention, the auxiliary layer SL may also be omitted.

[0166] A pixel-defining layer (PDL) may be disposed above the eighth insulating layer 80 and may cover a portion of each of the first electrodes AE and AE-S. Openings OP1 and OP2 are defined in the pixel-defining layer (PDL). Multiple emission areas PXA and multiple sensing areas SA may be defined by the openings OP1 and OP2.

[0167] The pixel-defining film PDL can be formed using a polymer resin. For example, the pixel-defining film PDL can be formed by including a polyacrylate resin or a polyimide resin. In addition, the pixel-defining film PDL can also be formed by including an inorganic substance in addition to the polymer resin. In addition, the pixel-defining film PDL can be formed by including a light-absorbing substance, or can be formed by including a black pigment or a black dye. The pixel-defining film PDL formed by including a black pigment or a black dye can realize a black pixel-defining film. When forming the pixel-defining film PDL, the black pigment or the black dye can use carbon black or aniline black, but the embodiment is not limited thereto. In addition, the pixel-defining film PDL can be formed by mixing a blue organic substance and a black organic substance. The pixel-defining film PDL can also include a liquid-repellent organic substance.

[0168] The light-emitting area PXA may be defined by a first opening OP1 of the pixel-defining layer PDL, and the sensing area SA may be defined by a second opening OP2 of the pixel-defining layer PDL. The first opening OP1 may expose at least a portion of the first electrode AE ​​of the light-emitting element ED, and the second opening OP2 may expose at least a portion of the first electrode AE-S of the sensing element OPD.

[0169] The light-emitting layer EL of the light-emitting element ED can be arranged in a region corresponding to the first opening OP1. The light-emitting layer EL can generate a predetermined colored light. In this embodiment, the light-emitting layer EL is patterned to correspond to the first opening OP1, but a single light-emitting layer can be arranged in multiple light-emitting regions. In this case, the light-emitting layer can also generate white light or blue light. Furthermore, the light-emitting layer EL can have a multilayer structure known as a tandem structure.

[0170] The light-emitting layer EL may include low-molecular-weight organic substances or high-molecular-weight organic substances as the light-emitting material. Alternatively, the light-emitting layer EL may include quantum dots as the light-emitting material. The core of the quantum dots may be selected from Group II-VI compounds, Group III-VI compounds, Group I-III-VI compounds, Group III-V compounds, Group III-II-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0171] The photoelectric conversion layer LRL may be arranged in a region corresponding to the second opening OP2. The photoelectric conversion layer LRL may include an organic photosensitive material. The second electrode CE may be arranged on the photoelectric conversion layer LRL. Each of the first electrode AE-S and the second electrode CE may receive an electrical signal. The first electrode AE-S and the second electrode CE may receive different signals. Thus, a predetermined electric field may be formed between the first electrode AE-S and the second electrode CE. The photoelectric conversion layer LRL generates an electrical signal corresponding to light incident on the sensor.

[0172] The charges generated in the photoelectric conversion layer LRL cause the electric field between the first electrode AE-S and the second electrode CE to vary. The amount of charge generated in the photoelectric conversion layer LRL can vary depending on whether light is incident on the sensing element OPD, the amount of light incident on the sensing element OPD, and the intensity of the light. Consequently, the electric field formed between the first electrode AE-S and the second electrode CE can vary. The sensing element OPD according to the present invention can acquire a user's fingerprint information by utilizing the changes in the electric field between the first electrode AE-S and the second electrode CE.

[0173] Although not shown, the element layer DP_ED may further include a covering layer arranged above the second electrode CE. The covering layer may improve the luminous efficiency by the principle of constructive interference. The covering layer may, for example, include a material having a refractive index of 1.6 or greater for light having a wavelength of 589 nm. The covering layer may be an organic covering layer including organic matter, an inorganic covering layer including inorganic matter, or a composite covering layer including organic matter and inorganic matter. For example, the covering layer may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof. The carbocyclic compound, the heterocyclic compound, and the amine-containing compound may optionally be substituted with a substituent including O, N, S, Se, Si, F, Cl, Br, I, or any combination thereof.

[0174] The encapsulation layer TFE is arranged above the device layer DP_ED. The encapsulation layer TFE includes at least one inorganic layer and at least one organic layer. In one embodiment of the present invention, the encapsulation layer TFE may include two encapsulation inorganic layers and an encapsulation organic layer arranged therebetween. In one embodiment of the present invention, the encapsulation layer TFE may include multiple inorganic layers and multiple organic layers stacked alternately.

[0175] The encapsulating inorganic layer protects the light-emitting element ED and the sensing element OPD from moisture and oxygen, while the encapsulating organic layer protects the light-emitting element ED and the sensing element OPD from foreign matter such as dust particles. The encapsulating inorganic layer may include, but is not limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The encapsulating organic layer may include, but is not limited to, an acrylic organic layer.

[0176] The display device 1000 may further include a sensor layer 200 and an optical layer 300 .

[0177] The sensor layer 200 may be disposed above the display layer 100. The sensor layer 200 may sense external input applied from the outside. The external input may be user input. User input may include various forms of external input, such as a part of the user's body, light, heat, a pen, or pressure. The sensor layer 200 may be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer 200 may include a sensor base layer 201, a first sensor conductive layer 202, a sensor insulating layer 203, a second sensor conductive layer 204, and a sensor cover layer 205.

[0178] In one embodiment, the sensor layer 200 may be formed on the display layer 100 through a continuous process. That is, the sensor layer 200 may be directly disposed on the display layer 100. However, the embodiment is not limited thereto.

[0179] In one embodiment, the sensor base layer 201 may be disposed directly above the display layer 100. The sensor base layer 201 may be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the sensor base layer 201 may be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The sensor base layer 201 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0180] Each of the first sensor conductive layer 202 and the second sensor conductive layer 204 may have a single-layer structure, or may have a multi-layer structure stacked along the third direction DR3 .

[0181] The single-layer sensor conductive layers 202 and 204 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide, or indium zinc tin oxide. Furthermore, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

[0182] The multi-layered sensor conductive layers 202 and 204 may be a stacked structure of a transparent conductive layer and a metal layer, or a stacked structure of metal layers comprising different metals. The metal layer may have a three-layer structure of titanium / aluminum / titanium, for example. The multi-layered conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0183] The sensor insulating layer 203 may be disposed between the first sensor conductive layer 202 and the second sensor conductive layer 204. The sensor insulating layer 203 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0184] Alternatively, the sensor insulating layer 203 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0185] The sensor cover layer 205 may be disposed above the sensor insulating layer 203 and may cover the second sensor conductive layer 204. The second sensor conductive layer 204 may include a conductive pattern. The sensor cover layer 205 may cover the conductive pattern and reduce or eliminate the possibility of damage to the conductive pattern during subsequent processes. The sensor cover layer 205 may include an inorganic material. For example, the sensor cover layer 205 may include silicon nitride, but is not particularly limited thereto. In one embodiment of the present invention, the sensor cover layer 205 may also be omitted.

[0186] The optical layer 300 may be disposed above the sensor layer 200. The optical layer 300 may be a reflection-reducing layer that reduces the reflectivity of external light incident from the outside. The optical layer 300 may be formed on the sensor layer 200 through a continuous process. For example, the optical layer 300 may include a polarizing film including a phase retarder and / or a polarizer, a multilayer reflective layer that causes destructive interference of reflected light, or a color filter arranged in consideration of the pixel arrangement and sensor arrangement included in the display layer 100. The optical layer 300 may selectively absorb light of a portion of the wavelength band of light reflected from within the display panel and / or electronic device, or light incident from outside the display panel and / or electronic device.

[0187] Reference Figure 6 In one embodiment, the optical layer 300 may include a segmentation layer 310 , a plurality of color filters 320 , and a planarization layer 330 .

[0188] The partition layer 310 can be arranged to overlap the conductive pattern of the second sensor conductive layer 204. The sensor cover layer 205 can be arranged between the partition layer 310 and the second sensor conductive layer 204. The partition layer 310 can prevent external light from being reflected by the second sensor conductive layer 204. The material constituting the partition layer 310 is not particularly limited, as long as it absorbs light. As a black layer, in one embodiment, the partition layer 310 can include a black coloring agent. The black coloring agent can include a black dye or a black pigment. The black coloring agent can include carbon black, a metal such as chromium, or an oxide thereof.

[0189] A plurality of segmentation openings OP-300 may be defined in the segmentation layer 310. The plurality of segmentation openings OP-300 may overlap the light-emitting layer EL and the photoelectric conversion layer LRL, respectively. Color filters 320 may be arranged corresponding to the plurality of segmentation openings OP-300. The color filters 320 may transmit light provided from the light-emitting layer EL overlapping with the color filters 320. Alternatively, the light may be transmitted through the color filters 320 and provided to the photoelectric conversion layer LRL.

[0190] In one embodiment, a single color filter 320 may be disposed over both the light-emitting layer EL and the photoelectric conversion layer LRL. However, the embodiment is not limited thereto. In one embodiment, a color filter of a different color than the color filter disposed over the light-emitting layer EL may be disposed over the photoelectric conversion layer LRL. Alternatively, the color filter 320 may not be disposed over the photoelectric conversion layer LRL.

[0191] For example, Figure 6The light emitting layer EL shown may be a green light emitting layer, and the color filter 320 may be a green color filter. A green color filter, a color filter of a color other than green, or no color filter may be arranged above the photoelectric conversion layer LRL.

[0192] Although not shown, the type of color filter disposed on the light-emitting layer EL may vary depending on the color of the light emitted from the light-emitting layer EL. A red color filter may be disposed on a light-emitting layer that emits red light, and a blue color filter or a transparent color filter may be disposed on a light-emitting layer that emits blue light.

[0193] The planarization layer 330 may cover the segmentation layer 310 and the color filter 320. The planarization layer 330 may include an organic material and may provide a flat surface on the upper surface of the planarization layer 330. In one embodiment, the planarization layer 330 may also be omitted.

[0194] Figure 7 is a plan view illustrating a display panel according to an embodiment. Figure 8 It is a plan view showing a partial area of ​​the display panel in an enlarged manner. Figure 8 Can be magnified Figure 7 Figure 1 shows the AA area of ​​the PDMS.

[0195] The display panel DP may be divided into an active area DA and a peripheral area NDA adjacent to the active area DA. The peripheral area NDA, which is arranged on at least one side of the active area DA, may include a wiring area CLA and a pad area PDA. The wiring area CLA may be arranged on one side of the active area DA, and the pad area PDA may be arranged adjacent to one side of the wiring area CLA.

[0196] Reference Figure 3 and Figure 7 The data lines DL1 to DLm and the sensing lines RL1 to RLh may be arranged in the active area DA and the peripheral area NDA of the display panel DP. The data lines DL1 to DLm may be electrically connected to the plurality of pixels PX in the active area DA and extend to the peripheral area NDA. The sensing lines RL1 to RLh may be electrically connected to the plurality of sensors FX in the active area DA and extend to the peripheral area NDA. In one embodiment, the data lines DL1 to DLm and the sensing lines RL1 to RLh may extend from the active area DA toward the adjacent peripheral area NDA in a first direction DR1.

[0197] That is, in the display panel DP according to an embodiment, the data lines DL1 to DLm may be arranged to be aligned with the light emitting elements ED ( Figure 6 ) are electrically connected and extend from the active area DA to the wiring area CLA. The sensing lines RL1 to RLh may be arranged to be connected to the sensing element OPD ( Figure 6) are electrically connected and extend from the active area DA to the wiring area CLA.

[0198] In a display panel DP according to an embodiment, a portion of the display panel DP may be curved. The display panel DP may include a first non-curved area NBA1, a second non-curved area NBA2 separated from the first non-curved area NBA1 on a first direction DR1, and a curved area BA defined between the first and second non-curved areas NBA1 and NBA2. The first non-curved area NBA1 may include an active area DA and a portion of a peripheral area NDA. The peripheral area NDA may include the curved area BA and the second non-curved area NBA2.

[0199] The bending area BA can be bent along a virtual axis IMX extending in the second direction DR2. When the bending area BA is bent, the second non-bending area NBA2 can face the first non-bending area NBA1. That is, the bending area BA can be bent so that the second non-bending area NBA2 is located below the first non-bending area NBA1 with respect to the third direction DR3. In the display panel DP of one embodiment, the width of the bending area BA in the second direction DR2 can be smaller than the width of the first non-bending area NBA1 in the second direction DR2. The width of the second non-bending area NBA2 in the second direction DR2 can be smaller than the width of the first non-bending area NBA1 in the second direction DR2.

[0200] The driver chip IC may be mounted on the display panel DP and may be connected to the data lines DL1 to DLm and the sensing lines RL1 to RLh, respectively. The driver chip IC may be arranged in the pad area PDA. The driver chip IC may be configured to drive a plurality of pixels PX ( Figure 3 ) and multiple sensor FX ( Figure 3 For example, the driver chip IC may include a data driver 100C2 and a sensor controller 100C6.

[0201] Each of the data lines DL1 to DLm and the sensing lines RL1 to RLh can extend from the first non-bending area NBA1 through the bending area BA to the second non-bending area NBA2. Each of the data lines DL1 to DLm and the sensing lines RL1 to RLh can be electrically connected to a pad portion located adjacent to an end of the second non-bending area NBA2. The pad portion can be located adjacent to an edge DPeg of the display panel DP. The pad portion can include a display pad 100pd connected to each of the data lines DL1 to DLm, a sensor pad 101pd connected to each of the sensing lines RL1 to RLh, and a touch pad 230pd electrically connected to each of the first and second traces 231 and 232.

[0202] A flexible circuit film FCB may be electrically connected to the pad portion. By attaching the flexible circuit film FCB to the pad portion using a conductive adhesive film or the like, the display panel DP may be electrically connected to the flexible circuit film FCB. A touch driver chip T-IC configured to drive the sensor layer 200 may be mounted on the flexible circuit film FCB.

[0203] Reference Figure 7 and Figure 8 The wiring area CLA may include an open area OPA. The wiring area CLA may include a first area NOP1 adjacent to the active area DA, and a second area NOP2 spaced apart from the first area NOP1 in the first direction DR1 with the open area OPA interposed therebetween.

[0204] In one embodiment, the open area OPA may be an area where the organic insulating layer is removed. The open area OPA may be the circuit layer DP_CL ( Figure 6 ) of the insulating layer as the upper insulating layer IL-U ( Figure 11 ) is removed. For example, unlike the adjacent first region NOP1 and the second region NOP2, the sixth insulating layer 60 may not be disposed in the open region OPA ( Figure 6 ) to the eighth insulating layer 80 ( Figure 6 ).

[0205] The first region NOP1 and the second region NOP2 may be referred to as a non-open region NOP. The non-open region NOP may be a portion adjacent to the open region OPA and arranged in the wiring region CLA. For example, a sixth insulating layer 60 ( Figure 6 ) to the eighth insulating layer 80 ( Figure 6 ).

[0206] The open area OPA may be located between the active area DA and the bending area BA. The bending area BA may include a second area NOP2.

[0207] A portion of the sensing lines RL1 to RLh arranged in the peripheral area NDA may overlap with the data lines DL1 to DLm. In one embodiment, a portion of the sensing lines RL1 to RLh may not overlap with the data lines DL1 to DLm in the wiring area CLA.

[0208] Furthermore, in the wiring area CLA, at least a portion of the data lines DL1 to DLm may overlap at least a portion of the sensing lines RL1 to RLh. In one embodiment, the data lines DL1 to DLm and the sensing lines RL1 to RLh may be arranged on different layers.

[0209] In one embodiment, the data lines DL1 to DLm arranged in the wiring area CLA may be connected to the data lines DL1 to DLm arranged in the circuit layer DP_CL ( Figure 6 ) in the transistor or any one of the electrodes constituting the capacitor is arranged on the same layer. For example, the data lines DL1 to DLm may be connected to Figure 6 The third electrode G1 of the first transistor T1 and the upper electrode UE or the third electrode G3 of the third transistor T3 are shown to be arranged on the same layer.

[0210] In addition, in one embodiment, the sensing lines RL1 to RLh arranged in the wiring area CLA may be arranged below the data lines DL1 to DLm in the open area OPA, and may be arranged above the data lines DL1 to DLm in the non-open area NOP. For example, the sensing lines RL1 to RLh may be arranged above the data lines DL1 to DLm in the open area OPA. Figure 6 The first back metal layer BMC1 is arranged on the same layer as shown, and can be connected to the non-open area NOP. Figure 6 The second connection electrode CNE20 is shown to be arranged on the same layer.

[0211] In addition, the display device according to one embodiment may further include a shielding pattern arranged between the data lines DL1 to DLm and the sensing lines RL1 to RLh. In the open area OPA, the shielding pattern may be arranged on the lower side of the data lines DL1 to DLm and may be arranged on the lower side of the inorganic insulating layer or between the inorganic insulating layers. For example, in the open area OPA, the shielding pattern may be arranged on the lower side of the buffer layer BFL. However, the embodiment is not limited thereto, and in the open area OPA, the shielding pattern may be arranged spaced apart from the data lines DL1 to DLm in a third direction DR3, which is a thickness direction, with the inorganic insulating layer arranged on the lower side of the data lines DL1 to DLm placed therebetween.

[0212] In the non-open area NOP, the shield pattern may be arranged below the sensing lines RL1 to RLh. Furthermore, in the non-open area NOP, the shield pattern may be arranged above the inorganic insulating layer. For example, in the open area OPA, the shield pattern may be arranged on the same layer as the first connection electrode CNE10.

[0213] However, the embodiment is not limited thereto, and for the arrangement relationship of the sensing lines RL1 to RLh and the data lines DL1 to DLm in the peripheral area NDA, the arrangement position of the shielding pattern, etc., refer to the following. Figures 9 to 11 etc. for more detailed description.

[0214] Reference Figure 8According to an embodiment, the display panel may further include at least one dam portion DM1, DM2, DM3. The at least one dam portion DM1, DM2, DM3 may be arranged in the peripheral area NDA. In an embodiment, the dam portion DM1, DM2, DM3 may be arranged in the open area OPA.

[0215] The dam portions DM1, DM2, and DM3 may include organic insulating layers 60, 70, and 80 (see Figure 6 The dam portions DM1, DM2, and DM3 may include a material corresponding to the upper insulating layer IL-U ( Figure 9 ) of the organic insulating layers 60, 70, 80 ( Figure 6 ) includes at least one layer of the same substance as at least one layer of the layers.

[0216] The dams DM1, DM2, and DM3 may overlap the sensing lines RL and the data lines DL and may be arranged to extend parallel to the second direction DR2.

[0217] exist Figure 8 3 shows a situation where three dam portions DM1 , DM2 , and DM3 are sequentially arranged in the first direction, but the embodiment is not limited thereto, and dam portions may be further added, or at least one of the illustrated dam portions may be excluded.

[0218] In addition, Figure 8 The figure shows that the dam portions DM1, DM2, and DM3 are formed in a strip form parallel to the second direction DR2, but the embodiment is not limited thereto. At least one of the dam portions DM1, DM2, and DM3 or at least a portion of at least one selected from the dam portions DM1, DM2, and DM3 can be extended along the first direction DR1 in a manner of surrounding the active area DA.

[0219] Figures 9 to 11 Each of them is a cross-sectional view of a portion of a display panel according to an embodiment. Figure 9 Can be shown with Figure 8 The cross-sectional view of the portion corresponding to the I-I' line, Figure 10 Can be shown with Figure 8 The cross-sectional view of the portion corresponding to the II-II' line, Figure 11 Can be shown with Figure 8 The section view of the portion corresponding to line III-III'.

[0220] Figure 9 It shows the non-open area NOP ( Figure 8 ) is a cross-sectional view of the arrangement of the data lines DL and the sensing lines RL, Figure 10 is the open area OPA ( Figure 8) is a cross-sectional view of the arrangement of the data lines DL and the sensing lines RL. In addition, Figure 11 This is a cross-sectional view of a portion of the display panel taken along one sensing line RL extending from the active area DA to the peripheral area NDA.

[0221] Reference Figures 9 to 11 In one embodiment, the sensing line RL arranged in the peripheral area NDA may be arranged on the lower side of the data line DL in the open area OPA, and may be arranged on the upper side of the data line DL in the first area NOP1 and the second area NOP2 of the non-open area NOP. The display device of one embodiment may include the sensing line RL arranged using a conductive pattern arranged in a different layer from the data line DL in the open area OPA from which the upper insulating layer IL-U as the organic insulating layer is removed. By using a conductive pattern arranged in the same layer as each of the conductive patterns arranged in layers different from each other in the circuit layer DP_CL, the data line DL and the sensing line RL may be effectively arranged in the space defined in the second direction DR2 in the open area OPA. That is, even in the open area OPA from which the organic insulating layer is removed, the sensing line RL does not need to use a conductive pattern in the same layer as the data line DL, and accordingly, the space for arranging the sensing line RL may be sufficiently ensured by arranging the sensing line RL regardless of the arrangement position of the data line DL. Therefore, as the arrangement space for the sensing line RL is sufficiently ensured, the number of sensing elements OPD (which can be arranged in the active area DA) may be increased. Figure 6 ) and the number of sensing lines RL, thereby further improving the sensing capability of the display device.

[0222] In one embodiment, at least one shielding pattern SMP-U, SMP-B may be disposed in the peripheral area NDA of the display device. The shielding patterns SMP-U, SMP-B may be disposed between the data lines DL and the sensing lines RL. The shielding patterns SMP-U, SMP-B may be shielding layers that prevent coupling between two adjacent conductive patterns.

[0223] The shielding patterns SMP-U and SMP-B may include a lower shielding pattern SMP-B and an upper shielding pattern SMP-U, wherein the lower shielding pattern SMP-B corresponds to the open area OPA and is arranged on the lower side of the lower insulating layer IL-L or within the lower insulating layer IL-L, and the upper shielding pattern SMP-U corresponds to the first area NOP1 and the second area NOP2 as the non-open area NOP and is arranged on the upper side of the lower insulating layer IL-L or within the upper insulating layer IL-U.

[0224] For example, in one embodiment, the sensing line RL, the lower shielding pattern SMP-B, and the data line DL may be arranged in this order in the third direction DR3 in the open area OPA. Furthermore, the data line DL, the upper shielding pattern SMP-U, and the sensing line RL may be arranged in this order in the first area NOP1 and the second area NOP2 as the non-open area NOP.

[0225] Figure 9 It may be a cross-sectional view showing a portion of the display panel in the first region NOP1. Figure 9 The arrangement of the data lines DL and the sensing lines RL and the layout of the upper shielding patterns SMP-U in FIG. 1 may be similarly applied to the second region NOP2 .

[0226] Reference Figure 9 The display panel may include a lower insulating layer IL-L and an upper insulating layer IL-U sequentially disposed on the base layer BL. The upper insulating layer IL-U may be a layer including an organic material. An encapsulation layer TFE may be disposed on the upper insulating layer IL-U.

[0227] The lower insulating layer IL-L may include a first lower insulating layer IL-L1, a second lower insulating layer IL-L2, and a third lower insulating layer IL-L3 sequentially arranged in the third direction DR3. The upper insulating layer IL-U may include a first upper insulating layer IL-U1, a second upper insulating layer IL-U2, and a third upper insulating layer IL-U3 sequentially arranged in the third direction DR3. Figure 9 The figure exemplarily illustrates a case where the lower insulating layer IL-L and the upper insulating layer IL-U each have a three-layer structure, but is not limited thereto. The lower insulating layer IL-L and the upper insulating layer IL-U may each have a two-layer structure, or may have a structure with four or more layers.

[0228] Each of the first lower insulating layer IL-L1, the second lower insulating layer IL-L2, and the third lower insulating layer IL-L3 included in the lower insulating layer IL-L may include an inorganic material. For example, each of the first lower insulating layer IL-L1, the second lower insulating layer IL-L2, and the third lower insulating layer IL-L3 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0229] Each of the first, second, and third upper insulating layers IL-U1, IL-U2, and IL-U3 included in the upper insulating layer IL-U may include an organic material. For example, each of the first, second, and third upper insulating layers IL-U1, IL-U2, and IL-U3 may include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0230] in addition, Figure 9 The lower insulating layer IL-L and the upper insulating layer IL-U shown may correspond to Figure 6 At least one of the first insulating layer 10 to the eighth insulating layer 80 described above. For example, in one embodiment, the first lower insulating layer IL-L1 may be Figure 6 The second lower insulating layer IL-L2 may be a layer corresponding to the first insulating layer 10. Figure 6 The third lower insulating layer IL-L3 may be a layer corresponding to the second insulating layer 20. Figure 6 The first upper insulating layer IL-U1 may be a layer corresponding to the third insulating layer 30 to the fifth insulating layer 50. Figure 6 The second upper insulating layer IL-U2 may be a layer corresponding to the sixth insulating layer 60. Figure 6 The third upper insulating layer IL-U3 may be a layer corresponding to the seventh insulating layer 70. Figure 6 The eighth insulating layer 80 corresponds to a layer. However, the embodiment is not limited thereto.

[0231] In one embodiment, the data line DL may be disposed on the lower insulating layer IL-L. For example, the data line DL may be disposed on the upper portion of the first lower insulating layer IL-L1 or the upper portion of the second lower insulating layer IL-L2. The data line DL may include a first layer data line DL-1 disposed on the first lower insulating layer IL-L1 and a second layer data line DL-2 disposed on the second lower insulating layer IL-L2. Either the first layer data line DL-1 or the second layer data line DL-2 may be omitted.

[0232] That is, the first layer data line DL-1 may be arranged on the first insulating layer 10 ( Figure 6), the second layer data line DL-2 may be arranged on the second insulating layer 20 ( Figure 6 ). The first-layer data line DL-1 can be arranged on the same layer as the third electrode G1 of the first transistor T1, and the second-layer data line DL-2 can be arranged on the same layer as the upper electrode UE. The first-layer data line DL-1 can be formed in the same process step as the third electrode G1 of the first transistor T1, and the second-layer data line DL-2 can be formed in the same process step as the upper electrode UE. However, the embodiment is not limited thereto.

[0233] Reference Figure 9 In the non-open region NOP, the sensing line RL may be arranged on the upper side of the lower insulating layer IL-L. The sensing line RL may be arranged on the first upper insulating layer IL-U1. That is, the sensing line RL may be arranged on the sixth insulating layer 60 ( Figure 6 ). The sensing line RL may be arranged on the same layer as the second connection electrode CNE20. The sensing line RL may be formed in the same process step as the second connection electrode CNE20. However, the embodiment is not limited thereto.

[0234] The upper shielding pattern SMP-U may be disposed between the data line DL and the sensing line RL in the third direction DR3. Figure 9 In one embodiment shown, the upper shield pattern SMP-U may be disposed on the lower insulating layer IL-L. The upper shield pattern SMP-U may be disposed on the third lower insulating layer IL-L3. In one embodiment, the upper shield pattern SMP-U may be disposed on the fifth insulating layer 50 ( Figure 6 The upper shielding pattern SMP-U may be arranged on the same layer as the first connection electrode CNE10. The upper shielding pattern SMP-U may be formed in the same process step as the first connection electrode CNE10, but the embodiment is not limited thereto.

[0235] In addition, the arrangement position of the upper shielding pattern SMP-U is not limited to the position shown in the figure, and may include the lower insulating layer IL-L or the upper insulating layer IL-U between the data line DL and the sensing line RL. The upper shielding pattern SMP-U may be arranged on the organic insulating layers 60, 70, 80 ( Figure 6 ) or the lower side of the organic insulating layer 60, 70, 80 ( Figure 6 ) in the inorganic insulating layers 10, 20, 30, 40, 50 ( Figure 6 ) Adjacent organic insulating layers 60 are arranged on the same layer.

[0236] In addition, Figure 9The figure illustrates a case where one insulating layer IL-L3 and one insulating layer IL-U1 are disposed between the data line DL and the upper shield pattern SMP-U, and between the sensing line RL and the upper shield pattern SMP-U, respectively. However, embodiments are not limited thereto. At least one insulating layer may be additionally disposed between at least one of the two locations: the data line DL and the upper shield pattern SMP-U, or the sensing line RL and the upper shield pattern SMP-U. The addition of the insulating layer further reduces coupling between the sensing line RL and the data line DL, thereby improving noise.

[0237] Figure 10 It can be a cross-sectional view showing a portion of a display panel in an open area OPA. Figure 10 is with Figure 8 The cross-sectional view of the portion corresponding to the II-II' line shows the arrangement of the data line DL and the sensing line RL at the portion overlapping with the dam portion DM3. Figure 10 The arrangement of the data lines DL and the sensing lines RL shown in the figure, except for the arrangement of the dam portion DM3 , can be similarly applied to other regions where the dam portions DM1 , DM2 , and DM3 are not arranged.

[0238] Reference Figure 10 , the display panel may include a lower insulating layer IL-L arranged on the base layer BL in the open area OPA. The upper insulating layer IL-U ( Figure 9 ). Encapsulation layer TFE ( Figure 9 ) can be arranged on the lower insulating layer IL-L. Figure 10 , the encapsulation layer TFE ( Figure 9 ) in the area of ​​the encapsulation inorganic layers TIL1 and TIL2, in addition to the encapsulation inorganic layers TIL1 and TIL2, an encapsulation organic layer TOL ( Figure 11 ).

[0239] Reference Figure 10 , the lower insulating layer IL-L may include a first lower insulating layer IL-L1, a second lower insulating layer IL-L2, and a third lower insulating layer IL-L3 sequentially arranged in the third direction DR3. Figure 10 The lower insulating layer IL-L is exemplarily shown as having a three-layer structure, but is not limited thereto. The lower insulating layer IL-L may also have a two-layer structure or a structure with more than four layers. Figure 9 The same contents as described in etc.

[0240] The third dam DM3 may include a plurality of layers stacked sequentially. The third dam DM3 may have a thickness greater than that of the first upper insulating layer IL-U1 ( Figure 9 ) and the second upper insulating layer IL-U2 ( Figure 9 ) corresponding to the first upper insulating layer IL-U1 and the second upper insulating layer IL-U2. In one embodiment, the third dam portion DM3 may have a three-layer structure including layers corresponding to the first upper insulating layer IL-U1 and the second upper insulating layer IL-U2, respectively, and an additional layer located above. The third dam portion DM3 may include a bottom portion DM3-B, a middle portion DM3-M, and an upper portion DM3-T. The bottom portion DM3-B may be made of the same material as the first upper insulating layer IL-U1 and formed using the same process. The middle portion DM3-M may be made of the same material as the second upper insulating layer IL-U2 and formed using the same process. Furthermore, the upper portion DM3-T may be made of a different material than the upper insulating layer IL-U.

[0241] exist Figure 10 In the open area OPA shown, the data line DL can be arranged on the lower insulating layer IL-L. For example, the data line DL can be arranged on the upper part of the first lower insulating layer IL-L1 or the upper part of the second lower insulating layer IL-L2. The data line DL may include a first layer data line DL-1 arranged on the first lower insulating layer IL-L1 and a second layer data line DL-2 arranged on the second lower insulating layer IL-L2. Any one of the first layer data line DL-1 and the second layer data line DL-2 may be omitted. In the open area OPA, the data line DL may be arranged with reference to FIG. Figure 9 The data lines DL in the non-open area NOP are arranged in the same layer. That is, the first layer data line DL-1 can be arranged in the first insulating layer 10 ( Figure 6 ), the second layer data line DL-2 may be arranged on the second insulating layer 20 ( Figure 6 The first layer data line DL-1 may be arranged on the same layer as the third electrode G1 of the first transistor T1, and the second layer data line DL-2 may be arranged on the same layer as the upper electrode UE.

[0242] exist Figure 10 In the open area OPA shown, the sensing line RL can be arranged under the lower insulating layer IL-L. In one embodiment, the sensing line RL can be arranged under the buffer layer BFL. For example, the sensing line RL can be arranged on the first barrier layer BR1. The sensing line RL can be arranged on the same layer as the first back metal layer BMC1. The sensing line RL can be formed in the same process step as the first back metal layer BMC1, but the embodiment is not limited thereto.

[0243] In the open area OPA, the lower shield pattern SMP-B may be arranged on the upper side of the sensing line RL. The lower shield pattern SMP-B may be arranged between the sensing line RL and the data line DL in the third direction DR3. The lower shield pattern SMP-B may be arranged on the inorganic insulating layers 10, 20, 30, 40, 50 ( Figure 6 ) or the lower side of the inorganic insulating layer 10, 20, 30, 40, 50 ( Figure 6 )between.

[0244] exist Figure 10 In one embodiment shown, the lower shield pattern SMP-B may be disposed on the second barrier layer BR2. The lower shield pattern SMP-B may be disposed on the lower side of the lower insulating layer IL-L. In one embodiment, the lower shield pattern SMP-B may be covered by the buffer layer BFL. That is, the lower shield pattern SMP-B may be disposed on the inorganic insulating layers 10, 20, 30, 40, 50 ( Figure 6 ) on the lower side.

[0245] In addition, the arrangement position of the lower shielding pattern SMP-B is not limited to the illustrated position, and may include the lower insulating layer IL-L between the sensing line RL and the data line DL, or may be arranged between other inorganic layers on the lower side of the lower insulating layer IL-L.

[0246] In addition, with Figure 10 Unlike the illustrated embodiment, at least one additional insulating layer may be disposed between the sensing line RL and the data line DL in addition to the illustrated insulating layer or inorganic layer. The addition of the insulating layer further reduces coupling between the sensing line RL and the data line DL, thereby improving noise.

[0247] Figure 11 It shows that according to Figure 8 A cross-sectional view of a portion of the display panel taken along line III-III'. Figure 11 FIG is a cross-sectional view along the extending direction of one sensing line RL.

[0248] Reference Figure 8 and Figure 11 , the sensing line RL may extend from the active area DA to the peripheral area NDA. Furthermore, within the peripheral area NDA, the sensing line RL may extend from the first non-bending area NBA1 to the bending area BA. The peripheral area NDA, adjacent to one side of the active area DA, may include an open area OPA, a first area NOP1 disposed between the active area DA and the open area OPA, and a second area NOP2 spaced apart from the first area NOP1 with the open area OPA interposed therebetween. The first area NOP1 and the second area NOP2 may be referred to as non-open areas NOP. The open area OPA may be located in the first non-bending area NBA1.

[0249] Reference Figure 11 In one embodiment, the sensing line RL may be located on different layers in the non-open area NOP and the open area OPA. In addition, in one embodiment, the data line DL may be located on the same layer in the non-open area NOP and the open area OPA.

[0250] The sensing line RL can be arranged on one of the organic insulating layers included in the upper insulating layer IL-U in the first and second regions NOP1 and NOP2. Furthermore, the sensing line RL can be arranged on one of the inorganic layers below the lower insulating layer IL-L in the open region OPA. That is, in the open region OPA where the upper insulating layer IL-U has been removed, the sensing line cannot be formed using a conductive pattern arranged on the organic insulating layer, as in the first or second regions NOP1 and NOP2. Therefore, in the open region OPA, the sensing line RL needs to be formed using a conductive pattern included between the lower insulating layers IL-L or a conductive pattern arranged below the lower insulating layer IL-L. However, if a conductive pattern on the same layer as the data line DL is used as the conductive pattern between the lower insulating layers IL-L in the open region OPA, the sensing line RL needs to be arranged in the remaining area excluding the fan-out area of ​​the data line DL, resulting in an excessively limited arrangement area for the sensing line RL.

[0251] However, in the display device of one embodiment, the first back metal layer BMC1 ( Figure 6 ) conductive pattern to form the sensing lines RL, thereby expanding the area in which the sensing lines RL can be arranged. Consequently, even in the open area OPA, the sensing lines RL can be effectively arranged without interference from the data lines DL, thereby enabling the inclusion of a sufficient number of sensing lines RL. Therefore, in a display device according to one embodiment, the sensing lines RL and the like can be arranged without being restricted by the arrangement of the data lines DL, without increasing dead zones, thereby achieving improved sensing capabilities.

[0252] Reference Figure 8 and Figure 11At least one dam portion DM1, DM2, or DM3 may be arranged in the open area OPA. The first dam portion DM1, the second dam portion DM2, and the third dam portion DM3 may be arranged sequentially in a direction away from the active area DA. That is, compared to the first dam portion DM1, the second dam portion DM2 may be arranged separately from the active area DA, and the first dam portion DM1 may be arranged between the area where the second dam portion DM2 is arranged and the active area DA. Compared to the second dam portion DM2, the third dam portion DM3 may be arranged separately from the active area DA, and the second dam portion DM2 may be arranged between the first dam portion DM1 and the third dam portion DM3.

[0253] Each of the dam portions DM1, DM2, and DM3 may include multiple layers. In one embodiment, the dam portions DM1, DM2, and DM3 may include a double-layer structure or a triple-layer structure. Each of the first dam portion DM1 and the second dam portion DM2 may include a bottom portion DM1-B, DM2-B and an upper portion DM1-T, DM2-T. Figure 10 As described above, the third dam portion DM3 may include a bottom portion DM3 -B, a middle portion DM3 -M, and an upper portion DM3 -T.

[0254] The first dam DM1 and the second dam DM2 may have substantially the same height. Each of the first dam DM1 and the second dam DM2 may have a layer corresponding to at least one of the aforementioned upper insulating layers IL-U. Each of the first dam DM1 and the second dam DM2 may have a layer corresponding to the sixth insulating layer 60 (or the first upper insulating layer) and the seventh insulating layer 70 (or the second upper insulating layer). In one embodiment, each of the first dam DM1 and the second dam DM2 may have a layer including a first upper insulating layer IL-U1 ( Figure 9 ) and the second upper insulating layer IL-U2 ( Figure 9 The bottom DM1-B and DM2-B may include a first upper insulating layer IL-U1 ( Figure 9 ) and may be a layer formed by the same process. The upper layer portions DM1-T, DM2-T may include the second upper insulating layer IL-U2 ( Figure 9 ) are of the same substance and may be layers formed by the same process.

[0255] The third dam portion DM3 may have a height higher than that of each of the first dam portion DM1 and the second dam portion DM2. Figure 10 The description contains the same content.

[0256] In addition, predetermined spacing may be defined between the plurality of dams DM1, DM2, and DM3. A valley structure may be formed between and adjacent to the plurality of dams DM1, DM2, and DM3. The dams DM1, DM2, and DM3 are arranged in the peripheral area NDA of the display panel DP, and the valley structure defined between and adjacent to the dams DM1, DM2, and DM3 prevents overflow of the encapsulation organic layer TOL included in the encapsulation layer TFE.

[0257] Reference Figure 11 , an encapsulation layer TFE may be disposed in the first region NOP1 and the open region OPA. A portion of the encapsulation layer TFE may be disposed in the open region OPA. As described above, the encapsulation layer TFE may cover the light emitting element ED ( Figure 6 ) and sensing element OPD ( Figure 6 ), and may include two encapsulation inorganic layers TIL1, TIL2 and an encapsulation organic layer TOL arranged therebetween.

[0258] A sensor layer 200 ( Figure 6 ) includes a first sensor conductive layer 202. The first sensor conductive layer 202 may correspond to at least one of the aforementioned first trace 231 and the second trace 232. Figure 11 Although omitted in the figure, a sensor base layer may also be arranged between the packaging layer TFE and the first sensor conductive layer 202 .

[0259] Reference Figure 11 , the sensing line RL may include a non-open area NOP ( Figure 8 ) and the second sensing wiring portion RL-OP arranged in the open area OPA. The first sensing wiring portion RL-NP1 and the third sensing wiring portion RL-NP2 can be referred to as the upper sensing wiring portion RL-NP1, RL-NP2, and the second sensing wiring portion RL-OP can be referred to as the lower sensing wiring portion RL-OP. The upper sensing wiring portions RL-NP1, RL-NP2 can be arranged in the non-open area NOP ( Figure 8 ), the lower sensing wiring portion RL-OP may be arranged in the open area OPA.

[0260] The first sensing wiring portion RL-NP1 may be arranged in the first region NOP1, and the third sensing wiring portion RL-NP2 may be arranged in the second region NOP2. The sensing line RL may include a connection wiring portion RL-CL connecting the first sensing wiring portion RL-NP1 and the second sensing wiring portion RL-OP, and the third sensing wiring portion RL-NP2 and the second sensing wiring portion RL-OP, respectively. The connection wiring portion RL-CL may pass through the circuit layer DP_CL ( Figure 6 ) is formed as a part of the . The connection wiring portion RL-CL can be arranged in the non-open area NOP ( Figure 8 ), that is, in the first area NOP1 and the second area NOP2.

[0261] The connection wiring portion RL-CL may include: a first connection portion RL-C1, which passes through the lower insulating layer IL-L and is partially arranged on the lower insulating layer IL-L; and a second connection portion RL-C2, which is arranged on the first connection portion RL-C1 and is arranged to pass through a portion of the upper insulating layer IL-U.

[0262] Reference Figure 11 The first connection portion RL-C1 may be disposed within a contact hole formed through the inorganic insulating layers 10, 20, 30, 40, 50, the buffer layer BFL, and the second barrier layer BR2. Furthermore, a portion of the first connection portion RL-C1 connected to the second connection portion RL-C2 may be disposed on the fifth insulating layer 50. For example, in one embodiment, a portion of the first connection portion RL-C1 may be located on the same layer as the upper shield pattern SMP-U.

[0263] That is, a sensing line RL can extend from the active area DA to the peripheral area NDA while connecting conductive patterns located in different layers in the open area OPA and the non-open area NOP. In one embodiment, the sensing line RL may include: a first sensing wiring portion RL-NP1 formed of a conductive pattern arranged between organic insulating layers; a connecting wiring portion RL-CL connected to the first sensing wiring portion RL-NP1 and penetrating the insulating layer; a second sensing wiring portion RL-OP connected to the first sensing wiring portion RL-NP1 via the connecting wiring portion RL-CL and formed of a conductive pattern arranged under the lower insulating layer IL-L; a connecting wiring portion RL-CL connected to the second sensing wiring portion RL-OP and penetrating the insulating layer; and a third sensing wiring portion RL-NP2 connected to the second sensing wiring portion RL-OP via the connecting wiring portion RL-CL and formed of a conductive pattern arranged between the organic insulating layers.

[0264] In addition, in one embodiment, the sensing line RL may be formed in at least a portion of the first non-bending area NBA1 before the bending area BA begins by connecting to the first back metal layer BMC1 ( Figure 6 ) is formed by a conductive pattern of the same layer. In particular, in the open area OPA defined between the bending area BA and the active area DA, the sensing line RL utilizes the conductive pattern of the first back metal layer BMC1 ( Figure 6 ) The conductive pattern of the same layer is formed, thereby minimizing the dead space between the bending area BA and the active area DA while increasing the degree of freedom of arrangement of the sensing lines RL.

[0265] In one embodiment of a display device, sensing lines electrically connected to sensing elements are formed in an open area in the peripheral region where the organic insulating layer has been removed, using a conductive pattern located below a data line electrically connected to a light-emitting element. This allows for the arrangement of sensing lines without being restricted by the arrangement of data lines, thereby achieving excellent sensing capabilities. Furthermore, in the open area, sensing lines can be formed to overlap with data lines, thereby reducing dead zones and increasing the active area.

[0266] The above description is made with reference to the preferred embodiments of the present invention. However, any person skilled in the art or having ordinary knowledge in the art to which the present invention belongs will understand that various modifications and changes can be made to the present invention without departing from the scope of the concept and technical field of the present invention as described in the claims.

[0267] Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, divided into an active area, a wiring area arranged on at least one side of the active area, and a pad area adjacent to the wiring area, comprising: base layer; a circuit layer comprising a buffer layer disposed on the base layer, a plurality of inorganic insulating layers disposed on the buffer layer, a plurality of organic insulating layers disposed on the inorganic insulating layer, and a plurality of conductive patterns; an element layer, arranged on the circuit layer and comprising a light-emitting element and a sensing element arranged in the effective area; a data line electrically connected to the light emitting element and extending from the active area to the wiring area; as well as a sensing line electrically connected to the sensing element and extending from the active area to the wiring area; The wiring area includes: a first area adjacent to the active area; a second area adjacent to the pad area; and an open area arranged between the first area and the second area, and the organic insulating layer is removed. Wherein, in the first area and the second area, the sensing line is arranged on the upper side of the data line, In the open area, the sensing line is arranged at a lower side of the data line.

2. The display device according to claim 1, wherein The sensing line includes: a first sensing wiring portion arranged on an upper side of the inorganic insulating layer in the first region; a second sensing wiring portion, arranged on a lower side of the inorganic insulating layer in the open region; a third sensing wiring portion arranged on an upper side of the inorganic insulating layer in the second region; and The connecting wiring portion connects the first sensing wiring portion and the second sensing wiring portion, and connects the second sensing wiring portion and the third sensing wiring portion.

3. The display device according to claim 2, wherein: The first sensing wiring portion and the third sensing wiring portion are respectively arranged on the same layer between the organic insulating layers. The second sensing wiring portion is arranged on a lower side of the buffer layer.

4. The display device according to claim 2, wherein: The circuit layer further includes: The lower shield pattern overlaps with the second sensing wiring portion in the open area and is disposed between the second sensing wiring portion and the data line.

5. The display device according to claim 4, wherein: The lower shield pattern is disposed on a lower side of the inorganic insulating layer or between the inorganic insulating layers.

6. The display device according to claim 2, wherein: The circuit layer further includes an upper shielding pattern arranged between the sensing line and the data line in the first region and the second region.

7. The display device according to claim 6, wherein: The upper shield pattern is disposed on a lower side of the organic insulating layer, or is disposed on the same layer as an organic insulating layer adjacent to the inorganic insulating layer among the organic insulating layers.

8. The display device according to claim 2, wherein: The connection wiring portion includes a first connection portion arranged to pass through at least one of the organic insulating layers; and a second connection portion arranged to pass through the inorganic insulating layer.

9. The display device according to claim 2, wherein: The data lines are arranged between the inorganic insulating layers.

10. The display device according to claim 1, wherein In the active area, the conductive pattern includes a transistor, a capacitor, a back metal layer overlapping the transistor on the lower side of the transistor, and a plurality of connection electrodes electrically connected to the light emitting element or the sensing element and arranged between the organic insulating layers. Wherein, the conductive pattern in the wiring area includes the data line and the sensing line.

11. The display device according to claim 10, wherein: In the wiring region, the data line is arranged on the same layer as any one of the electrodes constituting the transistor or any one of the electrodes constituting the capacitor.

12. The display device according to claim 11, wherein In the wiring area, the data line includes: a first layer of data lines, arranged on the same first inorganic insulating layer in the first region, the open region, and the second region; and The second layer of data lines is arranged on the same second inorganic insulating layer in the first area, the open area and the second area, and the second inorganic insulating layer is arranged on the first inorganic insulating layer.

13. The display device according to claim 10, wherein: In the open area, the sensing line and the back metal layer are arranged on the same layer.

14. The display device according to claim 10, wherein: In the first region and the second region, the sensing line and any one of the connecting electrodes are arranged on the same layer.

15. The display device according to claim 1, further comprising: at least one dam portion arranged on the inorganic insulating layer in the open region, The at least one dam portion overlaps with the sensing line.

16. The display device according to claim 15, wherein The at least one dam portion is arranged to extend along a second direction perpendicular to a first direction extending from the active area to the wiring area.

17. The display device according to claim 1, further comprising: The sensor layer is arranged on the element layer and includes a sensor conductive layer and a sensor insulating layer.

18. The display device according to claim 1, wherein: The wiring area includes: a first non-bending area adjacent to the effective area; a bending area bent with a virtual axis extending in one direction as a reference; and a second non-bending area separated from the first non-bending area and with the bending area positioned therebetween. The open area is included in the first non-bending area.

19. The display device according to claim 18, wherein: A width of the second non-bending region in the one direction is smaller than a width of the first non-bending region in the one direction.

20. A display device, divided into an active area and a peripheral area adjacent to the active area, comprising: base layer; a circuit layer comprising a lower insulating layer disposed on the base layer, an upper insulating layer disposed on the lower insulating layer and comprising an organic matter, and a conductive pattern; A display layer is arranged on the circuit layer, comprising a pixel definition film having an opening, and light-emitting elements and sensing elements respectively arranged in the opening; a data line electrically connected to the light emitting element and extending from the active area to the peripheral area; a sensing line electrically connected to the sensing element and extending from the active area to the peripheral area; as well as at least one shielding pattern arranged between the data line and the sensing line in the peripheral area, The peripheral area includes: an open area, where the upper insulating layer is removed; and a non-open area, which is adjacent to the open area and where the upper insulating layer is not removed. In the non-open area, the sensing line is arranged above the data line, and in the open area, the sensing line is arranged below the data line.

21. The display device according to claim 20, wherein: The sensing line includes: an upper sensing wiring portion arranged on an upper side of the lower insulating layer in the non-open region; and A lower sensing wiring portion is arranged on a lower side of the lower insulating layer in the open region.

22. The display device according to claim 21, wherein The conductive pattern includes a transistor, a capacitor, a back metal layer overlapping the transistor on the lower side of the transistor, and a plurality of connection electrodes electrically connected to the light emitting element or the sensing element and arranged on the upper insulating layer. In the peripheral region, the data line is arranged on the same layer as any one of the electrodes constituting the transistor or any one of the electrodes constituting the capacitor.

23. The display device according to claim 22, wherein: In the open area, the sensing line and the back metal layer are arranged on the same layer.

24. The display device according to claim 22, wherein: In the non-open area, the sensing line and any one of the connection electrodes are arranged on the same layer.

25. The display device according to claim 22, wherein The at least one shielding pattern comprises: a lower shield pattern arranged on a lower side of the upper sensing wiring portion in the non-open region; and An upper shield pattern is arranged on an upper side of the lower sensing wiring portion in the open region.

26. The display device according to claim 20, wherein The opening includes a first opening and a second opening that do not overlap each other on a plane, The light emitting element is arranged on the upper insulating layer and includes a first light emitting portion electrode whose upper portion is exposed from the first opening and a light emitting layer arranged in the first opening. The sensing element is disposed on the upper insulating layer and includes a first sensing electrode whose upper portion is exposed from the second opening and a photoelectric conversion layer disposed in the second opening.

27. A display device comprising: an active area and a peripheral area, wherein the peripheral area is arranged on one side of the active area and includes a curved area that is curved with respect to a virtual axis extending in one direction and is separated from the active area. Furthermore, the display device includes: base layer; a circuit layer comprising a plurality of inorganic insulating layers arranged on the base layer, a plurality of organic insulating layers arranged on the inorganic insulating layers, transistors, capacitors, a back metal layer overlapping the transistors on the lower side of the transistors, and a plurality of connection electrodes arranged on the organic insulating layers; an element layer, arranged on the circuit layer and comprising a light emitting element and a sensing element arranged in the active area; a data line electrically connected to the light emitting element and extending from the active area to the bending area; and a sensing line electrically connected to the sensing element and extending from the active area to the bending area; The peripheral area includes an open area defined between the bending area and the active area and where the organic insulating layer is removed. In the open area, the sensing line is arranged on the same layer as the back metal layer on the lower side of the data line. Between the active area and the open area, the sensing line is arranged on the same layer as one of the plurality of connecting electrodes on an upper side of the data line.

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