Display device, mother substrate, and method for manufacturing display device

Abstract

The invention relates to a display device, a mother substrate, and a manufacturing method of the display device. According to one embodiment, a display device includes: a substrate; an inorganic insulating layer disposed over the substrate over a display region in which an image is displayed and a peripheral region outside the display region; a display element disposed in the display region; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls disposed in the peripheral region; and a second sealing layer formed of an inorganic insulating material and disposed across the display region and the peripheral region, in which each of the plurality of peripheral partition walls has a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-041112 filed on March 15, 2024, and incorporates by reference all the contents described in that Japanese patent application. Technical Field

[0003] Embodiments of the present invention relate to a display device, a mother substrate, and a method for manufacturing the display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display elements include a pixel circuit containing a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer and functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the Invention

[0006] An object of the embodiments is to provide a display device, a mother substrate, and a method for manufacturing a display device that can suppress a decrease in reliability.

[0007] According to one embodiment, a display device includes: a substrate; an inorganic insulating layer, which is arranged above the above-mentioned substrate and covers a display area for displaying an image and a peripheral area outside the above-mentioned display area; a display element, which is arranged in the above-mentioned display area; a first sealing layer, which is formed of an inorganic insulating material and covers the above-mentioned display element; a plurality of peripheral partitions arranged in the above-mentioned peripheral area; and a second sealing layer, which is formed of an inorganic insulating material and is arranged over the above-mentioned display area and the above-mentioned peripheral area, each of the plurality of peripheral partitions having a first lower portion arranged on the above-mentioned inorganic insulating layer and a first upper portion arranged on the above-mentioned first lower portion, and covered by the above-mentioned second sealing layer.

[0008] According to one embodiment, the mother substrate comprises: a panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an inorganic insulating layer arranged throughout the panel portion and the blank portion; a display element arranged in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions arranged in the blank portion; and a second sealing layer formed of an inorganic insulating material and arranged throughout the panel portion and the blank portion, each of the plurality of peripheral partitions having a first lower portion arranged on the inorganic insulating layer and a first upper portion arranged on the first lower portion, and being covered by the second sealing layer.

[0009] According to one embodiment, in a method for manufacturing a display device, a processing substrate is prepared, wherein the processing substrate has an inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area, a display element located in the display area, a plurality of peripheral partitions located in the peripheral area, and a first sealing layer covering the display element and exposing the peripheral partitions, a second sealing layer extending over the display area and the peripheral area is formed of an inorganic insulating material, and each of the plurality of peripheral partitions has a first lower portion arranged on the inorganic insulating layer and a first upper portion arranged on the first lower portion, and is covered by the second sealing layer.

[0010] According to the embodiments, a display device, a mother substrate, and a method for manufacturing a display device capable of suppressing a decrease in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0012] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0013] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0014] Figure 4 1 is a plan view showing an example of the motherboard 100 .

[0015] Figure 5 Yes Figure 4 A plan view of one configuration example of the region 100A and the region 100B is shown.

[0016] Figure 6 It is along Figure 5 A cross-sectional view of the peripheral partition wall 7 along the CD line in FIG.

[0017] Figure 7 Yes Figure 4 A plan view of another configuration example of the region 100A and the region 100B is shown.

[0018] Figure 8 It is along Figure 7 A cross-sectional view of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line EF in FIG.

[0019] Figure 9 Yes Figure 4 A plan view of another configuration example of the region 100A and the region 100B is shown.

[0020] Figure 10 It is a diagram for explaining a method of manufacturing the display device DSP.

[0021] Figure 11 It is a diagram for explaining a method of manufacturing the display device DSP.

[0022] Figure 12 It is a diagram for explaining a method of manufacturing the display device DSP.

[0023] Figure 13 It is a diagram for explaining a method of manufacturing the display device DSP.

[0024] Figure 14 It is a diagram for explaining a method of manufacturing the display device DSP.

[0025] Figure 15 It is a diagram for explaining a method of manufacturing the display device DSP.

[0026] Figure 16 It is a diagram for explaining a method of manufacturing the display device DSP.

[0027] Figure 17 It is a diagram for explaining a method of manufacturing the display device DSP.

[0028] Figure 18 It is a diagram for explaining a method of manufacturing the display device DSP.

[0029] Figure 19 It is a diagram for explaining a method of manufacturing the display device DSP.

[0030] Figure 20 It is a diagram for explaining a method of manufacturing the display device DSP.

[0031] Figure 21 It is a diagram for explaining a method of manufacturing the display device DSP.

[0032] Figure 22 It is a diagram for explaining a method of manufacturing the display device DSP.

[0033] Figure 23 It is a diagram for explaining a method of manufacturing the display device DSP.

[0034] Figure 24 It is a diagram for explaining a method of manufacturing the display device DSP.

[0035] Figure 25 It is a diagram for explaining a method of manufacturing the display device DSP. DETAILED DESCRIPTION

[0036] The embodiments will be described with reference to the drawings.

[0037] The disclosure is merely an example, and appropriate modifications that maintain the spirit of the invention and that can be readily conceived by those skilled in the art are naturally within the scope of the present invention. Furthermore, to clarify the description, the drawings may sometimes schematically illustrate the width, thickness, shape, etc. of various components, as compared to actual embodiments. However, these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and the drawings, components that perform the same or similar functions as components previously described in connection with an existing drawing are denoted by the same reference numerals, and repeated detailed descriptions may be omitted as appropriate.

[0038] It should be noted that in the drawings, as necessary, mutually orthogonal X-axis, Y-axis, and Z-axis are depicted for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Observing various elements parallel to the third direction Z is referred to as a top view.

[0039] The display device of this embodiment is an organic electroluminescent display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0040] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0041] The display device DSP includes a display panel PNL on an insulating substrate 10. The display panel PNL includes a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0042] In this embodiment, the shape of the substrate 10 in a plan view is a rectangle. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0043] The display area DA includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP. In one example, a pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first, second, and third colors are different colors. It should be noted that the pixel PX may also include a sub-pixel SP of another color, such as white, in addition to or in place of the sub-pixels SP1, SP2, and SP3.

[0044] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0045] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0046] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0047] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0048] The peripheral area SA includes a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each terminal TE extends in a second direction Y, but the present invention is not limited thereto. Such a plurality of terminals TE can be electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0049] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0050] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0051] When the sub-pixels SP1, SP2, and SP3 are arranged in this manner, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0052] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in sequence in the first direction X.

[0053] In the display area DA, an inorganic insulating layer 5 and partition walls 6 are provided. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0054] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 similarly to the inorganic insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of terminals TE shown, terminals TE of common potential are electrically connected.

[0055] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 as display elements DE, respectively.

[0056] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the opening AP1. The periphery of the lower electrode LE1 is covered by an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 that constitute the display element DE1 are surrounded by a partition wall 6 when viewed from above. The periphery of each of the organic layer OR1 and the upper electrode UE1 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR1 includes a light-emitting layer that emits light in the blue wavelength region, for example.

[0057] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The periphery of the lower electrode LE2 is covered by an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 that constitute the display element DE2 are surrounded by a partition wall 6 when viewed from above. The periphery of the organic layer OR2 and the upper electrode UE2 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR2 includes a light-emitting layer that emits light in the green wavelength region, for example.

[0058] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The periphery of the lower electrode LE3 is covered by an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 that constitute the display element DE3 are surrounded by a partition wall 6 when viewed from above. The periphery of each of the organic layer OR3 and the upper electrode UE3 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength region, for example.

[0059] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. It should be noted that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the illustrations do not necessarily reflect their exact shapes.

[0060] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element and are in contact with the barrier ribs 6 .

[0061] The lower electrode LE1 and the pixel circuit 1 of the sub-pixel SP1 (refer to Figure 1 The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0062] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different. The area of ​​opening AP1 is larger than that of opening AP2, and the area of ​​opening AP2 is larger than that of opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0063] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0064] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an insulating layer 12 , which is an organic insulating layer that flattens the unevenness of the circuit layer 11 , and includes various circuits such as the pixel circuit 1 and various wirings such as the scanning lines GL, the signal lines SL, and the power supply lines PL.

[0065] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 Omitted in .

[0066] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0067] In the illustrated example, the lower portion 61 includes a base layer 63 disposed on the inorganic insulating layer 5 and an axial layer 64 disposed between the base layer 63 and the upper portion 62. The base layer 63 is thinner than the axial layer 64. The base layer 63 has a greater width than the axial layer 64. Both ends of the base layer 63 protrude from the side surfaces of the axial layer 64.

[0068] The upper portion 62 has a thin film 65 arranged on the shaft layer 64 and a thin film 66 arranged on the thin film 65. The upper portion 62 has a width greater than that of the shaft layer 64. Both ends of the upper portion 62 protrude from the side surfaces of the shaft layer 64. In this specification, the side surfaces of the shaft layer 64 refer to the surfaces of the shaft layer 64 that extend between the bottom layer 63 and the upper portion 62.

[0069] In the example shown in the figure, the upper portion 62 has a greater width than the bottom portion 63. It should be noted that the bottom portion 63 may have a greater width than the upper portion 62.

[0070] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 and covers the lower electrode LE1 exposed from the opening AP1 , with its peripheral portion positioned above the inorganic insulating layer 5 . The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61 .

[0071] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 , covers the lower electrode LE2 exposed from the opening AP2 , and has its peripheral portion located above the inorganic insulating layer 5 . The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61 .

[0072] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 , covers the lower electrode LE3 exposed from the opening AP3 , and has its peripheral portion located above the inorganic insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0073] It should be noted that the contact between each of the upper electrodes UE1, UE2, and UE3 and the lower portion 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and in direct contact with the side surface of the shaft layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the shaft layer 64 and the surface that protrudes from the shaft layer 64 and is opposite to the upper portion 62.

[0074] In the illustrated example, subpixel SP1 includes cap layer CP1 and sealing layer SE1, subpixel SP2 includes cap layer CP2 and sealing layer SE2, and subpixel SP3 includes cap layer CP3 and sealing layer SE3. Cap layers CP1, CP2, and CP3 serve as optical adjustment layers, improving the efficiency of light extraction from organic layers OR1, OR2, and OR3, respectively. It should be noted that cap layers CP1, CP2, and CP3 may also be omitted.

[0075] The cap layer CP1 is disposed on the upper electrode UE1 .

[0076] The cap layer CP2 is configured on the upper electrode UE2.

[0077] The cap layer CP3 is configured on the upper electrode UE3.

[0078] The sealing layer SE1 is disposed on the cap layer CP1, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP1. Specifically, the sealing layer SE1 is in contact with the axial layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE1.

[0079] The sealing layer SE2 is disposed on the cap layer CP2, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP2. Specifically, the sealing layer SE2 is in contact with the axial layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE2.

[0080] The sealing layer SE3 is disposed on the cap layer CP3, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP3. Specifically, the sealing layer SE3 is in contact with the axial layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE3.

[0081] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0082] In the example shown in the figure, a portion of the laminated film FL1 is located on the partition wall 6 around the sub-pixel SP1 and is separated from the laminated film FL1 located at the opening AP1 (a portion constituting the display element DE1 ).

[0083] Similarly, a portion of the stacked film FL2 is located on the partition wall 6 around the sub-pixel SP2 and is separated from the stacked film FL2 located at the opening AP2 (a portion constituting the display element DE2 ).

[0084] Similarly, a portion of the stacked film FL3 is located on the partition wall 6 around the sub-pixel SP3 and is separated from the stacked film FL3 located at the opening AP3 (a portion constituting the display element DE3 ).

[0085] In addition, the laminated films FL1, FL2, and FL3 on the partition walls 6 may be omitted. In this case, a cavity is formed between the sealing layers SE1, SE2, and SE3 and the partition walls 6.

[0086] The ends of the sealing layers SE1, SE2, and SE3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. Furthermore, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0087] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. If cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, these cavities are filled with the resin layer 13. The resin layer 13 is covered with a sealing layer 14. The wiring TL is arranged above the sealing layer 14, for example, directly above the partition wall 6. This wiring TL functions as, for example, sensor wiring for detecting objects approaching the display device DSP. The sealing layer 14 and the wiring TL are covered with a resin layer 15.

[0088] The inorganic insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0089] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material, such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, such as an aluminum-based material, such as aluminum or an aluminum compound.

[0090] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a different material from the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0091] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer structures including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0092] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range.

[0093] In addition, each of the organic layers OR1, OR2, and OR3 may include a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0094] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0095] The cap layers CP1, CP2, and CP3 are multilayer bodies of multiple thin films, all of which are transparent and have different refractive indices.

[0096] The wiring TL is formed of a metal material such as aluminum, titanium, or molybdenum. In one example, the wiring TL is a multilayer structure including an aluminum layer between a pair of titanium layers.

[0097] The circuit layer 11 , the insulating layer 12 , and the inorganic insulating layer 5 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0098] Next, a mother substrate for a display device (hereinafter simply referred to as a mother substrate) 100 for collectively manufacturing a plurality of display devices DSP will be described.

[0099] Figure 4 1 is a plan view showing an example of the motherboard 100 .

[0100] The motherboard 100 includes a plurality of panel portions PP and a blank portion MP outside the panel portions PP on a large substrate 10. The large substrate 10 is formed in a rectangular shape, for example. The plurality of panel portions PP are removed by cutting the motherboard 100 along cutting lines.

[0101] The removed panel parts PP are equivalent to Figure 1 The display panel PNL shown in FIG. 1 includes a display area DA and a peripheral area SA. The peripheral area SA has a configuration Figure 1 The plurality of wirings TL are respectively arranged in the display area DA, led out to the peripheral area SA, and electrically connected to the terminals TE included in the terminal area TA.

[0102] The region 100A in the figure is a part of the surrounding area SA, and the region 100B is a part of the blank portion MP.

[0103] Figure 5 Yes Figure 4 A plan view of one configuration example of the region 100A and the region 100B is shown.

[0104] A plurality of peripheral partition walls 7 are arranged in the region 100A and the region 100B. The plurality of peripheral partition walls 7 are formed in a lattice shape when viewed from above. In one example, the peripheral partition walls 7 are arranged in a manner similar to the lattice shape. Figure 2 The lattice-shaped partition walls 6 shown in the figure are formed in the same pattern. In addition, a plurality of peripheral partition walls 7 are arranged in the first direction X and the second direction Y and are separated from each other. These plurality of peripheral partition walls 7 are covered by the sealing layer 14. It should be noted that the planar shape of the peripheral partition walls 7 is not limited to the lattice-shaped one shown in the figure, and can also be a straight line, an L-shaped, an arc-shaped, etc.

[0105] Figure 6 It is along Figure 5 A cross-sectional view of the peripheral partition wall 7 along the CD line in FIG.

[0106] The peripheral partition wall 7 includes a lower portion 71 disposed on the inorganic insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The lower portion 71 includes a base layer 73 disposed on the inorganic insulating layer 5 and an axial layer 74 disposed between the base layer 73 and the upper portion 72. The upper portion 72 includes a thin film 75 disposed on the axial layer and a thin film 76 disposed on the thin film 75.

[0107] The bottom layer 73 is thinner than the shaft layer 74. The bottom layer 73 is wider than the shaft layer 74. Both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74. The upper portion 72 is wider than the shaft layer 74. Both ends of the upper portion 72 protrude from the side surfaces of the shaft layer 74. In the illustrated example, the upper portion 72 is wider than the bottom layer 73, and the bottom layer 73 is wider than the upper portion 72.

[0108] The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the bottom layer 73 is formed of the same material as the bottom layer 63, the shaft layer 74 is formed of the same material as the shaft layer 64, the film 75 is formed of the same material as the film 65, and the film 76 is formed of the same material as the film 66.

[0109] The sealing layer 14 contacts the base layer 73, the shaft layer 74, and the upper portion 72. Thus, the sealing layer 14 covers the peripheral partition walls 7, so that the unevenness caused by the cross-sectional shape of the peripheral partition walls 7 is alleviated compared to before the sealing layer 14 is formed.

[0110] Figure 3 The resin layers 13 and 15 shown are arranged in the display area DA, but do not overlap with the peripheral barrier ribs 7 .

[0111] Figure 7 Yes Figure 4 A plan view of another configuration example of the region 100A and the region 100B is shown.

[0112] Figure 7 The configuration example shown is the same as Figure 5 Compared to the illustrated configuration example, the sealing layer 14 is subdivided. In the illustrated example, each portion of the subdivided sealing layer 14 is formed to cover four peripheral partition walls 7. A gap of approximately 5 to 10 μm, for example, is formed between adjacent sealing layers 14. The peripheral partition walls 7A and 7B in the figure are separated from each other and arranged in the first direction X. The portion of the sealing layer 14 covering the peripheral partition walls 7A is separated from the portion covering the peripheral partition walls 7B.

[0113] Figure 8 It is along Figure 7 A cross-sectional view of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line EF in FIG.

[0114] The sealing layer 14 is in contact with the bottom layer 73, the axial layer 74, and the upper portion 72 of the peripheral wall 7A. Furthermore, the sealing layer 14 is in contact with the bottom layer 73, the axial layer 74, and the upper portion 72 of the peripheral wall 7B. The sealing layer 14 has a notch between the portion covering the peripheral wall 7A and the portion covering the peripheral wall 7B. Therefore, the inorganic insulating layer 5 is exposed from the sealing layer 14 between the peripheral wall 7A and the peripheral wall 7B.

[0115] like Figure 7 and Figure 8 By subdividing the sealing layer 14 as in the illustrated configuration example, stress acting on the sealing layer 14 can be alleviated, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0116] Figure 9 Yes Figure 4 A plan view of another configuration example of the region 100A and the region 100B is shown.

[0117] Figure 9 The configuration example shown is the same as Figure 7 Compared with the example shown in the figure, the sealing layer 14 is further divided into subdivisions. In the example shown in the figure, each subdivided portion of the sealing layer 14 is formed so as to cover one peripheral partition wall 7. In the sealing layer 14, the portion covering the peripheral partition wall 7 is separated. Between adjacent portions of the sealing layer 14, as shown in FIG. Figure 8 As shown, the inorganic insulating layer 5 is exposed from the sealing layer 14 .

[0118] Next, a method for manufacturing the display device DSP will be described. It should be noted that, in the figures used to illustrate the manufacturing method, illustrations below the insulating layer 12 are omitted. Figures 10 to 17The cross section on the left corresponding to the display area DA is equivalent to the cross section along Figure 2 The cross section along the AB line in FIG. 1 is equivalent to the cross section along the AB line in FIG. 1 and the cross section along the AB line in FIG. 1. Figure 7 The cross section of line EF in .

[0119] First, if Figure 10 As shown in FIG. 1 , a processing substrate SUB is prepared that includes lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, partition walls 6, and peripheral partition walls 7. The process of preparing the processing substrate SUB includes the following steps.

[0120] Specifically, a circuit layer 11 and an insulating layer 12 are formed over the display area DA, the peripheral area SA, and the blank portion MP on the substrate 10. Then, in the display area DA, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12.

[0121] Next, an inorganic insulating layer 5 is formed over the display area DA, the peripheral area SA, and the blank portion MP. The inorganic insulating layer 5 includes openings AP1, AP2, and AP3 that cover the peripheries of the lower electrodes LE1, LE2, and LE3 and overlap with the lower electrodes LE1, LE2, and LE3, respectively. The inorganic insulating layer 5 is formed, for example, of silicon oxynitride.

[0122] Next, a partition wall 6 is formed, which includes a lower portion 61 located above the inorganic insulating layer 5 and an upper portion 62 located above the lower portion 61. Simultaneously with the formation of the partition wall 6, a peripheral partition wall 7 is formed, which includes a lower portion 71 located above the inorganic insulating layer 5 and an upper portion 72 located above the lower portion 71. The bottom layer 63 and the upper portion 62 of the lower portion 61 protrude from the side of the shaft layer 64 of the lower portion 61. Similarly, the bottom layer 73 and the upper portion 72 of the lower portion 71 protrude from the side of the shaft layer 74 of the lower portion 71. The bottom layers 63 and 73 are formed of a titanium-based material, and the shaft layers 64 and 74 are formed of an aluminum-based material.

[0123] It should be noted that the step of forming the openings AP1 , AP2 , and AP3 in the inorganic insulating layer 5 may be performed before or after forming the partition walls 6 and the peripheral partition walls 7 .

[0124] Next, the display element DE1 is formed.

[0125] First, if Figure 11As shown, a stacked film FL1 comprising an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the stacked film FL1 includes forming the organic layer OR1 above the lower electrode LE1 at the opening AP1; forming the upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6; and forming the cap layer CP1 above the upper electrode UE1. The process of forming the organic layer OR1 includes forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer EM1, a hole blocking layer, an electron transport layer, and an electron injection layer. The upper electrode UE1 is formed from a mixture of magnesium and silver.

[0126] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. These organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0127] The laminated film FL1 is formed on the lower electrodes LE2 and LE3 in the display area DA, as well as in the peripheral area SA and the blank portion MP. This laminated film FL1 is divided into multiple sections by cantilevered partitions 6 and peripheral partitions 7. In particular, in the peripheral area SA and the blank portion MP, the laminated film FL1 is divided by the peripheral partitions 7, thereby subdividing the laminated film FL1. This reduces stress on the laminated film FL1 during the manufacturing process, preventing the laminated film FL1 from detaching from the inorganic insulating layer 5.

[0128] Next, a sealing layer SE1 is formed on the laminate film FL1 by depositing an inorganic insulating material. The sealing layer SE1 is formed using CVD (Chemical Vapor Deposition) over the display area DA, the peripheral area SA, and the blank area MP. The sealing layer SE1 continuously covers the partitioned portions of the laminate film FL1, the partition walls 6, and the peripheral partition walls 7. The sealing layer SE1 is formed, for example, of silicon nitride.

[0129] Next, if Figure 12 As shown, in the display area DA, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a portion of the partition 6 surrounding it. The resist RS is not disposed in the peripheral area SA and the blank portion MP.

[0130] Next, if Figure 13As shown, etching is performed using the resist RS as a mask to pattern the laminate film FL1 and the sealing layer SE1. That is, dry etching is performed using the resist RS as a mask to remove the sealing layer SE1 exposed from the resist RS. Then, the laminate film FL1 exposed from the resist RS is removed. At this time, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed from the laminate film FL1 in sequence. As a result, the laminate film FL1 covered by the resist RS remains in the sub-pixel SP1. In addition, a portion of the upper portion 62 of the partition wall 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are exposed. In addition, in the peripheral area SA and the blank portion MP, the peripheral partition wall 7 is exposed.

[0131] Then, the resist RS is removed, thereby forming the display element DE1 in the sub-pixel SP1.

[0132] In the process of removing the sealing layer SE1 and the laminated film FL1 and removing the resist RS, the laminated film FL1 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE1.

[0133] Next, if Figure 14 As shown, display element DE2 is formed. The steps for forming display element DE2 are the same as those for forming display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a laminate film FL2. Then, a sealing layer SE2 is formed on the laminate film FL2. Then, a resist is formed on the sealing layer SE2, and etching using the resist as a mask is performed to pattern the sealing layer SE2, the cover layer CP2, the upper electrode UE2, and the organic layer OR2. After this patterning, the resist is removed. Thus, display element DE2 is formed in sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 is exposed.

[0134] It should be noted that, in the process of removing the sealing layer SE2 and the laminated film FL2 and removing the resist, the laminated film FL2 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE2.

[0135] The laminate film FL2 does not remain on the peripheral partition walls 7 , and the peripheral partition walls 7 are not covered with the sealing layer SE2 .

[0136] Next, if Figure 15As shown, display element DE3 is formed. The steps for forming display element DE3 are the same as those for forming display element DE1. Specifically, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are sequentially formed on the lower electrode LE3 to form a laminate film FL3. A sealing layer SE3 is then formed on the laminate film FL3. A resist is then formed on the sealing layer SE3, and etching is performed using the resist as a mask to pattern the sealing layer SE3, cap layer CP3, upper electrode UE3, and organic layer OR3. After this patterning, the resist is removed. Thus, display element DE3 is formed in sub-pixel SP3.

[0137] It should be noted that, in the process of removing the sealing layer SE3 and the laminated film FL3 and removing the resist, the laminated film FL3 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE3.

[0138] The laminate film FL3 does not remain on the peripheral partition walls 7 , and the peripheral partition walls 7 are not covered with the sealing layer SE3 .

[0139] It should be noted that, in the above manufacturing process, the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0140] Next, if Figure 16 As shown, a resin layer 13 is formed in the display area DA, located above the sealing layers SE1, SE2, and SE3. Although not described in detail, the display area DA is surrounded by protrusions. The resin layer 13 is applied to the inner side of the protrusions. Therefore, the resin layer 13 is not disposed in the peripheral area SA or the blank portion MP, and does not overlap with the peripheral partition wall 7.

[0141] Next, if Figure 17 As shown, sealing layer 14 is formed by depositing an inorganic insulating material. Sealing layer 14 is formed using CVD over the display area DA, the peripheral area SA, and the blank portion MP. Sealing layer 14 is disposed on resin layer 13 in the display area DA and continuously covers peripheral partition walls 7 in the peripheral area SA and the blank portion MP. Specifically, the base layer 73, the shaft layer 74, and the upper portion 72 of the lower portion 71 are directly covered by sealing layer 14. Sealing layer 14 is formed, for example, of silicon nitride.

[0142] Next, the inorganic insulating layer 5 and the sealing layer 14 are patterned.

[0143] Figure 18 It is a cross-sectional view showing the terminal area TA.

[0144] Here, the terminal area TA is shown as a part of the peripheral area SA. Although not described in detail, the blank part MP has a terminal area where the inspection terminal is arranged. The terminal area of ​​the blank part MP also has Figure 18 The area shown is the same cross section.

[0145] like Figure 18 As shown on the left side of FIG, the terminal TE is formed in the process of forming the circuit layer 11. The insulating layer 12 covers the peripheral portion of the terminal TE. The inorganic insulating layer 5 covers the insulating layer 12 in the terminal area TA and covers the terminal TE. Figure 17 As described above, the sealing layer 14 is also formed in the peripheral area SA, and covers the inorganic insulating layer 5 in the terminal area TA.

[0146] Then, if Figure 18 As shown on the right side of FIG, the inorganic insulating layer 5 and the sealing layer 14 are patterned, and a through hole TH penetrating the inorganic insulating layer 5 and the sealing layer 14 is formed in the terminal area TA, thereby exposing the terminal TE.

[0147] Next, if Figure 19 As shown, the sealing layer 14 is patterned.

[0148] In the peripheral area SA and the blank portion MP, the sealing layer 14 covering the peripheral partition wall 7 is subdivided. In the terminal area TA, the sealing layer 14 around the terminal TE is removed, and the step difference in the through hole TH is relaxed.

[0149] Next, if Figure 20 As shown, a conductive layer 20 is formed. The conductive layer 20 is, for example, a multilayer structure composed of a titanium layer, an aluminum layer, and a titanium layer stacked in this order. In the peripheral area SA and the blank portion MP, the conductive layer 20 is disposed on the sealing layer 14 and also on the inorganic insulating layer 5. In the terminal area TA, the conductive layer 20 is disposed on the inorganic insulating layer 5 and also on the terminals TE in the through-holes TH. In the display area DA, the conductive layer 20 is disposed on the sealing layer 14.

[0150] Next, if Figure 21 As shown, a resist RS1 is applied on the conductive layer 20. At this time, in the peripheral area SA and the blank portion MP, the unevenness of the peripheral partition wall 7 is mitigated by the sealing layer 14 near the peripheral partition wall 7, thereby suppressing the formation of undesirable gaps between the resist RS1 and the peripheral partition wall 7. In addition, the surface of the resist RS1 can be flattened. Therefore, in the resist RS1, the formation of locally thickened areas and areas that become shadows of the peripheral partition wall 7 is suppressed. Such a resist RS1 is, for example, a positive type that becomes soluble in a developer by irradiation with light.

[0151] Next, if Figure 22As shown, the resist RS1 is patterned. This patterning allows the resist RS1 to overlap with the terminal TE in the terminal area TA and overlap with the partition 6 in the display area DA. Since substantially the entire area of ​​the resist RS1 is exposed in the peripheral area SA and the blank portion MP, no residue of the resist RS1 is generated.

[0152] Next, if Figure 23 As shown, the resist RS1 is used as a mask to pattern the conductive layer 20. In the peripheral area SA and the blank portion MP, the resist RS1 is removed, so there is no residue of the conductive layer 20. In the terminal area TA and the display area DA, the conductive layer 20 exposed from the resist RS1 is removed.

[0153] Next, if Figure 24 As shown in FIG, the resist RS1 is removed. Thus, the wiring TL is formed from the display area DA to the terminal area TA, and in the terminal area TA, the wiring TL is connected to the terminal TE.

[0154] Next, if Figure 25 As shown, a resin layer 15 is formed in the display area DA, located above the sealing layer 14 and the wiring TL. Although not described in detail, the resin layer 15 is applied to the inner side of the protrusion surrounding the display area DA. Therefore, the resin layer 15 is not disposed in the terminal area TA, the peripheral area SA, or the blank portion MP, and does not overlap with the peripheral partition wall 7.

[0155] As described above, since the peripheral partition walls 7 are covered by the sealing layer 14, they are protected by the sealing layer 14 during patterning of the conductive layer 20 in the process of forming the wiring TL. This prevents unintended removal of the peripheral partition walls 7. Furthermore, the generation of conductive particles caused by partial detachment of the peripheral partition walls 7 is suppressed.

[0156] Furthermore, during patterning of the conductive layer 20, the formation of gaps between the resist RS1 and the peripheral partition walls 7 and the local thickening of the resist RS1 are suppressed. Consequently, the generation of unwanted residues of the resist RS1 around the peripheral partition walls 7 is suppressed. Consequently, the generation of unwanted residues of the conductive layer 20 is suppressed.

[0157] It should be noted that, here, in particular, the resist RS1 used in patterning the conductive layer 20 is described, but in reference to Figure 18 The patterning of the inorganic insulating layer 5 and the sealing layer 14 described above and the reference Figure 19 During the patterning of the sealing layer 14 described above, when applying the respective resists, the formation of voids and local thickening of the resist are also suppressed. Therefore, the generation of undesirable resist residues is suppressed.

[0158] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability, a mother substrate for the display device, and a method for manufacturing the display device.

[0159] In the above embodiment, for example, sealing layers SE1, SE2, and SE3 correspond to the first sealing layer, and sealing layer 14 corresponds to the second sealing layer. Resin layer 13 corresponds to the first resin layer, and resin layer 15 corresponds to the second resin layer. In peripheral partition wall 7, lower portion 71 corresponds to the first lower portion, upper portion 72 corresponds to the second upper portion, base layer 73 corresponds to the first base layer, and axial layer 74 corresponds to the first axial layer. Peripheral partition wall 7A corresponds to the first peripheral partition wall, and peripheral partition wall 7B corresponds to the second peripheral partition wall. In partition wall 6, lower portion 61 corresponds to the second lower portion, upper portion 62 corresponds to the second upper portion, base layer 63 corresponds to the second base layer, and axial layer 64 corresponds to the second axial layer.

[0160] Based on the display device, mother substrate and display device manufacturing method described above as the embodiments of the present invention, all display devices, mother substrates and display device manufacturing methods that can be appropriately designed and modified by those skilled in the art also fall within the scope of the present invention as long as they include the main purpose of the present invention.

[0161] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, which also fall within the scope of the present invention. For example, with respect to the above-mentioned embodiments, those skilled in the art may appropriately add, delete, or modify the design of constituent elements, or add, omit, or modify the conditions of processes. As long as such additions and deletions are made, such modifications fall within the scope of the present invention.

[0162] In addition, regarding other effects brought about by the methods described in the above embodiments, effects that are clear from the description of this specification or effects that can be appropriately imagined by those skilled in the art are of course understood as effects brought about by the present invention.

Claims

1. A display device comprising: substrate; an inorganic insulating layer disposed above the substrate and extending over a display area for displaying an image and a peripheral area outside the display area; A display element is configured in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions disposed in the peripheral area; and a second sealing layer formed of an inorganic insulating material and arranged over the display area and the peripheral area; Each of the plurality of peripheral partition walls includes a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

2. The display device according to claim 1, wherein The first lower portion includes a first base layer disposed on the inorganic insulating layer and a first axial layer disposed between the first base layer and the first upper portion. The first bottom layer and the first upper portion protrude from the side surface of the first axial layer. The second sealing layer is in contact with the first base layer, the first shaft layer, and the first upper portion.

3. The display device according to claim 1, wherein The plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall separated from the first peripheral partition wall. The second sealing layer has a portion covering the first peripheral partition wall separated from a portion covering the second peripheral partition wall. The inorganic insulating layer is exposed from the second sealing layer between the first peripheral partition wall and the second peripheral partition wall. 4 . The display device according to claim 1 , further comprising a wiring, wherein the wiring is arranged on the second sealing layer in the display region and is led out to the peripheral region.

5. The display device according to claim 1, further comprising: a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; and The second resin layer is disposed on the second sealing layer in the display region, and the first resin layer and the second resin layer do not overlap with the peripheral barrier ribs.

6. The display device according to claim 2, further comprising a partition wall surrounding the display element. The partition wall has a second lower portion that is disposed on the inorganic insulating layer and has conductivity, and a second upper portion that is disposed on the second lower portion. The second lower portion includes a second bottom layer and a second axial layer, wherein the second bottom layer is arranged on the inorganic insulating layer and is formed of the same material as the first bottom layer, and the second axial layer is arranged between the second bottom layer and the second upper portion and is formed of the same material as the first axial layer. The second bottom layer and the second upper portion protrude from the side surface of the second axial layer. The first sealing layer is in contact with the second shaft layer and the second upper portion.

7. The display device according to claim 6, wherein: The display element comprises: a lower electrode having a peripheral portion covered by the inorganic insulating layer; an organic layer disposed on the lower electrode and comprising a light-emitting layer; and an upper electrode disposed on the organic layer and in contact with the second lower portion, The partition wall surrounds the organic layer and the upper electrode. 8 . The display device according to claim 7 , further comprising a cap layer disposed between the upper electrode and the first sealing layer.

9. A mother substrate having: a panel portion having a display area for displaying an image and a peripheral area outside the display area; a blank portion located outside the panel portion; an inorganic insulating layer disposed over the panel portion and the blank portion; A display element is configured in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions disposed in the blank portion; and The second sealing layer is formed of an inorganic insulating material and is arranged over the panel portion and the blank portion. Each of the plurality of peripheral partition walls includes a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

10. The mother substrate according to claim 9, wherein: The first lower portion includes a first base layer disposed on the inorganic insulating layer and a first axial layer disposed between the first base layer and the first upper portion. The first bottom layer and the first upper portion protrude from the side surface of the first axial layer. The second sealing layer is in contact with the first base layer, the first shaft layer, and the first upper portion.

11. The mother substrate according to claim 9, wherein The plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall separated from the first peripheral partition wall. The second sealing layer covering the first peripheral partition wall is separated from the second sealing layer covering the second peripheral partition wall. The inorganic insulating layer is exposed from the second sealing layer between the first peripheral partition wall and the second peripheral partition wall. 12 . The motherboard according to claim 9 , further comprising wiring, wherein the wiring is arranged on the second sealing layer in the display region and is led out to the peripheral region.

13. The mother substrate according to claim 9, further comprising: a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; and a second resin layer disposed on the second sealing layer in the display region, The first resin layer and the second resin layer do not overlap with the peripheral partition wall.

14. A method for manufacturing a display device, wherein: A processing substrate is prepared, the processing substrate comprising an inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area, a display element located in the display area, a plurality of peripheral partitions located in the peripheral area, and a first sealing layer covering the display element and exposing the peripheral partitions. forming a second sealing layer extending over the display area and the peripheral area from an inorganic insulating material, Each of the plurality of peripheral partition walls includes a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

15. The method for manufacturing a display device according to claim 14, wherein: The first lower portion includes a first base layer disposed on the inorganic insulating layer and a first axial layer disposed between the first base layer and the first upper portion. The first bottom layer and the first upper portion protrude from the side surface of the first axial layer. The second sealing layer is formed so as to be in contact with the first base layer, the first shaft layer, and the first upper portion.

16. The method for manufacturing a display device according to claim 14, wherein: The processing substrate includes terminals in the peripheral region. After forming the second sealing layer, forming a through hole penetrating the inorganic insulating layer and the second sealing layer to expose the terminal; The second sealing layer is patterned.

17. The method for manufacturing a display device according to claim 16, wherein: The plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall separated from the first peripheral partition wall. In patterning the second sealing layer, the second sealing layer is formed so that a portion covering the first peripheral partition wall is separated from a portion covering the second peripheral partition wall and the inorganic insulating layer is exposed between the first peripheral partition wall and the second peripheral partition wall.

18. The method for manufacturing a display device according to claim 14, wherein: Furthermore, after forming the second sealing layer, forming a conductive layer, forming a resist on the conductive layer, The conductive layer is removed using the resist as a mask, thereby forming wiring located on the second sealing layer in the display region and extending to the peripheral region.

19. The method for manufacturing a display device according to claim 18, wherein: Furthermore, before forming the second sealing layer, a first resin layer is formed on the first sealing layer in the display area. After forming the wiring, forming a second resin layer on the second sealing layer and the wiring in the display region, The first resin layer and the second resin layer do not overlap with the peripheral partition wall.

20. The method for manufacturing a display device according to claim 14, wherein: The display element is formed in the following manner: forming a lower electrode located in the display area, covering the peripheral edge of the lower electrode with the inorganic insulating layer, forming a laminated film including an organic layer including a light-emitting layer and an upper electrode located on the organic layer over the lower electrode, The first sealing layer is patterned together with the laminated film.

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