Display device

Abstract

A display device includes: a substrate including a display area including a fillet and a peripheral area outside the display area, where the display area includes a first display area and a second display area between the first display area and the peripheral area; a plurality of first driving circuits in the first display area; a plurality of first light emitting diodes electrically connected to the plurality of first driving circuits, respectively; a plurality of second driving circuits in the second display area; a plurality of second light emitting diodes electrically connected to the plurality of second driving circuits, respectively; a plurality of gate lines electrically connected to the plurality of first driving circuits and the plurality of second driving circuits; and a plurality of stages in the second display area and electrically connected to the plurality of gate lines, in which the plurality of stages are arranged in a stepped configuration along a fillet of the display area in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0037392 filed in the Korean Intellectual Property Office on March 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of one or more embodiments relate to a display device. Background Art

[0004] Recently, display panels have become more diverse in their uses. In addition, as display panels have become relatively thinner and lighter, the range of uses of display panels has expanded.

[0005] Research is being conducted to reduce the area of ​​a region outside the display region (ie, the area of ​​an unused region) while expanding the area occupied by the display region of the display panel.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0007] Aspects of one or more embodiments include a structure for a display device having rounded corners.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to one or more embodiments, a display device includes: a substrate including a display area including rounded corners and a peripheral area outside the display area, wherein the display area includes a first display area and a second display area between the first display area and the peripheral area; a plurality of first driving circuits in the first display area; a plurality of first light-emitting diodes electrically connected to the plurality of first driving circuits, respectively; a plurality of second driving circuits in the second display area; a plurality of second light-emitting diodes electrically connected to the plurality of second driving circuits, respectively; a plurality of gate lines electrically connected to the plurality of first driving circuits and the plurality of second driving circuits; and a plurality of stages in the second display area and electrically connected to the plurality of gate lines, wherein the plurality of stages are arranged in a stepped configuration (or stepped structure) along the rounded corners of the display area in a plan view.

[0010] According to some embodiments, a voltage line configured to apply voltages to the plurality of stages may overlap with the plurality of second driving circuits in the second display area.

[0011] According to some embodiments, the voltage line may overlap with the plurality of stages in the second display area.

[0012] According to some embodiments, the voltage line may be bent to have a stepped shape in a plan view.

[0013] According to some embodiments, each of the plurality of first drive circuits and the plurality of second drive circuits may include: a drive transistor; a first transistor; and a second transistor, the first transistor and the second transistor being electrically connected to the drive transistor, wherein the plurality of stages include: a plurality of first stages, each configured to provide a gate signal to a first transistor of a corresponding first drive circuit and a corresponding second drive circuit in the plurality of first drive circuits and the plurality of second drive circuits; and a plurality of second stages, each configured to provide a gate signal to a second transistor of a corresponding first drive circuit and a corresponding second drive circuit in the plurality of first drive circuits and the plurality of second drive circuits.

[0014] According to some embodiments, in a plan view, one of two adjacent first levels among a plurality of first levels and the other of the two adjacent first levels can be arranged in a first direction, and one of the two adjacent first levels among the plurality of first levels is shifted from the other of the two adjacent first levels in a second direction intersecting with the first direction, and in a plan view, one of two adjacent second levels among a plurality of second levels and the other of the two adjacent second levels can be arranged in the first direction, and one of two adjacent second levels among the plurality of second levels is shifted from the other of the two adjacent second levels in the second direction.

[0015] According to some embodiments, a length of each of the plurality of first stages in the first direction is different from a length of each of the plurality of second stages in the first direction.

[0016] According to some embodiments, the display device may further include multiple clock signal lines, the multiple clock signal lines being in the peripheral area, wherein a signal connection line connecting one of the multiple clock signal lines to a corresponding second level among the multiple second levels may be in the second display area and pass between two adjacent first levels.

[0017] According to some embodiments, a carry signal line between two adjacent first stages among the plurality of first stages or a carry signal line between two adjacent second stages among the plurality of second stages may be bent in a plan view.

[0018] According to some embodiments, one of the plurality of stages provides a gate signal to a corresponding gate line of the plurality of gate lines via an output signal line, wherein the output signal line and the corresponding gate line of the plurality of gate lines are electrically connected to each other in the peripheral region.

[0019] According to one or more embodiments, a display device includes: a substrate including a display area including a rounded corner and a peripheral area outside the display area, wherein the display area includes a first display area and a second display area between the first display area and the peripheral area; a plurality of driving circuits in the first display area and the second display area; a plurality of light-emitting diodes on the plurality of driving circuits, and the plurality of light-emitting diodes are electrically connected to the plurality of driving circuits; and a plurality of first levels between the substrate and the plurality of driving circuits, and the plurality of first levels are configured to provide a first gate signal to the plurality of driving circuits, wherein the plurality of first levels are in the second display area, and the plurality of first levels are arranged in a stepped configuration along the rounded corners of the display area in a plan view.

[0020] According to some embodiments, a voltage line configured to apply voltages to the plurality of first stages may overlap with the plurality of driving circuits in the second display area.

[0021] According to some embodiments, the voltage line may overlap with the plurality of first levels in the second display area.

[0022] According to some embodiments, the voltage line may extend in the first direction and be bent in a plan view.

[0023] According to some embodiments, the display device may further include a plurality of second stages in the second display area and configured to provide second gate signals to the plurality of driving circuits, wherein the plurality of second stages may be arranged in a stepped configuration in a plan view.

[0024] According to some embodiments, in a plan view, the plurality of second levels may be between the plurality of first levels and the first display area, and a length of each of the plurality of first levels in the first direction may be different from a length of each of the plurality of second levels in the first direction.

[0025] According to some embodiments, a length of each of the plurality of first stages in the first direction may be smaller than a length of each of the plurality of second stages in the first direction.

[0026] According to some embodiments, the display device may further include a plurality of clock signal lines in the peripheral area, wherein a signal connection line connecting one of the plurality of clock signal lines to a corresponding second level among the plurality of second levels may pass in the second display area and between two adjacent first levels among the plurality of first levels.

[0027] According to some embodiments, a carry signal line between two adjacent first stages among the plurality of first stages or a carry signal line between two adjacent second stages among the plurality of second stages may be bent in a plan view.

[0028] According to some embodiments, the display device may further include a first gate line electrically connected to a plurality of driving circuits, and one of the plurality of first stages may provide the first gate signal to the first gate line via an output signal line, and the output signal line and the first gate line may be electrically connected to each other in the peripheral area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and characteristics of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic plan view of a display device according to some embodiments;

[0031] Figure 2 is an equivalent circuit diagram schematically illustrating a driving circuit and a light emitting diode arranged in a display area of ​​a display device according to some embodiments;

[0032] Figure 3 is a circuit diagram schematically illustrating a gate driving circuit according to some embodiments;

[0033] Figure 4 Shown along Figure 1 Schematic cross-sectional views of display devices according to some embodiments, taken along lines IVa-IVa' and IVb-IVb';

[0034] Figure 5 According to some embodiments Figure 1 A schematic enlarged plan view of a region V of a display device;

[0035] Figure 6 According to some embodiments Figure 5 A schematic enlarged plan view of region VI of a display device; and

[0036] Figure 7 is a cross-sectional view of a portion of a display device according to some embodiments. DETAILED DESCRIPTION

[0037] With reference now to the aspects of some embodiments in more detail, examples of some embodiments are shown in the accompanying drawings, in which like reference numerals always refer to like elements. In this respect, the embodiments presented can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0038] Since the present disclosure allows for various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The effects and features of the present disclosure and methods of achieving them will be apparent with reference to the embodiments and drawings described in detail below. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0039] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the disclosure are shown. Like reference numerals in the drawings refer to like elements, and thus their description will not be repeated.

[0040] In the following embodiments, although terms such as “first,” “second,” etc. may be used to describe various elements, these elements are not necessarily limited to the above terms.

[0041] In the following embodiments, an expression in the singular includes an expression in the plural form unless it has an apparently different meaning in the context.

[0042] In the following embodiments, it will be understood that terms such as “including” and “having” are intended to indicate the presence of features or elements disclosed in the present disclosure, and are not intended to exclude the possibility that one or more other features or elements may exist or be added.

[0043] It will be understood that when a layer, region or element is referred to as being formed on another layer, region or element, the layer, region or element may be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0044] For the convenience of explanation, the sizes of the elements in the drawings may be exaggerated. In other words, since the sizes and thicknesses of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0045] When a specific embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of the described order.

[0046] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, the layer, region, or component may be directly or indirectly connected to the other layer, region, or component. That is, for example, there may be intervening layers, regions, or components. For example, it will be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, the layer, region, or component may be directly or indirectly electrically connected to the other layer, region, or component. That is, for example, there may be intervening layers, regions, or components.

[0047] The x-direction, y-direction, and z-direction are not limited to the directions of the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0048] Figure 1 is a schematic plan view of a display device 1 according to some embodiments.

[0049] Reference Figure 1 , the display device 1 may include a display area DA and a peripheral area PA. Figure 1 The shape of the display device 1 may be substantially the same as the shape of the substrate 100. For example, "the display device 1 includes a display area DA and a peripheral area PA" may mean that the substrate 100 includes the display area DA and the peripheral area PA. The display area DA may include rounded corners, and the substrate 100 may also have rounded corners substantially along the rounded corners of the display area DA.

[0050] The display area DA can display an image using light emitted from each light-emitting diode LED. The peripheral area PA is a non-display area arranged outside the display area DA (e.g., in the periphery of the display area DA or outside the cover area of ​​the display area DA) and does not display an image. The peripheral area PA may completely surround the display area DA.

[0051] The light emitting diode (LED) may be an organic light emitting diode including an organic emission layer. Alternatively, the light emitting diode (LED) may be an inorganic light emitting diode including an inorganic emission layer. The size of the light emitting diode (LED) may be micrometer-scale or nanometer-scale. For example, the light emitting diode (LED) may be a micro light emitting diode. Alternatively, the light emitting diode (LED) may be a nanorod light emitting diode. The nanorod light emitting diode may include gallium nitride (GaN). According to some embodiments, a color conversion layer may be above the nanorod light emitting diode. The color conversion layer may include quantum dots. Alternatively, the light emitting diode (LED) may be a quantum dot light emitting diode including a quantum dot emission layer.

[0052] The driving circuit PC (also referred to as the pixel circuit PC) electrically connected to each light emitting diode LED may be a circuit that controls the operation of the light emitting diode LED. A plurality of driving circuits PC may be arranged two-dimensionally in the display area DA. Each driving circuit PC may include a transistor and at least one storage capacitor. According to some embodiments, each driving circuit PC may be connected to a data line DL and a gate line GL. The data line DL may extend in a first direction (e.g., the y direction), and the gate line GL may extend in a second direction (e.g., the x direction) that intersects the first direction (e.g., the y direction). Although Figure 1 A single drive circuit PC and a single light emitting diode LED are shown, but one of ordinary skill in the art will recognize that the number of drive circuits PC and the number of light emitting diodes LED may vary depending on the design and size of the display device 1. The third direction (e.g., z-direction) may be substantially perpendicular to a plane defined by the second direction (e.g., x-direction) and the first direction (e.g., y-direction).

[0053] The driving voltage supply line VDL, the common voltage supply line VSL, and the first terminal unit TD1 may be disposed in the peripheral area PA. The driving voltage supply line VDL and the common voltage supply line VSL may be disposed between the display area DA and the first terminal unit TD1.

[0054] The driving voltage supply line VDL may be electrically connected to the driving voltage line VDDL arranged in the display area DA. The driving voltage line VDDL may include a vertical driving voltage line VDDLa extending in a first direction (e.g., the y-direction) and a horizontal driving voltage line VDDLb extending in a second direction (e.g., the x-direction). The horizontal driving voltage line VDDLb and the vertical driving voltage line VDDLa may be connected to each other in the display area DA, and the vertical driving voltage line VDDLa may be electrically connected to the driving voltage supply line VDL located in the peripheral area PA.

[0055] The common voltage supply line VSL may be electrically connected to a common voltage line VSSL disposed in the display area DA. The common voltage line VSSL may include a vertical common voltage line VSSLa extending in a first direction (e.g., the y-direction) and a horizontal common voltage line VSSLb extending in a second direction (e.g., the x-direction). The horizontal common voltage line VSSLb and the vertical common voltage line VSSLa may be connected to each other in the display area DA, and the vertical common voltage line VSSLa may be electrically connected to the common voltage supply line VSL located in the peripheral area PA.

[0056] The first terminal unit TD1 may be positioned on one side of the substrate 100. The printed circuit board 3000 may be attached to and electrically connected to the first terminal unit TD1. The printed circuit board 3000 may include a second terminal unit TD2 electrically connected to the first terminal unit TD1, and the controller 4000 may be located on the printed circuit board 3000. Control signals of the controller 4000 may be provided to the gate driver circuit 1000 disposed in the display area DA, the data driver circuit 2000 disposed in the peripheral area PA, the driving voltage supply line VDL, and the common voltage supply line VSL through the first terminal unit TD1 and the second terminal unit TD2, respectively.

[0057] Unlike the data driver circuit 2000, the gate driver circuit 1000 can be arranged in the display area DA, and thus the area of ​​the peripheral area PA can be relatively reduced. The gate driver circuit 1000 can be arranged on each of the opposite sides of the display area DA. For example, the display area DA can include a first display area DA1 and second display areas DA2 arranged on opposite sides of the first display area DA1, and the gate driver circuit 1000 can be arranged in each of the second display areas DA2. Compared to the first display area DA1, the second display area DA2 can have a relatively small area and can include rounded corners.

[0058] Figure 2 is a schematic diagram showing an arrangement of a display device 1 (see Figure 1 ) display area DA (refer to Figure 1 ) is the equivalent circuit diagram of the driving circuit PC and the light emitting diode LED. Figure 2 Various components of the drive circuit PC according to some embodiments are shown, but the components and structure of the drive circuit PC may vary according to various embodiments. For example, according to some embodiments, the drive circuit PC may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0059] The drive circuit PC can be electrically connected to a first gate line GWL that transmits a first gate signal GW, a second gate line GIL that transmits a second gate signal GI, a third gate line GCL that transmits a third gate signal GC, a fourth gate line EML that transmits a fourth gate signal EM, and a data line DL that transmits a data signal DATA. Because emission of the light-emitting diode LED is controlled by the fourth gate signal EM, the fourth gate signal EM can be referred to as an emission control signal, and the fourth gate line EML can be referred to as an emission control line. The drive circuit PC can also be electrically connected to a drive voltage line VDDL that transmits a drive voltage ELVDD, a reference voltage line VRL that transmits a reference voltage Vref, and an initialization voltage line VIL that transmits an initialization voltage Vint.

[0060] According to some embodiments, the plurality of transistors included in the driver circuit PC may be oxide thin film transistors. The oxide thin film transistors may be low temperature polycrystalline oxide (LTPO) thin film transistors in which the semiconductor layer includes an oxide. However, this is an example, and the transistors disclosed herein are not limited thereto. For example, the semiconductor layer included in the N-type transistor may include an inorganic material semiconductor (e.g., amorphous silicon, polycrystalline silicon) or an organic material semiconductor, etc.

[0061] In some embodiments, the drive circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, a first capacitor C1 and a second capacitor C2, and an auxiliary capacitor Ca. The first transistor T1 may be a drive transistor that outputs a drive current corresponding to the data signal DATA, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be switching transistors that transmit signals. Depending on the voltage of the first terminal and the second terminal, the first terminal (or first electrode) and the second terminal (or second electrode) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be a source (or source electrode) or a drain (or drain electrode), respectively. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node connected to the first-first gate of the first transistor T1 may be defined as a first node N1, and the node connected to the second terminal of the first transistor T1 may be defined as a second node N2.

[0062] The first transistor T1 can be connected to the driving voltage line VDDL and the light emitting diode LED. The first transistor T1 can be connected between the fifth transistor T5 and the light emitting diode LED. The first transistor T1 may include a gate (or gate electrode), a first terminal and a second terminal connected to the second node N2. The first transistor T1 may include a first-first gate connected to the first node N1. The first transistor T1 may also include a first-second gate connected to the second terminal of the first transistor T1. The first-first gate and the first-second gate may be located on different layers to face each other. For example, the first-first gate and the first-second gate of the first transistor T1 may face each other and the semiconductor layer is between the first-first gate and the first-second gate. Hereinafter, when referring to the gate (or gate electrode) of the first transistor T1, it may refer to the first-first gate that participates in turning on and off the first transistor T1.

[0063] The gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The first and second gate electrodes of the first transistor T1 can be connected to the light-emitting diode LED, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the drive voltage line VDDL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the light-emitting diode LED. According to some embodiments, other transistors may be arranged between the first transistor T1 and the pixel electrode of the light-emitting diode LED.

[0064] The first terminal of the first transistor T1 may be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 may be connected to the light emitting diode LED, the first capacitor C1, and the second capacitor C2. The first transistor T1 may receive the data signal DATA according to the switching operation of the second transistor T2 and control the amount of driving current flowing to the light emitting diode LED.

[0065] The second transistor T2 may be connected to the data line DL and the gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 may be connected to the gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 may be turned on by a first gate signal GW transmitted via the first gate line GWL to electrically connect the data line DL to the first node N1, and the data signal DATA transmitted via the data line DL may be transmitted to the first node N1.

[0066] The third transistor T3 may be connected to the gate of the first transistor T1 and a reference voltage line VRL. The third transistor T3 may include a gate connected to a third gate line GCL, a first terminal connected to a first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on by a third gate signal GC transmitted via the third gate line GCL to transmit a reference voltage Vref transmitted via the reference voltage line VRL to the first node N1. Figure 2 The second terminal of the third transistor T3 is shown connected to the reference voltage line VRL, but according to some embodiments, the second terminal of the third transistor T3 may be electrically connected to the gate, first terminal, or second terminal of one of the transistors of the driving circuit PC.

[0067] The fourth transistor T4 may be connected between the first transistor T1 and the initialization voltage line VIL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the initialization voltage line VIL. The fourth transistor T4 may be turned on by a second gate signal GI transmitted through the second gate line GIL to transmit the initialization voltage Vint transmitted through the initialization voltage line VIL to the second node N2.

[0068] The fifth transistor T5 may be connected to the driving voltage line VDDL and the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line VDDL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off according to a fourth gate signal EM transmitted via the fourth gate line EML.

[0069] The first capacitor C1 may be connected between the gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal of the first transistor T1 and the first and second gate electrodes of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the fourth transistor T4. The first capacitor C1 is a storage capacitor that can store the threshold voltage of the first transistor T1 and a voltage corresponding to the data signal DATA.

[0070] When the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 may be turned on. When the voltage of the second terminal of the first transistor T1 drops to the difference (Vref-Vth1) between the reference voltage Vref and the threshold voltage (Vth1) of the first transistor T1, the first transistor T1 may be turned off, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 may be stored in the first capacitor C1, so that the threshold voltage (Vth1) of the first transistor T1 can be compensated.

[0071] The second capacitor C2 may be connected between the driving voltage line VDDL and the second node N2. A first electrode of the second capacitor C2 may be connected to the driving voltage line VDDL. A second electrode of the second capacitor C2 may be connected to the second terminal and the first-second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the fourth transistor T4.

[0072] The capacitance of each of the first capacitor C1 and the second capacitor C2 may vary according to the color of light emitted by the light emitting diode LED.

[0073] The auxiliary capacitor Ca may be electrically connected to the common voltage line VSSL and the pixel electrode of the light emitting diode LED. The auxiliary capacitor Ca may store and maintain a voltage corresponding to a voltage difference between the pixel electrode of the light emitting diode LED and the common voltage line VSSL.

[0074] The light-emitting diode LED can be electrically connected to the first transistor T1. The light-emitting diode LED may include a pixel electrode (anode) and an opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive a common voltage ELVSS. According to some embodiments, the opposite electrode (cathode) may extend to the display area and may be electrically connected to a common voltage line VSSL that provides the common voltage ELVSS. The driving current output by the first transistor T1 may flow through the light-emitting diode LED through the turned-on fifth transistor T5, and the light-emitting diode LED may emit light at a brightness corresponding to the magnitude of the driving current.

[0075] Figure 2 The driving circuit PC is shown to include five transistors and three capacitors, but embodiments of the present disclosure are not limited thereto. According to some embodiments, the driving circuit PC may include six or more transistors or less than five transistors, or may include one or two capacitors.

[0076] Figure 3 is a circuit diagram schematically illustrating a gate driving circuit 1000 according to some embodiments.

[0077] Reference Figure 1 and Figure 3, the gate driver circuit 1000 arranged in the display area DA may include a plurality of stages. For example, the plurality of stages may include a first stage ST1 to an nth stage STn (where n is a natural number of 1 or greater). In some embodiments, each of the first to nth stages ST1 to STn may correspond to a row of driver circuits PC arranged in the second direction (e.g., the x direction) in the display area DA. Each of the first to nth stages ST1 to STn may include at least one transistor and at least one capacitor.

[0078] Each of the first to n-th stages ST1 to STn may output a signal in response to a start signal or a previous signal. The signal output by each of the first to n-th stages ST1 to STn may be a signal applied to a reference signal. Figure 2 According to some embodiments, the signal output by each of the first to n-th stages ST1 to STn may be a gate signal applied to a reference circuit. Figure 2 The scan signal of the pixel circuit PC is described as, for example, one of the first gate signal GW, the second gate signal GI, the third gate signal GC, and the fourth gate signal EM.

[0079] Each of the first to nth stages ST1 to STn may include an input terminal IN, a first clock terminal CK1 , a second clock terminal CK2 , a first voltage input terminal V1 , a second voltage input terminal V2 , a third voltage input terminal V3 , and an output terminal OUT.

[0080] The input terminal IN can receive an external signal STV or a previous signal as a start signal. According to some embodiments, the external signal STV can be applied to the input terminal IN of the first stage ST1, and the previous signal output by the previous stage can be applied to the input terminal IN of each of the second stage ST2 to the nth stage STn except the first stage ST1 as a carry signal. For example, the first stage ST1 can be driven by the external signal STV and generate and output the first signal SG1. The second stage ST2 can be driven by the carry signal (e.g., the first signal SG1) and generate and output the second signal SG2. The second signal SG2 output from the second stage ST2 can be input to the input terminal IN of the third stage ST3, and the third stage ST3 can generate and output the third signal SG3. The third signal SG3 output from the third stage ST3 can be input to the input terminal IN of the fourth stage ST4, and the fourth stage ST4 can generate and output the fourth signal SG4. The n-1th signal output from the n-1th stage can be input to the input terminal IN of the nth stage STn, and the nth stage STn can generate and output the nth signal SGn.

[0081] The first clock signal CLK1 or the second clock signal CLK2 can be applied to the first clock terminal CK1 and the second clock terminal CK2, respectively. According to some embodiments, the first clock signal CLK1 and the second clock signal CLK2 can be alternately applied to the first stage ST1 to the n-th stage STn. For example, the first clock signal CLK1 can be applied to the first clock terminal CK1 of the odd-numbered stage, and the second clock signal CLK2 can be applied to the second clock terminal CK2 of the even-numbered stage. The second clock signal CLK2 can be applied to the first clock terminal CK1 of the even-numbered stage, and the first clock signal CLK1 can be applied to the second clock terminal CK2 of the even-numbered stage.

[0082] The first voltage input terminal V1 can receive a first voltage VGH as a high voltage, and the second voltage input terminal V2 can receive a second voltage VGL as a low voltage. The first voltage VGH and the second voltage VGL can be rated voltages applied to the gate driver circuit 1000. The first voltage VGH and the second voltage VGL can be supplied from the controller 4000 as global signals. The third voltage input terminal V3 can receive a third voltage SESR. The third voltage SESR can be a voltage used to address flickering issues in the display device. In some embodiments, the third voltage SESR can be omitted.

[0083] The output terminal OUT can output a signal. According to some embodiments, the signal can be supplied to the pixel circuit PC via a scan line or a previous scan line as a scan signal or a previous scan signal. Alternatively, the signal can be supplied to the pixel circuit PC via an emission control line as an emission control signal. According to some embodiments, the signal can be supplied to the input terminal IN of the next stage as a carry signal.

[0084] Figure 4 Shown along Figure 1 Schematic cross-sectional views of the display device 1 according to some embodiments, taken along lines IVa-IVa' and IVb-IVb'.

[0085] Reference Figure 4 The display device 1 may include a substrate 100, a gate driving circuit 1000 located on the substrate 100 (refer to Figure 3 ) stage ST, drive circuit PC and light emitting diode LED. Figure 1As described, the display area DA may include a first display area DA1 and a second display area DA2, and the drive circuit PC and the light emitting diode LED may be arranged in the first display area DA1 and the second display area DA2. Hereinafter, the drive circuit PC arranged in the first display area DA1 is referred to as the first drive circuit PC1, the light emitting diode LED arranged in the first display area DA1 is referred to as the first light emitting diode LED1, the drive circuit PC arranged in the second display area DA2 is referred to as the second drive circuit PC2, and the light emitting diode LED arranged in the second display area DA2 is referred to as the second light emitting diode LED2.

[0086] The gate driving circuit 1000 (e.g., stage ST) may be disposed in the second display area DA2 and may overlap with the second driving circuit PC2 and the second light emitting diode LED2. For example, the stage ST may be disposed between the substrate 100 and the second driving circuit PC2, and the second driving circuit PC2 may be disposed between the stage ST and the second light emitting diode LED2.

[0087] The substrate 100 may include a glass material or a polymer resin. According to some embodiments, the substrate 100 may have an alternating stacking structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride. The polymer resin may include a polymer material such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0088] The stage ST may include a transistor TFT' located on the substrate 100. The transistor TFT' may include a semiconductor layer Act' and a gate electrode GE'. In this regard, Figure 4 The gate electrode GE' is shown overlapping the semiconductor layer Act' with the first insulating layer 111 between the gate electrode GE' and the semiconductor layer Act', and the electrode on the second insulating layer 113 is connected to the source region or the drain region of the semiconductor layer Act' through a contact hole penetrating the first insulating layer 111 and the second insulating layer 113. The semiconductor layer Act' may include a silicon-based semiconductor material, for example, polycrystalline silicon. The gate electrode GE' may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single-layer structure or a multilayer structure each including the above materials. Each of the first insulating layer 111 and the second insulating layer 113 may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. According to some embodiments, a buffer layer including an inorganic insulating material may be arranged between the substrate 100 and the transistor TFT' of the stage ST.

[0089] The third insulating layer 115 may be positioned on the transistor TFT' of the stage ST. The third insulating layer 115 may include an inorganic insulating material and / or an organic insulating material.

[0090] The first and second drive circuits PC1 and PC2 may be located on the fourth insulating layer 117. To prevent or reduce signal interference between the stage ST and the second drive circuit PC2, which overlap in the second display area DA2, a conductive layer CML may be disposed between the gate drive circuits 1000, for example, between the stage ST and the second drive circuit PC2. The conductive layer CML may be located on the third insulating layer 115, and the fourth insulating layer 117 may be located on the conductive layer CML. The fourth insulating layer 117 may include an inorganic insulating material and / or an organic insulating material.

[0091] The conductive layer CML may include a conductive material such as Mo, Al, Cu, or Ti, and may include a single-layer structure or a multi-layer structure each including the above materials. The conductive layer CML may overlap with the semiconductor layer Act of each of the first and second drive circuits PC1 and PC2, which will be described in more detail later. In some embodiments, the conductive layer CML may completely overlap with the semiconductor layer Act of each of the first and second drive circuits PC1 and PC2, and may have a width greater than that of the semiconductor layer Act.

[0092] Each of the first driving circuit PC1 and the second driving circuit PC2 may include the above reference Figure 2 description of the transistors and capacitors, and in this regard, Figure 4 A transistor TFT and a first capacitor C1 are shown. In some embodiments, Figure 4 The transistor TFT shown in FIG can be Figure 2 One of the transistors shown in , for example, the first transistor T1 .

[0093] The transistor TFT may include a semiconductor layer Act and a gate electrode GEt. The semiconductor layer Act of the transistor TFT in each of the first drive circuit PC1 and the second drive circuit PC2 may include a material different from the material of the semiconductor layer Act' of the transistor TFT' in the stage ST. The semiconductor layer Act may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer Act may be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer.

[0094] The gate electrode GEt may be located on the semiconductor layer Act with the sixth insulating layer 119 between the gate electrode GEt and the semiconductor layer Act. Figure 2 When describing the two gates, Figure 4 The gate electrode GEt shown in FIG can be the gate electrode of FIG. Figure 2 The first-first gate described above, and the gate electrode GEb located below the semiconductor layer Act (and the fifth insulating layer 118 between the semiconductor layer Act and the gate electrode GEb) may be Figure 2 The first and second gate electrodes are described.

[0095] The first capacitor C1 may include a first electrode CE1 and a second electrode CE2 that overlap each other with a seventh insulating layer 121 therebetween. In some embodiments, the first electrode CE1 may include the same material as the gate electrode GEt. Each of the first electrode CE1 and the second electrode CE2 may include a conductive material such as Mo, Al, Cu, or Ti, and may include a single-layer structure or a multi-layer structure each including the above materials. The seventh insulating layer 121 may include an inorganic insulating material.

[0096] The eighth insulating layer 123 may be located on the first capacitor C1, and the ninth insulating layer 125 may be located on the eighth insulating layer 123. Each of the eighth insulating layer 123 and the ninth insulating layer 125 may include an organic insulating material. The common voltage line VSSL may include a vertical common voltage line VSSLa and a horizontal common voltage line VSSLb, the vertical common voltage line VSSLa and the horizontal common voltage line VSSLb being located on different layers with the eighth insulating layer 123 between them.

[0097] Each of the first light-emitting diode LED1 and the second light-emitting diode LED2 may include a pixel electrode 210, a relative electrode 230, and an intermediate layer 220 between the pixel electrode 210 and the relative electrode 230, wherein the pixel electrode 210 of the first light-emitting diode LED1 and the pixel electrode 210 of the second light-emitting diode LED2 are electrically connected to the first driving circuit PC1 and the second driving circuit PC2, respectively.

[0098] The pixel electrode 210 may be located on the ninth insulating layer 125. The pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. According to some embodiments, the pixel electrode 210 may further include a conductive oxide layer located above and / or below the reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). According to some embodiments, the pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0099] The dam layer 127 may be located on the pixel electrode 210. The dam layer 127 may include an opening that overlaps with the pixel electrode 210, but may cover the edge of the pixel electrode 210. The dam layer 127 may include an organic insulating material. For example, the dam layer 127 may include an organic insulating material containing a light blocking material. In some embodiments, the dam layer 127 may include a polyimide (PI)-based binder and pigments in which red, green, and blue colors are mixed with each other. Alternatively, the dam layer 127 may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. The dam layer 127 may include an inorganic insulating material. For example, the dam layer 127 may include carbon black.

[0100] The intermediate layer 220 may include an emission layer 222. The emission layer 222 may include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color. The emission layer 222 may include a material that emits red light, green light, or blue light.

[0101] The intermediate layer 220 may further include a functional layer located below and / or above the emission layer 222. For example, a first functional layer 221 may be further included between the pixel electrode 210 and the emission layer 222, and a second functional layer 223 may be further included between the emission layer 222 and the opposing electrode 230, which will be described in more detail later. The first functional layer 221 may include a hole transport layer and / or a hole injection layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer.

[0102] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Alternatively, the counter electrode 230 may further include a layer including, for example, ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer including the above materials.

[0103] The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 4 The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 .

[0104] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each be a single layer or multiple layers each including the above materials. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, PI, or polyethylene, etc. According to some embodiments, the organic encapsulation layer 320 may include acrylate.

[0105] The common voltage line VSSL may be located below the pixel electrode 210. The common voltage line VSSL may include a horizontal common voltage line VSSLb and a vertical common voltage line VSSLa, and one of the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa (e.g., the vertical common voltage line VSSLa) may overlap the connection electrode 215. The horizontal common voltage line VSSLb and the vertical common voltage line VSSLa may be connected to each other in the display area DA.

[0106] The connection electrode 215 may be located on the same layer as the pixel electrode 210, for example, on the ninth insulating layer 125. The connection electrode 215 may be connected to a common voltage line VSSL (for example, a vertical common voltage line VSSLa) through a hole penetrating the ninth insulating layer 125. Figure 4 The connection point between the connection electrode 215 and the vertical common voltage line VSSLa and the connection point between the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa are shown overlapping, but embodiments of the present disclosure are not limited thereto. In the display area DA, the connection point between the connection electrode 215 and the vertical common voltage line VSSLa and the connection point between the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa may be arranged at different locations. The connection point between the connection electrode 215 and the vertical common voltage line VSSLa represents a contact hole in the ninth insulating layer 125 for electrically connecting the connection electrode 215 and the vertical common voltage line VSSLa, and the connection point between the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa represents a contact hole in the eighth insulating layer 123 for electrically connecting the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa.

[0107] Figure 4The connection point between the connection electrode 215 and the vertical common voltage line VSSLa and the connection point between the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa are shown to be arranged in the first display area DA1, but the embodiments of the present disclosure are not limited thereto. The connection point between the connection electrode 215 and the vertical common voltage line VSSLa and the connection point between the horizontal common voltage line VSSLb and the vertical common voltage line VSSLa may also be arranged in the second display area DA2.

[0108] Figure 4 The transistor TFT of the driving circuit PC and the first transistor T1 (see Figure 2 ) corresponds to the first transistor T1 is the above reference Figure 2 The driving transistor described above is not limited thereto, but the embodiments of the present disclosure are not limited thereto. The semiconductor layer of another transistor of the driving circuit PC may be connected to Figure 4 The semiconductor layer Act of the transistor TFT is located on the same layer and can be connected with Figure 4 The semiconductor layer Act of the transistor TFT includes the same material, and the gate electrode of another transistor of the driving circuit PC may be connected to Figure 4 The gate electrode GEt of the transistor TFT is located on the same layer and can be connected to the Figure 4 The gate electrode GEt of the transistor TFT includes the same material.

[0109] Figure 5 According to some embodiments Figure 1 Schematic enlarged plan view of a region V of the display device 1 .

[0110] Reference Figure 5 , the display area DA may include a rounded portion. The driving circuits PC arranged in the display area DA may be arranged in a matrix type in a first direction (e.g., y direction) and a second direction (e.g., x direction). In a plan view, the driving circuits PC may be arranged in a stepped configuration along the rounded portion of the display area DA. For example, the second driving circuit PC2 arranged in the second display area DA2 may be arranged along the substrate 100 (refer to FIG. 1 ). Figure 1 ) are arranged in a stepped configuration. In a plan view, the second drive circuits PC2 may be arranged in a first direction (e.g., y direction) and shifted from each other in a second direction (e.g., x direction), and thus the arrangement of the second drive circuits PC2 may have a stepped configuration.

[0111] Figure 5The second drive circuits PC2 are shown arranged in a stepped configuration by uniformly reducing the number of second drive circuits PC2 by two in a first direction (e.g., the y direction). For example, the number of second drive circuits PC2 may be varied, for example, by reducing the number of second drive circuits PC2 by two in the first direction (e.g., the y direction) and then reducing the number of second drive circuits PC2 by four.

[0112] Figure 5 The second drive circuits PC2 are shown as being arranged in a stepped configuration while being reduced by one, then by two, and then by four in the second direction (e.g., the x-direction), but the embodiments of the present disclosure are not limited thereto. For example, the second drive circuits PC2 may be arranged in a stepped configuration by being reduced by a specific number in the second direction (e.g., the x-direction).

[0113] Figure 6 According to some embodiments Figure 5 Display device 1 (refer to Figure 1 ) is a schematic enlarged plan view of region VI.

[0114] Reference Figure 6 , drive circuit PC and gate drive circuit 1000 (see Figure 3 ) may be arranged in the display area DA to overlap with each other. In this regard, Figure 6 A first gate driving circuit, a second gate driving circuit, and a third gate driving circuit arranged in the second display area DA2 are shown. Figure 6 Shown are first stages 1100A, 1100B, 1100C, and 1100D arranged in the second display area DA2 as part of the first gate drive circuit, second stages 1200A and 1200B arranged in the second display area DA2 as part of the second gate drive circuit, and third stages 1300A and 1300B arranged in the third display area DA3 as part of the third gate drive circuit.

[0115] According to some embodiments, first gate signals GW (see FIG. 1 ) may be provided to driving circuits corresponding to the first stages 1100A, 1100B, 1100C, and 1100D, respectively. Figure 2 ), a second gate signal GI may be provided to the driving circuits corresponding to the second stages 1200A and 1200B (refer to Figure 2 ) or the third gate signal GC (refer to Figure 2 ), and can provide a fourth gate signal EM (refer to Figure 2 ).

[0116] The first stages 1100A, 1100B, 1100C, and 1100D may be arranged to correspond to rows of the driving circuits PC and may be arranged along the substrate 100 (refer to FIG. Figure 1 ) of rounded corners 100RE (refer to Figure 5 ) or the rounded corners of the display area DA are arranged in a stepped configuration. For example, two first stages 1100A and 1100B may be arranged on the same line in a first direction (e.g., the y direction), and another two first stages 1100C and 1100D may be arranged on the same line in the first direction (e.g., the y direction), but may be shifted and arranged in a second direction (e.g., the x direction) from the above two first stages 1100A and 1100B. Figure 6 It is shown that two first stages form a group, and each group is arranged in a stepped configuration, but embodiments according to the present disclosure are not limited thereto. In another embodiment, three or more first stages may form a group, and each group may be arranged in a stepped configuration.

[0117] The second stages 1200A and 1200B may be arranged to correspond to the rows of the two drive circuits PC and may be arranged in a stepped configuration along the rounded corners 100RE of the substrate or the rounded corners of the display area DA. The second stages 1200A and 1200B are arranged in a first direction (e.g., the y-direction), but one second stage 1200B may be shifted from the other second stage 1200A and arranged in a second direction (e.g., the x-direction).

[0118] The third stages 1300A and 1300B may be arranged to correspond to the rows of the two drive circuits PC and may be arranged in a stepped configuration along the rounded corners 100RE of the substrate and the rounded corners of the display area DA. The third stages 1300A and 1300B are arranged in a first direction (e.g., the y-direction), but one third stage 1300B may be shifted from the other third stage 1300A and arranged in a second direction (e.g., the x-direction).

[0119] The first stages 1100A, 1100B, 1100C, and 1100D may be arranged in the first display area DA1 (see Figure 5 ) and the second display area DA2 (see Figure 5) provides a gate signal to the transistor of the corresponding driving circuit PC in the driving circuit PC in ). Each of the first stages 1100A, 1100B, 1100C and 1100D can be positioned to correspond to the driving circuit PC of any row and can be electrically connected to the first gate line of the driving circuit PC of each row. According to some embodiments, the first gate line can extend in the second direction (e.g., the x direction). Any one of the first stages 1100A can be positioned to correspond to the driving circuit PC of the (i)th row (i.e., the driving circuit PC arranged in the (i)th row) and can be electrically connected to the first gate line connected to the driving circuit PC of the (i)th row (wherein i is a natural number of 1 or greater). Another first stage 1100B can be positioned to correspond to the driving circuit PC of the (i+1)th row (i.e., the driving circuit PC arranged in the (i+1)th row) and can be electrically connected to the first gate line connected to the driving circuit PC of the (i+1)th row. Another first stage 1100C may be positioned to correspond to the drive circuit PC of the (i+2)th row (i.e., the drive circuit PC arranged in the (i+2)th row) and may be electrically connected to the first gate line connected to the drive circuit PC of the (i+2)th row. Another first stage 1100D may be positioned to correspond to the drive circuit PC of the (i+3)th row and may be electrically connected to the first gate line connected to the drive circuit PC of the (i+3)th row.

[0120] The second stages 1200A and 1200B may be arranged in the first display area DA1 (see Figure 5 ) and the second display area DA2 (see Figure 5 ) provides a gate signal to the transistor of the corresponding drive circuit PC in the drive circuit PC in the second stage 1200A and 1200B. Each of the second stage 1200A and 1200B can be positioned to correspond to a plurality of drive circuits PC in a plurality of rows. The second stage 1200A can be positioned to correspond to the drive circuit PC in the (i)th row and the drive circuit PC in the (i+1)th row. The second stage 1200A can be electrically connected to the second gate line connected to the drive circuit PC in the (i)th row, and can be electrically connected to the third gate line connected to the drive circuit PC in the (i+n)th row (where n is a natural number of 1 or greater). According to some embodiments, each of the second gate line and the third gate line can extend in a second direction (e.g., the x direction).

[0121] The third stages 1300A and 1300B may be arranged in the first display area DA1 (see Figure 5 ) and the second display area DA2 (see Figure 5) provides a gate signal to the transistor of the corresponding driver circuit PC in the driver circuit PC in the third stage 1300A and 1300B. Each of the third stages 1300A and 1300B can be positioned to correspond to multiple driver circuits PC in multiple rows. The third stage 1300A can be positioned to correspond to the driver circuit PC in the (i)th row and the driver circuit PC in the (i+1)th row. The third stage 1300A can be electrically connected to the fourth gate line connected to the driver circuit PC in the (i)th row, and can be electrically connected to the fourth gate line connected to the driver circuit PC in the (i+1)th row. According to some embodiments, the fourth gate line can extend in the second direction (e.g., the x direction).

[0122] The length of each of the first levels 1100A, 1100B, 1100C and 1100C in the first direction (e.g., y direction) may be smaller than the length of each of the second levels 1200A and 1200B in the first direction (e.g., y direction), and the length of each of the second levels 1200A and 1200B in the first direction (e.g., y direction) may be smaller than the length of each of the third levels 1300A and 1300B in the first direction (e.g., y direction).

[0123] The clock signal line PWL arranged in the peripheral area PA can be electrically connected to the corresponding stages of the first to third gate driving circuits to provide electrical signals. Figure 6 It is shown that at least one of the clock signal lines PWL is electrically connected to the first stage 1100A, 1100B, 1100C or 1100D, respectively, through the first signal connection line 1111 . Figure 6 It is shown that at least one further clock signal line PWL is electrically connected to the second stages 1200A and 1200B via a second signal connection line 1222 , and at least one further clock signal line PWL is electrically connected to the third stages 1300A and 1300B via a third signal connection line 1333 .

[0124] The second signal connection line 1222 and / or the third signal connection line 1333 may pass through the display area DA. The second signal connection line 1222 may pass between two adjacent first stages in the display area DA (e.g., the second display area DA2). The third signal connection line 1333 may pass between two adjacent first stages and between two adjacent second stages in the display area DA (e.g., the second display area DA2).

[0125] Reference Figure 6, a group of second signal connection lines 1222 electrically connected to the second stage 1200A may be arranged between the first stage 1100A corresponding to the (i)th row and the first stage corresponding to the previous row (e.g., the (i-1)th row (not shown)). A group of second signal connection lines 1222 electrically connected to the second stage 1200B may be arranged between the first stage 1100B corresponding to the (i+1)th row and the first stage 1100C corresponding to the (i+2)th row as the next row.

[0126] A group of third signal connection lines 1333 electrically connected to the third level 1300A can be arranged between the first level 1100A corresponding to the (i)th row and the first level 1100B corresponding to the (i+1)th row as the subsequent row, and can be arranged between two adjacent second levels 1200A and 1200B.

[0127] A group of third signal connection lines 1333 electrically connected to the third level 1300B can be arranged between the first level 1100C corresponding to the (i+2)th row and the first level 1100D corresponding to the (i+3)th row as the subsequent row, and can be arranged between adjacent second levels (for example, the second level 1200B and other second levels).

[0128] Unlike the clock signal line PWL, the voltage input line may be arranged in the display area DA. Figure 6 A first voltage input line VGH_1 and a second voltage input line VGL_1 electrically connected to the first gate drive circuit, a first voltage input line VGH_2 and a second voltage input line VGL_2 electrically connected to the second gate drive circuit, and a first voltage input line VGH_3 and a second voltage input line VGL_3 electrically connected to the third gate drive circuit are shown passing through the second display area DA2. The first voltage input lines VGH_1, VGH_2, and VGH_3 and the second voltage input lines VGL_1, VGL_2, and VGL_3 can be bent in a plan view to have a stepped shape. In some embodiments, the first voltage input lines VGH_1, VGH_2, and VGH_3 and the second voltage input lines VGL_1, VGL_2, and VGL_3 can be bent in a plan view to have a stepped shape along the stepped configuration of the drive circuit PC. That is, the voltage output lines (or voltage lines) configured to apply voltage to multiple stages can overlap with multiple second drive circuits PC2 in the second display area DA2. The voltage lines can overlap with multiple stages in the second display area DA2. In a plan view, the voltage line may extend in a first direction (eg, a y-direction) and may be bent.

[0129] The carry signal lines electrically connected to two adjacent stages may be bent in a plan view to have a stepped shape. For example, at least one of the first carry signal lines CRL1 electrically connected to two adjacent stages among the first stages 1100A, 1100B, 1100C, and 1100D may be bent in a plan view to have a stepped shape. According to some embodiments, Figure 6 As shown in FIG, the first carry signal line CRL1 between the first stage 1100B of the (i+1)th row and the first stage 1100C of the (i+2)th row may be bent to have a stepped shape in a plan view.

[0130] Similarly, the second carry signal line CLR2 electrically connected to the adjacent second stages 1200A and 1200B may be bent in a plan view to have a stepped shape. According to some embodiments, the third carry signal line CRL3 electrically connected to the third stages 1300A and 1300B may be bent in a plan view to have a stepped shape.

[0131] Figure 7 is a display device 1 according to some embodiments (see Figure 1 ) is a cross-sectional view of a portion of ).

[0132] Reference Figure 7 , the gate signal generated from each stage ST of the driving circuit in the second display area DA2 may be output through the output signal line OSL, and the output signal line OSL may be electrically connected to the gate line GL in the peripheral area PA.

[0133] In some embodiments, the output signal line OSL may be electrically connected to the gate line GL through a connection metal (or connection member) CM in the peripheral area PA, and the gate signal generated from each stage ST may be provided to the gate line GL through the electrical connection structure of the output signal line OSL, the connection metal CM, and the gate line GL. Figure 6 The drive circuits PC shown in FIG are arranged in the same row.

[0134] Figure 7 The level ST can be referred to above Figure 6 One of the described first stages 1100A, 1100B, 1100C, and 1100D, one of the second stages 1200A and 1200B, or one of the third stages 1300A and 11300B.

[0135] For example, when Figure 6 The level ST is the above reference Figure 6 When the first stage 1100A is described as being arranged in the (i)th row, the first gate signal output from the stage ST (or the first stage 1100A) can be transmitted to the driving circuit PC in the (i)th row through the output signal line OSL, the electrical connection structure connecting the metal CM and the gate line GL (e.g., the first gate line).

[0136] According to some embodiments, when the stage ST is above referenced Figure 6 When the second stage 1200A is described, the gate signal output from the stage ST (e.g., the second stage 1200A) can be provided as a second gate signal to the driver circuit PC in the (i)-th row via the output signal line OSL, the electrical connection structure connecting the metal CM and the gate line GL (e.g., the second gate line in the (i)-th row). The gate signal output from the stage ST (e.g., the second stage 1200A) can be provided as a third gate signal to the driver circuit PC in the (i+n)-th row via the output signal line OSL, the electrical connection structure connecting the metal CM and the gate line GL (e.g., the third gate line in the (i+n)-th row).

[0137] For example, when the level ST is above the reference Figure 6 When describing the third stage 1300A, the gate signal output from the stage ST (e.g., the third stage 1300A) can be provided as a fourth gate signal to the driver circuit PC in the (i)-th row via the output signal line OSL, the electrical connection structure connecting the metal CM and the gate line GL (e.g., the fourth gate line in the (i)-th row). The gate signal output from the stage ST (e.g., the third stage 1300A) can be provided to the driver circuit PC in the (i+1)-th row via the output signal line OSL, the electrical connection structure connecting the metal CM and the gate line GL (e.g., the fourth gate line in the (i+1)-th row).

[0138] According to some embodiments, the area of ​​the useless area outside the display area can be relatively reduced, and the stages can be arranged while effectively utilizing the space of the display area. However, these effects are examples, and the scope of the embodiments according to the present disclosure is not limited thereto.

[0139] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a substrate comprising a display area including rounded corners and a peripheral area outside the display area, wherein the display area comprises a first display area and a second display area between the first display area and the peripheral area; a plurality of first driving circuits, in the first display area; a plurality of first light emitting diodes, electrically connected to the plurality of first driving circuits respectively; a plurality of second driving circuits, in the second display area; a plurality of second light emitting diodes, electrically connected to the plurality of second driving circuits respectively; a plurality of gate lines electrically connected to the plurality of first driving circuits and the plurality of second driving circuits; and a plurality of stages in the second display area and electrically connected to the plurality of gate lines, The plurality of levels are arranged in a stepped configuration along the rounded corners of the display area in a plan view.

2. The display device according to claim 1, wherein A voltage line configured to apply voltages to the plurality of stages overlaps the plurality of second driving circuits in the second display area.

3. The display device according to claim 2, wherein The voltage line overlaps the plurality of stages in the second display area.

4. The display device according to claim 2, wherein The voltage line is bent to have a stepped shape in the plan view.

5. The display device according to claim 1, wherein Each of the plurality of first drive circuits and the plurality of second drive circuits comprises: driver transistors; a first transistor; and a second transistor, the first transistor and the second transistor being electrically connected to the driving transistor, Wherein, the multiple levels include: a plurality of first stages each configured to provide a gate signal to the first transistor of a corresponding first driver circuit and second driver circuit among the plurality of first driver circuits and the plurality of second driver circuits; and A plurality of second stages are each configured to provide a gate signal to the second transistor of a corresponding first driver circuit and second driver circuit in the plurality of first driver circuits and the plurality of second driver circuits. The display device according to claim 5 , wherein: In the plan view, one of two adjacent first stages among the plurality of first stages is arranged in a first direction with the other of the two adjacent first stages, and the one of the two adjacent first stages among the plurality of first stages is shifted from the other of the two adjacent first stages in a second direction intersecting the first direction, and In the plan view, one of two adjacent second levels among the multiple second levels is arranged in the first direction with the other of the two adjacent second levels, and the one of the two adjacent second levels among the multiple second levels is shifted from the other of the two adjacent second levels in the second direction.

7. The display device according to claim 6, wherein A length of each of the plurality of first stages in the first direction is different from a length of each of the plurality of second stages in the first direction.

8. The display device according to claim 6, wherein The display device further includes a plurality of clock signal lines, wherein the plurality of clock signal lines are in the peripheral area. A signal connection line connecting one of the plurality of clock signal lines to a corresponding second stage of the plurality of second stages passes in the second display area and between the two adjacent first stages.

9. The display device according to claim 5, wherein A carry signal line between two adjacent first stages among the plurality of first stages or a carry signal line between two adjacent second stages among the plurality of second stages is bent in the plan view.

10. The display device according to claim 1, wherein One of the plurality of stages provides a gate signal to a corresponding gate line of the plurality of gate lines via an output signal line, The output signal line and the corresponding gate line among the plurality of gate lines are electrically connected to each other in the peripheral region.

11. A display device, wherein: The display device comprises: a substrate comprising a display area including rounded corners and a peripheral area outside the display area, wherein the display area comprises a first display area and a second display area between the first display area and the peripheral area; a plurality of driving circuits in the first display area and the second display area; a plurality of light emitting diodes on the plurality of driving circuits, and the plurality of light emitting diodes are electrically connected to the plurality of driving circuits; and a plurality of first stages interposed between the substrate and the plurality of driving circuits, and the plurality of first stages are configured to provide first gate signals to the plurality of driving circuits, The plurality of first levels are in the second display area, and the plurality of first levels are arranged in a stepped configuration along the rounded corners of the display area in a plan view.

12. The display device according to claim 11, wherein A voltage line configured to apply a voltage to the plurality of first stages overlaps the plurality of driving circuits in the second display area.

13. The display device according to claim 12, wherein The voltage line overlaps the plurality of first levels in the second display area.

14. The display device according to claim 12, wherein The voltage line extends in a first direction and is bent in the plan view.

15. The display device according to claim 11, wherein The display device further includes a plurality of second stages in the second display area and configured to provide second gate signals to the plurality of driving circuits. Wherein, the plurality of second levels are arranged in a stepped configuration in the plan view.

16. The display device according to claim 15, wherein In the plan view, the plurality of second levels are between the plurality of first levels and the first display area, and A length of each of the plurality of first stages in the first direction is different from a length of each of the plurality of second stages in the first direction.

17. The display device according to claim 16, wherein: The length of each of the plurality of first stages in the first direction is smaller than the length of each of the plurality of second stages in the first direction.

18. The display device according to claim 15, wherein The display device further includes a plurality of clock signal lines, wherein the plurality of clock signal lines are in the peripheral area. A signal connection line connecting one of the plurality of clock signal lines to a corresponding second stage among the plurality of second stages passes in the second display area and between two adjacent first stages among the plurality of first stages.

19. The display device according to claim 15, wherein A carry signal line between two adjacent first stages among the plurality of first stages or a carry signal line between two adjacent second stages among the plurality of second stages is bent in the plan view.

20. The display device according to claim 11, wherein The display device further includes a first gate line electrically connected to the plurality of driving circuits. wherein one of the plurality of first stages is configured to provide the first gate signal to the first gate line via an output signal line, and The output signal line and the first gate line are electrically connected to each other in the peripheral area.

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