Display device, mother substrate, and method for manufacturing display device

Abstract

The invention relates to a display device, a mother substrate, and a manufacturing method of the display device. According to one embodiment, a display device includes: a substrate; a first inorganic insulating layer disposed over the substrate over a display region in which an image is displayed and a peripheral region outside the display region; an organic insulating layer disposed on the first inorganic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer; a display element disposed in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls disposed in the peripheral region; and a second sealing layer formed of an inorganic insulating material and disposed across the display region and the peripheral region, the organic insulating layer having a first through portion in the peripheral region, and the plurality of peripheral partition walls each having a first lower portion disposed in the first through portion and a first upper portion disposed above the first lower portion and covered by the second sealing layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-041113 filed on March 15, 2024, and incorporates by reference all the contents disclosed in that Japanese patent application. Technical Field

[0003] Embodiments of the present invention relate to a display device, a mother substrate, and a method for manufacturing the display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display elements comprise a pixel circuit consisting of a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer and functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the Invention

[0006] An object of the embodiment is to provide a display device, a mother substrate, and a method for manufacturing a display device that can suppress a decrease in reliability.

[0007] According to one embodiment, a display device includes: a substrate; a first inorganic insulating layer, which is arranged above the substrate over a display area displaying an image and a peripheral area outside the display area; an organic insulating layer, which is arranged on the first inorganic insulating layer; a second inorganic insulating layer, which is arranged on the organic insulating layer; a display element, which is arranged in the display area; a first sealing layer, which is formed of an inorganic insulating material and covers the display element; a plurality of peripheral partitions, which are arranged in the peripheral area; and a second sealing layer, which is formed of an inorganic insulating material and arranged over the display area and the peripheral area, the organic insulating layer having a first through portion in the peripheral area, the plurality of peripheral partitions respectively having a first lower portion arranged in the first through portion and a first upper portion arranged above the first lower portion, and being covered by the second sealing layer.

[0008] According to one embodiment, a mother substrate includes: a panel portion, the panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion, the blank portion being on the outside of the panel portion; a first inorganic insulating layer, the first inorganic insulating layer being arranged throughout the panel portion and the blank portion; an organic insulating layer, the organic insulating layer being arranged on the first inorganic insulating layer; a second inorganic insulating layer, the second inorganic insulating layer being arranged on the organic insulating layer; a display element, the display element being arranged in the display area; a first sealing layer, the first sealing layer being formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions, the plurality of peripheral partitions being arranged in the blank portion; and a second sealing layer, the second sealing layer being formed of an inorganic insulating material and being arranged throughout the panel portion and the blank portion, the organic insulating layer having a first through portion in the blank portion, the plurality of peripheral partitions respectively having a first lower portion arranged on the first through portion and a first upper portion arranged above the first lower portion, and being covered by the second sealing layer.

[0009] According to one embodiment, in a method for manufacturing a display device, a processing substrate is prepared, wherein the processing substrate includes a first inorganic insulating layer extending over a display area displaying an image and a peripheral area outside the display area, an organic insulating layer located above the first inorganic insulating layer, a second inorganic insulating layer located above the organic insulating layer, a display element located in the display area, a plurality of peripheral partitions located in the peripheral area, and a first sealing layer covering the display element and exposing the peripheral partitions. The second sealing layer extending over the display area and the peripheral area is formed using an inorganic insulating material, and patterning when forming the organic insulating layer includes a process of forming a first through portion in the peripheral area, wherein the plurality of peripheral partitions respectively include a first lower portion arranged on the first through portion and a first upper portion arranged above the first lower portion, and are covered by the second sealing layer.

[0010] According to the embodiment, a display device, a mother substrate, and a method for manufacturing a display device capable of suppressing a decrease in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0012] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0013] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0014] Figure 41 is a plan view showing an example of the shape of the insulating layer 12 in the display device DSP.

[0015] Figure 5 1 is a plan view showing an example of the shape of the sealing layer 14 in the display device DSP.

[0016] Figure 6 1 is a plan view showing an example of the motherboard 100 .

[0017] Figure 7 1 is a plan view showing an example of the motherboard 100 .

[0018] Figure 8 It is a top view showing a configuration example of the pad PD.

[0019] Figure 9 It is along Figure 6 Schematic cross-sectional view of the mother substrate 100 taken along line GH in FIG.

[0020] Figure 10 It is along Figure 5 A schematic cross-sectional view of the display panel PNL taken along line CD in FIG.

[0021] Figure 11 Yes Figure 9 The mother substrate 100 and Figure 10 1 is a cross-sectional view of a configuration example of a region 100A of each display panel PNL.

[0022] Figure 12 Yes Figure 9 The mother substrate 100 and Figure 10 1 and 2 are cross-sectional views of other configuration examples of the regions 100A of the display panels PNL shown.

[0023] Figure 13 Yes Figure 9 The mother substrate 100 and Figure 10 FIG. 1 is a cross-sectional view showing a configuration example of another region of the display panel PNL.

[0024] Figure 14 It means along Figure 8 A cross-sectional view of an example of the structure of the pad PD of the EF line.

[0025] Figure 15 It means along Figure 8 A cross-sectional view of another configuration example of the pad PD of the EF line.

[0026] Figure 16 It is a plan view showing a configuration example of the peripheral partition wall 7 in the through portion 12T.

[0027] Figure 17 It means along Figure 16 sectional view of a configuration example of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line IJ in FIG.

[0028] Figure 18 It means along Figure 16 sectional view of another configuration example of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the IJ line in FIG.

[0029] Figure 19 It is a plan view showing another configuration example of the peripheral partition wall 7 in the through portion 12T.

[0030] Figure 20 It is a diagram for explaining a method of manufacturing the display device DSP.

[0031] Figure 21 It is a diagram for explaining a method of manufacturing the display device DSP.

[0032] Figure 22 It is a diagram for explaining a method of manufacturing the display device DSP.

[0033] Figure 23 It is a diagram for explaining a method of manufacturing the display device DSP.

[0034] Figure 24 It is a diagram for explaining a method of manufacturing the display device DSP.

[0035] Figure 25 It is a diagram for explaining a method of manufacturing the display device DSP.

[0036] Figure 26 It is a diagram for explaining a method of manufacturing the display device DSP.

[0037] Figure 27 It is a diagram for explaining a method of manufacturing the display device DSP.

[0038] Figure 28 It is a diagram for explaining a method of manufacturing the display device DSP.

[0039] Figure 29 It is a diagram for explaining a method of manufacturing the display device DSP.

[0040] Figure 30 It is a diagram for explaining a method of manufacturing the display device DSP.

[0041] Figure 31 It is a diagram for explaining a method of manufacturing the display device DSP.

[0042] Figure 32 It is a diagram for explaining a method of manufacturing the display device DSP.

[0043] Figure 33It is a diagram for explaining a method of manufacturing the display device DSP.

[0044] Figure 34 It is a diagram for explaining a method of manufacturing the display device DSP.

[0045] Figure 35 It is a diagram for explaining a method of manufacturing the display device DSP. DETAILED DESCRIPTION

[0046] The embodiments will be described with reference to the drawings.

[0047] The disclosure is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the essence of the invention are naturally within the scope of the present invention. Furthermore, in the drawings, the widths, thicknesses, shapes, and other aspects of various components may be schematically illustrated to clarify the description, compared to actual dimensions. However, this is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, components that perform the same or similar functions as those described in connection with previously mentioned drawings are denoted by the same reference numerals, and repeated detailed descriptions may be omitted as appropriate.

[0048] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are depicted as necessary to facilitate understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a top-down view.

[0049] The display device according to this embodiment is an organic electroluminescent display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0050] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0051] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0052] In this embodiment, the shape of the substrate 10 in a plan view is a rectangle. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0053] The display area DA includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP. In one example, each pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first, second, and third colors are different from one another. It should be noted that the pixel PX may also include a sub-pixel SP of another color, such as white, in addition to or in place of the sub-pixels SP1, SP2, and SP3.

[0054] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0055] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0056] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0057] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0058] The peripheral area SA includes a terminal area TA. The terminal area TA includes a plurality of terminals TE and pads PD arranged along one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends along a second direction Y, but this is not limited to this. Such plurality of terminals TE can be electrically connected to, for example, a flexible printed circuit board or an IC chip. The pads PD can be electrically connected to, for example, an inspection device. It should be noted that the pads PD can also be omitted in the display device DSP.

[0059] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0060] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged along the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged along the first direction X. The sub-pixel SP1 and the sub-pixel SP3 are arranged along the first direction X.

[0061] When the sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA includes columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which a plurality of sub-pixels SP1 are arranged along the second direction Y. These columns are alternately arranged in the first direction X.

[0062] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may also be arranged in sequence along the first direction X.

[0063] In the display area DA, an inorganic insulating layer 5 and partitions 6 are provided. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0064] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 may also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the inorganic insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of terminals TE shown, terminals TE of common potential are electrically connected.

[0065] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 , respectively, as display elements DE.

[0066] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the opening AP1. The periphery of the lower electrode LE1 is covered by an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 that constitute the display element DE1 are surrounded by a partition wall 6 when viewed from above. The periphery of each of the organic layer OR1 and the upper electrode UE1 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0067] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The periphery of the lower electrode LE2 is covered by an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 that constitute the display element DE2 are surrounded by a partition wall 6 when viewed from above. The periphery of the organic layer OR2 and the upper electrode UE2 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR2 includes a light-emitting layer that emits light in the green wavelength range, for example.

[0068] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The periphery of the lower electrode LE3 is covered by an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 that constitute the display element DE3 are surrounded by a partition wall 6 when viewed from above. The periphery of each of the organic layer OR3 and the upper electrode UE3 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0069] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. It should be noted that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the illustrations do not necessarily reflect their exact shapes.

[0070] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element and are in contact with the barrier ribs 6 .

[0071] The lower electrode LE1 and the pixel circuit 1 of the sub-pixel SP1 (refer to Figure 1 The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0072] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different. Opening AP1 is larger than opening AP2, and opening AP2 is larger than opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0073] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0074] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The various circuits shown include the pixel circuit 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The inorganic insulating layer 111 included in the circuit layer 11 is covered with the insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens the unevenness generated in the circuit layer 11.

[0075] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 Omitted in .

[0076] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0077] In the illustrated example, the lower portion 61 includes a base layer 63 disposed on the inorganic insulating layer 5 and a shaft layer 64 disposed between the base layer 63 and the upper portion 62. The base layer 63 is thinner than the shaft layer 64. The base layer 63 has a greater width than the shaft layer 64. Both ends of the base layer 63 protrude from the side surfaces of the shaft layer 64.

[0078] The upper portion 62 includes a thin film 65 disposed on the shaft layer 64 and a thin film 66 disposed on the thin film 65. The upper portion 62 has a width greater than that of the shaft layer 64. Both ends of the upper portion 62 protrude from the side surfaces of the shaft layer 64. In this specification, the side surfaces of the shaft layer 64 are defined as surfaces in the shaft layer 64 that extend between the bottom layer 63 and the upper portion 62.

[0079] In the example shown in the figure, the upper portion 62 has a larger width than the bottom portion 63. It should be noted that the bottom portion 63 may also have a larger width than the upper portion 62.

[0080] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 and covers the lower electrode LE1 exposed from the opening AP1 . The peripheral portion of the organic layer OR1 is located on the inorganic insulating layer 5 . The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61 .

[0081] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 and covers the lower electrode LE2 exposed from the opening AP2 . The peripheral portion of the organic layer OR2 is located above the inorganic insulating layer 5 . The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61 .

[0082] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 and covers the lower electrode LE3 exposed from the opening AP3 . The peripheral portion of the organic layer OR3 is located above the inorganic insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0083] It should be noted that the so-called contact between the upper electrodes UE1, UE2, and UE3 and the lower portion 61 includes the case where the upper electrodes UE1, UE2, and UE3 are in direct contact with the upper surface of the bottom layer 63, and the case where the upper electrodes UE1, UE2, and UE3 are in direct contact with the upper surface of the bottom layer 63 and in direct contact with the side surface of the shaft layer 64. In this specification, the so-called upper surface of the bottom layer 63 is defined as including the surface of the bottom layer 63 that is in direct contact with the shaft layer 64 and the surface that protrudes from the shaft layer 64 and is opposite to the upper portion 62.

[0084] In the illustrated example, subpixel SP1 includes cap layer CP1 and sealing layer SE1, subpixel SP2 includes cap layer CP2 and sealing layer SE2, and subpixel SP3 includes cap layer CP3 and sealing layer SE3. Cap layers CP1, CP2, and CP3 serve as optical adjustment layers, improving the efficiency of light extraction from organic layers OR1, OR2, and OR3, respectively. It should be noted that cap layers CP1, CP2, and CP3 may also be omitted.

[0085] The cap layer CP1 is disposed on the upper electrode UE1 .

[0086] The cap layer CP2 is disposed on the upper electrode UE2.

[0087] The cap layer CP3 is disposed on the upper electrode UE3.

[0088] The sealing layer SE1 is disposed on the cap layer CP1, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP1. Specifically, the sealing layer SE1 is in contact with the shaft layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE1.

[0089] The sealing layer SE2 is disposed on the cap layer CP2, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP2. Specifically, the sealing layer SE2 is in contact with the axial layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE2.

[0090] The sealing layer SE3 is disposed on the cap layer CP3, in contact with the partition wall 6, and continuously covers the components of the sub-pixel SP3. In other words, the sealing layer SE3 is in contact with the axial layer 64 and the upper portion 62 of the partition wall 6 surrounding the display element DE3.

[0091] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0092] In the example shown in the figure, a portion of the laminated film FL1 is located on the partition wall 6 around the sub-pixel SP1 and is separated from the laminated film FL1 located in the opening AP1 (a portion constituting the display element DE1 ).

[0093] Similarly, a portion of the stacked film FL2 is located on the partition wall 6 around the sub-pixel SP2 and is separated from the stacked film FL2 located at the opening AP2 (a portion constituting the display element DE2 ).

[0094] Similarly, a portion of the stacked film FL3 is located on the partition wall 6 around the sub-pixel SP3 and is separated from the stacked film FL3 located at the opening AP3 (a portion constituting the display element DE3 ).

[0095] In addition, the laminated films FL1, FL2, and FL3 on the partition walls 6 may be omitted. In this case, a cavity is formed between the sealing layers SE1, SE2, and SE3 and the partition walls 6.

[0096] The ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the illustrated example, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. Furthermore, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0097] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. If cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, these cavities are filled with the resin layer 13. The resin layer 13 is covered with a sealing layer 14. The wiring TL is arranged above the sealing layer 14, for example, directly above the partition wall 6. Such wiring TL functions as sensor wiring for detecting objects approaching the display device DSP, for example. The sealing layer 14 and the wiring TL are covered with a resin layer 15.

[0098] The inorganic insulating layer 111 , the inorganic insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0099] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material, such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, such as an aluminum-based material, such as aluminum or an aluminum compound.

[0100] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a different material from the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0101] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0102] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range.

[0103] In addition, the organic layers OR1, OR2, and OR3 respectively include multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0104] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0105] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0106] The wiring TL is formed of a metal material such as aluminum, titanium, or molybdenum. In one example, the wiring TL is a multilayer structure including an aluminum layer between a pair of titanium layers.

[0107] The circuit layer 11 , the insulating layer 12 , and the inorganic insulating layer 5 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0108] Figure 4 FIG. 1 is a top view showing an example of the shape of the insulating layer 12 in the display device DSP. Figure 4 , the configuration required for explanation is shown, and details of the terminal area TA are omitted.

[0109] The insulating layer 12 overlaps the display area DA and extends toward the peripheral area SA. The insulating layer 12 has a through portion 12T penetrating the peripheral area SA to expose its base layer. The through portion 12T is formed in a ring shape along the end portion 10E.

[0110] The plurality of dam portions DM are insulating layers formed of the same material as the insulating layer 12, and may be a single layer or a multilayer structure of multiple insulating layers. The plurality of dam portions DM are arranged in the peripheral area SA and are formed in a ring shape surrounding the insulating layer 12. In the illustrated example, there are two dam portions DM, but three or more dam portions DM may be provided.

[0111] In addition, in the example shown in the figure, the through portion 12T and the dam portion DM are each formed in a rectangular frame shape, but may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0112] The dam portion (inner dam portion) DM adjacent to the insulating layer 12 is separated from the insulating layer 12. Furthermore, the plurality of dam portions DM are arranged at intervals. The through portion 12T includes regions between the insulating layer 12 and the inner dam portion DM, between adjacent dam portions DM, and between the outermost dam portion (outer dam portion) DM and the end portion 10E of the substrate 10.

[0113] Figure 5 1 is a top view showing an example of the shape of the sealing layer 14 in the display device DSP. Figure 5 , the configuration required for explanation is shown, and details of the terminal area TA are omitted.

[0114] The sealing layer 14 is disposed throughout the display area DA and the peripheral area SA. The sealing layer 14 has a through portion 14T extending through the peripheral area SA, exposing its base layer. The through portion 14T is formed in a ring shape, surrounding the display area DA. In the illustrated example, the through portion 14T is located between the outer dam portion DM and the end portion 10E of the substrate 10. When viewed from above, the through portion 14T overlaps the outer dam portion DM and the outermost through portion 12T. Meanwhile, the sealing layer 14 overlaps the insulating layer 12, the area between the insulating layer 12 and the inner dam portion DM, and the area between adjacent dam portions DM.

[0115] In addition, in the example shown in the figure, the through portion 14T is formed in a rectangular frame shape, but may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0116] Next, a mother substrate for a display device (hereinafter simply referred to as a mother substrate) 100 for collectively manufacturing a plurality of display devices DSP will be described.

[0117] Figure 6 1 is a plan view showing an example of the motherboard 100 .

[0118] The motherboard 100 includes a plurality of panel portions PP and a blank portion MP outside the panel portions PP on a large substrate 10. The large substrate 10 is formed in a rectangular shape, for example. The plurality of panel portions PP are removed by cutting the motherboard 100 along cutting lines.

[0119] The panel parts PP taken out are respectively equivalent to, for example Figure 1 The display panel PNL shown in FIG. 1 includes a display area DA and a peripheral area SA. The peripheral area SA has a display area DA and a peripheral area SA. Figure 1 The plurality of terminals TE and pads PD shown are arranged in the terminal area TA. The plurality of wirings TL are respectively arranged in the display area DA, drawn out to the peripheral area SA, and electrically connected to the terminals TE included in the terminal area TA.

[0120] The blank portion MP has, for example, a plurality of pads PD electrically connected to a test element group (Test Element Group) and the like.

[0121] Figure 7 1 is a plan view showing an example of the motherboard 100 .

[0122] The cut line CL for removing the panel portion PP is indicated by a dashed line in the figure. A through portion 12T is formed in each panel portion PP between the insulating layer 12 and the dam portion DM, as well as between adjacent dam portions. Furthermore, the through portion 12T is located at a location that straddles the panel portion PP and the blank portion MP, forming a ring shape surrounding each panel portion PP and overlapping the cut line CL.

[0123] Figure 8 1 is a top view showing an example of the structure of the pad PD. The pad PD shown in the figure is equivalent to Figure 1 The pad PD of the peripheral area SA shown or Figure 6 The pad PD of the blank portion MP is shown.

[0124] The metal layer MT indicated by the dashed line corresponds to the electrode of the pad PD. The metal layer MT overlaps with the opening 5AP in the inorganic insulating layer 5, the through-hole 12T in the insulating layer 12, and the through-hole 14T in the sealing layer 14, and is exposed through the opening 5AP. A portion of the sealing layer 14 is located between the edge of the opening 5AP and the edge of the through-hole 12T.

[0125] Figure 9 It is along Figure 6 Schematic cross-sectional view of the mother substrate 100 taken along line GH in FIG.

[0126] Inorganic insulating layer 111 included in circuit layer 11 is disposed over panel portion PP and blank portion MP. Insulation layer 12 and dam portion DM are disposed on inorganic insulating layer 111. Inorganic insulating layer 5 is disposed over panel portion PP and blank portion MP, covering insulating layer 12 and dam portion DM. Inorganic insulating layer 5 is in contact with inorganic insulating layer 111 in through portion 12T.

[0127] Although the partition walls 6 are shown in simplified form, they are disposed on the inorganic insulating layer 5 in the display area DA. Although the plurality of peripheral partition walls 7 are shown in simplified form, they are disposed on the inorganic insulating layer 5 in the peripheral area SA of the panel portion PP and in the blank portion MP. A portion of the plurality of peripheral partition walls 7 is disposed in the through-holes 12T. For example, near the cut line CL, the peripheral partition walls 7 are disposed in the through-holes 12T of the peripheral area SA and also in the through-holes 12T of the blank portion MP.

[0128] The sealing layer SE1 is disposed on the partition wall 6 in the display area DA. Figure 9 Although not shown, the other sealing layers SE2 and SE3 are also arranged in the display area DA. Figure 3 As described.

[0129] The resin layer 13 is arranged in the display area DA and also in the peripheral area SA, and has an end portion near the dam portion DM.

[0130] The sealing layer 14 is arranged throughout the panel portion PP and the blank portion MP. The sealing layer 14 covers the resin layer 13 in the panel portion PP and contacts the inorganic insulating layer 5 in the through-portion 12T. In the illustrated example, the sealing layer 14, as part of the through-portion 12T, contacts the inorganic insulating layer 5 between adjacent dam portions DM. In other words, a multilayer structure is formed in which the inorganic insulating layer 111, the inorganic insulating layer 5, and the sealing layer 14 are stacked in sequence, with no organic insulating material interposed therebetween. This multilayer structure is formed so as to surround the display area DA. Furthermore, this multilayer structure forms a moisture barrier region that blocks the path of moisture that may infiltrate from the outside through the organic insulating material.

[0131] The through-portion 14T of the sealing layer 14 is located in the peripheral area SA, formed closer to the dicing line CL than the moisture blocking area, exposing the inorganic insulating layer 5. In the illustrated example, the through-portion 14T overlaps the inclined surface of the dam portion DM. The sealing layer 14 also covers the peripheral partition wall 7 in the peripheral area SA and the margin MP.

[0132] The wiring TL is arranged on the sealing layer 14 in the display area DA. The resin layer 15 is arranged in the panel portion PP, covers the sealing layer 14 and the wiring TL, and has an end portion on the outside of the resin layer 13. In the example shown in the figure, the resin layer 15 is also arranged in the blank portion MP beyond the cutting line CL and has an end portion in the through portion 12T. In the through portion 14T, the resin layer 15 is in contact with the inorganic insulating layer 5. In addition, the resin layer 15 overlaps on the peripheral partition wall 7 located in the through portion 12T. It should be noted that when the resin layer 15 has an end portion near the cutting line CL, the resin layer 15 does not overlap on the peripheral partition wall 7 located on the side of the blank portion MP with respect to the cutting line CL.

[0133] According to this configuration example, when the mother substrate 100 is cut along the cutting line CL, even if a crack forms in the sealing layer 14 near the cutting line CL, the crack can be suppressed from extending into the through-portion 14T. Consequently, the crack is suppressed from extending into the moisture barrier region formed in the through-portion 12T between the through-portion 14T and the display area DA. Consequently, the intrusion of moisture into the display area DA is suppressed, thereby preventing a decrease in reliability.

[0134] Figure 10 It is along Figure 5 A schematic cross-sectional view of the display panel PNL taken along line CD in FIG.

[0135] The end portion 10E of the substrate 10 in the figure corresponds to Figure 9 The position of the cutting line CL of the mother substrate 100 shown. The through portion 12T is formed in the peripheral area SA. The inorganic insulating layer 5 is in contact with the inorganic insulating layer 111 in the through portion 12T. The peripheral partition wall 7 is arranged on the inorganic insulating layer 5 in the through portion 12T. The sealing layer 14 is in contact with the inorganic insulating layer 5 in the through portion 12T and covers the peripheral partition wall 7. The through portion 14T of the sealing layer 14 is located in the peripheral area SA, overlaps with the inclined surface of the dam portion DM, and exposes the inorganic insulating layer 5. In the through portion 12T between the through portion 14T and the display area DA, a moisture barrier region is formed as a multilayer body of the inorganic insulating layer 111, the inorganic insulating layer 5 and the sealing layer 14. The resin layer 15 is in contact with the inorganic insulating layer 5 in the through portion 14T.

[0136] Figure 11 Yes Figure 9 The mother substrate 100 and Figure 10 1 is a cross-sectional view of a configuration example of a region 100A of each display panel PNL.

[0137] The peripheral partition wall 7 includes a lower portion 71 disposed on the inorganic insulating layer 5 in the through portion 12T and an upper portion 72 disposed on the lower portion 71. The lower portion 71 includes a base layer 73 disposed on the inorganic insulating layer 5 and an axial layer 74 disposed between the base layer 73 and the upper portion 72. The upper portion 72 includes a thin film 75 disposed on the axial layer and a thin film 76 disposed on the thin film 75.

[0138] The bottom layer 73 is thinner than the shaft layer 74. The bottom layer 73 has a greater width than the shaft layer 74. Both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74. The upper portion 72 has a greater width than the shaft layer 74. Both ends of the upper portion 72 protrude from the side surfaces of the shaft layer 74. In the illustrated example, the upper portion 72 has a greater width than the bottom layer 73, but the bottom layer 73 may also have a greater width than the upper portion 72.

[0139] The peripheral partition wall 7 can be formed by the same process as the above-mentioned partition wall 6. In this case, the bottom layer 73 is formed of the same material as the bottom layer 63, the shaft layer 74 is formed of the same material as the shaft layer 64, the film 75 is formed of the same material as the film 65, and the film 76 is formed of the same material as the film 66.

[0140] The sealing layer 14 contacts the bottom layer 73, the shaft layer 74, and the upper portion 72, and covers the entire peripheral partition wall 7. Thus, the peripheral partition wall 7 is covered by the sealing layer 14, thereby reducing the unevenness caused by the cross-sectional shape of the peripheral partition wall 7 compared to before the sealing layer 14 is formed.

[0141] Furthermore, since the through portion 14T of the sealing layer 14 overlaps the steep slope of the dam portion DM, the stress acting on the sealing layer 14 near the slope is relaxed, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0142] Figure 12 Yes Figure 9 The mother substrate 100 and Figure 10 1 and 2 are cross-sectional views of other configuration examples of the regions 100A of the display panels PNL shown.

[0143] Figure 12 The configuration example shown is the same as Figure 11 Compared to the illustrated configuration example, the inorganic insulating layer 5 differs in that the inorganic insulating layer 5 includes a through portion 5T. The through portion 5T overlaps with the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the inclined surface of the dam portion DM in the through portion 5T. Furthermore, the through portion 5T overlaps with the through portion 12T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 in the through portion 5T.

[0144] The resin layer 15 is in contact with the dam portion DM in the through portion 5T and is in contact with the inorganic insulating layer 111 .

[0145] In such a configuration example, Figure 11 Similarly to the illustrated configuration example, since the peripheral partition walls 7 are covered with the sealing layer 14 , the unevenness due to the cross-sectional shape of the peripheral partition walls 7 is also alleviated.

[0146] Furthermore, since the through portion 5T of the inorganic insulating layer 5 overlaps with the steep slope of the dam portion DM, the stress acting on the inorganic insulating layer 5 near the slope is relieved, thereby suppressing the inorganic insulating layer 5 and the sealing layer 14 from being separated from the dam portion DM and the inorganic insulating layer 111 .

[0147] Figure 13 Yes Figure 9 The mother substrate 100 and Figure 10 FIG. 1 is a cross-sectional view showing a configuration example of another region of the display panel PNL.

[0148] The insulating layer 12 has a stepped cross section with a thickness decreasing toward the through portion 12T. It should be noted that the insulating layer 12 here may be a single layer or a multilayer body of multiple insulating layers. When the insulating layer 12 has a stepped cross section as shown in the figure, Figure 11 Compared to the inclined surface of the dam portion DM shown in FIG. , the inclination is gentler. However, for example, relatively large stress is likely to be generated near the intersection of the inclined surface of the insulating layer 12 and the inorganic insulating layer 111. Therefore, by overlapping the through portion 5T of the inorganic insulating layer 5 and the through portion 14T of the sealing layer 14 with the inclined surface of the insulating layer 12, it is possible to suppress the separation of the inorganic insulating layer 5 and the sealing layer 14 starting from the intersection.

[0149] Figure 14 It means along Figure 8 A cross-sectional view of a configuration example of the pad PD of the EF line.

[0150] The metal layer MT is disposed on the inorganic insulating layer 111. The insulating layer 12 overlaps the periphery of the metal layer MT and is disposed on the inorganic insulating layer 111. The through-hole 12T of the insulating layer 12 overlaps the metal layer MT. The inorganic insulating layer 5 covers the insulating layer 12 and contacts the metal layer MT in the through-hole 12T. The inorganic insulating layer 5 also has an opening 5AP that exposes the metal layer MT.

[0151] Peripheral partition walls 7 are disposed on inorganic insulating layer 5 in through-portion 12T. Sealing layer 14 contacts base layer 73, axial layer 74, and upper portion 72, and covers the entirety of peripheral partition walls 7. Through-portion 14T of sealing layer 14 overlaps the inclined surface of insulating layer 12, exposing inorganic insulating layer 5.

[0152] In such a configuration example, since the peripheral partition walls 7 are covered with the sealing layer 14 , the unevenness caused by the cross-sectional shape of the peripheral partition walls 7 is also alleviated.

[0153] Furthermore, since the through portion 14T of the sealing layer 14 overlaps the steep slope of the insulating layer 12 , the stress acting on the sealing layer 14 near the slope is relieved, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0154] Figure 15 It means along Figure 8 A cross-sectional view of another configuration example of the pad PD of the EF line.

[0155] Figure 15 The configuration example shown is the same as Figure 14 Compared to the illustrated configuration example, the inorganic insulating layer 5 differs in that the inorganic insulating layer 5 includes a through portion 5T. The through portion 5T overlaps with the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the inclined surface of the insulating layer 12 in the through portion 5T. Furthermore, the through portion 5T overlaps with the through portion 12T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 in the through portion 5T.

[0156] In such a configuration example, Figure 14 Similarly to the illustrated configuration example, since the peripheral partition walls 7 are covered with the sealing layer 14 , the unevenness due to the cross-sectional shape of the peripheral partition walls 7 is also alleviated.

[0157] Furthermore, since the through portion 5T of the inorganic insulating layer 5 overlaps with the steep slope of the insulating layer 12 , the stress acting on the inorganic insulating layer 5 near the slope is relieved, thereby suppressing the inorganic insulating layer 5 and the sealing layer 14 from being separated from the insulating layer 12 and the inorganic insulating layer 111 .

[0158] Figure 16 It is a plan view showing a configuration example of the peripheral partition wall 7 in the through portion 12T.

[0159] The peripheral partition walls 7 are formed in a lattice shape when viewed from above. Figure 2 The lattice-shaped partition walls 6 shown in the figure are formed in the same pattern. In addition, a plurality of peripheral partition walls 7 are arranged along the first direction X and the second direction Y and are separated from each other. These plurality of peripheral partition walls 7 are covered by a sealing layer 14. It should be noted that the top view shape of the peripheral partition walls 7 is not limited to the lattice shape shown in the figure, and can also be a straight line, L-shaped, arc-shaped, etc.

[0160] In the illustrated example, the sealing layer 14 is subdivided, with each portion of the subdivided sealing layer 14 formed to cover the four peripheral partition walls 7. A gap of approximately 5 to 10 μm, for example, is formed between adjacent sealing layers 14. The peripheral partition walls 7A and 7B in the figure are separated from each other and arranged along the first direction X. The portion of the sealing layer 14 covering the peripheral partition walls 7A is separated from the portion covering the peripheral partition walls 7B.

[0161] Figure 17It means along Figure 16 sectional view of a configuration example of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line IJ in FIG.

[0162] The sealing layer 14 is in contact with the bottom layer 73, the axial layer 74, and the upper portion 72 of the peripheral wall 7A. Furthermore, the sealing layer 14 is in contact with the bottom layer 73, the axial layer 74, and the upper portion 72 of the peripheral wall 7B. The sealing layer 14 has a through portion 14T between the portion covering the peripheral wall 7A and the portion covering the peripheral wall 7B. Therefore, the inorganic insulating layer 5 is exposed from the sealing layer 14 between the peripheral wall 7A and the peripheral wall 7B.

[0163] Through Figure 16 and Figure 17 By subdividing the sealing layer 14 as in the illustrated configuration example, the stress acting on the sealing layer 14 is relaxed, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0164] Figure 18 It means along Figure 16 sectional view of another configuration example of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the IJ line in FIG.

[0165] Figure 18 The configuration example shown is the same as Figure 17 The difference from the illustrated configuration example is that the inorganic insulating layer 5 has a through portion 5T. The through portion 5T overlaps with the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 in the through portion 5T.

[0166] Figure 19 It is a plan view showing another configuration example of the peripheral partition wall 7 in the through portion 12T.

[0167] Figure 19 The configuration example shown is the same as Figure 16 Compared with the example shown in the figure, the difference is that the sealing layer 14 is further divided. In the example shown in the figure, each part of the divided sealing layer 14 is formed in a manner that covers one peripheral partition wall 7. In the sealing layer 14, the parts covering the peripheral partition wall 7 are separated from each other. Between adjacent parts of the sealing layer 14, as shown in FIG. Figure 17 As shown in FIG. 1 , the inorganic insulating layer 5 is exposed from the sealing layer 14. Alternatively, between adjacent portions of the sealing layer 14, as shown in FIG. Figure 18 As shown, the inorganic insulating layer 111 is exposed from the sealing layer 14 and the inorganic insulating layer 5 .

[0168] Next, a method for manufacturing the display device DSP will be described. It should be noted that, in the figures used to illustrate the manufacturing method, illustrations below the inorganic insulating layer 111 are omitted. Figures 20 to 27 The cross section on the left corresponding to the display area DA is equivalent to the cross section along Figure 2 The cross section of the AB line in FIG. 1 is equivalent to the cross section along the right side corresponding to the through portion 12T. Figure 16 The cross section of the IJ line in .

[0169] First, if Figure 20 As shown in FIG. 1 , a processing substrate SUB is prepared that includes lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, partition walls 6, and peripheral partition walls 7. The process of preparing the processing substrate SUB includes the following steps.

[0170] Specifically, a circuit layer 11 including an inorganic insulating layer 111 is formed on a substrate 10, extending over the display area DA, the peripheral area SA, and the blank portion MP. Subsequently, an insulating layer 12 is formed on the inorganic insulating layer 111. During patterning during the formation of the insulating layer 12, through-holes 12T are formed at necessary locations in the peripheral area SA and the blank portion MP. This results in the formation of the insulating layer 12 and a plurality of dam portions DM that overlap the display area DA.

[0171] Thereafter, in the display area DA, the lower electrode LE1 of the sub-pixel SP1 , the lower electrode LE2 of the sub-pixel SP2 , and the lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12 .

[0172] Next, an inorganic insulating layer 5 is formed over the display area DA, the peripheral area SA, and the blank portion MP. The inorganic insulating layer 5 covers the periphery of each of the lower electrodes LE1, LE2, and LE3 and has openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively. In the through-hole portion 12T, the inorganic insulating layer 5 is formed on the inorganic insulating layer 111. The inorganic insulating layer 5 is formed of, for example, silicon oxynitride.

[0173] Next, a partition wall 6 is formed, having a lower portion 61 located above the inorganic insulating layer 5 and an upper portion 62 located above the lower portion 61. Simultaneously with the formation of the partition wall 6, a peripheral partition wall 7 is formed in the through-hole 12T, having a lower portion 71 located above the inorganic insulating layer 5 and an upper portion 72 located above the lower portion 71. The bottom layer 63 and upper portion 62 of the lower portion 61 protrude from the side of the shaft layer 64 of the lower portion 61. Similarly, the bottom layer 73 and upper portion 72 of the lower portion 71 protrude from the side of the shaft layer 74 of the lower portion 71. The bottom layers 63 and 73 are formed of a titanium-based material, and the shaft layers 64 and 74 are formed of an aluminum-based material.

[0174] It should be noted that the step of forming the openings AP1 , AP2 , and AP3 in the inorganic insulating layer 5 may be performed before or after forming the partition walls 6 and the peripheral partition walls 7 .

[0175] Next, the display element DE1 is formed.

[0176] First, if Figure 21 As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the stacked film FL1 includes forming the organic layer OR1 on the lower electrode LE1 in the opening AP1, forming the upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and forming the cap layer CP1 on the upper electrode UE1. The process of forming the organic layer OR1 includes the steps of separately forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The upper electrode UE1 is formed of a mixture of magnesium and silver.

[0177] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0178] The laminated film FL1 is formed on the lower electrodes LE2 and LE3 in the display area DA, and is also formed in the peripheral area SA and the blank portion MP. This laminated film FL1 is divided into multiple sections by cantilevered partitions 6 and peripheral partitions 7. Particularly in the peripheral area SA and the blank portion MP, the peripheral partitions 7 divide the laminated film FL1, thereby subdividing the laminated film FL1. This reduces stress on the laminated film FL1 during the manufacturing process, preventing it from detaching from the inorganic insulating layer 5.

[0179] Next, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminate film FL1. The sealing layer SE1 is formed using CVD (Chemical Vapor Deposition) over the display area DA, the peripheral area SA, and the blank area MP. The sealing layer SE1 continuously covers the partitioned portions of the laminate film FL1, the partition walls 6, and the peripheral partition walls 7. The sealing layer SE1 is formed, for example, of silicon nitride.

[0180] Then, if Figure 22 As shown, in the display area DA, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a portion of the partition 6 surrounding it. The resist RS is not disposed in the peripheral area SA and the blank portion MP.

[0181] Then, if Figure 23As shown, etching is performed using the resist RS as a mask to pattern the laminate film FL1 and the sealing layer SE1. That is, dry etching is performed using the resist RS as a mask to remove the sealing layer SE1 exposed from the resist RS. Thereafter, the laminate film FL1 exposed from the resist RS is removed. At this time, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed from the laminate film FL1 in sequence. As a result, the laminate film FL1 covered by the resist RS remains in the sub-pixel SP1. In addition, a portion of the upper portion 62 of the partition wall 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are also exposed. In addition, in the peripheral area SA and the blank portion MP, the peripheral partition wall 7 is exposed.

[0182] Thereafter, the resist RS is removed, thereby forming the display element DE1 in the sub-pixel SP1.

[0183] In the process of removing the sealing layer SE1 and the laminated film FL1 and further removing the resist RS, the laminated film FL1 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE1.

[0184] Then, if Figure 24 As shown, display element DE2 is formed. The steps for forming display element DE2 are the same as those for forming display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a cover layer CP2 are sequentially formed on the lower electrode LE2, thereby forming a laminate film FL2. A sealing layer SE2 is then formed on the laminate film FL2. A resist is then formed on the sealing layer SE2, and the sealing layer SE2, cover layer CP2, upper electrode UE2, and organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. Thus, display element DE2 is formed in sub-pixel SP2, exposing the lower electrode LE3 of sub-pixel SP3.

[0185] It should be noted that during the process of removing the sealing layer SE2 and the laminated film FL2 and then removing the resist, the laminated film FL2 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE2.

[0186] The laminate film FL2 does not remain on the peripheral partition walls 7 , and the peripheral partition walls 7 are not covered with the sealing layer SE2 .

[0187] Then, if Figure 25As shown, display element DE3 is formed. The steps for forming display element DE3 are the same as those for forming display element DE1. Specifically, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are sequentially formed on the lower electrode LE3, thereby forming a laminate film FL3. A sealing layer SE3 is then formed on the laminate film FL3. A resist is then formed on the sealing layer SE3, and the sealing layer SE3, cap layer CP3, upper electrode UE3, and organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. Thus, display element DE3 is formed in sub-pixel SP3.

[0188] It should be noted that during the process of removing the sealing layer SE3 and the laminated film FL3 and then removing the resist, the laminated film FL3 located on the upper portion 62 of the partition 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE3.

[0189] The laminate film FL3 does not remain on the peripheral partition walls 7 , and the peripheral partition walls 7 are not covered with the sealing layer SE3 .

[0190] It should be noted that, in the above manufacturing process, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0191] Then, if Figure 26 As shown, in the display area DA, a resin layer 13 is formed on the sealing layers SE1, SE2, and SE3. When the resin material for forming the resin layer 13 is applied, the resin material is Figure 9 The plurality of dam portions DM shown in the figure are blocked and are not arranged in the through portion 12T shown in the figure.

[0192] Then, if Figure 27 As shown, sealing layer 14 is formed by depositing an inorganic insulating material. Sealing layer 14 is formed by CVD over the display area DA, the peripheral area SA, and the blank portion MP. Sealing layer 14 is disposed on resin layer 13 in the display area DA and continuously covers peripheral barrier ribs 7 in the peripheral area SA and the blank portion MP. Specifically, the base layer 73 of the lower portion 71, the shaft layer 74, and the upper portion 72 are directly covered by sealing layer 14. Sealing layer 14 is formed, for example, of silicon nitride.

[0193] Next, the inorganic insulating layer 5 and the sealing layer 14 are patterned together.

[0194] Figure 28 It is a cross-sectional view showing the terminal area TA.

[0195] Here, the terminal area TA is shown as a part of the peripheral area SA.

[0196] like Figure 28 As shown on the left side of FIG, the terminal TE is formed in the process of forming the circuit layer 11. For example, the terminal TE is formed on the inorganic insulating layer 111. The insulating layer 12 covers the peripheral portion of the terminal TE. The inorganic insulating layer 5 covers the insulating layer 12 in the terminal area TA and covers the terminal TE. The sealing layer 14 is as shown in FIG. Figure 27 As described above, it is also formed in the peripheral area SA and covers the inorganic insulating layer 5 in the terminal area TA.

[0197] Afterwards, if Figure 28 As shown on the right side of FIG, the inorganic insulating layer 5 and the sealing layer 14 are patterned together, and a through hole TH penetrating the inorganic insulating layer 5 and the sealing layer 14 is formed in the terminal area TA to expose the terminal TE. Figure 12 、 Figure 13 、 Figure 15 and Figure 18 The through-holes 5T and 14T described above can be formed by collectively patterning the inorganic insulating layer 5 and the sealing layer 14. Thus, in the peripheral area SA and the blank portion MP, the inorganic insulating layer 5 and the sealing layer 14 are subdivided by the through-holes 5T and 14T.

[0198] Then, if Figure 29 As shown, the sealing layer 14 is patterned.

[0199] In the terminal area TA, the sealing layer 14 around the terminal TE is removed so that the step difference in the through hole TH is relaxed. Figure 11 、 Figure 14 and Figure 17 The through portion 14T described above can be formed by patterning the sealing layer 14 described here. Figure 29 The left side shows Figure 17 The through-portions shown are similar to the through-portions 14T. Thus, the sealing layer 14 is subdivided by the through-portions 14T in the peripheral area SA and the blank portion MP.

[0200] That is, the through portion 14T can be viewed by referring to Figure 28 The inorganic insulating layer 5 and the sealing layer 14 are formed by patterning together, and can also be formed by referring to Figure 29 The sealing layer 14 is formed by patterning as described above.

[0201] Then, if Figure 30As shown, a conductive layer 20 is formed. The conductive layer 20 is, for example, a multilayer structure formed by sequentially stacking a titanium layer, an aluminum layer, and a titanium layer. In the peripheral area SA and the blank portion MP, the conductive layer 20 is disposed on the sealing layer 14 and also on the inorganic insulating layer 5. In the terminal area TA, the conductive layer 20 is disposed on the inorganic insulating layer 5 and also on the terminals TE in the through-holes TH. In the display area DA, the conductive layer 20 is disposed on the sealing layer 14.

[0202] Then, if Figure 31 As shown, a resist RS1 is applied on the conductive layer 20. At this time, in the peripheral area SA and the blank portion MP, near the peripheral partition wall 7, the unevenness of the peripheral partition wall 7 is alleviated by the sealing layer 14, thereby suppressing the formation of undesirable gaps between the resist RS1 and the peripheral partition wall 7. In addition, the surface of the resist RS1 can be flattened. Therefore, in the resist RS1, the formation of locally thickened areas or areas blocked by the peripheral partition wall 7 is suppressed. Such a resist RS1 is, for example, a positive type that becomes soluble in a developer by being irradiated with light.

[0203] Then, if Figure 32 As shown, the resist RS1 is patterned. Through this patterning, the resist RS1 is formed so as to overlap with the terminal TE in the terminal area TA, and is also formed so as to overlap with the partition 6 in the display area DA. In the peripheral area SA and the blank portion MP, since substantially the entire area of ​​the resist RS1 is exposed, no residue of the resist RS1 is generated.

[0204] Then, if Figure 33 As shown, the resist RS1 is used as a mask to pattern the conductive layer 20. In the peripheral area SA and the blank portion MP, the resist RS1 is removed, so there is no residue of the conductive layer 20. In the terminal area TA and the display area DA, the conductive layer 20 exposed from the resist RS1 is removed.

[0205] Then, if Figure 34 As shown in FIG, the resist RS1 is removed. Thus, the wiring TL is formed from the display area DA to the terminal area TA, and in the terminal area TA, the wiring TL is connected to the terminal TE.

[0206] Then, if Figure 35 As shown, in the display area DA, a resin layer 15 is formed on the sealing layer 14 and the wiring TL. When the resin material for forming the resin layer 15 is applied, the resin material is Figure 9 Therefore, the resin layer 15 is not arranged in the terminal area TA, the peripheral area SA, and the blank area MP shown in the figure.

[0207] As described above, since the peripheral partition walls 7 are covered by the sealing layer 14, the peripheral partition walls 7 are protected by the sealing layer 14 during patterning of the conductive layer 20 in the process of forming the wiring TL. This prevents unwanted scratching of the peripheral partition walls 7. Furthermore, the generation of conductive particles caused by partial detachment of the peripheral partition walls 7 is suppressed.

[0208] Furthermore, during patterning of the conductive layer 20, the formation of gaps between the resist RS1 and the peripheral partition walls 7 or the local thickening of the resist RS1 is suppressed. Consequently, the generation of unwanted residues of the resist RS1 around the peripheral partition walls 7 is suppressed. Consequently, the generation of unwanted residues of the conductive layer 20 is suppressed.

[0209] It should be noted that the resist RS1 used for patterning the conductive layer 20 is described in particular herein, but in the reference Figure 28 The patterning of the inorganic insulating layer 5 and the sealing layer 14 described above and the reference Figure 29 When the sealing layer 14 is patterned as described above, when applying the respective applied resist, the formation of voids and local thickening of the resist can be suppressed, thereby suppressing the generation of unwanted resist residues.

[0210] As described above, according to the present embodiment, it is possible to provide a display device, a motherboard for a display device, and a method for manufacturing a display device that can suppress a decrease in reliability.

[0211] In the above embodiment, for example, sealing layers SE1, SE2, and SE3 correspond to the first sealing layer, and sealing layer 14 corresponds to the second sealing layer. Resin layer 13 corresponds to the first resin layer, and resin layer 15 corresponds to the second resin layer. In peripheral partition wall 7, lower portion 71 corresponds to the first lower portion, upper portion 72 corresponds to the second upper portion, base layer 73 corresponds to the first base layer, and axial layer 74 corresponds to the first axial layer. Peripheral partition wall 7A corresponds to the first peripheral partition wall, and peripheral partition wall 7B corresponds to the second peripheral partition wall. In partition wall 6, lower portion 61 corresponds to the second lower portion, upper portion 62 corresponds to the second upper portion, base layer 63 corresponds to the second base layer, and axial layer 64 corresponds to the second axial layer.

[0212] The inorganic insulating layer 111 corresponds to the first inorganic insulating layer, the inorganic insulating layer 5 corresponds to the second inorganic insulating layer, the through-hole 12T corresponds to the first through-hole, the through-hole 14T corresponds to the second through-hole, and the through-hole 5T corresponds to the third through-hole.

[0213] As long as they include the main purpose of the present invention, all display devices, mother substrates and methods for manufacturing display devices that can be implemented by those skilled in the art by making appropriate design changes based on the display devices, mother substrates and methods for manufacturing display devices described above as embodiments of the present invention also fall within the scope of the present invention.

[0214] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, and these variations should also be understood to fall within the scope of the present invention. For example, solutions obtained by those skilled in the art by appropriately adding, deleting, or modifying the design of components, or by adding, omitting, or modifying conditions in the above-mentioned embodiments, as long as they retain the spirit of the present invention, are also within the scope of the present invention.

[0215] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, effects that can be clearly understood from the description of this specification or effects that can be appropriately imagined by those skilled in the art should naturally be understood as effects brought about by the present invention.

Claims

1. A display device comprising: substrate; a first inorganic insulating layer disposed above the substrate over a display area where an image is displayed and a peripheral area outside the display area; an organic insulating layer, the organic insulating layer being disposed on the first inorganic insulating layer; a second inorganic insulating layer, the second inorganic insulating layer being disposed on the organic insulating layer; a display element, the display element being configured in the display area; a first sealing layer, the first sealing layer being formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions, the plurality of peripheral partitions being arranged in the peripheral area; and a second sealing layer, the second sealing layer being formed of an inorganic insulating material and being arranged over the display area and the peripheral area; The organic insulating layer has a first through portion in the peripheral region, Each of the plurality of peripheral partition walls includes a first lower portion disposed on the first through portion and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

2. The display device according to claim 1, wherein The first through portion is formed in a ring shape along the end portion of the substrate. In the first through-hole portion, the second inorganic insulating layer is in contact with the first inorganic insulating layer.

3. The display device according to claim 1, further comprising a metal layer disposed on the first inorganic insulating layer. The first through portion overlaps with the metal layer, In the first through-hole portion, the second inorganic insulating layer is in contact with the metal layer.

4. The display device according to claim 1, wherein The second sealing layer has a second through portion in the peripheral region.

5. The display device according to claim 4, wherein The second through portion is formed in a ring shape surrounding the display area in a plan view.

6. The display device according to claim 5, further comprising a dam portion disposed on the first inorganic insulating layer and formed in a ring shape surrounding the organic insulating layer. The second through portion overlaps with the inclined surface of the dam portion.

7. The display device according to claim 6, wherein: The second inorganic insulating layer has a third through portion overlapping with the second through portion, and exposes the inclined surface.

8. The display device according to claim 1, further comprising: a first resin layer disposed between the first sealing layer and the second sealing layer in the display area; and a second resin layer, the second resin layer being arranged on the second sealing layer in the display area, The second sealing layer has a second through portion and is in contact with the second inorganic insulating layer in the first through portion between the second through portion and the display region.

9. The display device according to claim 1, wherein The plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall separated from the first peripheral partition wall. The second sealing layer has a second through portion between a portion covering the first peripheral partition wall and a portion covering the second peripheral partition wall. 10 . The display device according to claim 1 , further comprising a wiring arranged on the second sealing layer in the display region and extending toward the peripheral region.

11. The display device according to claim 1, wherein The first lower portion includes a first bottom layer disposed on the second inorganic insulating layer and a first axial layer disposed between the first bottom layer and the first upper portion. The first bottom layer and the first upper portion protrude from the side of the first shaft layer, The second sealing layer contacts the first bottom layer, the first shaft layer, and the first upper portion.

12. The display device according to claim 11, further comprising a partition wall surrounding the display element. The partition wall includes a second lower portion disposed on the second inorganic insulating layer and having conductivity, and a second upper portion disposed on the second lower portion. The second lower portion includes a second base layer disposed on the second inorganic insulating layer and formed of the same material as the first base layer, and a second axial layer disposed between the second base layer and the second upper portion and formed of the same material as the first axial layer. The second bottom layer and the second upper portion protrude from the side of the second shaft layer, The first sealing layer contacts the second shaft layer and the second upper portion.

13. The display device according to claim 12, wherein: The display element comprises: a lower electrode having a peripheral portion covered by the second inorganic insulating layer; an organic layer, the organic layer being disposed on the lower electrode and comprising a light-emitting layer; and an upper electrode, the upper electrode being arranged on the organic layer and in contact with the second lower portion, The partition wall surrounds the organic layer and the upper electrode.

14. A mother substrate comprising: a panel portion having a display area for displaying an image and a peripheral area outside the display area; a blank portion, the blank portion being located outside the panel portion; a first inorganic insulating layer disposed over the panel portion and the blank portion; an organic insulating layer, the organic insulating layer being disposed on the first inorganic insulating layer; a second inorganic insulating layer, the second inorganic insulating layer being disposed on the organic insulating layer; a display element, the display element being configured in the display area; a first sealing layer, the first sealing layer being formed of an inorganic insulating material and covering the display element; a plurality of peripheral partitions, the plurality of peripheral partitions being arranged in the blank portion; and a second sealing layer formed of an inorganic insulating material and arranged over the panel portion and the blank portion; The organic insulating layer has a first through portion in the blank portion, Each of the plurality of peripheral partition walls includes a first lower portion disposed on the first through portion and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

15. The mother substrate according to claim 14, wherein: The first through portion is formed in a ring shape surrounding the panel portion. In the first through-hole portion, the second inorganic insulating layer is in contact with the first inorganic insulating layer.

16. The mother substrate according to claim 14, further comprising a metal layer disposed on the first inorganic insulating layer. The first through portion overlaps with the metal layer, In the first through-hole portion, the second inorganic insulating layer is in contact with the metal layer.

17. The mother substrate according to claim 14, wherein: The second sealing layer has a second through portion in the peripheral region.

18. The mother substrate according to claim 17, wherein: The second through portion is formed in a ring shape surrounding the display area in a plan view.

19. The mother substrate according to claim 18, further comprising a dam portion, the dam portion being arranged on the first inorganic insulating layer in the panel portion and formed in a ring shape surrounding the organic insulating layer. The second through portion overlaps with the inclined surface of the dam portion.

20. The mother substrate according to claim 19, wherein The second inorganic insulating layer has a third through portion overlapping with the second through portion, and exposes the inclined surface.

21. The mother substrate according to claim 14, further comprising: a first resin layer disposed between the first sealing layer and the second sealing layer in the display area; and a second resin layer, the second resin layer being arranged on the second sealing layer in the display area, The second sealing layer has a second through portion and is in contact with the second inorganic insulating layer in the first through portion between the second through portion and the display region.

22. The mother substrate according to claim 14, wherein The plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall separated from the first peripheral partition wall. The second sealing layer has a second through portion between a portion covering the first peripheral partition wall and a portion covering the second peripheral partition wall. 23 . The mother substrate according to claim 14 , further comprising a wiring arranged on the second sealing layer in the display region and led out to the peripheral region.

24. A method for manufacturing a display device, wherein: A processing substrate is prepared, the processing substrate comprising a first inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area, an organic insulating layer located on the first inorganic insulating layer, a second inorganic insulating layer located on the organic insulating layer, a display element located in the display area, a plurality of peripheral partitions located in the peripheral area, and a first sealing layer covering the display element and exposing the peripheral partitions. A second sealing layer is formed using an inorganic insulating material and covers the display area and the peripheral area. The patterning when forming the organic insulating layer includes a step of forming a first through portion in the peripheral region. Each of the plurality of peripheral partition walls includes a first lower portion disposed on the first through portion and a first upper portion disposed on the first lower portion, and is covered by the second sealing layer.

25. The method for manufacturing a display device according to claim 24, wherein: Further, after forming the second sealing layer, performing simultaneous patterning of the second inorganic insulating layer and the second sealing layer, The second sealing layer is patterned.

26. The method for manufacturing a display device according to claim 25, wherein: During the simultaneous patterning of the second inorganic insulating layer and the second sealing layer or the patterning of the second sealing layer, a second through portion is formed in the second sealing layer located in the peripheral region.

27. The method for manufacturing a display device according to claim 25, wherein: The patterning when forming the organic insulating layer includes the step of forming a ring-shaped dam portion located on the first inorganic insulating layer and surrounding the organic insulating layer. In the patterning of the second sealing layer, a second through portion penetrating the second sealing layer is formed at a position overlapping with the inclined surface of the dam portion.

28. The method for manufacturing a display device according to claim 25, wherein: The patterning when forming the organic insulating layer includes the step of forming a ring-shaped dam portion located on the first inorganic insulating layer and surrounding the organic insulating layer. In the simultaneous patterning of the second inorganic insulating layer and the second sealing layer, a second through portion penetrating the second sealing layer is formed at a position overlapping with the inclined surface of the dam portion, and a third through portion penetrating the second inorganic insulating layer and exposing the inclined surface is formed at a position overlapping with the second through portion.

29. The method for manufacturing a display device according to claim 24, wherein: Further, after forming the second sealing layer, forming a conductive layer, forming a resist on the conductive layer, The conductive layer is patterned using the resist as a mask to form wiring located on the second sealing layer in the display region and extending toward the peripheral region.

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