Method of manufacturing superconducting integrated circuit device

Abstract

The invention relates to a method of manufacturing a superconducting integrated circuit device. A method of manufacturing a superconducting integrated circuit device includes providing a Josephson junction (JJ) structure disposed on a first structured superconducting layer, a first superconducting material disposed on a substrate forming the first structured superconducting layer. A capping layer having a first feature and a second feature is formed over the first structured superconducting layer. Forming the capping layer includes forming a first feature surrounding a JJ structure from a sacrificial material in a first region of the capping layer, at least a portion of a top surface of the JJ structure facing away from the substrate being uncovered by the sacrificial material; a second feature is formed from the first dielectric material in a second region of the capping layer different from the first region. A via is formed in the capping layer over a portion of the first structured superconducting layer. A second structured superconducting layer of a second superconducting material is formed overlying the via hole and the top surface of the JJ structure. And removing the sacrificial material. Thus, the JJ structure is not in contact with any dielectric material, thus reducing the dielectric loss.

Description

Technical Field

[0001] The present disclosure relates generally to the field of superconducting integrated circuits, and in particular to integration concepts for Josephson junctions on substrates. Background Art

[0002] Electronic devices including superconducting integrated circuits are used in various technical fields in the field. For example, quantum computing devices that operate one or more superconducting quantum bits (qubits) rely on superconducting integrated circuits. To meet the demand for quantum hardware capable of performing useful calculations beyond the scope of classical supercomputers, quantum computing based on these superconducting circuits constitutes a leading platform. Circuits with up to dozens of superconducting qubits (and in some cases up to hundreds) have been used to demonstrate proof-of-concept calculations within the current era of noisy intermediate-scale quantum (NISQ) technology, in which non-error-corrected, error-prone physical qubits are used to perform quantum simulations and quantum algorithms. The first proof-of-concept of quantum error correction—the holy grail of quantum computing—has recently been achieved, but this also emphasizes the need for physical qubits with higher coherence. One approach to implementing circuits for such quantum computers is to create qubits comprising superconducting Josephson junctions and capacitors. Superconducting integrated circuits including Josephson junctions are also used in single-flux quantum (SFQ) devices and traveling-wave parametric amplifiers (TWPAs).

[0003] A central source of errors in superconducting qubits is dielectric loss. This occurs when the circuit's electric field penetrates a dielectric material containing microscopic defects, so-called two-level systems (TLS). While the origin of TLSs is not fully understood, they are often viewed as atoms or groups of atoms oscillating between two spatial configurations in an amorphous dielectric. The dipole moment of the TLSs couples to the electric field of the quantum circuit, resulting in a reduction in the lifetime of the qubit. Since the quantum state in the qubit is encoded using a separate, low-energy excitation, such TLS interactions significantly affect the performance of the physical qubit.

[0004] The electric fields in superconducting qubit circuits occur between disconnected conductors at different potentials (such as in designed or parasitic circuit capacitors). A typical location where parasitic capacitors exist is in the direct vicinity of a three-layer Josephson junction, which is formed by two superconducting electrodes separated by a thin dielectric barrier layer (e.g., aluminum oxide). While the Josephson junction itself includes intrinsic capacitance due to its parallel plate configuration, additional parasitic capacitance arises from fringe fields surrounding the Josephson junction, penetrating regions typically filled with a lossy dielectric forming the dielectric shell. The dielectric losses that occur in these regions degrade the performance of qubits built with such Josephson junctions. Summary of the Invention

[0005] According to one aspect of the present disclosure, a method for manufacturing a superconducting integrated circuit device includes providing a Josephson junction (JJ) structure disposed on a first structured superconducting layer, wherein the first structured superconducting layer is formed of a first superconducting material disposed on a substrate. A capping layer having a first component and a second component is formed over the first structured superconducting layer. Forming the capping layer includes: forming a first component from a sacrificial material in a first region of the capping layer, the first component surrounding the JJ structure, wherein at least a portion of a top surface of the JJ structure facing away from the substrate is not covered by the sacrificial material; and forming a second component from a first dielectric material in a second region of the capping layer, wherein the second region is different from the first region. A via is formed in the capping layer over a portion of the first structured superconducting layer. A second structured superconducting layer of a second superconducting material is formed, superimposed on the via and the top surface of the JJ structure. The sacrificial material is removed.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals identify corresponding similar components. Unless they are mutually exclusive, the features of the various illustrated embodiments may be combined and / or may be selectively omitted if not described as essential. The embodiments are depicted in the drawings and are described in detail by way of example in the following description.

[0008] Figure 1 、 2a , 3 - 4 , 5 a , 6 a , and 7 a are schematic cross-sectional views illustrating stages of the method of manufacturing the superconducting integrated circuit device according to the first embodiment.

[0009] Figure 2b 、 5b , 6b and 7b are schematic top views further illustrating stages of the method of manufacturing a superconducting integrated circuit device according to the first embodiment.

[0010] Figures 8 to 11 are schematic cross-sectional views illustrating stages of a method of manufacturing a superconducting integrated circuit device according to the second embodiment. DETAILED DESCRIPTION

[0011] The words “above” or “below” or similar words, with respect to a component, element, or material layer being formed or positioned or placed or arranged or disposed “above” or “below” a surface, may be used herein to mean that the component, element, or material layer is “directly positioned” (e.g., placed, formed, arranged, placed, etc.) “on” or “below” the implied surface, e.g., in direct contact. However, the words “above” or “below” or similar words, with respect to a component, element, or material layer being formed or positioned or placed or disposed “above” or “below” a surface, may be used herein to mean that the component, element, or material layer is “indirectly” positioned (e.g., placed, formed, arranged, placed, etc.) “on” or “below” the implied surface, with one or more additional components, elements, or layers disposed between the implied surface and the component, element, or material layer.

[0012] The following describes, by way of example, a method for fabricating a superconducting integrated circuit device including a Josephson junction. A superconducting integrated circuit (or device) using a Josephson junction is an example of a superconducting quantum circuit (or device) because the Josephson effect is based on a quantum mechanical tunneling process.

[0013] For example, these methods can be used to implement quantum computing devices. However, the present disclosure is not limited to methods for making quantum computing devices. Rather, the present disclosure essentially covers all methods for making superconducting integrated circuit devices containing Josephson junctions (i.e., superconducting Josephson junction quantum circuits).

[0014] In some examples, a superconducting integrated circuit may, for example, include a resonant circuit or a resonant circuit. A resonant circuit typically includes (at least) a capacitor and an inductor. The resonant circuit may be a linear resonant circuit (e.g., a harmonic oscillator) or a nonlinear resonant circuit (e.g., a non-harmonic oscillator). In quantum devices, such a resonant circuit is also referred to as a quantum oscillator (QO).

[0015] For example, a known technique used in quantum computing is to use a Josephson junction to make a resonant circuit nonlinear (or, in other words, to make the oscillator potential nonharmonic). In quantum computing devices, quantum anharmonic oscillators are used to "form" qubits. In other words, a nonlinear resonant circuit can "form" a qubit (or operate as a qubit). In the art, a qubit created by one or more (nonlinear) Josephson junctions in a (thus nonlinear) resonant circuit is sometimes also referred to as a "Josephson qubit."

[0016] Other examples of superconducting Josephson junction quantum circuits are Josephson parametric amplifiers or traveling-wave parametric amplifiers (TWPAs). These devices offer high gain, high dynamic range, and (almost) quantum-limited noise over bandwidths of several GHz. For example, to build large-scale multi-qubit quantum processors, it is necessary to read out the qubits via multiplexing, which requires amplifiers with large bandwidth, high dynamic range, and low additive noise. This capability is provided by traveling-wave parametric amplifiers (TWPAs).

[0017] Another example of an electronic device that includes a superconducting integrated circuit is a single-flux quantum (SFQ) device. This device uses voltage pulses generated by Josephson junctions in superconducting electronic (quantum) circuits (rather than the voltage levels generated by transistors in semiconductor electronics) to encode, process, and transmit (classical) digital information. Superconducting integrated circuits containing multiple SFQ devices allow the formation of (R)SFQ ((Fast) Single-Flux Quantum) logic.

[0018] refer to Figure 1 A substrate 110 is provided. Substrate 110 may, for example, include or be a sapphire substrate or a silicon substrate, particularly a high-resistance crystalline silicon substrate. Substrate 110 serves as a carrier for constructing a superconducting integrated circuit thereon. Substrate 110 may, for example, be unstructured or unprocessed. In particular, for example, no integrated circuit or integrated device is formed in substrate 110.

[0019] A first structured superconducting layer 120 of a first superconducting material is formed over the substrate 110. The first structured superconducting layer 120 can be obtained by structuring an unstructured continuous layer of the first superconducting material, which can, for example, be deposited over the entire substrate 110. For example, the unstructured continuous layer of the first superconducting material can be deposited using a CVD (chemical vapor deposition) or PVD (physical vapor deposition) process, in particular by sputtering. The first superconducting material is a material that can become superconducting at the operating temperature of the superconducting integrated circuit to be formed. Therefore, the term "superconducting" refers to the conductive state of a material at the operating temperature of the circuit. The superconducting material can, for example, include or be Al, Nb or Ta.

[0020] The unstructured continuous layer of the first superconducting material may then be structured to form a first structured superconducting layer 120. The first structured superconducting layer 120 comprises a first superconducting structure 121 and a second superconducting structure 122 of the first superconducting material. The superconducting structures 121, 122 may, for example, be electrically and / or structurally disconnected from each other.

[0021] For example, the first structured superconducting layer 120 may be obtained by patterning a photoresist (not shown) using, for example, a photolithographic mask and an etching process applied to an unstructured continuous layer of the first superconducting material. Other structuring processes compatible with semiconductor manufacturing may also be used.

[0022] A Josephson junction (JJ) layer stack 130 is formed over the first structured superconducting layer 120 (which in this embodiment has been structured into superconducting structures 121, 122). The JJ layer stack 130 may be a continuous, unstructured layer stack consisting of Figure 1 For example, the JJ layer stack 130 may extend through (ie, cover) the entire substrate 110 .

[0023] The JJ layer stack 130 includes a JJ barrier layer (not shown). The JJ barrier layer is a functional layer of the JJ layer stack 130 that provides JJ tunneling.

[0024] For example, the JJ layer stack 130 may include or be a three-layer stack of superconductor / tunneling barrier / superconducting material. Possible three-layers include, but are not limited to, Al / alox / Al, Nb / alox / Nb, or Ta / alox / Ta layer stacks. For example, other barrier layers besides AlOx (such as, for example, MgOx) may be used, and different combinations of superconducting materials may also be used.

[0025] The JJ layer stack 130 may be deposited by sputtering or any other suitable deposition process. The JJ layer stack 130 may have a topography resulting from a previous structuring process (i.e., be non-planar) and may include optional additional structured layers, such as a structured dielectric base layer, disposed on the substrate 110 and / or the first structured superconducting layer 120.

[0026] Still refer to Figure 1 The JJ layer stack 130 is then structured to form a JJ structure 131. In particular, the components of the JJ layer stack 130 that are superimposed (overlapped) on the optional first structured dielectric base layer may be completely removed.

[0027] The structuring of the JJ layer stack 130 may include an etching process. For example, reactive ion etching (RIE) may be used for metal and dielectric etching of the JJ layer stack 130 to form the JJ structure 131. RIE is anisotropic and is therefore suitable for forming a JJ structure 131 with (approximately) vertical sidewalls. Figure 1 As shown, the JJ structure 131 is in electrical contact with the structure of the first structured superconducting layer 120 (eg, in electrical contact with the second superconducting structure 122 ) at its bottom.

[0028] refer to Figure 2a, a first part 211 of the cover layer 210 is then formed in the first region, wherein the first region extends over and around the JJ structure 131. In other words, the first part 211 of the cover layer 210 completely surrounds the previously uncovered surface of the JJ structure 131. The first part 211 of the cover layer 210 can be obtained by structuring an unstructured continuous layer, which can, for example, cover the entire substrate 110, such as Figure 2a . The first portion 211 of the cover layer 210 may be formed of a sacrificial material to be removed at a later stage and may include or be one of the following: photoresist, carbon, silicon oxide, silicon nitride, or a combination of these materials (oxynitride). The material of the first portion 211 of the cover layer 210 may be different from the material of the optional dielectric base layer (and thus may be selectively structured). The material of the first portion 211 may fill the gaps between the structures 121, 122 of the first structured superconducting layer 120.

[0029] Figure 2b 1 shows a schematic top view of an intermediate product after forming the first component 211. As shown, the first component has a greater lateral extension than the JJ structure 131, so that the latter is completely surrounded by the first component 211 on the top surface facing away from the first structured superconducting layer 120 and on the side surfaces of the JJ structure 131. The first component may also cover a portion of the first superconducting structure 121 and / or the second superconducting structure 122 of the first structured superconducting layer 120, as shown in FIG. Figure 2a and 2b shown.

[0030] refer to Figure 3 , a second component 311 of the cover layer 210 is then formed in a second region of the cover layer 210, the second region being different from the first region. For example, the second component 311 completely covers the region of the first structured superconducting layer 120 not covered by the first component 211. In other words, the cover layer 210, including the first component 211 and the second component 311, completely covers the substrate 110. In other words, the second component 311 can be formed adjacent to or around the sacrificial material of the first component 211 in the same layer (i.e., the cover layer 210) and can be an interlayer dielectric material. The second component 311 can be continuous, for example, laterally surrounding the first component 211, or separated by the first component 211 within the cover layer 210. The material of the second component 311 can fill the gaps between the structures 121, 122 of the first structured superconducting layer 120.

[0031] The material of the second component 311 can be a dielectric (e.g., silicon oxide, silicon nitride, or a combination of these materials (oxynitride)). In particular, the materials of the first component 211 and the second component 311 allow the first component 211 to be selectively etched relative to the material of the second component 311 (and other materials involved, such as the material of the JJ structure 131 or all materials forming the JJ structure 131 and the first structured superconducting layer 120). Therefore, for example, the first component 211 can be formed of photoresist or carbon, while the second component 311 can be formed of silicon nitride.

[0032] Still refer to Figure 3 , the cover layer 210 is ground (e.g., polished back by chemical mechanical polishing (CMP)) to the JJ structure 131. The grinding can be performed before or after the deposition of the material forming the second part 311. The result of the grinding step is a (substantially) flat top surface of the cover layer 120 (the surface facing away from the substrate 110), wherein the top surface of the JJ structure 131 is exposed at this stage of the manufacturing process. In other words, the thickness of the first part 211 and the second part 311 can correspond to the thickness of the JJ structure 131, which is at least in the vicinity of the latter measured in the vertical direction (perpendicular to the main extension plane of the substrate 110).

[0033] refer to Figure 4 , an opening 410 in the cap layer 210 is formed in a selected location, for example, within the second component 311, adjacent to the first component 211, as shown. The opening 410 exposes a portion of the structure of the first structured superconducting layer 120. In particular, the opening 410 exposes a portion of the first superconducting structure 121 that is not in contact with the bottom surface of the JJ structure 131. The formation of the opening 410 in the cap layer 210 on top of the JJ structure 212 can be performed by a dedicated via etching process (e.g., by using RIE).

[0034] Additional openings may be formed in further selected locations in the capping layer for exposing portions of the first superconducting layer 120 (eg, for forming contact pads).

[0035] refer to Figure 5a , the opening 410 is filled with a superconducting material forming a via 511, which contacts the exposed portion of the first structured superconducting layer 120, in particular, the first superconducting structure 121. Similar to the first superconducting material of the first structured superconducting layer 120, the superconducting material used to fill the opening 410 and thus form the via 511 may include Al, Nb, or Ta. The superconducting material of the via 511 may be the same as the first superconducting material.

[0036] Still referring to FIG5A , a second structured superconducting layer 510 of a second superconducting material is formed above the substrate cover layer 210, superimposed (overlapping) at least on the top surface of the JJ structure 131 and the via 511. Similar to the first structured superconducting layer 120, the second structured superconducting layer 510 can be obtained by structuring an unstructured continuous layer of the second superconducting material, which can, for example, be deposited over the entire cover layer 210. For example, the unstructured continuous layer of the second superconducting material can be deposited using a CVD (chemical vapor deposition) or PVD (physical vapor deposition) process, particularly by sputtering. Similar to the first superconducting material of the first structured superconducting layer 120, the second superconducting material can, for example, include or consist of Al, Nb, or Ta. The superconducting material of the second structured superconducting layer 510 can be the same as the first superconducting material or the superconducting material of the via 511.

[0037] The unstructured continuous layer of the second superconducting material may then be structured to form a second structured superconducting layer 510. The second structured superconducting layer 510 forms an electrical interconnection between the JJ structure 131 and the via 511. In other words, the second structured superconducting layer 510 provides a third superconducting structure 512 connected to the via 511 and the top surface of the JJ structure 131, effectively forming a top contact of the JJ structure 131 connected to, for example, the first superconducting structure 121.

[0038] The formation of the via 511 and the second structured superconducting layer 510 (or the deposition of an unstructured continuous layer of the second superconducting material) can be performed in a single step, for example, the second superconducting material can fill the opening 410 and be deposited on the cover layer 210 in a single deposition process. Therefore, the via 511 and the second structured superconducting layer 510 can form a third superconducting structure 512 after structuring, which interconnects the first superconducting structure 121 with the JJ structure 131, in particular, with the top surface of the JJ structure 131.

[0039] Figure 5b A schematic top view of an intermediate product after forming the second structured superconducting layer 510 is shown. For illustrative purposes, the second component 311 of the cover layer 210 is excluded from this figure. As shown, the second structured superconducting layer 510 covers the top surface of the JJ structure 131 and the via 511. Therefore, the first superconducting structure 121 is in electrical contact with the top surface of the JJ structure 131 through the via 511 and the second structured superconducting layer 510.

[0040] The second structured superconducting layer 510 is formed so that a portion of the first component 211 of the cover layer 210 is exposed. In other words, a portion of the top surface of the first component 211 of the cover layer 210 is not covered by the second structured superconducting layer 510 (i.e., it is not covered by the second structured superconducting layer 510). This facilitates the later removal of the sacrificial material of the first component 211 by, for example, etching.

[0041] refer to Figure 6a , forming a structured encapsulation layer 610. The structured encapsulation layer 610 can, for example, be formed from an unstructured continuous layer that can cover the entire arrangement before being structured. The structured encapsulation layer 610 covers the second structured superconducting layer 510 and a portion of the first component 211 of the cover layer 210. The structured encapsulation layer 610 can also cover a portion of the second component 311 of the cover layer 210, for example in an area where the second structured superconducting layer 510 does not cover the first component 211. The structured encapsulation layer 610 is formed from a second dielectric material, which can be any of the above-mentioned dielectric materials, in particular a low-loss dielectric material (such as, for example, silicon nitride). For example, the second dielectric material is the same as the first dielectric material of the second component 311 of the cover layer 210.

[0042] In this exemplary embodiment, second structured superconducting layer 510 and vias 511 form a third superconducting structure 512 as described above, for example, because these elements are formed from the same superconducting material and / or during the same processing steps.

[0043] Figure 6b A schematic top view of an intermediate product after forming the structured encapsulation layer 610 is shown. For illustrative purposes, the second component 311 of the cover layer 210 is excluded from this figure. As shown, the structured encapsulation layer 610 covers the top surface of the third superconducting structure 512 (or the second structured superconducting layer 510). Thus, the third superconducting structure 512 is encapsulated by the structured encapsulation layer 610.

[0044] The structured encapsulation layer 610 is formed so that a portion of the first component 211 of the cover layer 210 is exposed. In other words, a portion of the top surface of the first component 211 of the cover layer 210 is not covered by the structured encapsulation layer 610 (i.e., it is free of the structured encapsulation layer 610). This facilitates the later removal of the sacrificial material of the first component 211 by, for example, etching.

[0045] refer to Figure 7a, the first component 211 of the capping layer 210 formed of the sacrificial material is removed. In other words, the sacrificial material forming the first component 211 is removed. Removal of the first component 211 can be achieved, for example, by selective etching. The etchant employed has a significantly higher etching efficiency for the sacrificial material than for the first dielectric material, the second superconducting material, and the JJ structure 131 (often referred to as etching selectivity).

[0046] Since a portion of the first component 211 is exposed after forming the second structured superconducting layer 510 and the optional structured encapsulation layer 610 , such exposed area facilitates the etching process for removing the sacrificial material of the first component 211 .

[0047] After removing the sacrificial material of the first component 211, a void is formed to replace the first component 211. This means that the JJ structure 131 is laterally surrounded by the void after removing the sacrificial material. In other words, after removal, the JJ structure 131 is in vertical contact with the first structured superconducting layer 120 (e.g., the second superconducting structure 122) at its bottom surface and in vertical contact with the second structured superconducting layer 510 (e.g., the third superconducting structure 512) at its top surface, while the side surfaces of the JJ structure 131 are in contact with the void and are therefore exposed to air. In particular, the JJ structure is not in contact with any dielectric material (e.g., the first dielectric material of the second component 311 of the cover layer 210 and the second dielectric material of the structured encapsulation layer 610). Similarly, the JJ structure 131 is not in contact with any additional dielectric layer (such as the optional base layer described above).

[0048] Figure 7b A schematic top view of an intermediate product is shown after removal of the first component 211 of the cover layer 210 .

[0049] Figure 7a and Figure 7b A superconducting integrated circuit device 10 according to the present disclosure is shown. It should be understood that the present disclosure is intended to illustrate the formation of a JJ structure without a dielectric surround. Other processing methods and steps can be applied to the device, for example, further forming openings and layers for forming other contact pads and / or circuit elements.

[0050] exist Figures 1 to 7b In the illustrated embodiment, the formation of the cover layer 210 results in the latter being formed as follows Figure 3 1. This can be achieved by the CMP step described above. In other embodiments, the capping layer 210 can be formed in alternative ways.

[0051] In this regard, reference Figures 8 to 11, showing an exemplary stage of manufacturing a second embodiment of a superconducting integrated circuit device, a JJ structure 131 is formed on the first structured superconducting layer 120 and is encapsulated by a first part 211 of a cover layer 210, such as in combination with Figure 1 、 Figure 2a and Figure 2b Reference is made to the above description to avoid repetition.

[0052] refer to Figure 8 , then a second component 311 of the cover layer 210 is formed in a second region of the cover layer 210, the second region being different from the first region. For example, the second component 311 completely covers the region of the first structured superconducting layer 120 not covered by the first component 211. In other words, the cover layer 210, including the first component 211 and the second component 311, completely covers the substrate 110. The second component 311 can be continuous (e.g., laterally surrounding the first component 211) or separated by the first component 211 within the cover layer 210. The material of the second component 311 can fill the gaps between the structures 121, 122 of the first structured superconducting layer 120.

[0053] The material of the second component 311 can be a dielectric (e.g., silicon oxide, silicon nitride, or a combination of these materials (oxynitride)). In particular, the materials of the first component 211 and the second component 311 allow the first component 211 to be selectively etched relative to the material of the second component 311 (and other related materials (such as the materials forming the JJ structure 131 and the first structured superconducting layer 120)). Therefore, for example, the first component 211 can be formed of photoresist or carbon, while the second component 311 can be formed of silicon nitride.

[0054] It should be noted that the cover layer 210 in this exemplary embodiment does not need to be planarized prior to further processing and, therefore, can have topographical features on its top surface, such as in the illustrated transition region between the first component 211 and the second component 311. The height of the topographical features can be characterized by the thickness of the first component 211 and the thickness of the second component 311.

[0055] refer to Figure 9 , a first opening 910 is formed at a first selected position in the cover layer 910. The first opening 910 exposes at least a portion of the top surface of the JJ structure 131. Similar to the first embodiment with reference to FIG. Figure 4The opening 410 is formed into a second opening 920 for exposing a portion of the first structured superconducting layer 120. The first opening 910 and the second opening 920 can be formed in separate etching steps. Alternatively, the first opening 910 and the second opening 920 can be formed simultaneously in a single etching step, wherein the etchant used is non-selective with respect to the sacrificial material of the first component 211 and the first dielectric material of the second component 311, but is selective with respect to the first superconducting material of the first structured superconducting layer 120. Alternatively, both the first opening 910 and the second opening 920 can extend through the first component 211.

[0056] refer to Figure 10 , with reference Figure 5a The third superconducting structure 1010 is formed in a manner similar to the third superconducting structure 512 described above. Forming the third superconducting structure 1010 may include filling the second opening 920 with a superconducting material to form a via, and forming a second structured superconducting layer from a second superconducting material covering the via and the top surface of the JJ structure. The superconducting material of the via and the second superconducting material may be the same as described above. Each or both of them may be the same as the first superconducting material of the first structured superconducting layer 120. The third superconducting structure 1010 is formed so that a portion of the first component 211 is exposed.

[0057] refer to Figure 11 , with reference Figure 6a The structured encapsulation layer 1110 is formed in a similar manner to the structured encapsulation layer 610. The structured encapsulation layer 1110 covers (eg, completely covers) the third superconducting structure 1010 and partially covers the first component 211, such that a portion of the first component 211 is exposed.

[0058] Then, with reference Figure 7a The sacrificial material of the first component 211 is removed in a similar manner as described.

[0059] Therefore, the present disclosure proposes various embodiments of techniques for forming a three-layer Josephson junction without a near dielectric. During operation of the dielectric-free three-layer Josephson junction, the fringe fields surrounding the dielectric-free three-layer Josephson junction are instead located in the void surrounding the JJ structure (e.g., in a vacuum), where lossy defects (TLS) are less prevalent. This significantly reduces the net dielectric loss budget of the three-layer Josephson junction.

[0060] Although specific examples are shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

[0061] It should be noted that the methods and apparatuses, including their preferred embodiments outlined in this document, can be used alone or in combination with other methods and apparatus disclosed in this document. Furthermore, features outlined in the context of an apparatus also apply to the corresponding method, and vice versa. Furthermore, all aspects of the methods and apparatuses outlined in this document may be combined in any manner. In particular, features of the claims may be combined with each other in any manner.

[0062] It should be noted that the description and drawings merely illustrate the principles of the proposed method and system. Those skilled in the art will be able to realize various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included within the spirit and scope of the present invention. In addition, all examples and embodiments summarized in this document are primarily and expressly intended to be used for illustrative purposes only to help the reader understand the principles of the proposed method and system. In addition, all statements of principles, aspects, and embodiments of the present invention and their specific examples provided herein are intended to encompass their equivalents.

[0063] The following examples relate to other aspects of the present disclosure:

[0064] Aspect 1: A method for manufacturing a superconducting integrated circuit device, comprising:

[0065] providing a Josephson junction (JJ) structure disposed on a first structured superconducting layer, wherein the first structured superconducting layer is formed of a first superconducting material disposed on a substrate;

[0066] forming a cover layer having a first component and a second component over the first structured superconducting layer, wherein forming the cover layer comprises:

[0067] forming a first feature of a sacrificial material in a first region of the cover layer, the first feature surrounding the JJ structure, wherein at least a portion of a top surface of the JJ structure facing away from the substrate is not covered by the sacrificial material; and

[0068] forming a second member from the first dielectric material in a second region of the cover layer, the second region being different from the first region;

[0069] forming a via in the cover layer over a portion of the first structured superconducting layer;

[0070] forming a second structured superconducting layer of a second superconducting material, the second structured superconducting layer of the second superconducting material overlying a top surface of the via and the JJ structure; and

[0071] Remove the first component.

[0072] Aspect 2: The method according to aspect 1, wherein forming the via comprises forming an opening in a selected position in the cover layer, thereby exposing a portion of the first structured superconducting layer, and filling the opening with a superconducting material, in particular the first superconducting material or the second superconducting material, to interconnect the structured first superconducting layer and the second superconducting layer.

[0073] Aspect 3: The method according to aspect 1 or 2, wherein the first superconducting material and the second superconducting material are the same material.

[0074] Aspect 4: The method according to any one of aspects 1 to 3, further comprising: forming a structured encapsulation layer of a second dielectric material over the second structured superconducting layer and over a portion of the first component of the cover layer before removing the first component.

[0075] Aspect 5: The method according to aspect 4, wherein the first dielectric material and the second dielectric material are the same material.

[0076] Aspect 6: The method according to one of aspects 1 to 5, wherein forming the capping layer comprises performing a chemical mechanical polishing (CMP) step.

[0077] Aspect 7: The method according to one of aspects 1 to 6, wherein the sacrificial material is a material that can be selectively etched relative to the first dielectric material and the material of the JJ structure.

[0078] Aspect 8: The method of one of aspects 1 to 7, wherein the sacrificial material is one of: photoresist, oxide, and carbon.

[0079] Aspect 9: The method according to one of aspects 1 to 8, wherein the first dielectric material is a nitride, in particular silicon nitride.

[0080] Aspect 10: The method according to one of aspects 1 to 9, wherein forming the second structured superconducting layer includes exposing a portion of the first component of the cover layer.

[0081] Aspect 11: The method according to one of aspects 1 to 10, wherein forming the capping layer comprises filling voids in the first structured superconducting layer with a sacrificial material or a first dielectric material.

[0082] Aspect 12: The method of one of aspects 1 to 11, wherein forming the first portion of the cover layer includes laterally surrounding the JJ structure with a sacrificial material.

[0083] Aspect 13: The method according to one of aspects 1 to 12, wherein providing the JJ structure comprises:

[0084] forming a first superconducting layer of a first superconducting material over the substrate;

[0085] forming a JJ layer stack including a JJ barrier layer on the first superconducting layer;

[0086] structuring the first superconducting layer to form a first structured superconducting layer; and

[0087] The JJ layer stack is structured to form a JJ structure.

[0088] Aspect 14: The method according to aspect 13, wherein structuring the JJ layer stack is performed simultaneously with structuring the first superconducting layer.

[0089] Aspect 15: The method according to one of aspects 1 to 14, wherein the first structured superconducting layer comprises a first superconducting structure and a second superconducting structure, wherein the first superconducting structure contacts the via and the second superconducting structure is connected to a bottom surface of the JJ structure facing the substrate.

[0090] Aspect 16: The method according to one of aspects 1 to 15, wherein the via and the second structured superconducting layer form a third superconducting structure interconnecting the top surface of the JJ structure with the first structured superconducting layer.

[0091] Aspect 17: The method according to one of aspects 1 to 16, wherein the first structured superconducting layer provides a first superconducting structure, the second structured superconducting layer provides a second superconducting structure, and wherein the second superconducting structure is connected to the JJ structure and the first superconducting structure.

[0092] Aspect 18: The method of any one of aspects 1 to 17, wherein the removal of the sacrificial material provides a void laterally surrounding the JJ structure.

[0093] Aspect 19: The method according to one of aspects 1 to 18, wherein forming the capping layer comprises partially covering the top surface of the JJ structure with a sacrificial material.

[0094] Aspect 20: The method of one of aspects 1 to 19, wherein the first superconducting material and the second superconducting material each comprise one of the following: Al, Nb, and Ta.

[0095] Aspect 21: A superconducting integrated circuit device (10), comprising:

[0096] substrate;

[0097] a first structured superconducting layer disposed on a substrate;

[0098] a Josephson junction (JJ) structure arranged in the first region on the first structured superconducting layer;

[0099] a cover layer disposed on the first structured superconducting layer in a second region, the second region being different from the first region; and

[0100] an interconnect structure interconnecting a top surface of the JJ structure facing away from the substrate and a portion of the first structured superconducting layer;

[0101] The JJ structure is laterally surrounded by voids.

Claims

1. A method for manufacturing a superconducting integrated circuit device (10), the method comprising: Providing a Josephson junction (JJ) structure (131) arranged on a first structured superconducting layer (120), wherein the first structured superconducting layer (120) is formed of a first superconducting material arranged on a substrate (110); A cover layer (210) is formed over the first structured superconducting layer (120), the cover layer (210) having a first component (211) and a second component (311), wherein forming the cover layer (210) comprises: forming the first feature (211) from a sacrificial material in a first region of the cover layer (210), the first feature (211) surrounding the JJ structure (131), wherein at least a portion of a top surface of the JJ structure (131) facing away from the substrate (110) is not covered by the sacrificial material; and forming the second component (311) from a first dielectric material in a second region of the cover layer (210), wherein the second region is different from the first region; forming a via hole (511) in the cover layer (210) above a portion of the first structured superconducting layer (120); forming a second structured superconducting layer (510) of a second superconducting material, the second structured superconducting layer (510) being superposed on the via (511) and the top surface of the JJ structure (131); and The first component (211) is removed.

2. The method of claim 1, wherein the first superconducting material and the second superconducting material are the same material.

3. The method according to claim 1 or 2, further comprising: Before removing the first component (211), a structured encapsulating layer (610) of a second dielectric material is formed over the second structured superconducting layer (510) and over a portion of the first component (211) of the cover layer (210). The method of claim 3 , wherein the first dielectric material and the second dielectric material are the same material.

5. The method according to any one of claims 1 to 4, wherein forming the capping layer (210) comprises performing a chemical mechanical polishing (CMP) step.

6. The method according to any one of claims 1 to 5, wherein the sacrificial material is a material that can be selectively etched relative to the first dielectric material and the material of the JJ structure (131).

7. The method of any one of claims 1 to 6, wherein the sacrificial material is one of: photoresist, oxide, or carbon.

8. The method of any one of claims 1 to 7, wherein the first dielectric material is a nitride.

9. The method according to any one of claims 1 to 8, wherein forming the second structured superconducting layer (510) comprises exposing a portion of the first component (211) of the cover layer (210).

10. The method according to any one of claims 1 to 9, wherein forming the capping layer (210) comprises filling voids in the first structured superconducting layer (120) with the sacrificial material or the first dielectric material.

11. The method according to any one of claims 1 to 10, wherein forming the first component (211) of the cover layer (210) comprises laterally surrounding the JJ structure (131) with the sacrificial material.

12. The method according to any one of claims 1 to 11, wherein providing the JJ structure (131) comprises: forming a first superconducting layer of the first superconducting material over the substrate (110); forming a JJ layer stack including a JJ barrier layer above the first superconducting layer; Structuring the first superconducting layer to form the first structured superconducting layer (120); as well as The JJ layer stack is structured to form the JJ structure (131). 13 . The method of claim 12 , wherein structuring the JJ layer stack is performed simultaneously with structuring the first superconducting layer.

14. The method according to any one of claims 1 to 13, wherein the first structured superconducting layer (120) comprises a first superconducting structure (121) and a second superconducting structure (122), the first superconducting structure being in contact with the via (511), the second superconducting structure being connected to a bottom surface of the JJ structure (131) facing the substrate (110).

15. The method according to any one of claims 1 to 14, wherein: The via (511) and the second structured superconducting layer (510) form a third superconducting structure (512), and the third superconducting structure (512) interconnects the top surface of the JJ structure (131) and the first structured superconducting layer (120).

16. The method according to any one of claims 1 to 15, wherein the first structured superconducting layer (120) provides a first superconducting structure (121), the second structured superconducting layer (510) provides a second superconducting structure (512), and wherein the second superconducting structure (512) is connected to the JJ structure (131) and the first structured superconducting layer (120).

17. The method of any one of claims 1 to 16, wherein removing the sacrificial material provides a void laterally surrounding the JJ structure (131).

18. The method according to any one of claims 1 to 17, wherein forming the capping layer (210) comprises partially covering the top surface of the JJ structure (131) with the sacrificial material.

19. The method of any one of claims 1 to 18, wherein the first superconducting material and the second superconducting material each comprise one of the following: Al, Nb, or Ta.

20. A superconducting integrated circuit device (10), comprising: a substrate (110); a first structured superconducting layer (120) disposed on the substrate (110); A Josephson junction JJ structure (131) is arranged in a first region on the first structured superconducting layer (120); a cover layer (210) arranged on the first structured superconducting layer (120) in a second region, the second region being different from the first region; as well as an interconnection structure (512) interconnecting a top surface of the JJ structure (131) facing away from the substrate (110) and a portion of the first structured superconducting layer (120); The JJ structure (131) is laterally surrounded by voids.

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