Off-chip and on-chip combined satellite-borne data acquisition system calibration method, equipment and medium

Abstract

The invention discloses an off-chip and on-chip combined satellite-borne data acquisition system calibration method and device and a medium, and relates to the technical field of satellite-borne remote sensing, and the method comprises the steps: off-chip calibration: generating a standard voltage value through an off-chip calibration device, and building a nonlinear calibration model through a segmented calibration strategy; on-chip self-calibration: transmitting the absolute precision of off-chip calibration to an onboard reference source, periodically triggering on-chip self-calibration by using the onboard reference source, and calculating a real-time gain error and an offset error based on a preset calibration point so as to obtain an on-chip self-calibration coefficient; real-time correction: performing two-stage real-time correction on the acquired voltage value by using an off-chip calibration coefficient and an on-chip self-calibration coefficient; according to the satellite-borne data calibration method, the precision and the stability of a data acquisition system are remarkably improved, the consumption of computing resources is low, and the application requirements of satellite-borne high-precision data acquisition are met.

Description

Technical Field

[0001] The present invention relates to the field of satellite-borne remote sensing technology, and in particular to a calibration method, equipment and medium for a satellite-borne data acquisition system that combines off-chip and on-chip. Background Art

[0002] The development of reference source systems for space-based radiation measurements has become a hot topic at the forefront of international Earth observation. With the gradual implementation of several major space observation programs in my country, the number of satellite remote sensors is rapidly increasing. At the same time, the next generation of space observation missions is further increasing the quantitative requirements for observation data.

[0003] The correlated photon-calibrated solar absolute spectroradiometer is a new type of absolute standard for optical radiation measurement. It is designed to achieve long-term, stable observations of solar absolute spectral irradiance with 0.3% accuracy from a space platform, improving the accuracy by nearly an order of magnitude compared to previous payloads. Its core features utilize the parametric down-conversion effect of nonlinear crystals to generate paired correlated photons, deriving system-level quantum efficiency through coincidence counting, and tracing absolute radiation measurements back to the Planck constant. It is independent of external standards and insensitive to system decay, offering broad application prospects in fields such as climate monitoring and deep space exploration.

[0004] High-precision acquisition of photodetector output signals is a key step in ensuring the accuracy of solar irradiance observations and a powerful guarantee for achieving absolute measurement and long-term stability. However, in actual engineering applications, data acquisition systems are constrained by the following factors: (1) inherent errors introduced by non-ideal components, including offset error, gain error, and integral / differential nonlinearity; (2) time-varying interference such as temperature drift caused by the space environment; and (3) the limited applicability of traditional calibration methods under spaceborne conditions.

[0005] In addition to accuracy requirements, spaceborne applications have high requirements for resource consumption. These resources include hardware resources and software resources. To this end, the gain switching range is reduced in hardware design, and the detector preamplifier gain switching is only set to 2 levels (5×10 9 V / A, 2×10 6 V / A), combined with data acquisition gain adjustment circuit covering 10 -12 ~10 -6 Dynamic range is increased, and the number of gain switching relays is reduced, thereby saving space, power consumption, and control interface resources. Software optimization measures are being implemented to reduce the utilization of onboard processor computing resources. However, this poses a challenge, placing higher demands on signal processing and acquisition, such as achieving 0.1% measurement accuracy at mV input voltages. This requires precise calibration of the data acquisition circuitry, minimizing resource consumption while ensuring calibration accuracy.

[0006] Existing calibration technologies primarily employ two approaches: off-chip calibration, which relies on high-precision external metrology equipment, achieves high-precision traceability but lacks real-time performance and cannot address parameter drift during on-orbit operation. On-chip self-calibration, while offering real-time advantages, is limited by the accuracy of the onboard reference source and struggles to effectively compensate for nonlinear errors. Traditional calibration methods are particularly limited for precision instruments operating on-orbit for extended periods, such as space radiation reference payloads. The unique nature of space applications makes it difficult to regularly calibrate system parameters through off-chip calibration. Furthermore, a purely self-calibration system struggles to meet the traceability chain integrity requirements of absolute measurement.

[0007] Therefore, the shortcomings of existing calibration technology have become a bottleneck problem restricting the performance improvement of space radiation reference payloads, and it is urgent to develop new composite calibration methods to break through the limitations of existing technology. Summary of the Invention

[0008] Based on the technical problems existing in the background technology, the present invention proposes a calibration method, equipment and medium for a satellite-borne data acquisition system that combines off-chip and on-chip, which significantly improves the accuracy and stability of the data acquisition system and meets the satellite's demand for high-precision data acquisition.

[0009] The present invention proposes a combined off-chip and on-chip onboard data calibration method for calibrating an onboard data acquisition system. The calibration method includes:

[0010] Off-chip calibration: Generate standard voltage values ​​through off-chip calibration equipment, and use a segmented calibration strategy to establish a nonlinear calibration model: linear fitting is used in the 50% FSR to 100% FSR range, and the 0% FSR to 50% FSR range is divided into three segments, and cubic polynomial fitting is performed on each segment to obtain the external calibration coefficients for each range. The FSR is the full-scale range.

[0011] On-chip self-calibration: The absolute accuracy of the off-chip calibration is transferred to the on-board reference source, which is used to periodically trigger on-chip self-calibration. The real-time gain error and offset error are calculated based on the preset calibration points to obtain the on-chip self-calibration coefficients.

[0012] Real-time correction: Utilizes off-chip calibration coefficients and on-chip self-calibration coefficients to perform two-level real-time correction on the collected voltage values.

[0013] Further, in the on-chip self-calibration, the preset calibration points are -1 / 2FSR, 0V and 1 / 2FSR;

[0014] Generate three standard voltage signals of -1 / 2FSR, 0V and 1 / 2FSR through the voltage divider network;

[0015] The current gain error and offset error coefficients of the system are calculated based on the three calibration points of -1 / 2FSR, 0V, and 1 / 2FSR.

[0016] Furthermore, in the off-chip calibration, the cubic polynomial fitting is used to solve the external calibration coefficients by the least square method, specifically:

[0017] Sample m1 calibration points in the range of 0% FSR to 10% FSR;

[0018] Sample m2 calibration points in the range of 10% FSR to 30% FS;

[0019] Sample m3 calibration points in the range of 30% FSR to 50% FSR.

[0020] Furthermore, m1>m2>m3.

[0021] Furthermore, dynamic gain switching is also included, specifically:

[0022] Automatically match the gain level according to the input signal amplitude;

[0023] Off-chip calibration and on-chip self-calibration are performed independently for each gain level.

[0024] Furthermore, the off-chip calibration device includes:

[0025] An external voltage source, used for providing a calibration voltage signal;

[0026] Data collector, traceable to the national metrology institute, used to measure the calibration voltage signal as the standard voltage value;

[0027] The data acquisition board to be calibrated is used to obtain the measured voltage value from the data source table.

[0028] Furthermore, the two-level real-time correction of the collected data is performed, specifically:

[0029] The collected voltage value is corrected for nonlinear errors through off-chip calibration coefficients;

[0030] The on-chip self-calibration coefficient is used to perform secondary correction on the off-chip calibrated data to compensate for linear error and environmental drift, thereby obtaining two-level corrected voltage data.

[0031] On-chip and off-chip calibration equipment for satellite-borne data acquisition systems, including an off-chip calibration module, an on-chip self-calibration module, and a real-time correction module;

[0032] In the off-chip calibration module, a standard voltage value is generated by an off-chip calibration device, and a segmented calibration strategy is adopted to establish a nonlinear calibration model: linear fitting is used in the 50% FSR to 100% FSR range, and the 0% FSR to 50% FSR range is divided into three segments, and cubic polynomial fitting is performed on each segment to obtain the external calibration coefficients of each range;

[0033] In the on-chip self-calibration module, the absolute accuracy of the off-chip calibration is transferred to the on-board reference source. The on-chip reference source is used to periodically trigger the on-chip self-calibration. The real-time gain error and offset error are calculated based on the preset calibration points to obtain the on-chip self-calibration coefficients.

[0034] In the real-time correction module, two-level real-time correction is performed on the collected voltage value using off-chip calibration coefficients and on-chip self-calibration coefficients.

[0035] Furthermore, off-chip calibration and on-chip self-calibration are independently performed for each gain level of the onboard data acquisition system.

[0036] A computer-readable storage medium stores a plurality of classification programs, wherein the plurality of classification programs are used to be called by a processor and execute the calibration method described above.

[0037] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0038] The advantages of the off-chip and on-chip combined satellite data acquisition system calibration method, equipment and medium provided by the present invention are: eliminating system nonlinear errors through off-chip calibration, and transferring absolute accuracy to the on-chip reference chip for on-chip self-calibration, while simultaneously using on-chip self-calibration to compensate for linear errors and environmental drift in real time, significantly improving the accuracy and stability of the data acquisition system, and with low computing resource consumption, meeting the satellite's demand for high-precision data acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the process of the present invention;

[0040] Figure 2 Schematic diagram of the calibration process of this embodiment;

[0041] Figure 3 Schematic diagram of off-chip calibration;

[0042] Figure 4 This is the schematic diagram of the data acquisition circuit;

[0043] Figure 5 This is the schematic diagram of the on-chip self-calibration circuit;

[0044] Figure 6 Schematic diagram of the fitted data curve after segmented calibration, comparing the input-output relationship of the system before and after calibration. DETAILED DESCRIPTION

[0045] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0046] like Figures 1 to 6 As shown, the on-chip and off-chip combined satellite data calibration method proposed by the present invention includes:

[0047] Step 1: Off-chip calibration: Generate a standard voltage value through an off-chip calibration device, and use a segmented calibration strategy to establish a nonlinear calibration model: linear fitting is used in the 50% FSR to 100% FSR range, and the 0% FSR to 50% FSR range is divided into three segments, and cubic polynomial fitting is performed on each segment to obtain the external calibration coefficients for each range, where FSR is the full-scale range.

[0048] Step 2: On-chip self-calibration: The absolute accuracy of the off-chip calibration is transferred to the on-board reference source. The on-chip reference source is used to periodically trigger the on-chip self-calibration. The real-time gain error and offset error are calculated based on the preset calibration points to obtain the on-chip self-calibration coefficients.

[0049] Step 3: Real-time correction: Using the off-chip calibration coefficient and the on-chip self-calibration coefficient, a two-level real-time correction is performed on the collected voltage value.

[0050] This embodiment eliminates system nonlinear errors through off-chip calibration and transfers absolute accuracy to the on-chip reference chip for on-chip self-calibration. It simultaneously uses on-chip self-calibration to compensate for linear errors and environmental drift in real time, thereby significantly improving the accuracy and stability of the data acquisition system and meeting the requirements of high-precision data acquisition onboard spacecraft.

[0051] In one embodiment, the off-chip calibration is specifically:

[0052] like Figure 3 The off-chip calibration equipment shown uses an external voltage source (Keilthey2601 Data Source Table) and a data logger (Keilthey2002) to generate standard voltage values. The Data Source Table serves as the calibration voltage source, and the data logger is a high-precision 8.5-bit data logger traceable to a national metrology institute.

[0053] Calibration method: Due to limited controller resources under onboard application conditions, this embodiment adopts a composite calibration method of linear fitting + polynomial fitting to establish a nonlinear mapping relationship between the standard voltage value and the measured voltage value, so as to achieve the target accuracy with minimal resource consumption. The method mainly selects calibration points within multiple ranges, obtains data pairs of measured values ​​and standard values, and then performs calibration.

[0054] To improve calibration accuracy and reduce processor resource consumption, this embodiment adopts a segmented calibration scheme, and the specific steps include (a1) to (a3):

[0055] (a1) When the input voltage signal is above level V, a linear fitting method can be used to obtain higher calibration accuracy. Therefore, a linear calibration method is used within 50% FSR to 100% FSR, and the linear fitting coefficient is solved based on the least squares method.

[0056] (a2) The range from 0% FSR to 50% FSR is divided into three segments for fitting, where 20 calibration points are sampled in the range from 0% FSR to 10% FSR; 10 calibration points are sampled in the range from 10% FSR to 30% FSR; and 5 calibration points are sampled in the range from 30% FSR to 50% FSR. The measured voltage values ​​of each segment are solved based on the least squares method to obtain the cubic polynomial coefficients to generate a calibration curve.

[0057] (a3) The generated external calibration coefficients are stored in the system for real-time correction of the collected measured voltage values.

[0058] The segmented calibration scheme (a1) to (a3) ​​is used. When the signal is large, the least squares method is used for calibration, which consumes less computing resources. When the signal is small, polynomial calibration is used, which has higher accuracy. The number of calibration points is selected according to the signal range. The smaller the signal, the more difficult it is to ensure nonlinearity, so more calibration points are needed. This ensures accuracy while minimizing resource consumption (including calibration time and on-chip computing resources). The following results are obtained through experiments: Figure 6 The relative deviations before and after calibration are shown. It can be intuitively concluded that the relative deviation after calibration is significantly smaller than that before calibration. At the same time, the calibration is most obvious for input voltage signals with absolute values ​​below 0.1V.

[0059] In one embodiment, the on-chip self-calibration is specifically:

[0060] Hardware Design: A high-precision onboard reference source (AD580) and a voltage divider network are integrated to generate multiple standard voltage signals (-1 / 2FSR, 0V, and 1 / 2FSR). The absolute accuracy of the onboard reference source is traceable to the data acquisition device (Keithley 2002). The reference source's own temperature drift coefficient is more than one order of magnitude lower than that of the core components of the acquisition circuit. The voltage divider resistors use 5ppm precision resistors with a temperature drift coefficient.

[0061] For details on the onboard data acquisition circuit, see Figure 4 The input voltage signal first enters the follower, and the follower selects an amplifier with high input impedance to reduce the nonlinear error introduced by the fluctuation of the output impedance of the input source; the sample-and-hold is used to "lock" the current signal and is suitable for the synchronous acquisition of multiple signals; the voltage reference and voltage divider network are used to generate on-chip calibration voltage; the analog switch selects the above input signal for acquisition; the subsequent operational amplifier circuit and gain adjustment circuit are used to dynamically adjust the gain to adjust the input signal to match the dynamic range of the ADC, among which the gain adjustment circuit selects an analog switch with low on-resistance; the analog switch signal enters the ADC for quantitative acquisition after gain adjustment; FPGA is used for ADC control, data acquisition and storage, data calibration, etc.

[0062] In this embodiment, the on-chip self-calibration logic includes (b1) to (b3):

[0063] (b1) Generate three standard voltage signals of -1 / 2FSR, 0V and 1 / 2FSR through a voltage divider network;

[0064] (b2) Calculate the current gain error and offset error coefficients of the system based on the three calibration points of -1 / 2FSR, 0V, and 1 / 2FSR;

[0065] (b3) Combined with the linear calibration formula, the collected data is corrected in real time.

[0066] This embodiment selects a three-point calibration method of -1 / 2FSR, 0V and 1 / 2FSR.

[0067] The calibration points should be distributed as evenly as possible across the entire input range (from negative full scale to positive full scale) that the system will use. This is crucial to capturing any nonlinear errors that may exist in the system. A three-point calibration can effectively separate the offset and gain errors, significantly improving midpoint accuracy. In combination with a zero point (0), using a three-point calibration scheme that includes ±1 / 2FSR is one of the best practices for balancing calibration efficiency with overall system accuracy, especially in the midpoint area.

[0068] To explain the on-chip self-calibration more clearly, the following uses specific data to illustrate the triggering process of the on-chip self-calibration:

[0069] (1) Switch to the -1 / 2FSR channel, collect 16 measured voltage values, and take the average value V1;

[0070] (2) Switch to the 0V channel, collect 16 measured voltage values, and take the average value V2;

[0071] (3) Switch to the 1 / 2FSR channel, collect 16 measured voltage values, and take the average value V3;

[0072] (4) Calculation ; and b = V2-kθ, where k is the gain error and b is the offset error coefficient, The 1 / 2 full-scale standard voltage value (i.e., true value) is generated by dividing the on-chip reference voltage source. The -1 / 2 full-scale standard voltage value (i.e., true value) is generated by dividing the on-chip reference voltage source, and θ is the theoretical value of zero-point input, that is, the theoretical value that should be output when the input is 0V in an ideal error-free system.

[0073] Where (V3 - V1) is the actual span measurement of the system in the symmetrical bipolar range. It includes gain error (amplifier / ADC scale deviation) and nonlinearity error (nonlinearity within the ±1 / 2 FSR range). It does not include offset error (the subtraction operation cancels out the fixed offset).

[0074] It is the theoretical standard span value of the system.

[0075] It can be understood that switching to the +1 / 2FSR channel means switching to the system's measurement channel for the +1 / 2FSR standard voltage. Similarly, switching to the 0V channel means switching to the system's measurement channel for zero point input, and switching to the -1 / 2FSR channel means switching to the system's measurement channel for the -1 / 2FSR standard voltage.

[0076] (5) The on-chip self-calibration coefficient of the current gain level is thereby updated.

[0077] In this embodiment, on-chip self-calibration utilizes Figure 5 The hardware circuit shown uses a +5V voltage reference from a standard voltage chip. This voltage is then passed through an inverting amplifier to generate a -5V signal, which then passes through the R1-R4 voltage divider network to produce the target voltage. A 1 / 2FSR is set between the R1 and R2 divider networks, a 0V voltage is set between the R2 and R3 divider networks, and a -1 / 2FSR is set between the R3 and R4 divider networks.

[0078] In this embodiment, the collaborative working mechanism of off-chip calibration and on-chip calibration is specifically as follows:

[0079] Initialization phase: Full-scale nonlinearity correction is completed through off-chip calibration. The specific correction process is as follows: the collected voltage value is first determined to be in which calibration interval (i.e., the sub-range and segment in the off-chip calibration mentioned above), and nonlinearity correction is performed based on the calibration coefficient within this interval to remove the nonlinear effects of the system.

[0080] During the operational phase, the difference between the ambient temperature during laboratory calibration (23°C ± 1°C) and the on-orbit operating temperature (15°C ± 1°C), as well as the slow drift of the ambient temperature during testing, introduces measurement errors. Therefore, on-chip self-calibration is periodically triggered during data acquisition to correct linear errors caused by temperature drift or device aging in real time. After external nonlinearity correction is completed during off-chip calibration, the on-chip self-calibration coefficients are substituted for correction to remove the effects of gain and offset errors.

[0081] Dynamic gain adjustment: Automatically switches gain levels based on the input signal amplitude, combining calibration parameters to achieve high-precision acquisition across multiple ranges. If multiple gain levels are available, the above steps must be performed for each gain level. This means that both off-chip calibration and on-chip self-calibration are performed independently for each gain level.

[0082] What needs to be understood is that the input signal is the voltage at the input, which is amplified and collected by the subsequent data acquisition circuit.

[0083] As an embodiment;

[0084] (c1) Hardware implementation;

[0085] The on-chip calibration circuit uses a voltage reference chip, an inverting amplifier circuit, and precision resistors to build a voltage divider network to output multiple standard voltages.

[0086] The data acquisition circuit uses a 16-bit successive approximation ADC, which supports multi-channel switching and high-resolution acquisition;

[0087] FPGA serves as the control core, realizing calibration logic, digital filtering and communication functions.

[0088] (c2) software implementation;

[0089] Off-chip calibration is controlled by host computer software to complete data acquisition, polynomial fitting and coefficient storage;

[0090] On-chip self-calibration is implemented by FPGA firmware, which periodically reads the reference signal and updates the calibration parameters;

[0091] The digital filtering module uses FIR low-pass filter and de-extreme sliding average filter to suppress noise interference.

[0092] This embodiment combines off-chip calibration with on-chip self-calibration to achieve both nonlinearity correction and real-time linear error compensation. It employs a combination of linear fitting and cubic polynomial fitting to address nonlinearities that are difficult to address with traditional linear calibration. Dynamic gain switching and calibration parameter linkage enable high-precision acquisition over a wide measurement range.

[0093] Tests have shown that this embodiment can reduce the nonlinear error of the onboard data acquisition system to less than 0.005%, achieve a stability of 0.015%, and reduce on-orbit calibration resource consumption by 24.5% compared to a solution that uses cubic polynomial fitting. It is suitable for high-precision measurement scenarios such as aerospace payloads and precision instruments.

[0094] Among them, the nonlinear error evaluation method is:

[0095] The least squares method is used for linearity evaluation. Assume that the input value of the satellite-borne data acquisition system is x and the output value is y. For the data acquisition system, its input and output values ​​satisfy the linear relationship of the following formula (1):

[0096] y=kx+b; (1)

[0097] Where k and b are the gain error and offset error coefficients of the data acquisition system. The output value y within the range E of the data acquisition system i and regression value kx i +bThe residual Δ i Expressed as:

[0098] Δ i =y i -(kx i +b); (2)

[0099] Among them, x i is the i-th input value, y i is x i The corresponding output value when used as input to the data acquisition system.

[0100] The linearity of the data acquisition system is obtained as:

[0101]

[0102] Where L is the linearity, k and b are obtained by the least squares method.

[0103] where y i The values ​​are processed by applying the calibration coefficient. Three gain levels were tested, and the nonlinearity of each level was evaluated under the condition of input signal range of 10% FSR to FSR.

[0104] Stability assessment method and formula:

[0105] Instability refers to the output change of the data acquisition system when a stable standard signal is input. It reflects the ability of the data acquisition system to maintain stability over time. The smaller the value, the more stable the system. The calculation formula is:

[0106]

[0107] Where St is the system stability, St max 、St min They are the maximum and minimum values ​​of the collected data within the collection time, is the average value of the collected data.

[0108] As an example, the onboard data calibration process is as follows:

[0109] S1, start off-chip calibration;

[0110] S2, switch gain;

[0111] S3. Adjust the output value of the digital source meter;

[0112] S4. Record the data acquisition circuit data (measured voltage value) and the standard voltage value;

[0113] S5, determine whether all calibration points are covered, if not, return to step S3, if yes, go to step S6;

[0114] S6, obtaining the off-chip calibration coefficient under the gain, and then determining whether all gains are covered, if not, proceeding to step S2, if so, proceeding to step S7;

[0115] S7, start the on-chip self-calibration process;

[0116] S8, switch gain;

[0117] S9. The analog switch switches the calibration signal and saves the collected voltage value.

[0118] S10, determining whether the current gain calibration signal acquisition data is completed, if not, proceeding to step S9, if yes, proceeding to step S11;

[0119] S11, calculate the on-chip self-calibration coefficient under the current gain, and then determine whether it is sufficient to cover all gains. If not, go to step S8, if so, go to step S12;

[0120] S12. Calibrate the measured voltage value using the off-chip calibration coefficient and calibrate the measured voltage value using the on-chip self-calibration coefficient, thereby performing two-level real-time correction on the collected voltage value.

[0121] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A calibration method for a spaceborne data acquisition system combining off-chip and on-chip, characterized in that: Used to calibrate the onboard data acquisition system. The calibration method includes: Off-chip calibration: Generate standard voltage values ​​through off-chip calibration equipment, and use a segmented calibration strategy to establish a nonlinear calibration model: linear fitting is used in the 50% FSR to 100% FSR range, and the 0% FSR to 50% FSR range is divided into three segments, and cubic polynomial fitting is performed on each segment to obtain the external calibration coefficients for each range. The FSR is the full-scale range. On-chip self-calibration: The absolute accuracy of the off-chip calibration is transferred to the on-board reference source, which is used to periodically trigger on-chip self-calibration. The real-time gain error and offset error are calculated based on the preset calibration points to obtain the on-chip self-calibration coefficients. Real-time correction: Utilizes off-chip calibration coefficients and on-chip self-calibration coefficients to perform two-level real-time correction on the collected voltage values.

2. The calibration method according to claim 1, wherein: In the on-chip self-calibration, the preset calibration points are -1 / 2FSR, 0V and 1 / 2FSR; Generate three standard voltage signals of -1 / 2FSR, 0V and 1 / 2FSR through the voltage divider network; The current gain error and offset error coefficients of the system are calculated based on the three calibration points of -1 / 2FSR, 0V, and 1 / 2FSR.

3. The calibration method according to claim 1, wherein: In the off-chip calibration, the cubic polynomial fitting is solved by the least squares method to obtain the external calibration coefficients, specifically: Sample m1 calibration points in the range of 0% FSR to 10% FSR; Sample m2 calibration points in the range of 10% FSR to 30% FS; Sample m3 calibration points in the range of 30% FSR to 50% FSR.

4. The calibration method according to claim 3, wherein: m1>m2>m3.

5. The calibration method according to claim 1, wherein: Also includes dynamic gain switching, specifically: Automatically match the gain level according to the input signal amplitude; Off-chip calibration and on-chip self-calibration are performed independently for each gain level.

6. The calibration method according to claim 1, wherein: The off-chip calibration device comprises: An external voltage source, used for providing a calibration voltage signal; Data collector, traceable to the national metrology institute, used to measure and calibrate voltage signals as standard voltage values; The data acquisition board to be calibrated is used to obtain the measured voltage value from the data source table.

7. The calibration method according to claim 1, wherein: The two-level real-time correction of the collected data is performed as follows: The collected voltage value is corrected for nonlinear errors through off-chip calibration coefficients; The on-chip self-calibration coefficient is used to perform secondary correction on the off-chip calibrated data to compensate for linear error and environmental drift, thereby obtaining two-level corrected voltage data.

8. A calibration device for a satellite-borne data acquisition system that combines off-chip and on-chip, characterized in that: Includes off-chip calibration module, on-chip self-calibration module and real-time correction module; In the off-chip calibration module, a standard voltage value is generated by an off-chip calibration device, and a segmented calibration strategy is adopted to establish a nonlinear calibration model: linear fitting is used in the 50% FSR to 100% FSR range, and the 0% FSR to 50% FSR range is divided into three segments, and cubic polynomial fitting is performed on each segment to obtain the external calibration coefficients of each range; In the on-chip self-calibration module, the absolute accuracy of the off-chip calibration is transferred to the on-board reference source. The on-chip reference source is used to periodically trigger the on-chip self-calibration. The real-time gain error and offset error are calculated based on the preset calibration points to obtain the on-chip self-calibration coefficients. In the real-time correction module, two-level real-time correction is performed on the collected voltage value using off-chip calibration coefficients and on-chip self-calibration coefficients.

9. The onboard data calibration device according to claim 8, characterized in that: Off-chip calibration and on-chip self-calibration are performed independently for each gain level of the onboard data acquisition system.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a plurality of classification programs, which are used to be called by a processor and execute the calibration method according to any one of claims 1 to 7.

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