Fixed soft start low dropout linear regulator

Abstract

The invention discloses a fixed soft start low dropout linear regulator, which comprises an error amplification circuit, a dropout voltage generation circuit, a load current circuit induction circuit, an output capacitor Cout and a capacitor Css, and is characterized in that the input end of the load current induction circuit is connected with the output end of the error amplification circuit; the output voltage Vout and the reference voltage Vref are respectively input to the reverse input end of the error amplification circuit and the non-inverting input end of the error amplification circuit, and the error amplification circuit comprises a second NMOS tube MN2; one end of the output capacitor Cout is connected with the output voltage Vout, and the other end of the output capacitor Cout is grounded; one end of the capacitor Css is connected with the output voltage Vout, and the other end of the capacitor Css is connected with the grid electrode of the second NMOS tube MN2. In conclusion, the defects in the prior art are overcome, the design is reasonable, the output voltage Vout is coupled to the grid input of the second NMOS tube MN2 of the error amplification circuit, so that the soft start time is adjusted not to change along with the output capacitor Cout and the load, and the soft start circuit has high social use value and application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of linear voltage regulators, and in particular to a fixed soft-start low-voltage-dropout linear voltage regulator. Background Art

[0002] A low-dropout (LDO) voltage regulator circuit provides a specified, stable DC voltage (keeping the difference between its input and output voltages low to reduce power consumption). The circuit operates by feeding back an amplified error signal, which is then used to control the output current of a pass transistor (such as a power transistor) driving the load. The dropout voltage is the input / output differential voltage when loop regulation is lost (when the pass transistor operates in its linear region).

[0003] Figure 1 A typical known LDO structure is described. The LDO circuit includes an error amplifier circuit and a load circuit sensing circuit. The non-inverting input terminal of the error amplifier circuit is connected to a reference voltage V ref , its inverting input terminal and output voltage V out connection, its output voltage V c Connect the gate of MN3 to control the current flowing through MP4. This current is mirrored to the input and output power transistor Mpwr to match the load current. When the load current increases, the current provided by Mpwr is not enough to meet the load, resulting in V out This will cause Vc to rise, thereby increasing the output current of Mpwr and achieving the effect of negative feedback.

[0004] In order to prevent the LDO from causing a large amount of inrush current when starting, a typical known LDO will be designed with a soft start mode. This design requires a slowly rising voltage (SS) to control the base of a bipolar transistor connected in parallel with B2. ref During the startup phase, V out Will rise along with SS. When SS is equal to or higher than V ref When V out will be adjusted to be equal to V ref voltage.

[0005] This design requires a nF level capacitor C ss To generate a linear increasing voltage. Figure 2 As shown, a fixed current is supplied to C ss-ext Charge to control V out This design leads to the following two problems:

[0006] 1. C ss-ext Capacitors cannot be integrated on the chip and require additional pins, which increases the cost and area of ​​board-level design.

[0007] 2. The charging current during soft start depends on C out The size of the capacitor is such that when using a larger C out When the capacitor is connected, the overcurrent protection of the low-dropout linear regulator will cause nonlinearity and instability in the soft-start waveform, thereby introducing noise and electromagnetic interference to the entire system.

[0008] In order to solve the above problems, a charging current during soft start does not follow the output capacitor C out And the variable fixed soft-start low dropout linear regulator. Summary of the Invention

[0009] In order to solve the problems mentioned in the above background technology, the present invention provides a fixed soft-start low-dropout linear regulator.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] A fixed soft start low voltage dropout linear regulator, comprising an error amplifier circuit, a voltage dropout generating circuit, a load current sensing circuit, an output capacitor C out and capacitor C ss The input end of the load current sensing circuit is connected to the output end of the error amplifier; the output voltage V out and reference voltage V ref The error amplifier circuit includes a second NMOS transistor MN2; an output capacitor C out One end is connected to the output voltage V out connected, with the other end grounded; capacitor C ss One end is connected to the output voltage V out The other end is connected to the gate of the second NMOS transistor MN2.

[0012] Preferably, the voltage difference generating circuit includes a bipolar transistor B1 and a bipolar transistor B2, the inverting input terminal of the error amplifier circuit is connected to the base of the bipolar transistor B1, the non-inverting input terminal of the error amplifier is connected to the base of the bipolar transistor B2, and the output terminal of the error amplifier circuit is connected to the input terminal of the load current circuit sensing circuit.

[0013] Preferably, the output voltage V out Connected to the base of the bipolar transistor B1, the emitter of the bipolar transistor B1 is connected to the bias current Ibias, the reference voltage V ref Connected to the base of bipolar transistor B2, the emitter of bipolar transistor B2 is connected to the bias current Ibias.

[0014] Preferably, the load current circuit includes a fifth PMOS transistor MP5, an input power transistor Mpwr and a third NMOS transistor MN3 forming a current mirror, and the source of the fifth PMOS transistor MP5 is connected to the power supply voltage V in The gate of the fifth PMOS transistor MP5 is connected to the gate of the input power transistor Mpwr, the drain of the fifth PMOS transistor MP5 is connected to the gate and the drain of the third NMOS transistor MN3, and the source of the input power transistor Mpwr is connected to the power supply voltage V in The drain of the input power tube Mpwr is connected to the output voltage V out .

[0015] Preferably, the source of the third NMOS transistor MN3 is grounded, and the gate of the third NMOS transistor MN3 is connected to the error amplifier output terminal V c connect.

[0016] Preferably, the error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1 and a second NMOS transistor MN2; the drain of the second PMOS transistor MP2 is connected to the collector of the bipolar transistor B1, and the source of the second PMOS transistor MP2 is connected to the power supply voltage V in The gate and drain of the second PMOS tube MP2 are connected and connected to the gate of a PMOS tube MP1; the source of the first PMOS tube MP1 is connected to the power supply voltage V in The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1; the gate of the first NMOS transistor MN1 is connected to the drain and the gate of the second NMOS transistor MN2, the source of the first NMOS transistor is grounded, the drain of the fourth PMOS transistor MP4 is connected to the gate of the third NMOS transistor MN3, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage V in The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3; the source of the third PMOS tube MP3 is connected to the power supply voltage V in The gate and drain of the third PMOS transistor MP3 are connected, and the drain of the third PMOS transistor MP3 is connected to the collector of the bipolar transistor B2.

[0017] 7. The fixed soft-start low-dropout linear regulator according to claim 6, wherein: the gate and drain of the first NMOS transistor MN1 are connected and connected to the gate of the second NMOS transistor MN2, and the source of the first NMOS transistor is grounded; the source of the second NMOS transistor MN2 is grounded, the drain of the second NMOS transistor MN2 is connected to the drain of the fourth PMOS transistor MP4, and connected to the gate of the third NMOS transistor MN3.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention outputs the voltage V out Coupled to the gate input of the second NMOS transistor MN2 of the error amplifier circuit (such as Figure 3 ). In this way, the output voltage V out Lower than the reference voltage V ref When the soft start charging current is adjusted through the loop, the soft start time is adjusted to be independent of the output capacitor C out and load changes.

[0020] 2. Capacitor C ss =33pF can achieve a soft start time of 1.5V / ms, ( Figure 1 1nF is required in the chip), so the capacitor can be integrated into the chip to reduce the number of pins and peripheral devices.

[0021] In summary, the present invention overcomes the shortcomings of the prior art, has a reasonable design, and reduces the output voltage V out The gate input of the second NMOS transistor MN2 of the error amplifier circuit is coupled to adjust the soft start time not to change with the output capacitor C out and load changes, and has high social use value and application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a typical known LDO structure;

[0024] Figure 2 for Figure 1 The output voltage of the LDO V out Startup time curve;

[0025] Figure 3 This is a structural diagram of the LDO circuit of the present invention. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0027] In the present application, a MOSFET includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of a P-type MOSFET are the source, drain, and gate, respectively. The first terminal, second terminal, and control terminal of an N-type MOSFET are the drain, source, and gate, respectively. A bipolar transistor includes a first terminal, a second terminal, and a control terminal. When the bipolar transistor is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of a PNP-type bipolar transistor are the emitter, collector, and base, respectively. The first terminal, second terminal, and control terminal of an NPN-type bipolar transistor are the collector, emitter, and base, respectively.

[0028] Example 1

[0029] Reference Figure 3 , a fixed soft start low voltage dropout linear regulator, including an error amplifier circuit, a voltage dropout generating circuit, a load current sensing circuit, an output capacitor C out and capacitor C ss The input end of the load current sensing circuit is connected to the output end of the error amplifier. The voltage difference generating circuit includes a bipolar transistor B1 and a bipolar transistor B2. The reverse input end of the error amplifier circuit is connected to the base of the bipolar transistor B1. The output voltage V out Connected to the base of the bipolar transistor B1, the emitter of the bipolar transistor B1 is connected to the bias current Ibias, the non-inverting input of the error amplifier is connected to the base of the bipolar transistor B2, and the reference voltage V ref Connected to the base of the bipolar transistor B2, the emitter of the bipolar transistor B2 is connected to the bias current Ibias; the output end of the error amplifier circuit is connected to the input end of the load current circuit sensing circuit, and the output end of the load current circuit sensing circuit is connected to the output voltage V out The source of the input power tube Mpwr is connected to the power supply voltage V in The drain of the input power tube Mpwr is connected to the output voltage V out .

[0030] The load current circuit includes a fifth PMOS transistor MP5, an input power transistor Mpwr, and a third NMOS transistor MN3 forming a current mirror. The source of the fifth PMOS transistor MP5 is connected to the power supply voltage Vin The gate of the fifth PMOS transistor MP5 is connected to the gate of the input power transistor Mpwr, the drain of the fifth PMOS transistor MP5 is connected to the gate and the drain of the third NMOS transistor MN3, the source of the third NMOS transistor MN3 is grounded, and the gate of the third NMOS transistor MN3 is connected to the error amplifier output terminal V c connect.

[0031] The error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1 and a second NMOS transistor MN2; the drain of the second PMOS transistor MP2 is connected to the collector of the bipolar transistor B1, and the source of the second PMOS transistor MP2 is connected to the power supply voltage V in The gate and drain of the second PMOS tube MP2 are connected and connected to the gate of a PMOS tube MP1; the source of the first PMOS tube MP1 is connected to the power supply voltage V in The drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1; the gate of the first NMOS tube MN1 is connected to the drain and connected to the gate of the second NMOS tube MN2, and the source of the first NMOS tube is grounded; the source of the second NMOS tube MN2 is grounded, the drain of the second NMOS tube MN2 is connected to the drain of the fourth PMOS tube MP4 and connected to the gate of the third NMOS tube MN3; the drain of the fourth PMOS tube MP4 is connected to the gate of the third NMOS tube MN3, and the source of the fourth PMOS tube MP4 is connected to the power supply voltage V in The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3; the source of the third PMOS tube MP3 is connected to the power supply voltage V in The gate and drain of the third PMOS transistor MP3 are connected, and the drain of the third PMOS transistor MP3 is connected to the collector of the bipolar transistor B2.

[0032] Output voltage V out and reference voltage V ref The error voltage V c Connected to the third PMOS transistor MP3 to control the current flowing through the fourth PMOS transistor MP4, this current is mirrored to the input power transistor Mpwr to match the load current. When the load current increases, the current provided by the input power transistor Mpwr is not enough to meet the load, resulting in the output voltage V out This will cause the error voltage V c Rising, thereby increasing the output current of the input power tube Mpwr to achieve the effect of negative feedback.

[0033] Output capacitor C outOne end is connected to the output voltage V out Connect, with the other end grounded;

[0034] Capacitor C ss One end is connected to the output voltage V out The other end is connected to the gate of the second NMOS transistor MN2.

[0035] Working principle: When the output voltage V out Much lower than the reference voltage V ref When the entire bias current Ibias flows through the bipolar transistor B2, the bipolar transistor B1, the first PMOS transistor MP1 and the second PMOS transistor MP2 have no current, and the current flowing through the first NMOS transistor MN1 is supplied by the capacitor C ss Provided, the charging current I can be obtained through the charging characteristics of the capacitor css :

[0036] I css =C ss *(d(V out -V mn1 ) / dt)

[0037] This current is equal to the current flowing through the fourth PMOS transistor MP4 in the equilibrium state and determines the error voltage V c The voltage is used to control the circuit. When the output voltage rises too fast, I css This will increase the current of the second PMOS transistor MP2 and reduce the error voltage V c , reducing the output current and slowing down the output voltage V out Ascent rate.

[0038] Capacitor C ss The calculation formula is as follows:

[0039] C ss =Ib / (dV out / dt)

[0040] 1. C ss =33pF can achieve a soft start time of 1.5V / ms, ( Figure 1 1nF is required in the chip), so the capacitor can be integrated into the chip to reduce the number of pins and peripheral devices.

[0041] 2. Charging current I css Will not change with the output capacitor C out The charging current can be kept below the overcurrent protection level, which reduces the impact on the power supply and reduces noise and electromagnetic interference.

[0042] In the description of the present invention, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0043] In the present invention, unless otherwise expressly specified or limited, terms such as "disposed," "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integration; they may refer to mechanical connections, direct connections, or indirect connections through an intermediate medium; they may refer to internal communication between two elements or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0044] The control method of the present invention is automatic control through a controller. The control circuit of the controller can be implemented by simple programming by a person skilled in the art. The provision of power is also common knowledge in the art. The present invention is mainly used to protect mechanical devices, so the control method and circuit connection are not explained in detail in the present invention.

[0045] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A fixed soft-start low-dropout linear regulator, comprising Error amplifier circuit, voltage difference generating circuit, load current sensing circuit, output capacitor C out and capacitor C ss , the input end of the load current sensing circuit is connected to the output end of the error amplifier; Output voltage V out and reference voltage V ref They are respectively input to the inverting input terminal and the non-inverting input terminal of the error amplifier circuit, and the error amplifier circuit includes a second NMOS transistor MN2; Output capacitor C out One end is connected to the output voltage V out Connect, with the other end grounded; Capacitor C ss One end is connected to the output voltage V out The other end is connected to the gate of the second NMOS transistor MN2.

2. The fixed soft-start low-dropout linear regulator according to claim 1, characterized in that: The voltage difference generating circuit includes a bipolar transistor B1 and a bipolar transistor B2, the inverting input end of the error amplifier circuit is connected to the base of the bipolar transistor B1, the non-inverting input end of the error amplifier is connected to the base of the bipolar transistor B2, and the output end of the error amplifier circuit is connected to the input end of the load current circuit sensing circuit.

3. The fixed soft-start low-dropout linear regulator according to claim 2, characterized in that: The output voltage V out Connected to the base of the bipolar transistor B1, the emitter of the bipolar transistor B1 is connected to the bias current Ibias, the reference voltage V ref Connected to the base of bipolar transistor B2, the emitter of bipolar transistor B2 is connected to the bias current Ibias.

4. The fixed soft-start low-dropout linear regulator according to claim 3, characterized in that: The load current circuit includes a fifth PMOS transistor MP5, an input power transistor Mpwr, and a third NMOS transistor MN3 forming a current mirror. The source of the fifth PMOS transistor MP5 is connected to the power supply voltage V in The gate of the fifth PMOS transistor MP5 is connected to the gate of the input power transistor Mpwr, the drain of the fifth PMOS transistor MP5 is connected to the gate and the drain of the third NMOS transistor MN3, and the source of the input power transistor Mpwr is connected to the power supply voltage V in The drain of the input power tube Mpwr is connected to the output voltage V out .

5. The fixed soft-start low-dropout linear regulator according to claim 4, characterized in that: The source of the third NMOS transistor MN3 is grounded, and the gate of the third NMOS transistor MN3 is connected to the output terminal V c connect.

6. The fixed soft-start low-dropout linear regulator according to claim 1, characterized in that: The error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1 and a second NMOS transistor MN2; the drain of the second PMOS transistor MP2 is connected to the collector of the bipolar transistor B1, and the source of the second PMOS transistor MP2 is connected to the power supply voltage V in The gate and drain of the second PMOS tube MP2 are connected and connected to the gate of a PMOS tube MP1; the source of the first PMOS tube MP1 is connected to the power supply voltage V in The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1; the gate of the first NMOS transistor MN1 is connected to the drain and the gate of the second NMOS transistor MN2, the source of the first NMOS transistor is grounded, the drain of the fourth PMOS transistor MP4 is connected to the gate of the third NMOS transistor MN3, and the source of the fourth PMOS transistor MP4 is connected to the power supply voltage V in The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3; the source of the third PMOS tube MP3 is connected to the power supply voltage V in The gate and drain of the third PMOS transistor MP3 are connected, and the drain of the third PMOS transistor MP3 is connected to the collector of the bipolar transistor B2.

7. The fixed soft-start low-dropout linear regulator according to claim 6, characterized in that: The gate and drain of the first NMOS transistor MN1 are connected and connected to the gate of the second NMOS transistor MN2, and the source of the first NMOS transistor is grounded; the source of the second NMOS transistor MN2 is grounded, and the drain of the second NMOS transistor MN2 is connected to the drain of the fourth PMOS transistor MP4 and connected to the gate of the third NMOS transistor MN3.

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