Hall device bias circuit and bias current control method

Abstract

The embodiment of the invention discloses a Hall device bias circuit and a bias current control method. The Hall device bias circuit comprises a channel selection module, an operational amplifier module, a first transistor, a first switch, a bias current control module, a current mirror module and a second switch, the Hall device biasing circuit is used for controlling the first switch and the second switch to be switched on when the channel selection module selects a power supply signal end so as to generate a bias current related to the equivalent impedance of the Hall device; and the control module is used for controlling the first switch and the second switch to be switched off when the channel selection module selects the other power supply signal end so as to bias the Hall device according to the bias current. According to the technical scheme provided by the embodiment of the invention, the problem that a traditional Hall device biasing circuit cannot dynamically adjust the biasing current according to the equivalent impedance change is solved, and the sensitivity of the Hall device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of Hall sensors, and in particular to a Hall device bias circuit and a bias current control method. Background Art

[0002] With the rapid development of automotive electrification, various control systems are transitioning from traditional mechanical control to electrical control, and the use of motors is gradually expanding. Hall effect sensors are essential components for motor applications. They use the Hall effect to sense the position and speed of the motor rotor, ensuring smooth and reliable operation. Hall effect sensors primarily consist of a Hall element, a Hall effect bias circuit, and an amplifier circuit.

[0003] Hall effect devices are passive devices that require a bias circuit to generate a voltage signal related to the magnetic field. This voltage signal can be used to determine the strength and direction of the magnetic field, thereby determining the position and speed of the motor rotor. Traditional Hall effect device bias circuits are implemented in two ways: voltage bias and current bias. Current bias is more effective in eliminating the Hall effect device's own offset voltage, so it is most commonly used.

[0004] However, the equivalent resistance of a Hall effect device varies with process and temperature. In particular, the resistance can vary significantly across temperatures. Designs typically prioritize the maximum equivalent resistance of the Hall effect device and select an appropriate bias current, but this can reduce the sensitivity of the Hall effect device. Summary of the Invention

[0005] The present invention provides a Hall effect device bias circuit and a bias current control method to solve the problem that the traditional Hall effect device bias circuit cannot dynamically adjust the bias current according to the change of equivalent impedance.

[0006] According to one aspect of the present invention, a Hall device bias circuit is provided, comprising: a channel selection module, an operational amplifier module, a first transistor, a first switch, a bias current control module, a current mirror module, and a second switch;

[0007] The input end of the channel selection module is connected to at least two power signal ends, the output end of the channel selection module is connected to the first input end of the operational amplifier module, the second input end of the operational amplifier module is connected to the second end of the Hall device and the fourth end of the Hall device, the output end of the operational amplifier module is connected to the gate of the first transistor and the first end of the first switch, the second end of the first switch is connected to the first end of the bias current control module, the second end of the bias current control module is connected to the ground end, the first electrode of the first transistor and the third end of the bias current control module are connected to the first power signal end, the second electrode of the first transistor is connected to the first end of the Hall device, the third end of the Hall device is connected to the first end of the current mirror module, the fourth end of the bias current control module is connected to the second end of the current mirror module, the first end of the second switch is connected to the third end of the Hall device, the second end of the second switch is connected to the third end of the current mirror module, and the third end of the current mirror module is connected to the ground end;

[0008] The channel selection module is used to select any input terminal and output terminal; the operational amplifier module is used to control the voltage of the second terminal of the Hall device and the fourth terminal of the Hall device to the voltage of the power signal terminal selected by the channel selection module; the bias current control module is used to control the bias current of the Hall device according to the on or off state of the first switch and the second switch; the Hall device bias circuit is used to control the first switch and the second switch to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device; and to control the first switch and the second switch to be turned off when the channel selection module selects another power signal terminal, so as to bias the Hall device according to the bias current.

[0009] Optionally, the bias current control module includes a first capacitor and a second transistor, the first end of the first capacitor is connected to the second end of the first switch and the gate of the second transistor, the second end of the first capacitor is connected to the ground end, the first electrode of the second transistor is connected to the first power supply signal end, and the second electrode of the second transistor is connected to the second end of the current mirror module.

[0010] Optionally, the current mirror module includes a third transistor and a fourth transistor, the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the ground terminal, the second electrode of the third transistor is connected to the fourth terminal of the bias current control module and the gate of the third transistor, the gate of the third transistor is connected to the gate of the fourth transistor, the second electrode of the fourth transistor is connected to the third terminal of the Hall device and the first terminal of the second switch, and the second terminal of the second switch is connected to the first electrode of the fourth transistor.

[0011] Optionally, the third transistor and the fourth transistor include NMOS transistors.

[0012] Optionally, the operational amplifier module includes a first operational amplifier, a first input terminal of the first operational amplifier is connected to the output terminal of the channel selection module, a second input terminal of the first operational amplifier is connected to the second terminal of the Hall device and the fourth terminal of the Hall device, and an output terminal of the first operational amplifier is connected to the gate of the first transistor.

[0013] Optionally, the channel selection module includes at least a first selection switch and a second selection switch, the first end of the first selection switch is connected to the second power supply signal end, the first end of the second selection switch is connected to the third power supply signal end, and the second end of the first selection switch and the second end of the second selection switch are connected to the first input end of the operational amplifier module.

[0014] Optionally, the first transistor and the second transistor include PMOS transistors.

[0015] According to another aspect of the present invention, a method for controlling a bias current of a Hall device is provided, which is applied to any of the above-mentioned Hall device bias circuits. The method for controlling a bias current of a Hall device comprises:

[0016] When the channel selection module selects a power signal terminal, controlling the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device;

[0017] When the channel selection module selects another power signal terminal, the first switch and the second switch are controlled to be turned off, so as to bias the Hall device according to the bias current.

[0018] Optionally, when the channel selection module selects a power signal terminal, controlling the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device includes:

[0019] When the channel selection module selects a power signal terminal, the first switch and the second switch are controlled to be turned on, and the bias current control module generates a bias current related to the equivalent impedance of the Hall device and maintains the bias current.

[0020] Optionally, when the channel selection module selects another power signal terminal, controlling the first switch and the second switch to be turned off so as to bias the Hall device according to the bias current includes:

[0021] When the channel selection module selects another power signal terminal, the first switch and the second switch are controlled to be turned off, and the bias current control module uses the maintained bias current to flow through the Hall device.

[0022] The technical solution of the embodiment of the present invention is to set a channel selection module, a first switch, a second switch, an operational amplifier module and a bias current control module. The operational amplifier module can ensure that the voltage at the second and fourth ends of the Hall device signal is stable at the selected power supply voltage. By controlling the states of the channel selection module, the first switch and the second switch, the bias circuit of the Hall device is divided into two stages. In the first stage, the bias current of the Hall device can be set to a suitable bias current according to the equivalent resistance of the Hall device. In the second stage, the bias current of the first stage can be used to enable the Hall device to work normally. The technical solution of the embodiment of the present invention solves the problem that the bias circuit of the traditional Hall device cannot dynamically adjust the bias current according to the change of the equivalent impedance, thereby improving the sensitivity of the Hall device.

[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 1 is a schematic diagram of a Hall device bias circuit in the related art;

[0026] Figure 2 1 is a schematic structural diagram of a Hall device bias circuit provided by an embodiment of the present invention;

[0027] Figure 3 1 is a schematic structural diagram of another Hall device bias circuit provided by an embodiment of the present invention;

[0028] Figure 4 1 is a schematic structural diagram of another Hall device bias circuit provided by an embodiment of the present invention;

[0029] Figure 5 1 is a circuit schematic diagram of a Hall device bias circuit provided by an embodiment of the present invention;

[0030] Figure 6 This is a flow chart of a Hall device bias current control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] The Hall device is equivalent to a four-resistor bridge model. Since it is a passive device, a bias circuit is required to generate a voltage signal related to the magnetic field. The strength and direction of the magnetic field can be determined by detecting the voltage signal, thereby obtaining the position and speed of the motor rotor. The structure of the Hall device bias circuit in related technology is as follows: Figure 1As shown, the negative terminal of the op amp OP is connected to 0.5*VDD as a reference voltage, and the two positive terminals of the op amp OP are connected to the B and D terminals of the Hall device, respectively, to clamp the common-mode voltage of the B and D terminals of the Hall device to 0.5*VDD. The output of the op amp is connected to the gate of transistor MP1, the source of transistor MP1 is connected to the power supply VDD, and the drain of transistor MP1 is connected to the A terminal of the Hall device. The first terminal of the bias current source Ibias is connected to the power supply VDD, and the other terminal of the bias current source Ibias is connected to the drain of transistor MN1. The drain of transistor MN1 is short-circuited with the gate of transistor MN1 and connected to the gate of transistor MN2. The drain of transistor MN2 is connected to the C terminal of the Hall device. The sources of transistors MN1 and MN2 are both connected to the ground terminal GND. Here, the power supply and power supply voltage are both represented by VDD, and the bias current source and bias current are both represented by Ibias.

[0034] Transistors MN1 and MN2 form a current mirror structure. The current flowing through transistor MN2 depends on the bias current Ibias and the size ratio of transistors MN2 and MN1. Here, transistors MN2 and MN1 are equal in size, so the current flowing through transistor MN2 is the bias current Ibias. Therefore, the current flowing through the Hall device is the bias current Ibias. Assuming the Hall device's equivalent resistance R1 = R2 = R3 = R4 = 5 kΩ, voltage VDD = 5 V, and bias current Ibias = 0.5 mA, due to the virtual short characteristic of op amp OP during normal operation, the voltages VB and VD at the B and D terminals of the Hall device are both 0.5 VDD, or 2.5 V. The current flowing through transistor MN2 is generated by transistor MP1 and flows through R1, R2, R3, and R4 into transistor MN2. Therefore, the voltage at terminal A of the Hall effect device is VA = VD + R1 * (0.5 * Ibias) = ​​3.75V, and the voltage at terminal C is VC = VD - R4 * (0.5 * Ibias) = ​​1.25V. At this time, the source-drain voltage of transistor MP1 is VDS1 = VDD - VA = 1.25V, and the source-drain voltage of transistor MN2 is VDS2 = VC = 1.25V. Choosing the appropriate sizes for transistors MP1 and MN2 ensures that their source-drain voltages are greater than the drive voltage, thereby ensuring that transistors MP1 and MN2 are in their saturation regions, ensuring reliable and normal operation of this structure.

[0035] In practice, the equivalent resistance of a Hall effect device exhibits varying values ​​depending on the process and temperature. In particular, the resistance can vary significantly at different temperatures. Assuming the equivalent resistance of the Hall effect device at high temperature is R1 = R2 = R3 = R4 = 10kΩ, the power supply VDD = 5V, the bias current Ibias = 0.5mA, the voltage at terminal A of the Hall effect device is VA = VD + R1 * (0.5 * Ibias) = ​​5V, and the voltage at terminal C is VC = VD - R4 * (0.5 * Ibias) = ​​0V. At this point, the source-drain voltage of transistor MP1 is VDS1 = VDD - VA = 0V, and the source-drain voltage of transistor MN2 is VDS2 = VC = 0V. Both transistors MP1 and MN2 are in their linear regions, which compromises the virtual short characteristics of the op amp OP. Furthermore, the current flowing through transistor MN2 no longer equals the bias current Ibias. Consequently, all of the above calculations fail, rendering the entire circuit uncontrollable. To avoid this problem, designs typically consider the maximum equivalent resistance of the Hall device and select an appropriate bias current. For example, a bias current of 0.25 mA is chosen here to meet the 10 kΩ equivalent resistance of the Hall device at high temperatures. However, this reduces the sensitivity of the Hall device, which is generally expressed as uV / mT / mA. This refers to the voltage signal generated in uV under a 1mT magnetic field with a 1mA bias current. When the bias current is halved, the voltage signal generated under a 1mT magnetic field is also halved. Simply to meet the high-temperature bias requirement, the bias current must be reduced to half the bias current required at room temperature, which reduces the sensitivity at room temperature by half. This imposes many limitations in practical applications. The fundamental drawback is that the bias current, generated by the bias current source, does not change synchronously with the equivalent resistance of the Hall device. When the resistance increases, the current cannot decrease, and when the resistance decreases, the current cannot increase, making dynamic adjustment impossible.

[0036] In view of this, Figure 2 This is a schematic diagram of the structure of a Hall device bias circuit provided by an embodiment of the present invention. This embodiment is applicable to scenarios where Hall sensors with high sensitivity are required, such as current detection, position sensing, and speed measurement. Figure 1 As shown, the Hall device bias circuit includes: a channel selection module 101 , an operational amplifier module 102 , a first transistor 103 , a first switch 104 , a bias current control module 105 , a current mirror module 106 and a second switch 107 .

[0037] The input end of the channel selection module 101 is connected to at least two power signal ends, the output end of the channel selection module 101 is connected to the first input end of the operational amplifier module 102, the second input end of the operational amplifier module 102 is connected to the second end of the Hall device 201 and the fourth end of the Hall device 201, the output end of the operational amplifier module 102 is connected to the gate of the first transistor 103 and the first end of the first switch 104, the second end of the first switch 104 is connected to the first end of the bias current control module 105, the second end of the bias current control module 105 is connected to the ground end GND, and the first transistor 103 is connected to the gate of the first transistor 103 and the first end of the first switch 104. A first terminal of the first transistor 103 and a third terminal of the bias current control module 105 are connected to the first power signal terminal VDD, a second terminal of the first transistor 103 is connected to the first terminal of the Hall device 201, a third terminal of the Hall device 201 is connected to the first terminal of the current mirror module 106, a fourth terminal of the bias current control module 105 is connected to the second terminal of the current mirror module 106, a first terminal of the second switch 107 is connected to the third terminal of the Hall device 201, a second terminal of the second switch 107 is connected to the third terminal of the current mirror module 106, and a third terminal of the current mirror module 106 is connected to the ground terminal GND.

[0038] The channel selection module 101 is used to select any input terminal and output terminal of itself; the operational amplifier module 102 is used to control the voltage of the second terminal of the Hall device 201 and the fourth terminal of the Hall device 201 to the voltage of the power signal terminal selected by the channel selection module 101; the bias current control module 105 is used to control the bias current of the Hall device 201 according to the on or off state of the first switch 104 and the second switch 107; the Hall device bias circuit is used to control the first switch 104 and the second switch 107 to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device 201; and to control the first switch 104 and the second switch 107 to be turned off when the channel selection module selects another power signal terminal, so as to bias the Hall device 201 according to the bias current.

[0039] The channel selection module 101 may include multiple switches. The input of the channel selection module 101 is connected to at least two power signal terminals, and it can select a power signal from the at least two power signal terminals and output the selected power signal to the operational amplifier module 102. The voltages of the two power signal terminals can be different. For example, the voltage of one power signal terminal can be 0.25 times the voltage of the first power signal terminal, and the voltage of the other power signal terminal can be 0.5 times the voltage of the first power signal terminal. The operational amplifier module 102 may be an operational amplifier. The operational amplifier module 102 may clamp the voltages of the second and fourth terminals of the Hall effect device 201 to the voltage of the power signal terminal selected by the channel selection module 101. The gate voltage of the first transistor 103 is controlled by the operational amplifier module 102. The first transistor 103 may be a PMOS transistor. The first electrode of the first transistor 103 may be a source electrode, and the second electrode may be a drain electrode. The first switch 104 may control the connection between the output of the operational amplifier module 102 and the bias current control module 105. The bias current control module 105 can generate a bias current based on the equivalent impedance of the Hall device 201 when the first switch 104 and the second switch 107 are turned on, and maintain the bias current based on the equivalent impedance of the Hall device 201 when the first switch 104 and the second switch 107 are turned off. The current mirror module 106 can include two or more transistors, which can include a reference transistor and a mirror transistor. The current mirror module 106 can mirror the current flowing through its second terminal to its first terminal. The mirror current is the bias current flowing through the Hall device 201. The third terminal of the current mirror module 106 is connected to the second terminal of the second switch 107, and the third terminal of the current mirror module 106 is also connected to the ground terminal GND.

[0040] Specifically, in the first stage, the channel selection module 101 selects a power signal terminal, which can be a power signal terminal with a lower voltage, and controls the first switch 104 and the second switch 107 to be conductive. The operational amplifier module 102 clamps the voltages of the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is conductive, the output terminal of the operational amplifier module 102 is also connected to the bias current control module 105. The first transistor 103 is conductive, and current flows through the first transistor 103 into the first terminal of the Hall device 201. The current flows through the internal resistance of the Hall device 201 and out of the third terminal. Since the second switch 107 is conductive, the third terminal of the Hall device 201 is connected to the third terminal of the current mirror module 106, that is, to the ground terminal GND. At this time, the current generated by the bias current control module 105 is the same as the bias current flowing into the Hall device 201 from the first transistor 103. The current generated by the bias current control module 105 flows into the current mirror module 105 and then flows into the ground terminal GND. In the second phase, channel selection module 101 selects another power signal terminal, which can be a higher voltage power signal terminal. It controls first switch 104 and second switch 107 to turn off, and operational amplifier module 102 clamps the second and fourth terminals of Hall device 201 to the voltage of the selected power signal terminal. Since first switch 104 is turned off, the output terminal of operational amplifier module 102 is no longer connected to bias current control module 105. At this point, bias current control module 105 is no longer controlled by the voltage of operational amplifier module 102. Second switch 107 is turned off, disconnecting the third terminal of Hall device 201 from the third terminal of current mirror module 106, effectively disconnecting it from ground GND. At this point, current mirror module 106 is in normal operation. Bias current control module 105 uses the bias current generated in the first phase to flow through the second terminal of current mirror module 106. Current mirror module 106 mirrors the bias current to its first terminal, whereupon it flows into Hall device 201, ensuring that the current flowing into Hall device 201 is the bias current maintained during the first phase. At this point, the source-drain voltage of the first transistor and the source-drain voltage of the mirror transistor in the current mirror module 105 can be guaranteed to have sufficient margin to ensure that they operate in the saturation region, thereby ensuring that the bias current of the Hall device 201 is maintained at the current maintained in the first stage, while maintaining the second and fourth terminals of the Hall device 201 clamped to the voltage of the selected power signal terminal. This stage is the normal operating mode of the Hall device 201, which is used to sense the magnetic field and output the Hall voltage.

[0041] The technical solution of the embodiment of the present invention is to set a channel selection module, a first switch, a second switch, an operational amplifier module and a bias current control module. The operational amplifier module can ensure that the voltage at the second and fourth ends of the Hall device signal is stable at the selected power supply voltage. By controlling the states of the channel selection module, the first switch and the second switch, the bias circuit of the Hall device is divided into two stages. In the first stage, the bias current of the Hall device can be set to a suitable bias current according to the equivalent resistance of the Hall device. In the second stage, the bias current of the first stage can be used to enable the Hall device to work normally. The technical solution of the embodiment of the present invention solves the problem that the bias circuit of the traditional Hall device cannot dynamically adjust the bias current according to the change of the equivalent impedance, thereby improving the sensitivity of the Hall device.

[0042] Figure 3 is a schematic structural diagram of another Hall device bias circuit provided by an embodiment of the present invention. In some optional embodiments of the present invention, such as Figure 3 As shown, the bias current control module 105 includes a first capacitor C1 and a second transistor 1051, the first end of the first capacitor C1 is connected to the second end of the first switch 104 and the gate of the second transistor 1051, the second end of the first capacitor C1 is connected to the ground end, the first electrode of the second transistor 1051 is connected to the first power signal end VDD, and the second electrode of the second transistor 1051 is connected to the second end of the current mirror module 106.

[0043] Wherein, the first capacitor C1 can be a storage capacitor. The first electrode of the second transistor 1051 can be a source electrode, and the second electrode can be a drain electrode. When the first switch 104 is turned on, the voltage at the output terminal of the operational amplifier module 102 is transmitted to the first end of the first capacitor C1 and the gate of the second transistor 1051 through the turned-on first switch 104. At this time, the first capacitor C1 is charged, and the voltage across it reaches and remains at this voltage value. When the first switch 104 is turned off, the voltage stored by the first capacitor C1 continues to be applied to the gate of the second transistor 1051, and the current flowing through the second transistor 1051 will not change.

[0044] In some optional embodiments of the present invention, continue to refer to Figure 3 The current mirror module 106 includes a third transistor 1061 and a fourth transistor 1062. The first electrode of the third transistor 1061 and the first electrode of the fourth transistor 1062 are connected to the ground terminal GND, the second electrode of the third transistor 1061 is connected to the fourth terminal of the bias current control module 105 and the gate of the third transistor 1061, the gate of the third transistor 1061 is connected to the gate of the fourth transistor 1062, the second electrode of the fourth transistor 1062 is connected to the third terminal of the Hall device 201 and the first terminal of the second switch 107, and the second terminal of the second switch 107 is connected to the first electrode of the fourth transistor 1062.

[0045] The current mirror module 106 may be an NMOS current mirror, and the third transistor 1061 and the fourth transistor 1062 may be NMOS transistors. The first electrodes of the third transistor 1061 and the fourth transistor 1062 may be sources, and the second electrodes may be drains. The third transistor 1061 may be a reference transistor for the current mirror module 106. The gate and drain of the third transistor 1061 are short-circuited for setting a reference current. The fourth transistor 1062 may be a mirror transistor for the current mirror module 106. The gate of the fourth transistor 1062 is connected to the gate of the third transistor 1061 for replicating the reference current to provide a bias current for the Hall effect device 201.

[0046] In some alternative embodiments of the present invention, the third transistor and the fourth transistor include NMOS transistors.

[0047] The sources of the third transistor and the fourth transistor are both connected to the ground terminal, and the bias current of the Hall device needs to flow from the third terminal to the ground.

[0048] Figure 4 is a structural diagram of another Hall device bias circuit provided by an embodiment of the present invention. In some optional embodiments of the present invention, such as Figure 4 As shown, the operational amplifier module 102 includes a first operational amplifier 1021, a first input terminal of the first operational amplifier 1021 is connected to the output terminal of the channel selection module 101, a second input terminal of the first operational amplifier is connected to the second terminal of the Hall device 201 and the fourth terminal of the Hall device 201, and an output terminal of the first operational amplifier is connected to the gate of the first transistor 103.

[0049] Unlike conventional op amps, first operational amplifier 1021 has a structure similar to a common-mode feedback circuit. Leveraging its virtual short characteristic, first operational amplifier 1021 clamps the voltages at the second and fourth terminals of Hall effect device 201 to the power supply signal voltage selected by channel selection module 101, providing a stable common-mode operating point for Hall effect device 201 and ensuring current control.

[0050] In some optional embodiments of the present invention, continue to refer to Figure 4 The channel selection module 101 includes at least a first selection switch 1011 and a second selection switch 1012, a first end of the first selection switch 1011 is connected to the second power signal terminal VDD1, a first end of the second selection switch 1012 is connected to the third power signal terminal VDD2, and a second end of the first selection switch 1011 and a second end of the second selection switch 1012 are connected to the first input terminal of the operational amplifier module 102.

[0051] The second end of the first selection switch 1011 and the second end of the second selection switch 1012 are connected in parallel and connected to the first input terminal of the operational amplifier module 102. The first selection switch 1011 is used to control the connection between the second power supply signal terminal VDD1 and the first input terminal of the operational amplifier module 102. The second selection switch 1012 is used to control the connection between the third power supply signal terminal VDD2 and the first input terminal of the operational amplifier module 102. The first selection switch 1011 and the second selection switch 1012 are mutually exclusive. For example, when the second power supply signal terminal VDD1 is to be selected, the first selection switch 1011 is closed and the second selection switch 1012 is open. When the third power supply signal terminal VDD2 is to be selected, the second selection switch 1012 is closed and the first selection switch 1011 is closed.

[0052] In some optional embodiments of the present invention, the first transistor and the second transistor include PMOS transistors.

[0053] The sources of the first transistor and the second transistor are both connected to the first power signal terminal VDD, and current flows from the first power signal terminal VDD. The first transistor can control the current flowing from the first power signal terminal VDD to the first terminal of the Hall device. The second transistor can generate a reference circuit that flows from the first power signal terminal VDD to the current mirror module. The PMOS transistor is turned on when the gate voltage is lower than the source voltage by a threshold voltage. When turned on, current flows from the source to the drain. The first transistor and the second transistor, including the PMOS transistor, can ensure the current path of the Hall bias circuit.

[0054] Figure 5 FIG. 1 is a circuit schematic diagram of a Hall device bias circuit provided by an embodiment of the present invention, such as Figure 5As shown, the negative terminal of the first operational amplifier 1021 is connected to the second power signal terminal VDD1 and the third power signal terminal VDD2 via the first selection switch 1011 and the second selection switch 1012, respectively. The two positive terminals of the first operational amplifier 1021 are connected to the B terminal and the D terminal of the Hall device 201, respectively, so that the common-mode voltage of the B terminal and the D terminal of the Hall device can be clamped to the voltage of the second power signal terminal VDD1 or the third power signal terminal VDD2. The output terminal of the first operational amplifier 1021 is connected to the gate of the first transistor 103, and is connected to the gate of the second transistor 1051 and one end of the first capacitor C1 via the first switch 104. The other end of the capacitor C1 is connected to the ground terminal GND. The source of the first transistor 103 is connected to the first power signal terminal VDD, and the drain is connected to the A terminal of the Hall device 201. The source of the second transistor 1051 is connected to the first power signal terminal VDD, and the drain is connected to the drain and gate of the third transistor 1061 and the gate of the fourth transistor 1062. The drain of the fourth transistor 1062 is connected to the C terminal of the Hall device 201 and one end of the second switch 107. The other end of the second switch 107 and the sources of the third and fourth transistors 1061 and 1062 are all connected to the ground terminal GND. Here, the first transistor 103 and the second transistor 1051 are of equal size, and the third transistor 1061 and the fourth transistor 1062 are of equal size.

[0055] Assume that the voltage of the second power signal terminal VDD1 is 0.25 times the voltage of the first power signal terminal VDD, the voltage of the third power signal terminal VDD2 is 0.5 times the voltage of the first power signal terminal VDD, and the voltage of the first power signal terminal VDD is 5V. At room temperature, R1=R2=R3=R4=5KΩ, and at high temperature, R1=R2=R3=R4=10KΩ.

[0056] At room temperature, in the first stage, first selection switch 1011 is on, controlling the conduction of first switch 104 and second switch 107. Due to the virtual short characteristic of first operational amplifier 1021 during normal operation, the voltages VB and VD at terminals B and D of the Hall device are both 0.25VDD, where VDD = 5V and VB = VD = 1.25V. At this time, terminal C of the Hall device is connected to ground GND via second switch 107. The on-resistance of second switch 107 is very small and can be ignored. Therefore, the current flowing through the Hall device is Ibias1 = VB / R3 + VD / R4 = 0.5mA, meaning that the current flowing through first transistor 103 is also 0.5mA. At this time, since first switch 104 is on, the gate-source voltages VGS of first transistor 103 and second transistor 1051 are the same, and since the sizes of first transistor 103 and second transistor 1051 are equal, the current flowing through second transistor 1051 and third transistor 1061 is also 0.5mA.

[0057] In the second phase, the second selection switch 1012 is turned on, controlling the first switch 104 and the second switch 107 to be turned off. Due to the presence of the first capacitor C1, the gate voltage of the second transistor 1051 remains unchanged from the state when the first switch 104 and the second switch 107 are turned on, and its current remains unchanged. Therefore, the current of the third transistor 1061 remains at 0.5 mA. Since the fourth transistor 1062 and the third transistor 1061 have the same size and the same gate-source power supply VGS, the current that can flow through the fourth transistor 1062 is also 0.5 mA. The current Ibias2 flowing through the Hall device 201 and the fourth transistor 1062 is also 0.5 mA. The negative terminal of the first operational amplifier 1021 is connected to 0.5VDD via the second selection switch 1012. Due to the virtual short characteristic of the first operational amplifier 1021, the voltages VB at the B and D terminals of the Hall device 201 are VD = 0.5*VDD = 2.5V, the voltage VA at the A terminal is VD + R1*(0.5*Ibias2) = 3.75V, and the voltage VC at the C terminal is VD - R4*(0.5*Ibias2) = 1.25V. At this time, the source-drain voltage VDS_1 of the first transistor 103 is VDD - VA = 1.25V, and the source-drain voltage VDS_2 of the fourth transistor 1062 is VDS_2 = VC = 1.25V. Selecting the appropriate sizes of the first transistor 103 and the fourth transistor 1062 ensures that their source-drain voltages are greater than the drive voltage, thereby ensuring that the first transistor 103 and the fourth transistor 1062 are in the saturation region, and this structure can operate reliably and normally.

[0058] At high temperatures, in the first stage, first selection switch 1011 is turned on, controlling the conduction of first switch 104 and second switch 107. Due to the virtual short characteristic of first operational amplifier 1021 during normal operation, the voltages VB and VD at terminals B and D of Hall device 201 are both 0.25VDD, where VDD = 5V and VB = VD = 1.25V. At this time, terminal C of Hall device 201 is connected to GND via second switch 107. The on-resistance of second switch 107 is very small and can be ignored here. Therefore, the current flowing through Hall device 201 is Ibias3 = VB / R3 + VD / R4 = 0.25mA, meaning that the current flowing through first transistor 103 is also 0.25mA. At this time, since the first switch 104 is turned on, the gate-source voltage VGS of the first transistor 103 and the second transistor 1051 are the same, and the sizes of the first transistor 103 and the second transistor 1051 are equal, so the current flowing through the second transistor 1051MP2 and the third transistor 1061 is also 0.25 mA.

[0059] In the second phase, the second selection switch 1012 is turned on, turning off the first switch 104 and the second switch 107. Due to the presence of the first capacitor C1, the gate voltage of the second transistor 1051 remains unchanged from the state when the first switch 104 and the second switch 107 are turned on, and its current remains unchanged. Therefore, the current of the third transistor 1061 remains at 0.25 mA. Since the fourth transistor 1062 has the same size as the third transistor 1061 and the same gate-source power supply VGS, the current that can flow through the fourth transistor 1062 is also 0.25 mA. The current Ibias4 flowing through the Hall device 201 is equal to that of the fourth transistor 1062, which is 0.25 mA. The negative terminal of the first operational amplifier 1021 is connected to 0.5VDD via the second selection switch 1012. Based on the virtual short characteristic of the first operational amplifier 1021, the voltages at terminals B and D of the Hall device 201 are: VB = VD = 0.5*VDD = 2.5V, the voltage at terminal A is VA = VD + R1*(0.5*Ibias4) = 3.75V, and the voltage at terminal C is VC = VD - R4*(0.5*Ibias4) = 1.25V. At this point, the source-drain voltage of the first transistor 103 is VDS_1 = VDD - VA = 1.25V, and the source-drain voltage of the fourth transistor 1062 is VDS_2 = VC = 1.25V. By selecting appropriately sized first and fourth transistors 103 and 1062 to ensure that their source-drain voltages are greater than the drive voltage, the first and fourth transistors 103 and 1062 are in their saturation regions, ensuring reliable and normal operation of the structure.

[0060] It can be seen that no matter what the temperature is, no matter how the equivalent impedance of the Hall device 201 changes, the source-drain voltage margin of the first transistor 103 and the fourth transistor 1062 can be guaranteed, thereby ensuring the normal operation of the Hall device bias circuit. There is no need to select a very small bias current to meet the equivalent impedance of the Hall device 201 under the maximum condition, as in the traditional structure, resulting in a reduction in the sensitivity of the Hall device 201. The technical solution of the embodiment of the present invention is applicable to all environments where the equivalent impedance of the Hall device 201 changes, including but not limited to temperature, process, packaging stress, etc.

[0061] Figure 6 This is a flow chart of a Hall device bias current control method provided by an embodiment of the present invention, which is applied to the Hall device bias circuit of any of the above embodiments, with reference to Figure 5 and Figure 6 , the Hall device bias current control method includes:

[0062] S301 , when the channel selection module 101 selects a power signal terminal, the first switch 105 and the second switch 107 are controlled to be turned on to generate a bias current related to the equivalent impedance of the Hall device 201 .

[0063] The channel selection module 101 selects a power signal terminal, which can be a power signal terminal with a lower voltage, and controls the first switch 104 and the second switch 107 to conduct. The operational amplifier module 102 clamps the voltages of the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is turned on, the output terminal of the operational amplifier module 102 is also connected to the bias current control module 105. The first transistor 103 is turned on, and current flows through the first transistor 103 into the first terminal of the Hall device 201. The current flows through the internal resistance of the Hall device 201 and out of the third terminal. Since the second switch 107 is turned on, the third terminal of the Hall device 201 is connected to the third terminal of the current mirror module 106, that is, to the ground terminal. At this time, the current generated by the bias current control module 105 is the same as the bias current flowing into the Hall device 201 from the first transistor 103. The current generated by the bias current control module 105 flows into the current mirror module 105 and then flows to the ground terminal.

[0064] S302 : When the channel selection module 101 selects another power signal terminal, the first switch 104 and the second switch 107 are controlled to be turned off, so as to bias the Hall device 201 according to the bias current.

[0065] The channel selection module 101 selects another power signal terminal, which can be a power signal terminal with a higher voltage, and controls the first switch 104 and the second switch 107 to be turned off. The operational amplifier module 102 clamps the second and fourth terminals of the Hall device 201 to the voltage of the selected power signal terminal. Since the first switch 104 is turned off, the output terminal of the operational amplifier module 102 is no longer connected to the bias current control module 105. At this time, the bias current control module 105 is no longer controlled by the voltage of the operational amplifier module 102. The second switch 107 is turned off, disconnecting the third terminal of the Hall device from the third terminal of the current mirror module 106, that is, no longer connected to the ground terminal. At this time, the current mirror module 106 is in normal operation. The bias current control module 105 uses the bias current stored in the first stage to flow through the second terminal of the current mirror module 106. The current mirror module 106 copies the bias current to its first terminal, thereby flowing into the Hall device 201, ensuring that the current flowing into the Hall device 201 is the bias current maintained in the first stage. At this point, the source-drain voltage margins of the first transistor 103 and the fourth transistor 1062 are guaranteed to be sufficient to ensure that they operate in the saturation region, thereby ensuring that the bias current of the Hall device 201 is maintained at the current maintained in the first stage, while maintaining the second and fourth terminals of the Hall device 201 clamped to the voltage of the selected power signal terminal. This stage is the normal operating mode of the Hall device 201, which is used to sense the magnetic field and output the Hall voltage.

[0066] In some optional embodiments of the present invention, continue to refer to Figure 5When the channel selection module 101 selects a power signal terminal, controlling the first switch 104 and the second switch 107 to be turned on to generate a bias current related to the equivalent impedance of the Hall device 201 includes:

[0067] When the channel selection module 101 selects a power signal terminal, the first switch 104 and the second switch 107 are controlled to be turned on, and the bias current control module 105 generates a bias current related to the equivalent impedance of the Hall device 201 and maintains the bias current.

[0068] In some optional embodiments of the present invention, continue to refer to Figure 5 When the channel selection module 101 selects another power signal terminal, controlling the first switch 104 and the second switch 107 to be turned off so as to bias the Hall device 201 according to the bias current includes:

[0069] When the channel selection module 101 selects another power signal terminal, the first switch 104 and the second switch 107 are controlled to be turned off, and the bias current control module 105 uses the maintained bias current to flow through the Hall device 201 .

[0070] In some optional embodiments of the present invention, continue to refer to Figure 5 The Hall device 201 includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The first end of the first resistor R1 is connected to the first end of the second resistor R2, and their common end is the first end A of the Hall device 201. The second end of the second resistor R2 is connected to the first end of the third resistor R3, and their common end is the second end B of the Hall device 201. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4, and their common end is the third end C of the Hall device 201. The second end of the fourth resistor R4 is connected to the second end of the first resistor R1, and their common end is the fourth end D of the Hall device 101.

[0071] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0072] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A Hall device bias circuit, characterized in that: include: A channel selection module, an operational amplifier module, a first transistor, a first switch, a bias current control module, a current mirror module, and a second switch; The input end of the channel selection module is connected to at least two power signal ends, the output end of the channel selection module is connected to the first input end of the operational amplifier module, the second input end of the operational amplifier module is connected to the second end of the Hall device and the fourth end of the Hall device, the output end of the operational amplifier module is connected to the gate of the first transistor and the first end of the first switch, the second end of the first switch is connected to the first end of the bias current control module, the second end of the bias current control module is connected to the ground end, the first electrode of the first transistor and the third end of the bias current control module are connected to the first power signal end, the second electrode of the first transistor is connected to the first end of the Hall device, the third end of the Hall device is connected to the first end of the current mirror module, the fourth end of the bias current control module is connected to the second end of the current mirror module, the first end of the second switch is connected to the third end of the Hall device, the second end of the second switch is connected to the third end of the current mirror module, and the third end of the current mirror module is connected to the ground end; The channel selection module is used to select any input terminal and output terminal; the operational amplifier module is used to control the voltage of the second terminal of the Hall device and the fourth terminal of the Hall device to the voltage of the power signal terminal selected by the channel selection module; the bias current control module is used to control the bias current of the Hall device according to the on or off state of the first switch and the second switch; the Hall device bias circuit is used to control the first switch and the second switch to be turned on when the channel selection module selects a power signal terminal, so as to generate a bias current related to the equivalent impedance of the Hall device; And it is used to control the first switch and the second switch to be turned off when the channel selection module selects another power signal terminal, so as to bias the Hall device according to the bias current.

2. The Hall device bias circuit according to claim 1, wherein: The bias current control module includes a first capacitor and a second transistor, wherein the first end of the first capacitor is connected to the second end of the first switch and the gate of the second transistor, the second end of the first capacitor is connected to the ground end, the first electrode of the second transistor is connected to the first power signal end, and the second electrode of the second transistor is connected to the second end of the current mirror module.

3. The Hall device bias circuit according to claim 1, wherein: The current mirror module includes a third transistor and a fourth transistor, wherein a first electrode of the third transistor and a first electrode of the fourth transistor are connected to a ground terminal, a second electrode of the third transistor is connected to a fourth terminal of the bias current control module and a gate of the third transistor, a gate of the third transistor is connected to a gate of the fourth transistor, a second electrode of the fourth transistor is connected to a third terminal of the Hall device and a first terminal of a second switch, and a second terminal of the second switch is connected to the first electrode of the fourth transistor.

4. The Hall device bias circuit according to claim 3, wherein: The third transistor and the fourth transistor include NMOS transistors.

5. The Hall device bias circuit according to claim 1, wherein: The operational amplifier module includes a first operational amplifier, a first input end of the first operational amplifier is connected to the output end of the channel selection module, a second input end of the first operational amplifier is connected to the second end of the Hall device and the fourth end of the Hall device, and an output end of the first operational amplifier is connected to the gate of the first transistor.

6. The Hall device bias circuit according to claim 1, wherein: The channel selection module includes at least a first gating switch and a second gating switch, wherein the first end of the first gating switch is connected to the second power signal end, the first end of the second gating switch is connected to the third power signal end, and the second end of the first gating switch and the second end of the second gating switch are connected to the first input end of the operational amplifier module.

7. The Hall device bias circuit according to claim 2, wherein: The first transistor and the second transistor include PMOS transistors.

8. A method for controlling bias current of a Hall device, characterized in that: Applied to the Hall device bias circuit according to any one of claims 1 to 7, the Hall device bias current control method includes: When the channel selection module selects a power signal terminal, controlling the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device; When the channel selection module selects another power signal terminal, the first switch and the second switch are controlled to be turned off, so as to bias the Hall device according to the bias current.

9. The Hall device bias current control method according to claim 8, characterized in that: When the channel selection module selects a power signal terminal, controlling the first switch and the second switch to be turned on to generate a bias current related to the equivalent impedance of the Hall device includes: When the channel selection module selects a power signal terminal, the first switch and the second switch are controlled to be turned on, and the bias current control module generates a bias current related to the equivalent impedance of the Hall device and maintains the bias current.

10. The Hall device bias current control method according to claim 8, wherein: When the channel selection module selects another power signal terminal, controlling the first switch and the second switch to be turned off so as to bias the Hall device according to the bias current includes: When the channel selection module selects another power signal terminal, the first switch and the second switch are controlled to be turned off, and the bias current control module uses the maintained bias current to flow through the Hall device.

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