Output power detection maximum power point tracking circuit and method based on time sampling
Through the output power detection maximum power point tracking circuit and method based on time sampling, the problem of traditional circuits being unable to achieve end-to-end maximum power output and high power consumption is solved, low-power application and modular design are realized, and it is adapted to different interface circuit structures.
Patent Information
- Application Number
- CN202510868351.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-09-26
AI Technical Summary
Traditional maximum power point tracking circuits cannot achieve end-to-end maximum power output, and high-precision current and voltage sampling leads to large power consumption, limiting their application in low-power scenarios.
An output power detection maximum power point tracking circuit and method based on time sampling is adopted, including a buck-boost converter and a maximum power point tracking control circuit. The output power detection and control are realized through time-voltage conversion, disturbance direction control, hill climbing algorithm control, peak current control and current zero-crossing detection.
The system can maintain sampling accuracy without high-power consumption current and voltage sampling, reduce sampling power consumption, achieve end-to-end maximum power output, and adapt to different interface circuit structures, thereby improving the modular design freedom of the system.
Smart Images
Figure CN120704465A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a circuit and method for output power detection and maximum power point tracking based on time sampling. Background Art
[0002] The output power of the energy harvesting interface circuit changes with load conditions. To ensure that the energy harvesting interface circuit can stably output at maximum power under different load conditions, a maximum power point tracking circuit is required. This circuit can maximize the output power of the energy harvesting interface circuit under varying input and load conditions. Traditional maximum power point tracking circuits only track input power and cannot achieve end-to-end maximum power output. Furthermore, the maximum power point tracking circuit requires high-precision current and voltage sampling, which results in significant power consumption and reduces the output power of the energy harvesting interface circuit. Summary of the Invention
[0003] The main purpose of the embodiments of the present application is to propose an output power detection maximum power point tracking circuit and method based on time sampling to achieve end-to-end maximum power output of the energy harvesting interface circuit and reduce the sampling power consumption of the tracking circuit.
[0004] To achieve the above-mentioned object, an embodiment of the present application provides an output power detection maximum power point tracking circuit based on time sampling, wherein the tracking circuit includes: a buck-boost converter and a maximum power point tracking control circuit;
[0005] The maximum power point tracking control circuit includes a time-voltage conversion circuit, a disturbance direction control circuit, a hill climbing algorithm control circuit, a peak current control circuit, a current zero-crossing detection circuit and a switch control logic circuit;
[0006] The buck-boost converter serves as a power path for transmitting current, and a switch control signal of the buck-boost converter is provided by the maximum power point tracking control circuit.
[0007] In some embodiments, the time-to-voltage conversion circuit includes: 5 PMOS transistors, namely PM1, PM2, PM3, PM4, and PM5; a constant current source; 6 switches, namely S1, S2, S3, S4, S5, and S6; and 2 capacitors, namely C1 and C2.
[0008] Among them, the source of PM1 is connected to the source of PM4; the gate of PM1, the gate of PM4, the drain of PM2, and the source of PM3 are connected to the same point;
[0009] The drain of PM1 is connected to the source of PM2, the drain of PM3 is connected to the first end of the first constant current source; the second end of the first constant current source is grounded;
[0010] The gate of PM3, the first end of the first constant current source, the gate of PM2, and the gate of PM5 are connected to the same point;
[0011] The drain of PM4 is connected to the source of PM5, and the drain of PM5 is connected to the first ends of S1 and S2 respectively;
[0012] The second end of S1 is connected to the first end of S3 and S5 respectively; the second end of S2 is connected to the first end of S4 and S6 respectively;
[0013] The second ends of S3 and S4 are grounded; the second end of S5 is connected to the first end of C1; the second end of S6 is connected to the second end of C2;
[0014] The second ends of C1 and C2 are grounded.
[0015] In some embodiments, the disturbance direction control circuit includes: a first comparator, a NOT gate, a multiplexer, a JK trigger, three D triggers, two pulse generating circuits, and two NAND gates.
[0016] In some embodiments, the peak current control circuit includes: three PMOS transistors, namely PM6, PM7, and PM8; a second constant current source; two resistors, namely R1 and R2; a second comparator; two switches, namely S7 and S8; a first inductor; an NMOS transistor, denoted as NM1;
[0017] Among them, the sources of PM6, PM7, and PM8 are connected to the same point;
[0018] The gates of PM6, PM7, and PM8, the drain of PM6, and the first end of the second constant current source are connected to the same point;
[0019] The drain of PM7 and the first end of R1 are connected to the negative input terminal of the second comparator;
[0020] The drain of PM8 and the first end of R2 are connected to the positive input terminal of the second comparator;
[0021] The second end of R2 is connected to the first ends of S7 and S8 respectively;
[0022] The second terminal of S8 and the drain of NM1 are connected to the first terminal of the first inductor;
[0023] The second end of the second constant current source, the second end of R1 , the second end of S7 , and the source of NM1 are grounded.
[0024] In some embodiments, the buck-boost converter includes: two PMOS transistors, PM9 and PM10; two NMOS transistors, NM2 and NM3; a second inductor;
[0025] The drain of PM9, the drain of NM2, and the first end of the second inductor are connected to the current zero-crossing detection circuit;
[0026] The source of PM10, the drain of NM3, and the second end of the second inductor are connected to the peak current control circuit;
[0027] The source of NM2 and the source of NM3 are grounded.
[0028] In some embodiments, the tracking circuit is connected to a rectifier circuit.
[0029] To achieve the above objectives, another aspect of an embodiment of the present application provides a method for tracking a maximum power point of output power detection based on time sampling. The tracking method is applied to the above-described maximum power point tracking circuit for output power detection based on time sampling. The tracking method includes the following steps:
[0030] Determine the disturbance direction control signal and proportional coefficient;
[0031] Sampling the first output power of the energy harvesting interface circuit at the current time step;
[0032] Comparing the first output power with a second output power sampled at a previous time step before the current time step;
[0033] If the first output power is greater than the second output power, the disturbance direction control signal and the proportional coefficient are added together as the current proportional coefficient, the time step is increased by 1, and then the step of sampling the first output power of the energy harvesting interface circuit at the current time step is returned to, until the output power of the current time step reaches the maximum power;
[0034] If the first output power is less than the second output power, the disturbance direction control signal is first inverted, and then the inverted disturbance direction control signal and the proportional coefficient are added as the current proportional coefficient, the time step is increased by 1, and then the step of the first output power of the sampling energy collection interface circuit at the current time step is returned until the output power of the current time step is the maximum power.
[0035] The embodiments of the present application include at least the following beneficial effects:
[0036] The tracking method of the present application can obtain the output power without high-power consumption current and voltage sampling. While maintaining the sampling accuracy, it reduces the power consumption of the sampling and improves the practicality of the maximum power point tracking circuit in low-power applications. The tracking circuit of the present application uses this tracking method to detect the output power, and makes the next change based on the output power size before and after the energy collection interface circuit changes, and finally realizes the maximum power point tracking. The tracking circuit can achieve end-to-end maximum power output. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0038] Figure 1 A schematic diagram of the structure of a maximum power point tracking circuit for output power detection based on time sampling provided in an embodiment of the present application;
[0039] Figure 2 A flow chart of a method for output power detection and maximum power point tracking based on time sampling provided in an embodiment of the present application;
[0040] Figure 3 An example flow chart of a method for output power detection and maximum power point tracking based on time sampling provided in an embodiment of the present application;
[0041] Figure 4 A schematic diagram of the structure of a time-to-voltage conversion circuit provided in an embodiment of the present application;
[0042] Figure 5 A schematic diagram of the structure of a disturbance direction control circuit provided in an embodiment of the present application;
[0043] Figure 6 A schematic diagram of the structure of a peak current control circuit provided in an embodiment of the present application;
[0044] Figure 7 A schematic diagram of the structure of a maximum power point tracking circuit connected to a load circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0045] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.
[0046] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0047] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.
[0049] Before describing the embodiments of the present application in detail, some of the related technologies involved in the embodiments of the present application are first described as follows:
[0050] Maximum power point tracking (MPPT) can be categorized as input power tracking or output power tracking, depending on the target being tracked. Input power tracking is widely used due to its simpler algorithm design and circuit implementation. However, maximizing input power does not guarantee maximizing output power, making end-to-end MPPT impossible.
[0051] Since power P = V * I, current and voltage sampling is required to obtain power information, which requires a large power consumption overhead, which conflicts with the application scenario of energy harvesting and limits the application of maximum power point tracking technology in low-power scenarios.
[0052] Traditional maximum power point tracking circuits are designed for only one type of interface circuit and cannot adapt to different interface circuit structures. The bundling of interface circuits and maximum power point tracking circuits reduces system design freedom and prevents modular design.
[0053] Reference Figure 1 , an embodiment of the present application provides a maximum power point tracking circuit for output power detection based on time sampling, the tracking circuit comprising: a buck-boost converter and a maximum power point tracking control circuit;
[0054] The maximum power point tracking control circuit includes a time-voltage conversion circuit, a disturbance direction control circuit, a hill climbing algorithm control circuit, a peak current control circuit, a current zero-crossing detection circuit and a switch control logic circuit;
[0055] The buck-boost converter serves as a power path for transmitting current, and a switch control signal of the buck-boost converter is provided by the maximum power point tracking control circuit.
[0056] Optionally, the time-to-voltage conversion circuit includes: 5 PMOS transistors, namely PM1, PM2, PM3, PM4, and PM5; a constant current source; 6 switches, namely S1, S2, S3, S4, S5, and S6; and 2 capacitors, namely C1 and C2;
[0057] Among them, the source of PM1 is connected to the source of PM4; the gate of PM1, the gate of PM4, the drain of PM2, and the source of PM3 are connected to the same point;
[0058] The drain of PM1 is connected to the source of PM2, the drain of PM3 is connected to the first end of the first constant current source; the second end of the first constant current source is grounded;
[0059] The gate of PM3, the first end of the first constant current source, the gate of PM2, and the gate of PM5 are connected to the same point;
[0060] The drain of PM4 is connected to the source of PM5, and the drain of PM5 is connected to the first ends of S1 and S2 respectively;
[0061] The second end of S1 is connected to the first end of S3 and S5 respectively; the second end of S2 is connected to the first end of S4 and S6 respectively;
[0062] The second ends of S3 and S4 are grounded; the second end of S5 is connected to the first end of C1; the second end of S6 is connected to the second end of C2;
[0063] The second ends of C1 and C2 are grounded.
[0064] Optionally, the disturbance direction control circuit includes: a first comparator, a NOT gate, a multiplexer (MUX), a JK flip-flop, three D flip-flops, two pulse generating circuits, and two NAND gates.
[0065] Optionally, the peak current control circuit includes: three PMOS transistors, namely PM6, PM7, and PM8; a second constant current source, two resistors, namely R1 and R2; a second comparator; two switches, namely S7 and S8; a first inductor; an NMOS transistor, denoted as NM1;
[0066] Among them, the sources of PM6, PM7, and PM8 are connected to the same point;
[0067] The gates of PM6, PM7, and PM8, the drain of PM6, and the first end of the second constant current source are connected to the same point;
[0068] The drain of PM7 and the first end of R1 are connected to the negative input terminal of the second comparator;
[0069] The drain of PM8 and the first end of R2 are connected to the positive input terminal of the second comparator;
[0070] The second end of R2 is connected to the first ends of S7 and S8 respectively;
[0071] The second terminal of S8 and the drain of NM1 are connected to the first terminal of the first inductor;
[0072] The second end of the second constant current source, the second end of R1 , the second end of S7 , and the source of NM1 are grounded.
[0073] Optionally, the buck-boost converter includes: two PMOS transistors, PM9 and PM10; two NMOS transistors, NM2 and NM3; a second inductor;
[0074] The drain of PM9, the drain of NM2, and the first end of the second inductor are connected to the current zero-crossing detection circuit;
[0075] The source of PM10, the drain of NM3, and the second end of the second inductor are connected to the peak current control circuit;
[0076] The source of NM2 and the source of NM3 are grounded.
[0077] Optionally, the tracking circuit is connected to a rectifier circuit.
[0078] Reference Figure 2The embodiment of the present application further proposes a method for tracking a maximum power point based on output power detection using time sampling. The tracking method is applied to the above-described maximum power point tracking circuit for output power detection using time sampling. The tracking method includes the following steps S200 to S240:
[0079] S200: Determine a disturbance direction control signal and a proportional coefficient;
[0080] S210: sampling the first output power of the energy harvesting interface circuit at the current time step;
[0081] S220: Compare the first output power with the second output power sampled in the previous time step of the current time step;
[0082] S230: If the first output power is greater than the second output power, add the disturbance direction control signal and the proportional coefficient to obtain the current proportional coefficient, increment the time step by 1, and then return to the step of sampling the first output power of the energy harvesting interface circuit at the current time step until the output power at the current time step reaches the maximum power;
[0083] S240: If the first output power is less than the second output power, the disturbance direction control signal is first inverted, and then the inverted disturbance direction control signal and the proportional coefficient are added as the current proportional coefficient, the time step is increased by 1, and then the step of the first output power of the sampling energy collection interface circuit at the current time step is returned until the output power of the current time step is the maximum power.
[0084] Next, the solution of the embodiment of the present application will be introduced and explained in detail with reference to specific application examples.
[0085] First, the parameters involved in this embodiment are described:
[0086] V REC : rectifier circuit output voltage;
[0087] V OUT : Buck-boost converter output voltage;
[0088] S H : Control the inductor magnetizing switch signal;
[0089] S L : Control the inductor demagnetization switch signal;
[0090] V C1 / V C2 : capacitor voltage;
[0091] U_D: disturbance direction control signal;
[0092] k: proportionality coefficient;
[0093] V REF : reference voltage;
[0094] IPEAK: inductor peak current signal;
[0095] I L : inductor current;
[0096] I B : bias current;
[0097] S F : Bias flip control signal.
[0098] This embodiment proposes a method for obtaining power information through time sampling. In this embodiment, the peak current IPEAK after each inductor magnetization is fixed and then the inductor demagnetization time is sampled to obtain power information.
[0099] This embodiment proposes a maximum power point tracking circuit based on output power detection. The aforementioned method for acquiring power information through time sampling is applied to output power detection. Changing the input impedance of a DC-DC converter (DC-DC converter) changes the output power accordingly. The direction of the next change is determined based on the change in output power before and after the change, ultimately stabilizing the circuit at the maximum power point.
[0100] Still refer to Figure 1 The maximum power point tracking circuit of this embodiment includes a buck-boost converter and a maximum power point tracking control circuit. The buck-boost converter transmits current as a power path, and its switching control signal is provided by the maximum power point tracking control circuit. The maximum power point tracking control circuit samples the switching signal S during inductor demagnetization. L , obtain the output power information. After processing, the output control signal S H ,S L Specifically, first the switch signal S L Converted into voltage signal V C , and then compare the two converted voltages V through the disturbance direction control circuit C1 ,V C2 , the next disturbance direction control signal U_D is obtained. After passing through the hill climbing algorithm control circuit and comparator, it is output to the switch control logic to achieve hysteresis control.
[0101] Figure 3 This is an example flow chart of the tracking method of the maximum power point tracking circuit. First, the disturbance direction control signal U_D is set to 1 and the proportional coefficient is set to k; then the current state P is sampled. OUT (i) and compare P OUT (i) With POUT (i-1) size relationship; if P OUT (i)>P OUT (i-1), then U_D remains unchanged, that is, the disturbance direction remains unchanged. Otherwise, U_D is reversed, that is, the disturbance direction changes. Repeating the above process, the maximum power point is finally cycled and the maximum power point tracking is achieved.
[0102] Figure 4 is the structural diagram of the time-voltage conversion circuit. Figure 5 It is a structural diagram of the disturbance direction control circuit. Figure 4 The circuit charges the capacitors C1 / C2 through a constant current source and converts the inductor demagnetization time into a voltage signal. The switching signal is Figure 5 The circuit in the right figure has the following inputs: IPEAK, the output of the peak current control circuit, and ZCD, the output of the current zero-crossing detection circuit.
[0103] When the IPEAK signal arrives, Q1 is inverted, triggering one of the subsequent D-type flip-flops, thereby enabling the switch signal in the time-to-voltage conversion circuit. When the ZCD signal arrives, the D-type flip-flop is reset, clearing all switch signals to zero. Taking signals S1, S3, and S5 as an example, when the D-type flip-flop is triggered, S3 and S5 are set to 1, and switches S3 and S5 close, clearing the voltage on capacitor C1 to zero. When the pulse generator circuit's pulse ends, S3 is set to 0, S1 is set to 1, and switches S1 and S5 close, allowing the constant current source to charge capacitor C1. When the ZCD signal arrives, all signals are cleared, the switches are opened, and the voltage on C1 remains unchanged. Capacitor C2 operates in the same way as C1, alternating between charging and discharging to sample the inductor's demagnetization time.
[0104] After sampling the inductor demagnetization time and converting it into voltages VC1 and VC2, a comparator compares the two voltages. The sampling order is determined by Q1, and the two-way selector outputs the relationship between the current sampled voltage and the previous sampled voltage. If the output is 0, the JK flip-flop output U_D remains unchanged; if the output is 1, the JK flip-flop output U_D is inverted.
[0105] Figure 6 It is a schematic diagram of the peak current control circuit. When DCDC starts working, the power tube M POWER Closed, the inductor current gradually increases, M POWER The drain voltage changes with the inductor current I L At this time, switch S8 is also closed, so the positive input voltage of the comparator is I B R2+V DS,POWER , when the positive input voltage is greater than the negative input voltage I BWhen R1 is on, the comparator outputs a high level, the inductor ends the magnetizing stage and enters the demagnetizing stage, which controls the inductor peak current.
[0106] In this embodiment, the power switch and the control circuit except the inductor and the capacitor are all integrated on a silicon chip using an integrated circuit process. Figure 7 The parallel synchronous switch rectifier circuit and the maximum power point tracking circuit of this embodiment are included. The parallel synchronous switch rectifier circuit converts the input AC energy into DC energy, and the maximum power point tracking circuit stabilizes the output voltage V of the rectifier circuit. REC , so that the system can maintain maximum power output under different inputs and different loads.
[0107] The maximum power point tracking circuit first samples the inductor demagnetization time S L The demagnetization time is converted into voltage through the time-voltage conversion circuit, and then the disturbance direction control circuit compares the voltage before and after to determine the disturbance direction. The voltage division coefficient k is determined according to the output signal of the hill climbing algorithm control circuit. The rectifier circuit output V REC After voltage division, the output is kV REC After that, use a comparator with V REC Comparison, the comparator output is controlled by the control logic to obtain the switching signal S H , S L . Through hysteresis control, V REC Stable at V REF / k.
[0108] In addition to the solutions mentioned herein, the embodiments of the present application can also be transformed as follows:
[0109] 1. In addition to the buck-boost converter power structure, a buck converter structure can also be used.
[0110] 2. V REC The voltage can also be controlled using various control methods such as variable frequency control and constant on-time control. The core is to adjust the input impedance by changing the input impedance of the DCDC power stage.
[0111] 3. The front-stage interface circuit of the maximum power point tracking circuit proposed in this embodiment can also use other rectifier structures, such as a series synchronous switch rectifier circuit, a synchronous switch capacitor circuit, etc. It can also be used in DC energy sources such as thermoelectric and solar energy.
[0112] Beneficial effects:
[0113] 1. The time sampling method proposed in this embodiment can obtain power information without performing high-power consumption current and voltage sampling. While maintaining sampling accuracy, it reduces the power consumption of the sampling circuit and improves the practicality of the maximum power point tracking circuit in low-power applications.
[0114] 2. This embodiment proposes a maximum power point tracking circuit design based on output power detection. It uses the aforementioned time sampling method to detect output power and makes subsequent changes based on the output power before and after the DCDC change, ultimately achieving maximum power point tracking. This method can achieve end-to-end maximum power output.
[0115] 3. The maximum power point tracking circuit proposed in this embodiment is decoupled from the front-stage interface circuit and can operate under different inputs and different interface circuits, which is conducive to system modular design and has wide applicability.
[0116] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0117] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.
[0118] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0119] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0120] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.
Claims
1. Output power detection maximum power point tracking circuit based on time sampling, characterized in that: The tracking circuit includes: a buck-boost converter and a maximum power point tracking control circuit; The maximum power point tracking control circuit includes a time-voltage conversion circuit, a disturbance direction control circuit, a hill climbing algorithm control circuit, a peak current control circuit, a current zero-crossing detection circuit and a switch control logic circuit; The buck-boost converter serves as a power path for transmitting current, and a switch control signal of the buck-boost converter is provided by the maximum power point tracking control circuit.
2. The output power detection maximum power point tracking circuit based on time sampling according to claim 1, characterized in that: The time-voltage conversion circuit includes: 5 PMOS tubes, namely PM1, PM2, PM3, PM4, PM5; a constant current source; 6 switches, namely S1, S2, S3, S4, S5, S6; 2 capacitors, namely C1, C2; Among them, the source of PM1 is connected to the source of PM4; the gate of PM1, the gate of PM4, the drain of PM2, and the source of PM3 are connected to the same point; The drain of PM1 is connected to the source of PM2, the drain of PM3 is connected to the first end of the first constant current source; the second end of the first constant current source is grounded; The gate of PM3, the first end of the first constant current source, the gate of PM2, and the gate of PM5 are connected to the same point; The drain of PM4 is connected to the source of PM5, and the drain of PM5 is connected to the first ends of S1 and S2 respectively; The second end of S1 is connected to the first end of S3 and S5 respectively; the second end of S2 is connected to the first end of S4 and S6 respectively; The second ends of S3 and S4 are grounded; the second end of S5 is connected to the first end of C1; the second end of S6 is connected to the second end of C2; The second ends of C1 and C2 are grounded.
3. The output power detection maximum power point tracking circuit based on time sampling according to claim 2, characterized in that: The disturbance direction control circuit includes: a first comparator, a NOT gate, a multiplexer, a JK trigger, three D triggers, two pulse generating circuits, and two NAND gates.
4. The output power detection maximum power point tracking circuit based on time sampling according to claim 1, characterized in that: The peak current control circuit includes: three PMOS transistors, namely PM6, PM7, and PM8; a second constant current source, two resistors, namely R1 and R2; a second comparator; two switches, namely S7 and S8; a first inductor; an NMOS transistor, denoted as NM1; Among them, the sources of PM6, PM7, and PM8 are connected to the same point; The gates of PM6, PM7, and PM8, the drain of PM6, and the first end of the second constant current source are connected to the same point; The drain of PM7 and the first end of R1 are connected to the negative input terminal of the second comparator; The drain of PM8 and the first end of R2 are connected to the positive input terminal of the second comparator; The second end of R2 is connected to the first ends of S7 and S8 respectively; The second terminal of S8 and the drain of NM1 are connected to the first terminal of the first inductor; The second end of the second constant current source, the second end of R1 , the second end of S7 , and the source of NM1 are grounded.
5. The output power detection maximum power point tracking circuit based on time sampling according to claim 1, characterized in that: The buck-boost converter includes: two PMOS transistors, PM9 and PM10; two NMOS transistors, NM2 and NM3; a second inductor; The drain of PM9, the drain of NM2, and the first end of the second inductor are connected to the current zero-crossing detection circuit; The source of PM10, the drain of NM3, and the second end of the second inductor are connected to the peak current control circuit; The source of NM2 and the source of NM3 are grounded.
6. The output power detection maximum power point tracking circuit based on time sampling according to any one of claims 1 to 5, characterized in that: The tracking circuit is connected to the rectifier circuit.
7. The output power detection maximum power point tracking method based on time sampling is characterized in that: The tracking method is applied to the output power detection maximum power point tracking circuit based on time sampling according to claim 1, and the tracking method includes the following steps: Determine the disturbance direction control signal and proportional coefficient; Sampling the first output power of the energy harvesting interface circuit at the current time step; Comparing the first output power with a second output power sampled at a previous time step before the current time step; If the first output power is greater than the second output power, the disturbance direction control signal and the proportional coefficient are added together as the current proportional coefficient, the time step is increased by 1, and then the step of sampling the first output power of the energy harvesting interface circuit at the current time step is returned to, until the output power of the current time step reaches the maximum power; If the first output power is less than the second output power, the disturbance direction control signal is first inverted, and then the inverted disturbance direction control signal and the proportional coefficient are added as the current proportional coefficient, the time step is increased by 1, and then the step of the first output power of the sampling energy collection interface circuit at the current time step is returned until the output power of the current time step is the maximum power.