System timing management method, system, and electronic device

Abstract

The application relates to the technical field of servers, in particular to a system timing management method, a system and electronic equipment. The system timing management method comprises the following steps: after a switch module obtains a power supply signal, a controller performs initial reset on the switch and a graphic processor; after the switch and the graphic processor complete the initial reset, a central processor triggers a global reset; during the global reset, the controller controls to stop supplying power to the switch and the graphic processor until the central processor completes the global reset control to restore the power supply, and then the central processor performs link training by using the switch and the graphic processor. The method solves the technical problem that the graphic processor initialization and the switch reset fail, and then the link training is prone to failure, and achieves the technical effects of improving the link training reliability and operation stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a system timing management method, a system and an electronic device. BACKGROUND

[0002] In the evolution of AI (Artificial Intelligence) server architecture to high-performance heterogeneous computing, the application of multi-level switching topology and normalized firmware improves production efficiency and wiring flexibility, but chips from different manufacturers differ in initialization process and reset function, resulting in compatibility problems of inconsistent underlying reset timing. In related technologies, the mainboard module reset is usually synchronized with the indication of the switch magic module to perform graphics processor initialization and switch reset, which is prone to lose graphics processors and switches, causing graphics processor initialization and switch reset to fail, and further leading to link training failure. SUMMARY

[0003] The present application provides a system timing management method, system and electronic device to at least solve the technical problem of graphics processor initialization and switch reset failure, which further easily leads to link training failure.

[0004] The present application provides a system timing management method, which includes: in response to the switch module obtaining a power supply signal, the controller controls the switch and the graphics processor to perform initial reset; in response to completing the initial reset, the central processor triggers global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processor completes the global reset control to restore power supply; in response to the graphics processor and the switch restoring power supply, the central processor uses the switch and the graphics processor to perform link training.

[0005] The present application provides a system timing management system, which includes: a mainboard module including a central processor; a switch module including a controller and a plurality of switches and graphics processors connected to the controller; the controller is used to control the switch and the graphics processor to perform initial reset in response to the switch module obtaining a power supply signal; in response to the central processor triggering global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processor completes the global reset control to restore power supply; the central processor is used to trigger global reset in response to completing the initial reset; in response to the graphics processor and the switch restoring power supply, the central processor performs link training on a preset device connected to the switch.

[0006] The present application also provides an electronic device, which includes: a memory for storing a computer program; a processor for executing the computer program to implement the steps of any of the above system timing management methods.

[0007] The application avoids the risk of secondary link training caused by traditional normalization firmware by designing the sequence to make the controller control the switch and the graphics processor to perform initial reset as soon as the switch module is powered on, so that the reset state is prior to the central processor; then the central processor triggers global reset, and the controller synchronously cuts off the power supply of the switch and the graphics processor to match the reset period of the central processor, so as to ensure the synchronization of the device state in the clock environment when the clock environment is interrupted; after the global reset is completed, the power supply is restored and the device state is reconstructed, the central processor performs unified link training on all preset devices, so that the success rate of the first link training is maximized, thereby solving the card loss and bandwidth reduction problems caused by firmware normalization, supporting single-version firmware deployment across multiple switches, reducing production and maintenance costs, and improving hardware layout flexibility.

[0008] Therefore, the method can solve the technical problems of graphics processor initialization and switch reset failure, which can easily lead to link training failure, and achieve the technical effects of improving link training reliability and operation stability. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1 A hardware architecture diagram carrying multiple graphics processors is provided for the embodiments of the present application.

[0011] Figure 2 A reset timing diagram carrying multiple graphics processors is provided for the embodiments of the present application.

[0012] Figure 3 An application environment diagram of a system timing management method is provided for the embodiments of the present application.

[0013] Figure 4 A flowchart of a system timing management method is provided for the embodiments of the present application.

[0014] Figure 5 A timing diagram of a system timing management method is provided for the embodiments of the present application.

[0015] Figure 6 A structural diagram of a system timing management system is provided for the embodiments of the present application.

[0016] Figure 7 A structural diagram of a system timing management device is provided for the embodiments of the present application.

[0017] Figure 8 A structural schematic diagram of an electronic device is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0019] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0020] It should be noted that the terms “S101”, “S102” and the like are only used for the purpose of describing the steps, and do not particularly refer to the order or sequence, nor limit the present application. They are only used to facilitate the description of the method of the present application, and cannot be understood as indicating the sequence of the steps. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of the person of ordinary skill in the art. When the combination of the technical solutions contradicts each other or cannot be realized, it should be considered that the combination of the technical solutions does not exist, nor is it within the protection scope of the present application.

[0021] In recent years, artificial intelligence servers have become an important hardware foundation for the development of artificial intelligence technology. AI servers have powerful computing and storage capabilities, enabling them to handle massive amounts of data and complex algorithms. They have been widely used in natural language processing, image recognition, autonomous driving, and other fields, leading to a growing demand for AI servers. In addition, AI servers use efficient cooling designs and energy-saving technologies to ensure stable operation under high loads and reduce energy consumption. They also support various AI frameworks and algorithm libraries, making it easy for users to quickly build AI applications. Due to the need to handle massive amounts of data and complex algorithms, AI servers have high requirements for computing power, storage capacity, and energy efficiency. With advancements in chip technology, heterogeneous computing, and other technologies, the performance of AI servers continues to improve. Specifically, AI servers include chips and other upstream components, server brand manufacturers and other midstream components, and internet companies, cloud service providers, and other downstream components. AI server applications have expanded from centralized AI services to edge AI services, and the development of terminal devices driven by AI server infrastructure. GPU manufacturers have introduced high-performance AI chips and system integration solutions. Therefore, customers based on different application scenarios and cost-effectiveness considerations may choose different CPU manufacturers' CPUs with other manufacturers' Switch chips, and then configure other platforms' GPUs under the Switch chips. However, due to differences in PCIE controller initialization efficiency, initialization process, and global reset function among different CPU manufacturers, Switch chip manufacturers, and GPU manufacturers, compatibility issues such as card loss, switch loss, and bus bandwidth reduction may occur when chips or components from different manufacturers are combined.

[0022] The present application provides a hardware architecture for a central processing unit platform combined with a graphics processing unit module. As shown in Figure 1 Figure 1 A hardware architecture for a central processing unit platform combined with a graphics processing unit module is provided.

[0023] ​Specifically, the hardware architecture includes a main board module (MB: Main Board, which carries the core computing resources and the central hardware of system control), which includes one or more central processing units. The CPU can include CPU0 and CPU1, which are interconnected by an XGMI (eXascale Global Memory Interconnect, extreme speed global memory interconnect: CPU interconnection of high-speed data channels) high-speed bus to meet the data interaction needs between different CPUs. The main board module also includes a controller, such as a field programmable gate array (FPGA, Field Programmable Gate Array), a hardware-level timing controller.

[0024] The hardware architecture also includes a switch module (SW BOARD, Switch Board, switch board: an independent hardware module that expands PCIe channels), which can be used as a PCIe channel expansion. Through multiple switch chips, the limited PCIe channels of the CPU are expanded to dozens of channels to meet the parallel computing needs of multiple GPUs or NPUs (Neural Processing Unit, neural network processor: a hardware circuit optimized for neural network operations such as convolutional neural networks, which can replace GPUs and be mounted on the switch board, and is suitable for the same timing control logic). The switch module is connected to the main board module, and the switch module includes multiple switches (SW: switch), which can be PCIE switch (Peripheral Component Interconnect Express Switch: high-speed peripheral component interconnect switch), CXL Switch (Compute Express Link Switch: Compute Express Link Switch), FPGA soft-core switch matrix (Field-Programmable Gate Array: Field-Programmable Gate Array), DPU acceleration card (Data Processing Unit: Data Processing Unit), without specific limitations. Taking the PCIE switch as an example, Figure 1The diagram shows four switches: Switch A, Switch B, Switch C, and Switch D. The S0, S1, S5, S6, S7, and S8 controllers of the PCIe Switch chip represent different controllers. Each switch may include multiple controllers. PCIe Switch A and PCIe Switch D are connected to CPU0 and CPU1 respectively via their S2 and S7 controllers. PCIe Switch B is connected to CPU1 via its S5 and S6 controllers, and PCIe Switch C is connected to CPU0 via its S6 and S7 controllers. This uplink structure design allows for smoother routing of monitored PCIe devices in the PCB and actual cable layout.

[0025] When this hardware architecture, based on a CPU and a multi-GPU computing module, is running, the following timing sequence may occur when resetting the PCIe switch and the multi-GPUs: Figure 2 As shown, Figure 2 This is a reset timing diagram for an embodiment of the present application that includes a multi-graphics processor.

[0026] Specifically, the motherboard reset signal refers to the reset signal output by the motherboard to the PCIe devices. The switch reset signal refers to the reset signal output by the CPLD (Complex Programmable Logic Device, integrated on the Switch Board and working in conjunction with the FPGA) on the switch motherboard to the four switch chips, as well as the reset signals output to the PCIe devices and GPU in the slots. Therefore, in the current design, the reset signals output to the switch chips, the PCIe devices in the slots, and the GPU are referenced from the motherboard CPU's PCIe reset signal. Figure 2 The timing diagram shows that both are pulled high and released synchronously. In this case, after the CPU releases the PCIe reset signal, it sends a PCIe CPU detection signal to start searching for PCIe devices. Simultaneously, the switch chip releases its reset signal and sends a switch detection signal to the CPU to initiate a handshake between the CPU and the PCIe device. However, the firmware (written in erasable memory, running after power-on to initialize the chip and its peripherals) of these four PCIe switch chips is identical. Therefore, compatibility issues between different servers can arise during the AC Cycle, Warm Reset, and Cold Reset processes.

[0027] When different servers share a common firewall, there is a risk of bandwidth loss on the link between the CPU and the PCIe switch. This is because, in order to normalize, the switch will reset all ports within a certain period of time after the initial link training with the CPU. This reset will be recognized by the CPU as an abnormal link drop, and retraining the link will fail probabilistically.

[0028] The relevant technology involves independently programming each switch firmware, which significantly reduces production line efficiency and firmware maintenance costs. Furthermore, the CPU clock is interrupted during a reset, and if the GPU continues to run at this time, it can lead to timing non-compliance and consequently, GPU failure to be detected.

[0029] To address the technical problem of link training failure caused by reset conflicts and reset clock interruptions in switches, this application proposes a solution whereby, in response to the switch module receiving a power supply signal, the controller controls the switch and graphics processor to perform an initial reset; in response to the completion of the initial reset, the central processing unit (CPU) triggers a global reset; in response to the global reset, the controller stops supplying power to the switch and graphics processor until the CPU completes the global reset and restores power; and in response to the restoration of power to the graphics processor and switch, the CPU uses the switch and graphics processor to perform link training, thereby improving the reliability and stability of link training.

[0030] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The system timing management method provided in this application can be applied to, for example... Figure 3 , Figure 3 This diagram illustrates an application environment for a system timing management method provided in this embodiment. Terminal 12 communicates with server 14 via a network. Terminal 12 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 14 can be a standalone server or a server cluster consisting of multiple servers.

[0031] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Embodiments of this application provide a system timing management method, such as... Figure 4 , Figure 4 This is a flowchart illustrating a system timing management method provided in an embodiment of this application. The method is described in detail below in conjunction with the execution flow of the system timing management method.

[0033] S101: In response to the switch module obtaining the power supply signal, the controller controls the switch to perform an initial reset with the graphics processor.

[0034] In one embodiment, the controller refers to an FPGA1 chip on the switch board, which is used to execute hardware-level timing control logic, and the timing control logic can be written by a coding language such as Verilog.

[0035] When the switch module receives the power supply signal, the controller immediately responds to the signal, performs its own power-on initialization process, and then actively controls the switch to reset the graphics processor. The reset operation includes sending a reset signal to the switch to force it to reset, and controlling the graphics processor to initialize, to ensure that both enter a stable initial state before the central processor intervenes. This step ensures that the device reset is prioritized over the central processor operation of the mainboard module through strict timing control, laying the foundation for subsequent global link training. This step can avoid compatibility problems caused by firmware normalization to improve the first link training success rate. In this embodiment, the switch and the graphics processor are reset in advance in response to the power supply signal to ensure that the device completes the reset state synchronization before the central processor starts.

[0036] In one of the embodiments, the switch module includes a power module. The controller can also be used to monitor the power supply signal state of the power module and decide the reset release time. The power module refers to the P1V8 power supply unit of the switch board, which is used to reduce the external 12V input to 1.8V as the PCIe I / O standard voltage to provide working voltage for the switch chip and FPGA. The power supply signal refers to the P1V8 power supply signal, which is a symbol of voltage stability. The power supply signal is high level, indicating that the 1.8V voltage output reaches the PCIe I / O standard voltage standard, which is the enable condition for the power-on initialization of the FPGA.

[0037] Specifically, the power module responds to the input power supply, and the switch power signal P1V8 of the power module is switched from a first level to a second level to form a first timing rising edge and a power supply signal; the controller responds to the first timing rising edge and the power supply signal to perform power-on initialization. For example, Figure 5 , Figure 5 A timing diagram of a system timing management method provided by the embodiment of the present application.

[0038] Specifically, the external 12V power supply is input to the switch module power supply module, and the P1V8 power supply is ready. When the voltage is switched from the first level to the second level, a first timing rising edge is generated, indicating that the P1V8 power supply signal jumps, wherein the first level is a low level, indicating that the power supply is not ready, which may be that the voltage does not reach the threshold or the fluctuation is greater than the fluctuation threshold, and the second level is a high level, indicating that the power supply is stable output. The controller FPGA1 detects the first timing rising edge to start the initialization process, loads the configuration firmware from the internal memory, starts the reset control state machine, and prepares to receive GPU and switch state signals. In this embodiment, the P1V8 power supply is ready as the only starting source of the entire reset control chain, ensuring that subsequent actions are based on stable power supply.

[0039] In one embodiment, the controller sends an initialization signal to the graphics processor; the graphics processor acquires the initialization signal for initialization; the graphics processor generates a graphics processor enable signal in response to completing the initialization; the controller acquires the graphics processor enable signal, delays for a first preset time, and determines that the graphics processor completes the initialization; in response to the graphics processor completing the initialization, the controller sends a reset signal to the switch; and the switch acquires the reset signal for reset.

[0040] Specifically, the FPGA1 sends an initialization signal to the graphics processor to start the GPU core power supply, and the graphics processor acquires the initialization signal and initializes in response to detecting stable voltage.

[0041] Specifically, the controller controls the graphics processor initialization, and the graphics processor power signal GPU_BASE_PWRGD is switched from the first level to the second level to form the fourth timing rising edge and the graphics processor enable signal GPU_BASE_PWRGD.

[0042] Specifically, the clock environment is prepared based on the motherboard, so that the central processor clock signal is in a stable state. The controller controls the graphics processor initialization, and the graphics processor power signal is switched from the first level to the second level, wherein the first level is a low level, indicating that the GPU core power supply is closed, and the second level is a high level, indicating that the GPU core power supply is enabled. The jump edge of GPU_BASE_PWRGD from low level to high level, i.e. the fourth timing rising edge, ensures that the power supply is enabled strictly after the clock is stable.

[0043] The controller controls the switch clock signal to be switched from the first level to the second level to form the fifth timing rising edge.

[0044] Specifically, the clock generator is locked, the switch clock signal SW_CLK is switched from the first level to the second level to form a fifth timing rising edge, and the clock signal is activated to provide a stable clock reference for the switch, while the fourth timing rising edge is formed.

[0045] The controller forms a duration reaching a first preset duration in response to the fourth timing rising edge and / or the fifth timing rising edge, and controls the switch reset signal SWA / B / C / D / SLOT / PEX_RESE to be switched from the first level to the second level to form a sixth timing rising edge and the switch reset signal.

[0046] Specifically, the fourth timing rising edge lasts for a duration reaching a first preset duration, or the fifth timing rising edge lasts for a duration reaching a first preset duration. Since the fourth timing rising edge and the fifth timing rising edge are at the same time, the controller controls the switch reset signal to refer to the fourth timing rising edge or the fifth timing rising edge, so that when the GPU_BASE_PWRGD unexpectedly drops, the SW_CLK still triggers the release of the switch reset signal. The delay of the first preset duration can be set to 5 seconds through experiments. If the time is too short, individual GPUs may be lost, and if the time is too long, it will be consistent with the reset signal of the motherboard. The switch reset signal is switched from the first level to the second level, the first level is a low level indicating a forced reset state, i.e., the link training is suspended, and the second level is a high level indicating a reset release, i.e., the link training is started. The sixth timing rising edge indicates that SWA / B / C / D / SLOT / PEX_RESET jumps from a low level to a high level.

[0047] Further, in response to the completion of the initialization of the controller, the base preparation signal controller ready signal GPU_BASE_FPGA_RDY is switched from the first level to the second level to form a second timing rising edge.

[0048] Specifically, when the FPGA completes the firmware loading, the controller ready signal is actively pulled high to generate a jump edge from low to high. The rising edge is a trigger condition for subsequent operations and a timing reference for the cooperative work of multiple devices.

[0049] In response to the completion of the initialization of the controller, the GPU_BASE_PWRGD is output as 1, and the FPGA1 acquires the graphics processor enable signal after a first preset duration to determine that the graphics processor is initialized, sends a reset signal to the switch, and the switch acquires the reset signal to reset, so as to realize that the controller controls the switch reset signal to be switched from the first level to the second level.

[0050] The output controller is ready signal as an initialization completion flag, wherein the first level is low, indicating that the FPGA has not completed initialization, such as firmware loading or self-checking failure, and the second level is high, indicating that the FPGA initialization is ready, and the state machine can receive instructions.

[0051] In this embodiment, the FPGA 1 performs a first preset time delay after receiving the GPU_BASE_PWRGD enable signal, effectively avoiding the fluctuation period of the GPU core voltage and eliminating the interference of power supply noise on the switch link training; at the same time, the delay window covers the forced reset period of the switch normalization firmware, reduces the resource conflict rate of multi-switch parallel training under the premise of maintaining the advantages of single firmware production, and releases the SWA / B / C / D / SLOT / PEX_RESET reset signal by time sharing, providing initialization guarantee for heterogeneous computing architecture.

[0052] In one of the embodiments, the controller obtains a power supply signal for power-on initialization, and in response to completing the initialization, sends a first feedback signal to the motherboard module; the motherboard module obtains the first feedback signal and constructs a clock environment for coordinating the work of the switch; in response to completing the construction of the clock environment, the controller controls the initialization of the graphics processor and controls the reset of the plurality of switches.

[0053] Specifically, the controller controls the switching of its basic power supply signal, i.e., the motherboard switch ready signal MB_SW_PWRGD, from the first level to the second level in response to the first and second timing rising edges, to form a third timing rising edge and a first feedback signal. The motherboard module forms a periodic clock timing signal to form a clock environment in response to the third timing rising edge and the first feedback signal.

[0054] Specifically, after the P1V8 first timing takes effect and the GPU_BASE_FPGA_RDY second timing takes effect, and both conditions are met at the same time, the MB_SW_PWRGD is immediately pulled high to generate a third timing rising edge. The first level is low, indicating that the state is not ready, i.e., the power supply or FPGA is abnormal, and the second level is high, indicating that the switch board is ready as a whole, which is a prerequisite for allowing the motherboard to construct a clock environment. The double conditions ensure that MB_SW_PWRGD is switched only when the double rising edges take effect at the same time, avoiding the risk of single signal mis-triggering. The MB_SW_PWRGD serves as a first feedback signal for transmitting the switch board ready state to the motherboard module.

[0055] Specifically, after the mainboard FPGA0 captures the rising edge of the MB_SW_PWRGD feedback by the FPGA1, the clock generator is started to prepare the clock environment. The clock environment provides a global clock reference for the switch chip, ensures the phase alignment of multi-device data transmission, and is used to meet the timing requirements of the manufacturer that the central processor clock remains stable before the power-on completion of the GPU. In addition, the unified clock source forces multiple switches to respond to the link training instruction synchronously, thereby avoiding resource competition caused by asynchronous operation, and can also stabilize the clock compensation for the delay difference of the PCB wiring.

[0056] In this embodiment, after the P1V8 power-on completion and the GPU_BASE_FPGA_RDY is ready, the MB_SW_PWRGD can be directly generated, and the MB_SW_PWRGD is fed back to the mainboard module to inform the mainboard that the switch board power-on completion and preparation are ready. At this time, the mainboard can prepare the central processor CPU CLK clock and enter the S0 stage. In this embodiment, the signal of the power-on completion of the graphics processor, i.e., the graphics processor enable signal GPU_BASE_PWRGD, is not needed, because if the mainboard enters the S0 stage (Working State: normal working state) after waiting for the power-on completion of the GPU, after the mainboard receives the MB_SW_PWRGD=1, the mainboard enters the S0 stage, the mainboard exits the sleep state, controls the whole machine to exit the low-power state, and enters the full-function running mode. In this embodiment, the mainboard enters the S0 only needs the switch board basis to be ready, and does not need all devices to be powered on before entering the S0. If the mainboard enters the S0 needs all devices to be powered on before entering, it will cause the CPU CLK signal sent by the mainboard to be later than the power-on completion signal of the GPU, thereby possibly causing the problem of GPU enumeration failure.

[0057] In this embodiment, the key signal dependency is restructured and the delay mechanism is introduced. The MB_SW_PWRGD signal is independent and only responds to the switch board basis ready signal, i.e., P1V8 and FPGA_READY, which is independent of the GPU state, avoids the delay of the mainboard clock start caused by waiting for the power-on completion of the GPU GPU_BASE_PWR_GD, ensures that the CPU CLK is ahead of the GPU power supply, and avoids the signal regenerator loading failure caused by the clock lag of the graphics processor module, thereby meeting the timing specification. After a certain delay time of the fourth timing GPU_BASE_PWRGD or the fifth timing SW CLK jump, SWA / B / C / D / SLOT / PEX_RESET is released, thereby avoiding the competition of multiple devices and covering the forced reset action of the switch firmware.

[0058] S102: In response to completing the initial reset, the central processor triggers a global reset.

[0059] In the embodiment, when the controller completes the initial reset of the switch and the graphics processor, the central processor detects the completion event and initiates a global reset. The global reset is a system-level event that involves interrupting the clock environment of the entire system and broadcasting a reset instruction to all related devices to ensure that the motherboard, switch module and connected devices are synchronized to enter a full reset period. The global reset is uniformly coordinated by the CPU to avoid device state synchronization. The embodiment ensures the consistency of the device state, thereby eliminating compatibility problems under the normalized firmware and improving the reliability of the first link training.

[0060] In one embodiment, the motherboard module feeds back a global reset signal to the controller of the switch module in response to triggering the global reset. The clock environment is interrupted during the global reset.

[0061] Specifically, in response to completing the initial reset, the central processor triggers the global reset, at which time the clock environment has been interrupted, i.e., the central processor clock is interrupted. CPU0 or CPU1 sends a cold reset signal coldreset to FPGA0, which is then transmitted to FPGA1, which obtains the cold reset signal. FPGA1 then sends the cold reset signal to the PCIE Switch A / B / C / D chips and all GPU modules. In the embodiment, when the central processor triggers the global reset, the cold reset signal is transmitted to all PCIE switch chips and GPU modules through the cascade control chain of FPGA0 and FPGA1, and the GPU core power supply GPU_BASE_PWRGD and the switch power supply SWA / B / C / D / SLOT / PEX_RESET are simultaneously cut off, thereby eliminating the risk of charge residue and inconsistent state during clock interruption.

[0062] S103: In response to the global reset, the controller controls to stop supplying power to the switch and the graphics processor until the central processor completes the global reset control to restore power supply.

[0063] In the embodiment, when the central processor triggers the global reset, the controller immediately obtains the global reset signal. Subsequently, the controller actively controls to stop supplying power to the switch and the graphics processor, i.e., to cut off the power supply input. This power-off state is maintained until the central processor completes the global reset operation, at which time the controller responds to the recovery of the clock environment to control to restore the power supply, thereby ensuring that the switch and the graphics processor are re-powered under a unified timing.

[0064] Specifically, the FPGA 1 acquires a cold reset signal coldreset, and a mainboard reset signal MB_SW_PWRGD is switched from a first level to a second level to form a global cold reset signal. The MB_SW_PWRGD is switched from a first level low to a second level high, indicating that the global cold reset is activated. The FPGA 1 controls to stop supplying power to the graphics processor and the switch. After the rising edge of the MB_SW_PWRGD, the FPGA 1 controls the graphics processor enable signal GPU_BASE_PWRGD of the graphics processor to be switched from the second level to the first level to form a first timing falling edge, that is, to cut off the GPU core power supply. Since the cold reset will disconnect the clock, but the GPU will not be powered off, which will cause state residues. The graphics processor enable signal of the graphics processor is at the first level, which can clear the residual charge. At the same time, the FPGA 1 controls the switch reset signal SWA / B / C / D / SLOT / PEX_RESET to be switched from the second level to the first level to form a second timing falling edge. The CPLD can use an open drain output stage, and the resistance is pulled down to the ground, so as to force all switches to enter the reset state and clear the link training residual parameters.

[0065] S104: In response to the graphics processor and the switch recovering power supply, the central processor performs link training with the switch and the graphics processor.

[0066] In the embodiment, in response to the clock environment recovering, the controller controls to recover the power supply to the graphics processor in response to acquiring the global reset signal and after delaying for a second preset time length; the controller controls to recover the power supply to the switch in response to acquiring the global reset signal and after delaying for a third preset time length; wherein the second preset time length is greater than or equal to a clock interruption time length, and the clock interruption time length represents the interruption time length of the clock environment in the global reset; and the third preset time length is greater than the second preset time length.

[0067] Specifically, in response to acquiring the coldreset signal transmitted by the mainboard, the controller triggers the entire switch board to enter a cold reset state, and controls the graphics processor enable signal to be switched from the first level to the second level after delaying for a second preset time length from or after the occurrence time of the first timing falling edge of the GPU_BASE_PWRGD and / or the second timing falling edge of the SWA / B / C / D / SLOT / PEX_RESET. The controller controls the switch reset signal to be switched from the first level to the second level after delaying for a third preset time length.

[0068] The clock interruption duration represents an interruption duration of a clock environment of the switch reset signal when the switch reset signal globally resets, the second preset duration is greater than or equal to the clock interruption duration, and the power supply is restored only after the clock is stably reconstructed, thereby avoiding the risk of power supply preceding the clock. The second preset duration can be selected as 1 second. The third preset duration is greater than the second preset duration of the switch reset signal, and the third preset duration can be selected as 1 second greater than the second preset duration. The GPU can be prevented from entering the link training due to unstable voltage. In this embodiment, the second preset duration delay and the third preset duration delay of the voltage stabilization margin expansion are applied to the clock interruption duration, thereby avoiding the clock and power supply timing deadlock in the cold reset scenario.

[0069] Further, the mainboard module controls the mainboard reset signal to recover to the first level at a target time; wherein the target time represents an occurrence time of the first timing falling edge and / or the second timing falling edge, or the target time lags behind the occurrence time, or the mainboard module is reset to the first level after the global reset is started.

[0070] Specifically, when the falling edge of the GPU or the switch is detected, the mainboard is released from the reset state, and lags behind the occurrence time of the device falling edge, so as to reserve the capacitor discharge time and avoid the false triggering caused by signal rebound. This mechanism cooperates through the device signal priority response and lag, maintains the normalized firmware production advantage, and eliminates the timing conflict in the cold reset release process.

[0071] In this embodiment, after the clock environment is recovered, the central processing unit triggers the cold reset, the FGPA0 transmits the cold reset signal to the FGPA1, the FGPA1 performs the operation of pulling down and then pulling up the GPU_BASE_PWRGD on the GPU and performs the operation of powering off and then powering on the GPU again. When the CPU outputs interrupt the central processing unit clock during the cold reset, the graphics processor enable signal clock is also disconnected, so that the clock is disconnected but the GPU is not powered off, thereby causing the GPU to lose the card due to the stable state of the clock before the GPU is powered on. Therefore, when the CPU triggers the cold reset, the GPU is powered off and then powered on again, and the SWA / B / C / D / SLOT / PEX_RESET also performs the pull-down operation, so as to ensure that the GPU is released after being stable. The FPGA1 realizes the clock leading power supply specification hierarchical recovery of the device power supply through the dynamic delay algorithm, and the switch power supply is additionally delayed to avoid surge interference. This cooperative mechanism improves the GPU detection rate after the cold reset, and reduces the multi-switch training conflict rate.

[0072] The embodiment avoids the risk of secondary link training caused by the traditional normalization firmware by designing the sequence to make the controller control the switch and the graphic processor to perform initial reset, so that the reset state is prior to the central processor; then the central processor triggers global reset, and the controller synchronously cuts off the power supply of the switch and the graphic processor to match the reset period of the central processor, so as to ensure the synchronization of the device state in the clock environment; after the global reset is completed, the power supply is restored and the device state is reconstructed, the central processor performs unified link training on all preset devices, so that the success rate of the first link training is maximized, thereby solving the card loss and bandwidth reduction problems caused by firmware normalization, supporting single-version firmware deployment across multiple switches, reducing production and maintenance costs, and improving hardware layout flexibility.

[0073] In one embodiment, the plurality of switch reset signals are connected to the switch ports of the switch reset signal controller to form normalized ports; the switch reset signal controls the plurality of switch reset signals, which includes sending a reset signal to the normalized ports of the switch reset signal; the plurality of switch reset signals connected to the normalized ports of the switch reset signal controller obtain the switch reset signal through the normalized ports of the switch reset signal to reset.

[0074] In the embodiment, in order to improve the efficiency of the production line, the PCIE switch is normalized, that is, although the uplink and downlink ports of the plurality of PCIE switches are inconsistent, they are unified into one FW, that is, normalized ports, and the uplink and downlink ports are adaptively allocated through different physical pin configurations of the switch chip. When the switch is powered on, the physical pin level is read to fix the port role, so that a single firmware can adapt to any port configuration, and multiple version FWs are avoided.

[0075] In one embodiment, as shown in Figure 6 , a structure diagram of a system timing management system provided by the embodiment of the application is provided. Figure 6

[0076] The system timing management system includes a mainboard module 10 including a central processor 11, a switch module 20 including a controller 21 and a plurality of switches 22 connected to the switch reset signal controller, and a graphic processor 23.

[0077] The controller is configured to control the switch and the graphic processor to perform initial reset in response to the switch module obtaining a power supply signal; and to control the power supply to the switch and the graphic processor to be stopped in response to the central processor triggering global reset, until the central processor completes global reset control to restore the power supply.

[0078] ​The central processor is configured to trigger a global reset in response to completion of the initial reset, and perform link training on preset devices connected to the switch in response to the graphics processor and the switch resuming power supply.

[0079] In one embodiment, as shown in Figure 7 Figure 7 A structural schematic diagram of a system timing management apparatus provided by an embodiment of the present application is shown. The system timing management apparatus can include a first reset module 31, a second reset module 32, a power supply module 33, and a link training module 34.

[0080] The first reset module 31 is configured to control the switch and the graphics processor to perform an initial reset in response to the switch module obtaining a power supply signal.

[0081] The second reset module 32 is configured to trigger a global reset by the central processor in response to completion of the initial reset.

[0082] The power supply module 33 is configured to control the controller to stop supplying power to the switch and the graphics processor until the central processor completes the global reset control to resume power supply in response to the global reset.

[0083] The link training module 34 is configured to perform link training on preset devices connected to the switch by the central processor in response to the graphics processor and the switch resuming power supply.

[0084] The above-mentioned modules in the system timing management apparatus can be implemented by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of a processor in the electronic device in hardware form, or stored in a memory in the electronic device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above-mentioned modules.

[0085] Embodiments of the present application also provide an electronic device including a memory for storing a computer program, and a processor for executing the computer program to perform at least the following steps:

[0086] The controller controls the switch and the graphics processor to perform an initial reset in response to the switch module obtaining a power supply signal, triggers a global reset by the central processor in response to completion of the initial reset, controls the controller to stop supplying power to the switch and the graphics processor until the central processor completes the global reset control to resume power supply in response to the global reset, and performs link training on preset devices connected to the switch by the central processor in response to the graphics processor and the switch resuming power supply.

[0087] In one embodiment, the electronic device can be a server, and an internal structural diagram of the server can be as shown in Figure 8 ​As shown in the figure. The electronic device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium, an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the electronic device is used to store software management data. The network interface of the electronic device is used to communicate with the external terminal through the network connection.

[0088] Those skilled in the art can understand that, Figure 8 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0089] The embodiment of the present application also provides a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by a processor to at least perform the following steps:

[0090] In response to the switch module obtaining the power supply signal, the controller controls the switch to perform initial reset with the graphic processor; in response to completing the initial reset, the central processor triggers global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphic processor, until the central processor completes the global reset control to restore the power supply; in response to the graphic processor and the switch restoring the power supply, the central processor uses the graphic processor and the switch to perform link training.

[0091] In one exemplary embodiment, the above computer readable storage medium can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0092] The embodiment of the present application also provides a computer program product, the computer program product includes a computer program, and the computer program is executed by a processor to at least perform the following steps:

[0093] In response to the switch module obtaining the power supply signal, the controller controls the switch to perform an initial reset with the graphic processor; in response to completion of the initial reset, the central processor triggers a global reset; in response to the global reset, the controller controls to stop supplying power to the switch and the graphic processor until the central processor completes the global reset control to resume the power supply; in response to the graphic processor and the switch resuming the power supply, the central processor performs link training with the graphic processor and the switch.

[0094] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiment methods. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM) and memory bus dynamic RAM (RDRAM) and the like.

[0095] It can be further realized that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0096] The above describes in detail the system timing management method, system and electronic device provided by the present application. The principles and implementation modes of the present application are described by applying specific examples, and the above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A system timing management method, characterized in that, The system includes a motherboard module and a switch module connected to the motherboard module; the motherboard module includes a central processing unit; The switch module includes a controller and multiple switches and a graphics processor connected to the controller; The timing management method includes: In response to the switch module receiving a power supply signal, the controller controls the switch and the graphics processor to perform an initial reset. In response to the completion of the initial reset, the central processing unit triggers a global reset; In response to the global reset, the controller stops supplying power to the switch and the graphics processor until the central processing unit completes the global reset control and restores power. In response to the restoration of power to the graphics processor and the switch, the central processing unit uses the switch and the graphics processor to perform link training.

2. The system timing management method according to claim 1, characterized in that, The controller controls the switch and the graphics processor to perform an initial reset, including: The controller receives the power supply signal to perform power-on initialization, and responds to complete the initialization. Send a first feedback signal to the motherboard module; The motherboard module acquires the first feedback signal and constructs a clock environment for coordinating the operation of the switch. In response to the completion of the clock environment setup, the controller controls the initialization of the graphics processor and the reset of the multiple switches.

3. The system timing management method according to claim 1, characterized in that, The controller controls the initialization of the graphics processor and the reset of multiple switches, including: The controller sends an initialization signal to the graphics processor; The graphics processor acquires the initialization signal and performs initialization; In response to the graphics processor completing initialization, the controller sends a reset signal to the switch; The switch receives the reset signal and performs a reset.

4. The system timing management method according to claim 3, characterized in that, After the graphics processor receives the initialization signal and initializes itself, it further includes: The graphics processor generates a graphics processor enable signal in response to its initialization completion. The controller acquires the graphics processor enable signal and determines that the graphics processor has completed initialization after a first preset time delay.

5. The system timing management method according to claim 4, characterized in that, The switch module includes a power module; The timing management method includes: In response to receiving input power, the power module switches its power signal from a first level to a second level to form a first timing rising edge and the power supply signal. The controller performs power-on initialization in response to the first rising edge of the timing signal and the power supply signal. In response to the completion of the controller initialization, its basic preparation signal switches from the first level to the second level to form the second rising edge of the timing signal. The controller responds to the first rising edge and the second rising edge of the timing signal by switching its basic power supply signal from the first level to the second level to form the third rising edge of the timing signal and the first feedback signal. The motherboard module responds to the third rising edge and the first feedback signal to form a periodic clock timing signal to form a clock environment; In response to the clock timing signal, the controller controls the graphics processor to initialize, causing the graphics power signal of the graphics processor to switch from a first level to a second level to form a fourth rising edge and a graphics processor enable signal; the controller controls the switch clock signal to switch from a first level to a second level to form a fifth rising edge. In response to the fourth rising edge and / or the fifth rising edge reaching the first preset duration, the controller controls the switch reset signal to switch from the first level to the second level to form the sixth rising edge and the switch reset signal.

6. The system timing management method according to claim 1, characterized in that, The process until the central processing unit completes the global reset control and restores power includes: In response to triggering a global reset, the motherboard module sends a global reset signal to the controller of the switch module; wherein, the clock environment is interrupted during the global reset. In response to receiving the global reset signal, the controller controls the resumption of power supply to the graphics processor after a second preset time delay. In response to receiving the global reset signal, the controller restores power supply to the switch after a third preset time delay. Wherein, the second preset duration is greater than or equal to the clock interrupt duration, the clock interrupt duration representing the interrupt duration of the clock environment during the global reset; the third preset duration is greater than the second preset duration.

7. The system timing management method according to claim 6, characterized in that, After the controller controls the initialization of the graphics processor and the reset of the multiple switches, it also includes: In response to triggering a global reset, the motherboard module switches its motherboard reset signal from a first level to a second level to form the global reset signal. The controller acquires the global reset signal, controls the graphics processor's graphics processor enable signal to switch from a second level to a first level to form a first timing falling edge, and controls the switch reset signal to switch from a second level to a first level to form a second timing falling edge; The motherboard module controls its motherboard reset signal to return to the first level at a target time; wherein, the target time represents the occurrence time of the first timing falling edge and / or the second timing falling edge, or, the target time lags behind the occurrence time, or, the motherboard module resets to the first level after a global reset startup; The controller delays the occurrence time by the second preset duration and controls the graphics processor enable signal to switch from the first level to the second level. The controller delays the occurrence time by the third preset duration and controls the switch reset signal to switch from the first level to the second level.

8. The system timing management method according to claim 1, characterized in that, The ports of the multiple switches connected to the controller are normalized to form a normalized port; the control of resetting the multiple switches includes: The controller sends a reset signal to the normalization port; Multiple switches connected to the normalized port receive the reset signal through the normalized port and perform a reset.

9. A system timing management system, characterized in that, The system timing management system includes: Motherboard module, including the central processing unit; A switch module includes a controller and a power module, multiple switches, and a graphics processor connected to the controller. The controller is used to control the switch and the graphics processor to perform an initial reset in response to the switch module receiving a power supply signal; and to control the stop supply of power to the switch and the graphics processor in response to the central processing unit triggering a global reset, until the central processing unit completes the global reset control and restores power supply. The central processing unit is used to trigger a global reset in response to the completion of the initial reset; and to perform link training on preset devices connected to the switch in response to the restoration of power to the graphics processor and the switch.

10. An electronic device, characterized in that, The electronic device includes: Memory, used to store computer programs; A processor, configured to implement the steps of the system timing management method as described in any one of claims 1 to 8 when executing the computer program.

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