Pen

Abstract

The invention relates to a pen. Provided is a pen capable of transmitting a signal at a sufficient high voltage while suppressing circuit area and power consumption. A pen (1) is provided with: an electrode (P0); a power supply circuit (30) that supplies a first voltage (= VDD1); an LVI (10) connected to the power supply circuit (30) and outputting a downlink signal at a first voltage; an HVIC (20) including a level shifter (22) that outputs a downlink signal at a second voltage (= VDD2-VSS2) higher than the first voltage; an inter-IC Tx wiring (WTx0) that supplies a downlink signal of the first voltage from the LVICs (10) to the HVICs (20); an electrode wiring (WP0) that supplies a downlink signal of the second voltage from the HVI (20) to the electrode (P0); and a booster circuit (40) that is connected to the power supply circuit (30) and supplies the second voltage to the level shifter (22).

Description

[0001] This application is a divisional application of the Chinese invention patent application. The invention name of the original application is "Pen", the application number of the original application is 201910977438.8, and the application date of the original application is October 15, 2019. Technical Field

[0002] The present invention relates to a pen, and more particularly to a pen capable of transmitting a signal at a high voltage of several tens of volts. Background Art

[0003] Among pens (electronic pens) used with position detection devices such as tablet computers, some transmit signals at high voltages of tens of volts. For example, Patent Document 1 discloses a pen that transmits a high-voltage signal of 10 to 20 volts to a position detection device. Furthermore, Patent Document 2 discloses a pen that includes a voltage-boosting section using a charge pump and a voltage-boosting section using a transformer.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent No. 8,866,767

[0007] Patent Document 2: Japanese Patent No. 6148423 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] When integrating the internal circuitry of a pen that transmits signals at high voltage into a single integrated circuit (IC), all circuits must be manufactured using a high-voltage process. This increases the circuit size and area, and also increases power consumption. Therefore, there is a need for a pen that can transmit signals at a sufficiently high voltage while minimizing circuit area and power consumption.

[0010] Therefore, one of the objects of the present invention is to provide a pen that can transmit a signal at a sufficiently high voltage while suppressing the circuit area and power consumption.

[0011] Solutions to Problems

[0012] The pen of the present invention includes: an electrode; a power supply circuit that supplies a specified voltage; an LVIC that is connected to the power supply circuit and outputs a transmission signal at a first voltage; an HVIC that includes a level converter that outputs the transmission signal at a second voltage higher than the first voltage; an inter-IC wiring that supplies the transmission signal of the first voltage from the LVIC to the HVIC; an electrode wiring that supplies the transmission signal of the second voltage from the HVIC to the electrode; and a boost circuit that is connected to the power supply circuit and supplies the second voltage to the level converter.

[0013] Effects of the Invention

[0014] According to the present invention, since the transmission signal is generated using an LVIC that can be manufactured using a low-voltage process, the circuit area and power consumption of an HVIC that requires a high-voltage process can be reduced accordingly. Therefore, it is possible to transmit signals at a sufficiently high voltage while suppressing the circuit area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a diagram showing a pen 1 and a position detection device 2 according to a first embodiment of the present invention.

[0016] Figure 2 1 is a diagram showing the internal structure of the pen 1 .

[0017] Figure 3 1 is a diagram showing a configuration example of the high voltage switch 23 .

[0018] Figure 4 (a) is a diagram showing the internal structure of the switching circuits 26 and 27 , (b) is a diagram showing the internal structure of the buffer circuit 53 shown in (a), and (c) is a waveform diagram illustrating the operation of the switching circuits 26 and 27 .

[0019] Figure 5 (a) is a diagram showing the internal structure of the Rx unit 13, (b) is a diagram showing the relationship between the reception level of the uplink signal US and the amplitude level of the signal output from the variable gain amplifier 61, and (c) is a diagram showing the relationship between the reception level of the uplink signal US and the gain of the variable gain amplifier 61.

[0020] Figure 6 This is a diagram showing the internal structure of a pen 1 according to a second embodiment of the present invention.

[0021] Figure 7 It is a waveform diagram for explaining the operation of the logic circuit 12 in the reflective mode. DETAILED DESCRIPTION

[0022] Below, with reference to the attached Figure 1The embodiments of the present invention will be described in detail.

[0023] Figure 1 This figure shows a pen 1 and a position detection device 2 according to a first embodiment of the present invention. As shown in the figure, the pen 1 is a pen-shaped device that can be held in the user's hand. The position detection device 2 is a computer with an input surface, such as a tablet terminal, and is configured to include a sensor 3. Although not shown, the sensor 3 is composed of a plurality of linear electrodes arranged to cover the entire interior of the input surface.

[0024] Electrodes (the pen tip electrode P0 and the annular electrode P1 described later) are provided at the pen tip of the pen 1, and the pen 1 is configured to be able to transmit and receive signals bidirectionally with the position detection device 2 via the electrodes. Hereinafter, among the signals thus transmitted and received, the signal transmitted from the position detection device 2 toward the pen 1 is referred to as the uplink signal US (receiving signal), and the signal transmitted from the pen 1 toward the position detection device 2 is referred to as the downlink signal DS (transmitting signal). As will be described in detail later, the downlink signal DS is composed of a downlink signal DS1 transmitted from the pen tip electrode P0 described later and a downlink signal DS2 transmitted from the annular electrode P1 described later. Specifically, as Figure 1 As shown, transmission and reception of the uplink signal US and the downlink signal DS are achieved via electrostatic capacitance formed between the electrodes of the pen 1 and the linear electrodes constituting the sensor 3 .

[0025] Figure 2 This figure shows the internal structure of the pen 1 according to this embodiment. As shown, the pen 1 includes a pen tip electrode P0 (first electrode), a ring electrode P1 (second electrode), a low-voltage integrated circuit (LVIC) 10 that can be manufactured using a low-voltage process, a high-voltage integrated circuit (HVIC) 20 that requires a high-voltage process, a power supply circuit 30, and a boost circuit 40. The power supply circuit 30 generates three power supply potentials: VDD1, VDD2, and VDD3 (for example, 1.8V, 5.0V, and 2.3V, respectively). As detailed later, some of the components that make up the boost circuit 40 (specifically, the DC-DC circuit 21, described later) are located within the HVIC 20.

[0026] The pen tip electrode P0 is located at the pen tip and is connected to the HVIC 20 via electrode wiring WP0 (first electrode wiring). The annular electrode P1, a ring-shaped electrode surrounding the pen shaft, is connected to the HVIC 20 via electrode wiring WP1 (second electrode wiring). The electrode wiring WP0 is shared by both the downlink signal DS1 and the uplink signal US. Similarly, the electrode wiring WP1 is shared by both the downlink signal DS2 and the uplink signal US.

[0027] The LVIC 10 and the HVIC 20 are connected by at least four independently configured inter-IC wiring lines. These four inter-IC wiring lines include an inter-IC Rx wiring line WRx for supplying an uplink signal US from the HVIC 20 to the LVIC 10, an inter-IC Tx wiring line WTx0 (a first inter-IC Tx wiring line) for supplying a downlink signal DS1 from the LVIC 10 to the HVIC 20, an inter-IC Tx wiring line WTx1 (a second inter-IC Tx wiring line) for supplying a downlink signal DS2 from the LVIC 10 to the HVIC 20, and an inter-IC control wiring line WCtrl for supplying a control signal from the LVIC 10 to the HVIC 20. In the following description, the output terminal of the HVIC20 connected to the inter-IC Rx wiring WRx (the terminal to which the uplink signal US arriving at the pen tip electrode P0 or the annular electrode P1 is output) is referred to as the Rx terminal, the input terminal of the HVIC20 connected to the inter-IC Tx wiring WTx0 (the terminal to which the downlink signal DS1 is supplied) is referred to as the Tx0 terminal (first Tx terminal), and the input terminal of the HVIC20 connected to the inter-IC Tx wiring WTx1 (the terminal to which the downlink signal DS2 is supplied) is referred to as the Tx1 terminal (second Tx terminal).

[0028] The LVIC 10 includes an MCU 11, a logic circuit 12, an Rx unit 13, and a pen pressure detection unit 14. The MCU 11 is a microcontroller unit that controls the entire pen 1. The Rx unit 13 receives an uplink signal US via an inter-IC Rx wiring WRx, demodulates the uplink signal US, and outputs it to the logic circuit 12. The details of the Rx unit 13 will be discussed later. Figure 5 The writing pressure detection unit 14 is a functional unit that detects writing pressure based on the capacitance of a capacitive element (not shown) whose capacitance changes according to the pressure applied to the pen tip (writing pressure). The writing pressure detected by the writing pressure detection unit 14 is supplied to the logic circuit 12.

[0029] The logic circuit 12 receives the uplink signal US via the Rx unit 13 and generates downlink signals DS1 and DS2 corresponding to the contents of the uplink signal US. The downlink signals DS1 and DS2 generated by the logic circuit 12 are supplied to the HVIC 20 via the inter-IC Tx wirings WTx0 and WTx1, respectively.

[0030] Here, the uplink signal US and the downlink signals DS1 and DS2 are described in detail. First, the uplink signal US is a signal composed of symbols including a predetermined detection pattern and a command for controlling the pen 1 . Figure 1The position detection device 2 shown is configured to convert each symbol constituting the uplink signal US into an extension code (code chip string), modulate the obtained extension code using a prescribed modulation method (such as pulse width modulation), and then send it from each linear electrode constituting the sensor 3.

[0031] The downlink signal DS1 is a signal that includes a pulse train signal and a data signal in sequence. The pulse train signal is an unmodulated sinusoidal wave signal and is used to enable the position detection device 2 to detect the position of the pen 1. The data signal is a signal formed by modulating the sinusoidal wave signal using the data requested to be sent by the instruction in the uplink signal US. As an example of data sent by the data signal, the pen pressure detected by the pen pressure detection unit 14 can be cited. In addition, when the pen 1 has a side switch and a tail switch, the on / off information of these switches can be sent by the data signal. When an independent pen ID is assigned to the pen 1, the pen ID can be sent by the data signal.

[0032] Downlink signal DS2 is a sinusoidal signal having a frequency different from that of downlink signal DS1 and is used to enable position detection device 2 to detect the tilt of pen 1. Downlink signal DS2 may be an unmodulated signal as a whole, or may include a pulse train signal and a data signal like downlink signal DS1.

[0033] Let's return to the description of logic circuit 12. Although not shown, a driver circuit is provided at the output stage of logic circuit 12, and power supply potential VDD1 is supplied to this driver circuit from power supply circuit 30. Consequently, downlink signals DS1 and DS2 output from logic circuit 12 oscillate between power supply potential VDD1 and ground potential VSS. In other words, logic circuit 12 is configured to output downlink signals DS1 and DS2 at power supply potential VDD1 (first voltage).

[0034] The logic circuit 12 also generates and supplies various control signals for controlling the HVIC 20. These supplied control signals include a control signal DCEN (a first control signal) for controlling the DCDC circuit 21 (boost circuit 40), described later, and a control signal ULEN (a second control signal) for controlling the high-voltage switch 23, described later. Details will be provided when describing each circuit.

[0035] A DCDC circuit 21 , a level shifter 22 , and a high voltage switch 23 are provided inside the HVIC 20 .

[0036] The DCDC circuit 21, along with a transistor 41, an external coil 42, a resistor 43, a diode 44, and a capacitor 45, which are provided outside the LVIC 10 and HVIC 20, constitutes the boost circuit 40. It operates by receiving a supply of power supply potential VDD2 from the power supply circuit 30. The basic function of the DCDC circuit 21 is to control the on / off switching of the transistor 41 based on a feedback input of the power supply potential VSS2, the output of the boost circuit 40. This control controls the on / off switching of the current flowing through the external coil 42 so that the difference between the power supply potentials VDD2 and VSS2 is a predetermined value (e.g., 20V). This control enables the DCDC circuit 21 to generate the power supply potential VSS2 (the second voltage) in the boost circuit 40.

[0037] The DCDC circuit 21 controls the on / off switching of the transistor 41 by controlling the duty cycle of the rectangular wave signal BA supplied to the control electrode of the transistor 41. Furthermore, the DCDC circuit 21 is configured to be controllable by the control signal DCEN supplied from the logic circuit 12. When the control signal DCEN is active, the duty cycle of the rectangular wave signal BA is controlled. When the control signal DCEN is inactive, the rectangular wave signal BA is fixed inactive. Therefore, the boost circuit 40 generates the power supply potential VSS2 when the control signal DCEN is active, and does not generate the power supply potential VSS2 when the control signal DCEN is inactive.

[0038] The structure and operation of the boost circuit 40 are described in detail below. In the following description, the output terminal of the boost circuit 40, which outputs the power supply potential VSS2, is referred to as the first node n1. The ground terminal of the boost circuit 40, which receives the ground potential VSS, is referred to as the second node n2. The input terminal of the boost circuit 40, which receives the power supply potential VDD3 from the power supply circuit 30, is referred to as the third node n3.

[0039] Transistor 41, external coil 42, and resistor 43 are connected in series between third node n3 and second node n2. Transistor 41 is, for example, a PNP bipolar transistor, with its emitter connected to third node n3 and its collector connected to external coil 42. A rectangular wave signal BA is supplied to the base of transistor 41 from DC-DC circuit 21. A coil with an inductance of 1 μH or greater is used as external coil 42 to ensure that the absolute value of power supply potential VSS2 is sufficiently large. The cathode of diode 44 is connected to the collector of transistor 41, and the anode is connected to first node n1. Capacitor 45 is connected between first node n1 and second node n2.

[0040] With the above configuration, when the rectangular wave signal BA is activated and transistor 41 is turned on, a current flows from the first node n1 to the second node n2 via diode 44 and external coil 42. This causes the voltage at the first node n1 (=power supply potential VSS2) to drop, increasing the difference between the power supply potential VDD2 and the power supply potential VSS2. This allows the boost circuit 40 to boost the voltage.

[0041] The DCDC circuit 21 monitors the power supply potential VSS2, which serves as its feedback input. If the power supply potential VSS2 falls below a specified value (e.g., below -15V), the rectangular wave signal BA is inactive. Consequently, transistor 41 is turned off, halting the boosting operation of the boost circuit 40, and the difference between the power supply potentials VDD2 and VSS2 gradually decreases. The DCDC circuit 21 continues monitoring the power supply potential VSS2. If the power supply potential VSS2 rises above a specified value, the rectangular wave signal BA is restored to its active state. Consequently, transistor 41 is turned on, resuming the boosting operation of the boost circuit 40, and the difference between the power supply potentials VDD2 and VSS2 gradually increases. The boost circuit 40 generates the power supply potential VSS2 in this manner.

[0042] Returning to the description of the internal structure of the HVIC 20, the level shifter 22 amplifies the downlink signals DS1 and DS2 supplied from the LVIC 10 via the inter-IC Tx wirings WTx0 and WTx1, respectively, and supplies them at a voltage corresponding to the difference between the power supply potential VDD2 supplied by the power supply circuit 30 and the power supply potential VSS2 supplied by the boost circuit 40 (VDD2 - VSS2, a second voltage). The downlink signals DS1 and DS2 output from the level shifter 22 oscillate between the power supply potentials VDD2 and VSS2.

[0043] The high-voltage switch 23 switches the connection destination of the electrode wiring WP0 between the Rx terminal and the Tx0 terminal, and switches the connection destination of the electrode wiring WP1 between the Rx terminal and the Tx1 terminal. It is controlled by the control signal ULEN supplied from the LVIC 20. The high-voltage switch 23 must pass the high-voltage downlink signals DS1 and DS2 and is therefore designed to withstand at least the voltage of the downlink signals DS1 and DS2 output from the level shifter 22 (VDD2 - VSS2). For example, if the voltage of the downlink signals DS1 and DS2 is 10V, the high-voltage switch 23 must be designed to withstand at least 10V.

[0044] Figure 32 is a diagram showing a configuration example of a high voltage switch 23. As shown in the diagram, the high voltage switch 23 can be configured to include drive circuits 24 and 25 and switch circuits 26 and 27. These circuits will be described in detail below.

[0045] Drive circuits 24 and 25 function as buffers for downlink signals DS1 and DS2, respectively. Specifically, drive circuits 24 and 25 are preferably configured using CMOS circuits. Downlink signal DS1, output from level shifter 22, is supplied to electrode wiring WP0 via drive circuit 24. Similarly, downlink signal DS2, output from level shifter 22, is supplied to electrode wiring WP1 via drive circuit 24.

[0046] The switch circuit 26 is a circuit that switches the connection state between the Rx terminal and the electrode wiring WP0 based on the control signal ULEN supplied from the logic circuit 12. Furthermore, the switch circuit 27 is a circuit that switches the connection state between the Rx terminal and the electrode wiring WP1 based on the control signal ULEN supplied from the logic circuit 12. The logic circuit 12 generates the control signal ULEN so that the Rx terminal is connected to both the electrode wirings WP0 and WP1 when receiving the uplink signal US, and is disconnected from both the electrode wirings WP0 and WP1 when transmitting the downlink signals DS1 and DS2. The Rx terminal and the inter-IC Rx wiring WRx are provided in a manner common to the electrodes P0 and P1, and the switch circuits 26 and 27 operate so that the electrode wirings WP0 and WP1 merge at the junction 28 shown in the figure and are connected to the Rx terminal when receiving the uplink signal US.

[0047] The switch circuits 26 and 27 also function as Rx protection circuits to prevent the downlink signals DS1 and DS2 from flowing into the Rx terminal. This function is necessary because when the electrode wirings WP0 and WP1 are connected to the Rx terminal in order to receive the uplink signal US, the high voltage remaining in the electrode wirings WP0 and WP1 will flow into the Rx terminal and the Rx unit 13 may be damaged. Figure 4 Provide detailed explanation.

[0048] Figure 4 (a) is a diagram showing the internal structure of the switch circuits 26 and 27. Figure 4 (b) shows Figure 4 (a) shows the internal structure of the buffer circuit 53, Figure 4 (c) is a waveform diagram illustrating the operation of the switch circuits 26 and 27 .

[0049] First refer to Figure 4 (a) The switch circuits 26 and 27 are respectively configured to include CMOS switch circuits 50 and 51 , an NMOS 52 , and a buffer circuit 53 .

[0050] like Figure 4 As shown in (b), the buffer circuit 53 is configured to include a constant current circuit 55, a CMOS gate circuit 56, and a capacitor 57. A control signal ULEN is supplied to the input terminal of the CMOS gate circuit 56, and a control signal ULEN_dl is output from the output terminal of the CMOS gate circuit 56. The constant current circuit 55 is provided at the Figure 2 The power supply circuit 30 shown is provided between a power supply line to which the power supply potential VDD1 is supplied and a high-voltage power supply terminal of the CMOS gate circuit 56. A capacitor 57 is provided between the output terminal of the CMOS gate circuit 56 and the ground terminal.

[0051] The control signal ULEN is as follows Figure 4 (c) is a rectangular wave signal. When such a control signal ULEN is input to the input terminal of the CMOS gate circuit 56, a signal is output from the CMOS gate circuit 56. However, during the period until the charging of the capacitor 57 is completed, the signal is used for charging the capacitor 57. As a result, Figure 4 As shown in (c), the control signal ULEN_d1 output from the buffer circuit 53 has a rising edge delayed by a predetermined time Δ relative to the control signal ULEN. Hereinafter, the timing at which the control signal ULEN rises is referred to as time t1, the timing at which the control signal ULEN_d1 rises is referred to as time t2, and the timing at which both the control signals ULEN and ULEN_d1 fall is referred to as time t3.

[0052] Refer again Figure 4 (a) CMOS switch circuits 50 and 51 are sequentially inserted between electrode wiring WP0 or electrode wiring WP1 and the Rx terminal. Hereinafter, the wiring connecting the output of CMOS switch circuit 50 and the input of CMOS switch circuit 51 is referred to as "intermediate wiring MIDW." A control signal ULEN is supplied to the control terminal of CMOS switch circuit 50, and a control signal ULEN_dl is supplied to the control terminal of CMOS switch circuit 51. Furthermore, an NMOS transistor 52 is connected between intermediate wiring MIDW and a power supply wiring that receives ground potential VSS. An inverted signal of control signal ULEN_dl is supplied to the control terminal of NMOS 52.

[0053] Through the above structure, such as Figure 4As shown in (c), CMOS switch circuit 50 is turned on at time t1 and turned off at time t3. Therefore, from time t1 to time t3, CMOS switch circuit 51 is connected to electrode wiring WP0 or electrode wiring WP1. On the other hand, CMOS switch circuit 50 is turned on at time t2 and turned off at time t3. Therefore, the Rx terminal is connected to electrode wiring WP0 or electrode wiring WP1 between time t2 and time t3.

[0054] Here, if the NMOS 52 does not exist, then when the electrode wirings WP0 and WP1 have a high voltage, the intermediate wiring MIDW becomes a high voltage at time t1, and the Rx terminal becomes a high voltage at time t2. However, in this case, the Rx unit 13 connected to the other end of the Rx terminal will be destroyed. Therefore, the NMOS 52 is provided in the switch circuits 26 and 27. Figure 4 As shown in (c), NMOS 52 is configured to remain on until time t2, then temporarily turn off at time t2 before returning to on again at time t3. Therefore, even if a high voltage remains on electrode wirings WP0 and WP1 at time t1, the potential of intermediate wiring MIDW is forcibly neutralized to ground potential VSS between time t1 and time t2. This eliminates the possibility of a high voltage at the Rx terminal at time t2, and thus, the switch circuits 26 and 27 function as an Rx protection circuit, preventing the downlink signals DS1 and DS2 from flowing into the Rx terminal.

[0055] It should be noted that the initial state of the switch circuits 26 and 27 is preferably set to a state where the electrode wirings WP0 and WP1 are connected to the Rx terminal. This is to enable the uplink signal US to be received at any time. Figure 4 In the configuration (a), when the Rx terminal is disconnected from the electrode wirings WP0 and WP1, the disconnection occurs quickly in response to the inactivation of the control signal ULEN. Therefore, it is considered unlikely that a situation will occur where, when the level shifter 22 begins outputting the downlink signals DS1 and DS2, the switch circuits 26 and 27 are unable to disconnect the Rx terminal in time, causing a portion of the downlink signals DS1 and DS2 to be supplied to the Rx terminal.

[0056] Next, the details of the Rx unit 13 will be described. Figure 5 (a) is a diagram showing the internal structure of the Rx unit 13, Figure 5 (b) is a diagram showing the relationship between the reception level of the uplink signal US and the amplitude level of the signal output from the variable gain amplifier 61 . Figure 5 (c) is a graph showing the relationship between the reception level of the uplink signal US and the gain of the variable gain amplifier 61 .

[0057] First, refer to Figure 5 FIG. (a), the Rx section 13 is configured to include a bypass filter 60, a variable gain amplifier 61, a demodulation circuit 62, a matched filter 63, and a level detection circuit 64.

[0058] The bypass filter 60 is used to remove high-order harmonics that appear in the Rx wiring WRx, and is constituted by, for example, an RC circuit as shown in Figure 5 FIG. (a). The variable gain amplifier 61 is a receiving amplifier circuit (reception amplifier) configured to be able to control the gain, and functions to amplify the uplink signal US supplied via the Rx wiring WRx from the HVIC 20. The demodulation circuit 62 is a circuit that demodulates the uplink signal US output from the variable gain amplifier 61 using a predetermined modulation method (for example, pulse width modulation) to obtain the string of the above-described spreading codes. The matched filter 63 is a circuit that calculates the correlation between the spreading code obtained by the demodulation circuit 62 and each of a plurality of pre-stored spreading codes, and supplies the resulting symbol string to the logic circuit 12. The logic circuit 12 receives the uplink signal US (detection mode and instruction) transmitted from the position detection device 2 based on the symbol string thus supplied.

[0059] The level detection circuit 64 is a circuit that detects the amplitude level of the signal output from the variable gain amplifier 61 by referring to the demodulation result of the demodulation circuit 62. The level detection circuit 64 has two types of outputs, high (High) and low (Low), and is configured to activate the high output when the detected amplitude level exceeds the threshold Vth shown in Figure 5 FIG. (b), and activate the low output when the detected amplitude level is lower than the threshold Vtl (<Vth) shown in Figure 5 FIG. (b). The MCU 11 monitors the output of the level detection circuit 64, and generates a control signal GC for controlling the gain of the variable gain amplifier 61 based on the result.

[0060] If the details of the gain control based on the control signal GC are described, the MCU 11 is configured to control the gain of the variable gain amplifier 61 in multiple stages. Specifically, it is configured to lower the gain of the variable gain amplifier 61 by one stage according to the activation of the high output of the level detection circuit 64, and raise the gain of the variable gain amplifier 61 by one stage according to the activation of the low output of the level detection circuit 64. By this control, as shown in Figure 5 FIG. (c), the greater the reception level of the uplink signal US (the amplitude level at the time point when it reaches the electrodes P0 and P1), the smaller the gain of the variable gain amplifier 61 in stages. Therefore, as a result, as shown in Figure 5As shown in (b), the amplitude level of the signal output from the variable gain amplifier 61 can be set between the threshold value Vth and the threshold value Vtl under the condition that the reception level is within a predetermined range.

[0061] As described above, according to the pen 1 of this embodiment, since the LVIC 10, which can be manufactured using a low-voltage process, is used to generate the downlink signals DS1 and DS2, the circuit area and power consumption of the HVIC 20, which requires a high-voltage process, can be reduced accordingly. Therefore, the downlink signals DS1 and DS2 can be transmitted at a sufficiently high voltage while suppressing the circuit area and power consumption.

[0062] In addition, according to the pen 1 of this embodiment, since the external coil 42 of 1 μH or more, which cannot be configured in the integrated circuit, is configured outside the LVIC 10 and the HVIC 20, and the boost circuit 40 is constructed in a manner including the external coil 42, high voltage (for example, 20 V) downlink signals DS1 and DS2 can be obtained in the HVIC 20.

[0063] Furthermore, according to the pen 1 of this embodiment, since the switch circuits 26 and 27 function as an Rx protection circuit, it is possible to prevent the Rx unit 13 from being destroyed by the downlink signals DS1 and DS2 .

[0064] In addition, according to the pen 1 of this embodiment, since the receiving amplifier in the Rx part 13 is set as a variable gain amplifier 61, and the gain of the variable gain amplifier 61 is controlled based on the amplitude level of its output signal, the amplitude level of the signal output from the variable gain amplifier 61 can be made between the threshold Vth and the threshold Vtl.

[0065] Next, the pen 1 according to the second embodiment of the present invention will be described. The pen 1 of this embodiment differs from the pen 1 of the first embodiment in that it is configured to operate in a mode (hereinafter referred to as "reflection mode") in which the position detection device 2 detects the pen 1 as a finger by transmitting a second signal from the pen tip electrode P0 or the annular electrode P1. This second signal is a phase-inverted signal of the first signal received by the pen tip electrode P0 or the annular electrode P1. Here, the first signal is a signal intermittently transmitted by the position detection device 2; specifically, it is a finger detection signal that the position detection device 2 supplies to the sensor 3 for finger detection. In other respects, the pen 1 of this embodiment is identical to the pen 1 of the first embodiment. Therefore, the following description will focus on the differences from the first embodiment, with the same reference numerals being used for components identical to those of the first embodiment.

[0066] Figure 6 This is a diagram showing the internal structure of the pen 1 of this embodiment. Figure 2 It can be understood from the comparison that the pen 1 of this embodiment has the advantages of the Rx terminal and the variable gain amplifier 61 (see Figure 5 ) is different from the pen 1 of the first embodiment in that the output terminal is directly electrically connected to the logic circuit 12.

[0067] After starting operation in reflective mode, the logic circuit 12 controls the high-voltage switch 23 to connect the electrode wiring WP1 (and / or the electrode wiring WP0) to the Rx terminal. Consequently, when the ring electrode P1 (and / or the pen tip electrode P0) receives a first signal, the first signal is supplied to the Rx terminal.

[0068] The logic circuit 12, operating in reflection mode, monitors whether the first signal has reached the Rx terminal by referring to the output of the variable gain amplifier 61. Upon detecting that the first signal has reached the Rx terminal, the logic circuit 12 generates a second signal by inverting the phase of the first signal. At a timing corresponding to the reception of the first signal, the logic circuit 12 controls the high-voltage switch 23 to disconnect the electrode wiring WP1 from the Rx terminal (switching it to the Tx0 and Tx1 terminals), and supplies the second signal to one or both of the Tx0 and Tx1 terminals. This transmits the second signal from one or both of the pen tip electrode P0 and the annular electrode P1, making it appear to the position detection device 2 that the first signal has been absorbed. This allows the pen 1 to be detected as a finger.

[0069] Furthermore, the logic circuit 12 is configured to execute a muting logic for grounding the Rx terminal at a timing corresponding to the reception timing of the first signal. This allows the second signal to flow into the Rx terminal side and cause oscillation.

[0070] Figure 7 This is a waveform diagram illustrating the operation of the logic circuit 12 in the reflection mode. Figure 7Let's explain the reflection mode in more detail. First, the variable gain amplifier 61 operates with a predetermined reference potential as the center, setting its output high on the rising edge of the first signal and low on the falling edge of the first signal. The logic circuit 12 is configured to activate a mask signal, an internal signal, for a predetermined time T starting at a timing (time t5) corresponding to this timing (time t4) when the first signal arrives at the Rx terminal. Time t5 is preferably set to a time sufficient from time t4 for the logic circuit 12 to generate the second signal. While the mask signal is active, the logic circuit 12 maintains the potential of the Rx terminal at the aforementioned reference potential (quiet logic) and generates a second signal, a phase-inverted version of the first signal, to supply to one or both of the Tx0 and Tx1 terminals. This allows the position detection device 2 to detect the pen 1 as a finger while preventing oscillation caused by the second signal entering the Rx terminal.

[0071] As described above, the pen 1 of this embodiment has, in addition to the effects of the first embodiment, further effects of enabling the position detection device 2 to detect the pen 1 as a finger and preventing oscillation caused by the second signal entering the Rx terminal side.

[0072] While preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments at all, and the present invention can of course be implemented in various forms within the scope of the present invention.

[0073] Label Description

[0074] 1 transaction

[0075] 2 Position detection device

[0076] 3 Sensors

[0077] 10 LVIC

[0078] 11 MCU

[0079] 12 Logic Circuits

[0080] 13 Rx Department

[0081] 14 Pen pressure detection unit

[0082] 20 HVIC

[0083] 21 DC-DC circuit

[0084] 22 Level Shifter

[0085] 23 High Voltage Switch

[0086] 24, 25 drive circuit

[0087] 26, 27 Switching Circuit

[0088] 28 Confluence

[0089] 30 Power circuit

[0090] 40 Boost Circuit

[0091] 41 transistors

[0092] 42 External coil

[0093] 43 resistors

[0094] 44 diodes

[0095] 45, 57 capacitors

[0096] 50, 51 CMOS switch circuit

[0097] 52 NMOS

[0098] 53 Buffer Circuit

[0099] 55 Constant Current Circuit

[0100] 56 CMOS gate circuit

[0101] 60 Bypass filter

[0102] 61 Variable Gain Amplifier

[0103] 62 Demodulation Circuit

[0104] 63 Matched Filter

[0105] 64 Horizontal detection circuit

[0106] DCEN, ULEN, ULEN_dl, GC control signals

[0107] DS, DS1, DS2 downlink signals

[0108] MIDW intermediate wiring

[0109] P0 pen tip electrode

[0110] P1 ring electrode

[0111] US uplink signal

[0112] VDD1, VDD2, VDD3, VSS2 power supply potential

[0113] VSS ground potential

[0114] WCtrl IC control wiring

[0115] WP0, WP1 electrode wiring

[0116] WRx IC Rx wiring

[0117] Tx wiring between WTx0 and WTx1 ICs.

Claims

1. A pen comprising: electrode; a power supply circuit, the power supply circuit supplying a first voltage during operation; a first integrated circuit connected to the power circuit, wherein the first integrated circuit outputs a transmit signal at the first voltage during operation; a second integrated circuit comprising a level shifter, the level shifter being operable to output the transmit signal at a second voltage higher than the first voltage; an inter-IC wiring that, in operation, supplies the transmission signal having the first voltage from the first IC to the second IC; an electrode wiring configured to supply the transmission signal having the second voltage from the second integrated circuit to the electrode during operation; and a boost circuit connected to the power supply circuit, wherein the boost circuit supplies the second voltage to the level converter during operation; Wherein, the second integrated circuit further includes: an Rx terminal, wherein the Rx terminal outputs a reception signal received by the electrode during operation; a Tx terminal that receives the transmit signal in operation, and a switch that switches a destination to which the electrode wiring is connected between the Rx terminal and the Tx terminal during operation, wherein the switch includes an Rx protection circuit for preventing the transmission signal from flowing into the Rx terminal during operation, The Rx protection circuit sets the potential of the wiring connected to the Rx terminal to a predetermined potential during operation.

2. The pen according to claim 1, wherein The boost circuit includes an external coil provided outside the first integrated circuit and the second integrated circuit, and wherein the external coil is controlled in operation by a first control signal supplied from the first integrated circuit.

3. The pen according to claim 2, wherein The boost circuit includes the external coil and a circuit disposed in the second integrated circuit.

4. The pen according to claim 2, wherein The boost circuit generates the second voltage by performing on-off control of the current flowing in the external coil during operation.

5. The pen according to claim 1, wherein In the initial state of the switch, the electrode wiring is connected to the Rx terminal.

6. The pen according to claim 1, wherein The switch is subjected to the second voltage in operation.

7. The pen according to claim 6, wherein The switch is subjected to a voltage of 10V in operation.

8. The pen according to claim 1, in, The inter-IC wiring comprises: an inter-IC Rx wiring connected to the Rx terminal, and an inter-IC Tx wiring connected to the Tx terminal, wherein the inter-IC Rx wiring and the inter-IC Tx wiring are independently constructed, and The electrode wiring is shared by the transmitting signal and the receiving signal during operation.

9. The pen according to claim 8, in, The electrode comprises: a first electrode disposed at the tip of the pen, and having a ring-shaped second electrode, Wherein, the electrode wiring includes: a first electrode wiring connected to the first electrode, and a second electrode wiring connected to the second electrode, Wherein, the Tx terminal includes: a first Tx terminal corresponding to the first electrode, and a second Tx terminal corresponding to the second electrode, The inter-IC Tx wiring includes: a first inter-IC Tx wiring connected to the first Tx terminal, and a second inter-IC Tx wiring connected to the second Tx terminal, and The Rx terminal and the inter-IC Rx wiring are provided in common with the first electrode and the second electrode.

10. The pen according to claim 9, wherein The second integrated circuit includes a merging circuit that, in operation, connects the first electrode wiring and the second electrode wiring to the Rx terminal when receiving the reception signal.

11. The pen according to claim 1, wherein The switch is controlled in operation by a second control signal supplied from the first integrated circuit.

12. The pen according to claim 1, wherein The first integrated circuit includes a receive amplifier that is operable to amplify the receive signal.

13. The pen according to claim 9, wherein The pen operates in a reflection mode that causes a position detection device to detect the pen by transmitting a second signal from the first electrode or the second electrode, the second signal being obtained by inverting a phase of a first signal received by the first electrode or the second electrode.

14. The pen according to claim 13, wherein The second signal is transmitted at a timing based on a reception timing of the first signal.

15. The pen according to claim 14, wherein The potential of the Rx terminal is fixed to a predetermined reference potential at a timing based on the reception timing of the first signal.

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