Double reading check method and device for OTP

Abstract

The application relates to a dual-reading check method and device for OTP, which comprises the following steps: generating a power-on reset signal based on a power supply voltage, performing signal response, obtaining a periodic reading signal and a check control signal; performing OTP one-time reading on an OTP reading and writing system according to a first period of the periodic reading signal and the check control signal, storing the data into a static random access memory, and obtaining reference data; performing OTP two-time reading according to a second period of the periodic reading signal and in combination with the check control signal, comparing the data with the reference data, and obtaining a check result; and performing closed-loop detection on the check result, and obtaining an OTP inspection result. The application can effectively avoid the data misreading risk caused by power transient fluctuation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of OTP verification, and particularly relates to a double-reading verification method and device for OTP. BACKGROUND

[0002] As the core carrier of firmware storage and security key configuration, the reliability of data reading of one-time programmable memory (OTP) directly affects the overall stability of the system. The current mainstream single-reading scheme has systematic defects in the operation process: the traditional method directly reads the storage unit in the power-on reset stage, but the transient fluctuation in the power voltage climbing process easily causes data misjudgment; the redundancy design or verification algorithm used to improve fault tolerance often needs to significantly increase the hardware resource overhead, making it difficult for cost-sensitive devices to bear; at the same time, the asynchronous clock control mechanism is easy to trigger sampling deviation in the unstable stage of timing, causing systematic data distortion. More seriously, the existing scheme lacks effective on-chip real-time error correction mechanism, and when an error is detected, it needs to rely on external processing units to intervene, resulting in error recovery delay far exceeding the time requirement of safety critical scenarios. SUMMARY

[0003] The main purpose of the present application is to provide a double-reading verification method and device for OTP, which can effectively avoid the risk of data misreading caused by power transient fluctuation and significantly improve the integrity protection capability of stored information.

[0004] To achieve the above purpose, the present application provides a double-reading verification method for OTP, comprising:

[0005] Generating a power-on reset signal based on the power voltage, performing signal response, obtaining a periodic reading signal and a verification control signal;

[0006] Performing OTP one-time reading on the OTP read-write system according to the first period of the periodic reading signal and the verification control signal, and storing it into a static random access memory to obtain reference data;

[0007] Performing OTP two-time reading according to the second period of the periodic reading signal combined with the verification control signal, and comparing with the reference data to obtain a verification result;

[0008] Performing closed-loop detection on the verification result to obtain an OTP verification result.

[0009] Further, the power-on reset signal is generated based on the power voltage, and the signal response is performed to obtain a periodic reading signal and a verification control signal, comprising:

[0010] Performing voltage detection and threshold comparison on the power voltage to generate a power-on reset signal;

[0011] acquire a periodic read signal generated by the OTP read-write system based on the power-on reset signal;

[0012] activate OTP control based on the power-on reset signal to obtain an OTP read-write control enable signal;

[0013] convert the state machine of the OTP read-write control enable signal according to the periodic read signal to obtain a check control signal.

[0014] Further, according to the first period of the periodic read signal and the check control signal, OTP one-time reading of the OTP read-write system is performed and stored in a static random access memory to obtain reference data, including:

[0015] detect the high-level interval of the first period to obtain a one-time operation window signal;

[0016] read the level state of the check control signal according to the one-time operation window signal to obtain a first level state;

[0017] increment the address pointer of the OTP read-write system according to the first level state to obtain a first read address;

[0018] select and translate the storage array of the OTP read-write system according to the first read address to obtain a target storage unit row;

[0019] conduct the bit selection of the target storage unit row to read and output a first signal data;

[0020] input the first signal data to the static random access memory for latch processing to obtain the reference data.

[0021] Further, the input of the first signal data to the static random access memory for latch processing to obtain the reference data includes:

[0022] generate a bit selection control signal from the check control signal;

[0023] convert the first signal data to obtain an in-phase data signal and an anti-phase data signal;

[0024] drive the in-phase data signal through a first input path gate according to the bit selection control signal to obtain a first node voltage;

[0025] drive the anti-phase data signal through a second input path gate according to the bit selection control signal to obtain a second node voltage;

[0026] cross-coupling inverter latch the first node voltage and the second node voltage to obtain a stable node voltage pair;

[0027] output buffer the stable node voltage pair to obtain reference data.

[0028] Further, the second period of the periodic read signal is combined with the verification control signal for OTP secondary reading, and compared with the reference data to obtain a verification result, including:

[0029] identify a high level interval of the second period to obtain a secondary operation window signal;

[0030] According to the secondary operation window signal, the state switching of the verification control signal is detected to obtain a low level state signal;

[0031] According to the low level state signal, the output path multiplexing control of the static random access memory is activated to read back the path, and the reference data is extracted;

[0032] According to the secondary operation window signal, the address pointer increment trigger of the OTP read-write system is triggered to obtain a second read address;

[0033] According to the second read address, the target cell of the OTP read-write system is read to obtain a second signal data;

[0034] The second signal data and the reference data are compared in real time by XOR to obtain the verification result.

[0035] Further, the second signal data and the reference data are compared in real time by XOR to obtain the verification result, including:

[0036] Signal buffer the reference data to obtain an enhanced driving reference signal;

[0037] The second signal data is converted to obtain a full swing data signal;

[0038] The enhanced driving reference signal and the full swing data signal are operated by an XOR logic gate to obtain original verification data;

[0039] According to the periodic read signal, the edge trigger of the original verification data is verified to obtain the verification result.

[0040] Further, the verification result is detected in a closed loop to obtain an OTP verification result, including:

[0041] State analysis is performed on the verification result to obtain a verification state identification signal;

[0042] The decision branch identification is performed on the check state identification signal to obtain an operation mode;

[0043] When the operation mode is a data output mode:

[0044] The tri-state gate activation is performed on the OTP read-write system according to the check state identification signal to obtain a data output channel;

[0045] The driving capability of the second signal data is enhanced through the data output channel to obtain bus-compatible data;

[0046] The bus-compatible data is protocol-encapsulated and outputted to obtain the OTP check result.

[0047] Further, when the operation mode is an error handling trigger mode:

[0048] The reset control pulse is obtained by performing the reset pulse width modulation on the check state identification signal;

[0049] The reset addressing state is obtained by performing the address pointer asynchronous zero-clearing according to the reset control pulse;

[0050] The residual data clearing signal is obtained by performing the node charge discharge on the static random access memory according to the reset control pulse;

[0051] The reset signal generation state is obtained by performing the signal generation state reset on the reset control pulse according to the reset addressing state and the residual data clearing signal;

[0052] The restart check signal is obtained by performing the check control signal reinitialization according to the reset signal generation state;

[0053] The restart flow information is obtained by performing the double-read check flow restart according to the restart check signal.

[0054] The application further provides an OTP double-read check device applied to the OTP double-read check method.

[0055] The power-on reset and address generation module is used for generating a power-on reset signal based on a power supply voltage, performing signal response, and obtaining a periodic reading signal and a check control signal;

[0056] The reading module is used for performing OTP one-time reading on an OTP read-write system according to a first period of the periodic reading signal and the check control signal, storing the data into a static random access memory, and obtaining reference data;

[0057] A comparison module is configured to perform OTP secondary reading in combination with the check control signal according to a second period of the periodic reading signal, and compare with the reference data to obtain a check result.

[0058] A processing module is configured to perform closed-loop detection on the check result to obtain an OTP inspection result.

[0059] The OTP double-reading check method and device provided by the application have the following beneficial effects.

[0060] Through the timing coordination mechanism of the periodic reading signal and the check control signal, the reference data is established in the first reading stage and is instantaneously latched through the static random access memory, and the real-time comparison structure of the secondary reading is combined, which effectively avoids the data misreading risk caused by power transient fluctuation, and significantly improves the integrity protection capability of the key storage information. The input / output physical path of the static random access memory is innovatively reused, the reference data establishment and the check read-back function are integrated in the same hardware unit, the double-channel check function is realized, and the storage resource consumption of the traditional triple modular redundancy is eliminated, thereby providing a resource-efficient reliability solution for cost-sensitive devices. Relying on the synchronous timing control system constructed by the periodic reading signal, the data sampling point is accurately triggered in the secondary reading window, the establishment time conflict problem of the asynchronous clock is completely avoided, and the timing consistency of the storage unit and the check logic is guaranteed. When the check result is abnormal, the closed-loop detection mechanism automatically triggers the address pointer reset and the memory state refresh, and the self-contained error recovery is realized through the reset of the signal generation state, and the millisecond-level error correction response is completed at the hardware level. This double-period check architecture strengthens the timing robustness while compressing the physical resource occupation, can meet the strict requirements of the zero-tolerance scene in the functional safety standard, and provides a storage access paradigm with economy and safety. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 is a flowchart of an OTP double-reading check method provided by the application;

[0062] Figure 2 is a structure diagram of an OTP read-write control system in an OTP double-reading check device provided by the application;

[0063] Figure 3 is a static random access memory circuit diagram used in an embodiment of the application;

[0064] Figure 4 is a word selection and bit selection control schematic diagram of an embodiment of the application;

[0065] Figure 5 is a signal timing diagram of an embodiment of the application;

[0066] Figure 6 is a structure diagram of the OTP double reading verification device provided by the present application.

[0067] The implementation, functional features and advantages of the present application will be further described with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0069] The present application will be further described below in combination with the accompanying drawings and specific embodiments.

[0070] Referring to Figures 1-5 The present application provides an OTP double reading verification method, which comprises the following steps:

[0071] Step S1: generating a power-on reset signal based on a power supply voltage, performing signal response, obtaining a periodic reading signal and a verification control signal;

[0072] Step S1: performing OTP one-time reading on the OTP reading and writing system according to the first period of the periodic reading signal and the verification control signal, and storing it into a static random access memory to obtain reference data;

[0073] Step S3: performing OTP two-time reading according to the second period of the periodic reading signal in combination with the verification control signal, and comparing it with the reference data to obtain a verification result;

[0074] Step S4: performing closed loop detection on the verification result to obtain an OTP verification result.

[0075] Based on the above steps, the detailed step process is described as follows:

[0076] Step S1:

[0077] The power-on reset signal (POR_OK) is generated by the power voltage detection through the power-on reset signal module, triggering the OTP read-write control system to activate. The periodic read signal (READ) is generated by clock division and pulse width modulation, which matches the access timing requirements of the OTP storage unit array in fixed period and high level pulse width. The check control signal (READ_CHECK) generated synchronously realizes level switching control through the state machine conversion mechanism: output high level in the first cycle of the periodic read signal (READ), and switch to low level in the subsequent cycle. The signal coordination relationship is that the rising edge of the periodic read signal (READ) drives the address counter, and the level state of the check control signal (READ_CHECK) controls the switching of the access mode of the static random access memory (SRAM).

[0078] Step S2:

[0079] In the first high level cycle of the periodic read signal (READ), the POR_OK signal is high, activating the addressing operation of the OTP read-write system. When either the POR_OK signal or the CHECK_QN signal is low, the RSTN is low, and the OTP read-write control system is reset. The address pointer generation module outputs the current addressing position, and the target storage unit array is located through the word selection signal (WL) of the word selection decoding and the bit selection signal (BL) of the bit selection control. Turn on switch S1, the first data signal read is transmitted through the static random access memory (SRAM) input path, and the check control signal (READ_CHECK) controls the switch S1. The bit selection control signal (BL) turns on the NM1 / NM4 input tube, and the data is written into the cross-coupled inverter latch structure. The inverter pair composed of PM1 / NM2 and PM2 / NM3 stores the data stably in L1 / L2 node through positive feedback loop, forms the reference data and continuously maintains to the next operation stage.

[0080] Step S3:

[0081] In the second high level cycle of the periodic read signal (READ), the check control signal (READ_CHECK) is switched to low level state. Turn off switch S1, the bit selection control signal (BL) turns on the NM1 / NM4 input tube, and the multiplexing in-phase end (INP_SRAM) and the anti-phase end (INN_SRAM)

[0082] of the reference data are read back to the comparison unit. The OTP read-write system performs twice reading on the same storage unit address, and outputs the second data signal. The reference data and the second data signal are compared in real time through the XOR gate (XOR1) to generate the original check level. The synchronous sampling clock signal (CLK_CK) is triggered before the falling edge of the periodic read signal (READ) to synchronize the sampling pulse ( Figure 3 Figure 5 ​Timing), capture the check result and latch as a digital signal: output low level when data is consistent, output high level when data is inconsistent. The check result signal (CHECK) is converted to the check state identifier by decision logic.

[0083] Step S4:

[0084] The check state identifier signal drives the dual-mode decision branch: when the identifier signal represents consistent data, the tri-state gate circuit is activated to turn on the data output channel. After the second data signal is level-converted and driven, the frame header is packaged according to the AMBA bus protocol, the OTP check result is generated and output to the system bus. When the identifier signal represents inconsistent data, a 200ns low-level reset control signal (RSTN) is generated. This pulse synchronously triggers three operations: asynchronous clearing of the address counter, discharging of the static random access memory (SRAM) node charge (L2 forced to L2 ground by the NM5 tube), and resetting of the timing control state machine. The reset signal generation module restarts the periodic reading signal (READ) and check control signal (READ_CHECK) generation process after resetting, returning to step S2 to execute reference data reconstruction, forming a self-correcting closed loop. Figure 3

[0085] PM1 / NM2 and PM2 / NM3 (cross-coupled inverters):

[0086] PM1 / NM2 and PM2 / NM3 form the data latch unit of the static random access memory (SRAM):

[0087] PM1 and NM2: form the first inverter, the input end is connected to the L1 node, and the output end is connected to the L2 node.

[0088] PM2 and NM3: form the second inverter, the input end is connected to the L2 node, and the output end is connected to the L1 node.

[0089] A positive feedback loop (L1-inverter 2-L2-inverter 1-L1) is formed by cross-coupling to achieve stable data latching. When the input path is activated, the differential signal between the non-inverted end of the input signal (INP_SRAM) and the inverted end of the input signal (INN_SRAM) drives the node voltage, and data writing and holding are completed during the high level of the check control signal (READ_CHECK).

[0090] NM1 / NM4 (input path gate tube):

[0091] NM1 and NM4 are input path control switches of the static random access memory (SRAM):

[0092] NM1: connects the non-inverted end of the input signal (INP_SRAM) to the L1 node and is directly controlled by the bit selection signal (BL).​

[0093] NM4: connects the inverting terminal of the input signal (INN_SRAM) and the L2 node, and is directly controlled by the bit selection signal (BL).

[0094] When the check control signal (READ_CHECK) is high, the bit selection signal (BL) drives NM1 / NM4 to turn on, so that the differential input signal is written into the latch unit. This design realizes hardware level path isolation through MOS tube cascade, and guarantees that there is no crosstalk during writing.

[0095] NM5 (reset discharge tube):

[0096] NM5 is the charge discharge control tube of the static random access memory (SRAM), and its gate is connected to the reset signal (RST). When the reset control signal (RSTN) is generated due to check failure:

[0097] RSTN low level is converted into a high level signal (RST) through the inverter INV1.

[0098] RST high level drives NM5 to turn on.

[0099] The L2 node is forced to ground, the L1 node voltage is pulled up, and the output buffer INV2 outputs low level. This realizes millisecond-level fast discharge of storage charge and eliminates the interference of residual data on the restart process.

[0100] L1 node is the first node (Node L1):

[0101] Connection position:

[0102] The input end of inverter 1 (PM1 / NM2), the output end of inverter 2 (PM2 / NM3), and the input end of the output buffer (INV2) are directly determined by the voltage state of the output value (OUT_SRAM).

[0103] L2 node is the second node (Node L2):

[0104] Connection position:

[0105] The output end of inverter 1 (PM1 / NM2), the input end of inverter 2 (PM2 / NM3), and the drain end of the reset tube (NM5) are always complementary to the first node (L1) in voltage state.

[0106] The application provides a double reading check method of OTP. Through the time sequence cooperation mechanism of periodic reading signal and check control signal, the reference data is established in the first reading stage and is instantaneously locked through static random access memory, and the real-time comparison structure of secondary reading is combined, so that the data misreading risk caused by power transient fluctuation is effectively avoided, and the integrity guarantee capability of key storage information is significantly improved. The input / output physical path of the static random access memory is innovatively reused, the reference data establishment and the check read-back function are integrated in the same hardware unit, the double channel check function is realized, and the storage resource consumption of the traditional three-mode redundancy is eliminated, so that a resource efficient reliability solution is provided for cost sensitive equipment. Relying on the synchronous time sequence control system constructed by the periodic reading signal, the data sampling point is accurately triggered in the secondary reading window, the establishment time conflict problem of asynchronous clock is completely avoided, and the time sequence consistency of the storage unit array and the check logic is guaranteed. When the check result is abnormal, the closed loop detection mechanism automatically triggers the address pointer reset and the memory state refresh, the self-contained error recovery is realized through the reset of the signal generation state, and the millisecond level error correction response is completed at the hardware level. The double cycle check architecture strengthens the time sequence robustness while compressing the physical resource occupation, can meet the strict requirements of zero fault tolerance scene in the functional safety standard, and provides a storage access paradigm with economy and safety.

[0107] Referring to Figures 2-5 In one embodiment, a power-on reset signal is generated based on a power supply voltage, and a signal response is performed to obtain a periodic reading signal and a check control signal, including:

[0108] The power supply voltage is monitored in real time by a voltage detection circuit, which includes a voltage division sampling network and a hysteresis comparator. The sampling network captures the power transient value and outputs a proportional voltage to the positive input terminal of the comparator, and a threshold voltage source provides a threshold voltage connected to the inverting input terminal. When the power supply voltage continuously rises and exceeds the preset threshold, the output level of the hysteresis comparator flips, generating a high-level power-on reset signal (POR_OK). The signal jump point strictly corresponds to the stable state of the power supply, eliminating the ringing interference in the voltage climbing process. The power-on reset signal serves as a system startup flag and directly drives the subsequent control module to activate.

[0109] The power-on reset signal (POR_OK) is connected to the enable port of the OTP read-write control system, triggering the internal state machine to switch from sleep mode to working mode. The state machine outputs an OTP read-write control enable signal, whose high-level state unlocks the clock gating circuit and the address generation unit. The control enable signal serves as a hardware level switch, which forcibly freezes all read-write operations when it is at low level, and releases the work permission of the frequency divider and the pulse width modulation module when it is at high level. This design ensures that the OTP access operation is started only after the power supply is completely stable, avoiding the risk of mistriggering at the voltage critical point.

[0110] The OTP read-write control enable signal activates the frequency divider chain to divide the system master clock by an integer. A square wave signal with a fixed 50% duty cycle is generated. The period of the square wave is fixed at 100 ns, and the high level lasts for 50 ns, forming a periodic read signal (READ). The rising edge of the signal precisely triggers the address counter to increment, and the high level window ensures stable data transmission, strictly matching Figure 5 the timing specifications shown.

[0111] The periodic read signal (READ) drives the finite state machine transition.

[0112] The state machine output directly controls the pass mode of the static random access memory (SRAM): when the high level is activated, the input pass gate transistor (NM1 / NM4 transistor) is activated, the output pass multiplexer is enabled Figure 3 (OUT_SRAM port) is enabled through the output buffer (INV2), avoiding the influence of output signal flipping on the internal L1 and L2 nodes. During the storage phase, data flows from the non-inverted terminal (INN_SRAM) and the inverted terminal (INP_SRAM) into the L1 and L2 nodes. In the verification phase, the data latched by the L1 and L2 nodes are written to the non-inverted terminal (INN_SRAM) and the inverted terminal (INP_SRAM), respectively. This transition mechanism realizes seamless switching between the storage and verification phases.

[0113] The embodiment generates a power-on reset signal through voltage detection and threshold comparison, which can accurately identify the stable state of the power supply and eliminate the ringing interference in the power supply climbing stage, thereby ensuring the reliability of the system startup timing. Based on the power-on reset signal, the OTP control module is activated to generate a read-write control enable signal, ensuring that the OTP access operation is only performed after the power supply is stable, thereby avoiding the risk of false triggering under critical voltage. The state machine is driven by the periodic read signal to automatically output a dual-mode verification control signal, realizing seamless switching between the storage phase and the verification phase, thereby providing accurate timing control basis for the static random access memory pass mode switching.

[0114] Referring to Figures 2-5 In one embodiment, according to the first period of the periodic read signal and the verification control signal, the OTP read-write system is subjected to OTP one-time reading and stored in the static random access memory (SRAM) to obtain reference data, including:

[0115] The first read cycle of the periodic read signal (READ) is precisely identified by the high level turning on the OTP read circuit. The detection process utilizes the hysteresis voltage characteristic to effectively eliminate the risk of false triggering caused by signal edge jitter. The generated one-time operation window signal strictly limits the valid period of the first read operation, ensuring that the operation window fully matches the electrical characteristics and timing requirements of the memory cell. The high level state of the one-time operation window signal serves as the enable reference for subsequent operations, providing time boundary constraints for the entire read process.

[0116] During the high level duration of the one-time operation window signal, the control switch S1 is controlled by the check control signal (READ_CHECK). The output stable first level state: high level represents the first read mode activation, and low level indicates an abnormal state. This state signal directly drives the enable control of the address addressing module, establishing the operation mode identification for memory array access. The level reading process is strictly synchronized with the window signal, and the sub-stable state risk is eliminated by establishing a time margin design.

[0117] The high level output of the first level state enables the trigger function of the address pointer generation module. The address counter responds to the trigger signal on the rising edge of the periodic read signal (READ) to perform step increment operation. The counter uses normal binary coding or Gray code coding scheme, and outputs the first read address in binary format. The address bit width fully matches the physical structure of the memory array, supporting full range addressing from 0 to 2 N-1 The generated first read address is transmitted to the word selection decoding unit through a low delay bus.

[0118] The first read address is input to the word selection decoding logic unit. The decoding process preferentially analyzes the high bit address bit (MSB) to generate the word selection signal (WL) corresponding to the target memory cell row. The activated word selection signal drives the access tube of a specific row in the memory array to turn on, connecting the storage charge to the bit line. The decoding delay is strictly controlled within 3ns, ensuring that the row selection operation is completed in the early stage of the high level window of the periodic read signal (READ).

[0119] The bit selection decoder generates a bit selection signal (BL) according to the low bit (LSB) of the first read address. The bit selection signal turns on the column selection tube of the target memory cell, allowing the bit line charge to be output to the sense amplifier. The sense amplifier uses a differential structure to convert the micro-current signal into a 1.8V full-swing voltage. The output signal is shaped by the driver circuit to eliminate the ringing overshoot, forming a stable first signal data. The bit selection read operation covers all column groups of the memory array, supporting M-bit parallel data output.

[0120] The first signal data is transmitted to a static random access memory (SRAM) through a differential line pair (INP_SRAM / INN_SRAM). A check control signal (READ_CHECK) controls a switch S1, and a bit selection control signal (BL) turns on NM1 / NM4 input tubes. After the data is loaded to L1 node / L2 node, the cross-coupled inverters latch the charge through a positive feedback loop: the PM1 / NM2 inverter maintains the L1 node level, and the PM2 / NM3 inverter maintains the L2 node complementary level. The latching process is completed before the high level of the periodic read signal (READ) ends, and the node voltage is kept in a stable state through an output buffer, forming the reference data which lasts until the check phase.

[0121] The embodiment ensures that the address pointer increment operation is only performed in the valid period by reading the level state of the check control signal through the operation window signal, thereby eliminating the risk of addressing deviation caused by asynchronous timing. Through the cooperative operation of the address pointer increment and the storage array word selection decoding, the precise row-column positioning of the target storage unit is realized, thereby overcoming the data distortion problem caused by the charge crosstalk of adjacent units. Through the bit selection on-off reading mechanism, high-quality signal data is output, and in combination with the differential latching structure of the static random access memory, the reference data with zero attenuation is formed, so that the stable and reliable comparison reference is obtained in the secondary check phase.

[0122] Referring to Figures 2-5 In one embodiment, as shown in the figure, the first signal data is input to a static random access memory (SRAM) for latching processing to obtain reference data, including:

[0123] The check control signal (READ_CHECK) is input to a switch control logic circuit, and the control signal path is subjected to signal conditioning and driving enhancement processing. The circuit adopts a three-stage architecture to realize reliable conversion: a primary level conversion module adapts the voltage amplitude of the input signal to the driving requirement of the MOS tube, and through a hysteresis comparison mechanism, it ensures that the output is stable when the power supply fluctuates; a middle-stage filter unit suppresses high-frequency noise interference, and an RC low-pass network is used to attenuate power coupling ripple; a final-stage push-pull amplifier improves the current driving capacity to meet the demand of multiple parallel loads. When the check control signal (READ_CHECK) presents a high level state, a high level bit selection control signal (BL) is output after a reasonable delay, and the rising time is optimized to match the response characteristics of the storage unit; when the check control signal (READ_CHECK) turns to a low level, a preset low level static level is output. The signal generation process introduces tolerance compensation design, and the voltage threshold is set with a reasonable margin to ensure functional correctness under process angle variation. The bit selection control signal is connected to the gate tube array of the static random access memory (SRAM) through a matching impedance transmission line, and the transmission path layout avoids crosstalk risk.

[0124] The first signal data is input into a full-differential conversion module for processing. The module is based on a folded common-source common-gate operational amplifier structure. The non-inverting input end receives a single-ended input signal through a precision resistor network, and the inverting input end is connected to a high-stability bandgap reference voltage source. The conversion mechanism dynamically calibrates the output operating point through an active common-mode feedback loop, eliminating the direct current offset caused by process deviation. The in-phase data signal maintains the phase and amplitude characteristics of the original signal, and the anti-phase data signal generates an accurate complementary voltage waveform, with the swing range of both strictly constrained within the device operating zone. The differential signal output stage adopts a symmetric driving structure, and the transmission path implements an equal-length wiring design to ensure that the transmission delays of the two signals are matched. The common-mode rejection performance is strengthened through circuit topology, effectively suppressing power supply noise and substrate coupling interference.

[0125] The high level state of the bit selection control signal (BL) drives the NMOS gate tube of the first input path to turn on. The in-phase data signal is transmitted through a source follower architecture, which includes a gate-driven amplifier and an active load current mirror to achieve high-precision voltage transmission. During the gate tube conduction period, the signal is loaded to the L1 node of the static random access memory (SRAM) through a low-impedance path. The node parasitic capacitance is neutralized through the pre-charge circuit, and the voltage establishment process adopts a slope control technology to optimize the transient response. The final value of the first node voltage is stabilized in the target interval through a negative feedback mechanism, and the deviation range meets the input sensitivity requirements of the cross-coupled inverter. The temperature adaptability of the driving circuit is achieved through adaptive adjustment of the bias current, covering the full temperature range defined in the device specification.

[0126] The high level of the bit selection control signal (BL) synchronously activates the gate driving circuit of the second input path. The anti-phase data signal is loaded to the L2 node of the static random access memory (SRAM) through a mirror-symmetric transmission architecture. During the gate tube conduction period, the charge compensation technology is adopted to accurately offset the switching transient effect by injecting an equal amount of reverse charge. The signal transmission path adopts a common-source common-gate cascade structure to maintain the voltage gain stable near unity gain, with the phase shift controlled within a reasonable range. The L2 node voltage and the L1 node always maintain a complementary relationship, with the differential voltage swing covering the complete operating interval of the memory cell. The dynamic substrate biasing technology adjusts the back gate potential in real time, significantly suppressing the sub-threshold leakage current. The voltage establishment process introduces a slope control mechanism to optimize the signal edge characteristics and eliminate the risk of high-frequency oscillation. The accuracy of the second node voltage is maintained through closed-loop calibration, meeting the input tolerance requirements of the cross-coupled inverter.

[0127] Step 5: Cross-coupled inverter latching of the first node voltage and the second node voltage to obtain a stable node voltage pair.

[0128] The first node and the second node access a cross-coupled inverter latch structure. Inverter 1 (PM1 / NM2) and inverter 2 (PM2 / NM3) form a positive feedback loop: the first node drives the input end of inverter 1 and is connected to the output end of inverter 2 at the same time; the second node drives the input end of inverter 2 and is connected to the output end of inverter 1 at the same time. The positive feedback coefficient is optimized and designed to ensure that the first node voltage and the second node voltage are quickly locked within a reasonable time. The latch process strengthens the noise tolerance through the negative resistance effect, and the power supply fluctuation suppression capability is significantly improved. The static power consumption is minimized in the data retention state, and the charge retention time meets the demand of the complete verification period. The anti-soft error capability is optimized through the circuit topology, and has inherent immunity to particle bombardment and other interference. Finally, the stable node voltage pair is output.

[0129] The stable node voltage pair drives a three-stage cascade output buffer to reconstruct the signal. The first stage source follower provides a high input impedance interface to block the interference of the subsequent stage load; the second stage differential amplifier realizes accurate voltage gain to compensate for the influence of process deviation; and the third stage AB class output stage enhances the current driving capability to support the bus capacitance load. The frequency response of the buffer is optimized in phase margin to eliminate ringing and overshoot. The reference data is reconstructed to a rail-to-rail digital level, and the logic threshold is designed with hysteresis to strengthen the noise immunity. The output stage static current is automatically reduced to microampere level in the retention state, and the power efficiency is significantly optimized. The driving capability is adapted to the standard bus load characteristics, and the signal integrity meets the requirements of high-speed interface specifications. The reference data is continuously output until the second verification phase is completed.

[0130] The embodiment realizes reliable switching of the static random access memory pass mode through a precise generation mechanism of the switch control signal, thereby time-multiplexing the input and output functions in a single hardware unit, and significantly reducing the chip area overhead. Strictly complementary in-phase and anti-phase signals are generated through differential conversion technology to effectively suppress common-mode noise interference, thereby ensuring the signal integrity of the reference data establishment process. Through the synergistic effect of gate drive and cross-coupled inverters, the node voltage is locked at a stable double working point, thereby forming a reference data retention capability against power supply fluctuations and temperature drift. Through impedance conversion and driving enhancement of the output buffer, a bus-compatible reference data signal is generated, thereby providing a high-reliability comparison reference for the second verification.

[0131] Referring to Figures 2-5 In one embodiment, according to the second period of the periodic read signal, combined with the verification control signal, the OTP second read is performed, and compared with the reference data to obtain the verification result, including:

[0132] The second high level period of the periodic read signal (READ) is accurately identified by the timing detection circuit. The detection mechanism uses a window comparator structure to capture the complete 50ns high level interval of the READ signal from the rising edge to the falling edge. The identification process uses the hysteresis characteristics of the Schmitt trigger to effectively eliminate the risk of false triggering caused by signal edge jitter. The generated secondary operation window signal is limited to the execution period of the second read operation, ensuring that the operation window accurately matches the electrical characteristics of the storage unit. The high level state of the secondary operation window signal serves as the enable reference for subsequent operations, providing clear time boundary constraints for the secondary read process and ensuring the timing reliability of data capture.

[0133] During the high level duration of the secondary operation window signal, the level state is determined by the state detection circuit to identify the check result signal (CHECK). The detection circuit uses a bistable latch structure to trigger state sampling at the rising edge of the window signal.

[0134] Directly read the physical level state of the check control signal (READ_CHECK):

[0135] When READ_CHECK is stable at low level, it is determined to be in the verification mode active state.

[0136] When the first read cycle appears at high level, the switch (S1) is closed, and the data is written to the static random access memory (SRAM).

[0137] The state switching detection process establishes a time margin design to eliminate the risk of metastability. The low level state signal serves as the trigger reference for path multiplexing control, providing mode identification for the activation of the static random access memory output path.

[0138] When the verification mode is activated, the output enable signal (OE) is generated by driving the path multiplexing control logic. This signal activates the output path multiplexing switch of the static random access memory: turns on the transmission path of the output buffer (INV2) to the data bus, while closing the input path gate tube. The multiplexing control circuit uses complementary switch design to eliminate the charge injection effect during path switching. After the read-back path is activated, the reference data stored in the cross-coupled inverter is output to the data bus through the output port (OUT_SRAM port) of the static random access memory. The data extraction process introduces a timing synchronization mechanism to ensure stable transmission of the reference data within the secondary read window, providing reliable input for real-time comparison.

[0139] In the high level duration of the secondary operation window signal, the address pointer generation module executes a trigger operation in response to the rising edge of the READ signal. The address counter adopts a Gray code encoding mechanism and performs a step increment operation at the trigger edge. The counter outputs a second read address in binary format, and the address bit width is accurately matched with the physical structure of the storage array. The address generation process is strictly constrained by the window signal, ensuring that the addressing operation is only performed within the valid period. At this time, the check control signal (READ CHECK) maintains a low level state, indicating that the system is in the secondary read mode, and the address pointer points to the same storage cell position as the first read. The address transmission path adopts a low latency bus design.

[0140] The second read address is input to the storage array access interface. The word select decoder analyzes the high bit of the address and activates the word select signal (WL) of the target cell row; the bit select decoder analyzes the low bit and generates the bit select signal (BL) to turn on the target column. The bit select control signal (BL) turns on the NM1 / NM4 input tube, which multiplexes the in-phase end (INP_SRAM) and the anti-phase end (INN_SRAM), so that the reference data is read back to the comparison cell.

[0141] The storage cell charge is converted to a voltage signal by a sensitive amplifier and shaped into a full-swing digital level by a drive circuit. The read process is completed synchronously within the READ high level window, and the data setup time margin is greater than the timing specification requirement. The second signal data is output, and the check control signal (READ CHECK) remains in a low level state, ensuring that the static random access memory is in the output path multiplexing mode, avoiding accidental writing to the current read data.

[0142] The second signal data and the read-back reference data are input to the XOR logic unit in parallel. This unit adopts a current-mode logic architecture and performs real-time comparison within the READ high level window: when the data bits are exactly the same, a low level is output, and when there is a difference, a high level is output. The comparison process introduces a timing alignment circuit to eliminate transmission path delay deviation. The check result signal (CHECK) is latched as a stable output by the synchronous sampling clock (CLK_CK) before the READ falling edge. At this time, the low level state of the check control signal (READ CHECK) maintains the output path activation, ensuring continuous supply of reference data. The check result immediately drives the subsequent decision-making process to form a complete closed-loop verification chain.

[0143] The embodiment cooperates the mechanisms of high-level interval identification and state switching detection, accurately defines the reliable time window of the secondary reading operation, and verifies the low-level state of the check control signal, thereby guaranteeing the timing stability and mode correctness of the check process. The multiplexing control of the static random access memory output path is driven by the low-level state of the check control signal, the reference data is seamlessly read and extracted, thereby multiplexing the same storage unit to complete the data storage and check output functions, and the hardware resource overhead is significantly reduced. Through the synchronization operation of the address pointer increment trigger and the target unit reading, it is ensured that the secondary reading address is strictly consistent with the first addressing position, thereby avoiding the risk of data comparison distortion caused by bit offset. Through the real-time XOR comparison mechanism, the hardware-level check of the second signal data and the reference data is completed within the operation window, and the check result required for the decision-making closed loop is generated, thereby realizing high-reliability error detection within a single clock cycle.

[0144] Referring to Figures 2-5 As shown in the figure, in one embodiment, the second signal data and the reference data are subjected to real-time XOR comparison to obtain a check result, including:

[0145] The reference data is accessed and driven by an enhanced driving circuit for signal conditioning. The circuit adopts a current multiplexing push-pull amplifier structure, including a symmetrically distributed PMOS pull-up tube array and an NMOS pull-down tube array. The input stage is isolated from the load effect by a source follower, realizing high input impedance characteristics. The reference data voltage drives the push-pull output stage, generating a full-swing output signal between the power supply rails, and the voltage conversion rate is optimized to meet the high capacitive load driving requirements. The output impedance of the enhanced driving reference signal is reduced to below 200Ω, the driving capability is adapted to the bus transmission load, and the signal ringing is eliminated. Internal phase compensation is introduced in the buffering process to ensure stability in the full frequency band and avoid the risk of oscillation caused by capacitive load. The enhanced signal transmission path implements impedance matching design to ensure that the signal edge remains monotonic.

[0146] The second signal data is processed by a level conversion module. The module adopts a latch-type level converter architecture, the low-voltage side input port receives the original signal through a level shifter, and the high-voltage side output port is connected to a dual-power supply system. The conversion mechanism realizes signal amplitude expansion through cross-coupled inverters, generating a full-swing output that meets the target logic level requirements. The high-level and low-level values of the full-swing data signal are strictly constrained within the power supply rail range, and the threshold hysteresis is controlled within the 200mV range. The setup time of the conversion process is matched with the high-level window of the periodic read signal, and the delay deviation is maintained within the ±1ns accuracy range. The output stage is configured with an electrostatic protection structure to improve the interface reliability.

[0147] An enhanced drive reference signal and full swing data signal are input in parallel to an XOR logic gate. The logic gate uses a complementary transmission gate design: a P-type network is formed by a series PMOS tube and a parallel NMOS tube to form an input path, and an N-type network is arranged in mirror symmetry. When the two input signals present opposite levels, the logic gate outputs a high level state; when the input signals are in phase, the output is a low level state. The operation result is reconstructed into a digital logic level through an output buffer stage to form the original check data. The transmission delay of the logic gate is strictly controlled within 3ns to meet the real-time comparison timing constraints. Power supply noise suppression is achieved through substrate isolation and independent supply pins, with a voltage fluctuation tolerance range of ±10%. A glitch filter is integrated at the original check data output end to eliminate the risk of metastability.

[0148] The original check data input edge triggers a verification circuit for processing. The core of the circuit is a synchronous sampling clock (CLK_CK) generation module, whose trigger source is the falling edge of the periodic read signal (READ). When the periodic read signal (READ) transitions from high to low, the trigger clock generator outputs a 5ns wide sampling pulse. The verification circuit uses a master-slave D flip-flop structure: the master latch captures the original check data level state at the rising edge of the synchronous sampling clock (CLK_CK), and the slave latch outputs a stable synchronous check result at the falling edge of the synchronous sampling clock (CLK_CK). The setup time design ensures that the data is stable before the sampling window, and the hold time constraint eliminates the risk of metastability. The timing deviation control mechanism is realized through a delay-locked loop, with a phase alignment accuracy of ±0.5ns. The temperature compensation circuit maintains timing stability within the full operating temperature range, ensuring sampling reliability in extreme conditions.

[0149] The synchronous check result is input into a bistable latch for state solidification processing. The latch uses a cross-coupled NOR gate architecture: the first NOR gate input port receives the check data signal, and the output end is connected to the input end of the second NOR gate; the output of the second NOR gate is fed back to the input of the first NOR gate. The locking process is completed in 3ns through a positive feedback loop, and the noise tolerance design enhances the noise immunity. The latch output stage integrates a three-state control logic: when the periodic read signal (READ) is at a low level, the output drive is enabled, and when it is at a high level, it is switched to a high resistance state. The check result is latched as a stable digital level signal: a low level represents that the data consistency verification is passed, and a high level represents that the data is abnormal. The static power consumption optimization design controls the leakage current at the level of nanoamperes, and the data retention time covers the complete decision cycle requirement.

[0150] The latched check result drives the decision state machine to perform a branch operation: when the check result presents a low level, the enable port of the tri-state output buffer is activated to turn on the OTP data bus transmission channel. When the check result presents a high level, a 200 ns wide reset control signal (RSTN) negative pulse is generated. The RSTN pulse synchronously triggers a three-way linkage operation: the address counter is asynchronously reset to clear the addressing pointer; the static random access memory charge discharge module forces the first node and the second node to be initialized (grounded by turning on the NM5 tube); and the timing control state machine resets the generation process of the periodic read signal (READ) and the check control signal (READ_CHECK). The linkage response delay is within 10 ns, and the hardware state machine realizes autonomous error correction without software intervention. The check result is simultaneously input to a 32-bit error counter, and when the number of exceptions exceeds the preset threshold, a fuse protection mechanism is triggered.

[0151] The embodiment uses a periodic read signal falling edge to accurately trigger a sampling clock to realize synchronous capture of the check data, thereby completely eliminating the metastability risk caused by asynchronous sampling. Through result latching technology, the check state is fixed by using a cross-coupled bistable structure, thereby greatly improving the noise tolerance and anti-interference ability. Through closed-loop feedback linkage design, the check result directly drives the collaborative operation of multiple modules, thereby completing error detection and system reset within a single clock cycle. Through the collaborative processing of level conversion and signal buffering, the voltage domain and driving characteristics of the data signal are unified, thereby ensuring the electrical compatibility of the comparison operation. Through real-time hardware-level XOR operation, data consistency verification is completed within the read window, thereby avoiding the millisecond-level delay of traditional software verification. Through tri-state control and error counting mechanism, a hierarchical response strategy is realized to ensure core functions while providing cumulative protection.

[0152] Reference Figures 2-5 As shown in the figure, in one embodiment, the check result is detected in a closed loop to obtain an OTP check result, including:

[0153] The check result signal is input to a state analysis circuit for processing. The circuit uses a window comparator architecture to set a high-low level judgment threshold interval: below 0.3V is identified as a logic low level, and above 1.5V is identified as a logic high level. The level detection result is transmitted to an encoding logic unit to map a single-bit check state into a 2-bit binary code: 00 represents a standby state, 01 indicates a data consistent state, and 10 indicates a data abnormal state. When 01 indicates a data consistent state, the reference read-back data line (DR) is 101 and the real-time read data line (DL) is 101. When 10 indicates a data abnormal state, the reference read-back data line (DR) is 101 and the real-time read data line (DL) is 111.

[0154] The state identification signal output stage is configured with an electrostatic protection network and an RC low-pass filter to eliminate high-frequency noise interference and electrostatic discharge risk. The signal transmission path uses differential balanced wiring, and the path delay deviation is controlled within ±5 ps. The total delay of the analysis process is strictly constrained within 3 ns, and the falling edge of the synchronous sampling clock (CLK_CK) triggers the output latch, and the falling edge of the state identification signal and the periodic read signal (READ) are aligned. The verification state identification signal is transmitted to the decision module through a low-impedance bus, and a buffer repeater is inserted in the transmission path to ensure signal integrity.

[0155] The verification state identification signal is input into the decision state machine for pattern recognition. The state machine uses a synchronous finite state machine architecture, and the clock source is bound to the falling edge of the periodic read signal (READ). The state transition logic strictly follows the coding definition: when the identification signal is 01, switch to the data output branch, and output the "data output mode" enable signal which is high level valid; when the identification signal is 10, switch to the error handling branch, and output the "error handling mode" trigger pulse. The state transition process integrates a protection mechanism: illegal coding state (00 or 11) triggers a watchdog timer, which forces the state machine to reset to the initial state within 10 ns. The operation mode output signal is kept stable through master-slave latches, and the latch enable end is connected to the synchronous sampling clock (CLK_CK), which maintains a constant level within the periodic read signal (READ) period. The signal transmission path implements equal-length zigzag wiring to eliminate multi-path transmission delay differences. The operation mode signal is used as a core control variable to directly drive the activation timing of the subsequent tri-state gate and data output process.

[0156] When the verification state identification signal is in the data consistent state (01 code), the operation mode switches to the data output mode. The 01 code of the verification state identification signal input tri-state gate circuit generates a drive signal: this signal turns on the PMOS / NMOS transistor array of the output stage to form a low-impedance path, while the input buffer circuit is locked to prevent signal conflict. The gate activation process binds the low-level window of the periodic read signal (READ) in timing, and completes the channel establishment within 5 ns after the falling edge of the synchronous sampling clock (CLK_CK). The output channel integrates a dynamic impedance matching network to eliminate waveform distortion caused by signal reflection, and the return loss index meets the high-speed bus transmission standard. The reference read data line (DR) has completed the verification mission in this stage, and the second signal data carried by the real-time read data line (DL) becomes the core processing object.

[0157] After the data output channel is activated, the second signal data is physically enhanced through a three-stage driving architecture: the current mode pre-driver optimizes the signal conversion rate to the order of 200 V / μs, eliminating transmission delay deviation; the push-pull output stage expands the current driving capability to 10 mA threshold, supporting multiple node parallel loads; the active terminal matching circuit compensates for impedance fluctuations in real time, suppressing intersymbol interference. The driving process reconstructs the DL signal into a full-swing digital level of 0V-1.8V, with the rise / fall time symmetrically controlled within 1.5ns±0.1ns, and the overshoot phenomenon constrained within a voltage swing of 5%. The electrical characteristics of the bus-compatible data completely match the AMBA bus specification, and the setup / hold time margin meets the most stringent timing constraints.

[0158] The bus-compatible data input protocol packaging engine performs structured processing: adds a hexadecimal synchronization header (55AAh) to identify the starting boundary of the data frame, with a duty cycle tolerance controlled to ±0.1% precision; inserts a CRC8 check byte to verify transmission integrity, using an industry standard polynomial; and adds a 24-bit timestamp tag to record the operation time to the nanosecond level. The packaging process uses a four-stage pipeline architecture, with each processing stage strictly aligned with the 10MHz system clock cycle. The final generated OTP verification result is structured into a standard bus data packet: [2-byte synchronization header]-[2-byte length field]-[N-byte payload]-[1-byte CRC8]-[3-byte timestamp], with the frame structure optimized for signal integrity through pre-emphasis technology. The output timing parameters meet the boundary requirements of a setup time of 2ns and a hold time of 1ns, and the flow control mechanism dynamically adjusts the data throughput rate to avoid bus bandwidth overload.

[0159] The data output process establishes a physical path through tri-state gating, ensures signal quality through driving enhancement, and standardizes the bus through protocol packaging, forming a complete conversion chain from the verification result to the application layer data. The entire process follows the timing requirements: tri-state activation is completed in the early stage of the low-level window of the periodic read signal (READ), driving enhancement is performed in the middle stage of the window, and protocol packaging is output in the late stage of the window, with a time boundary accuracy of ±0.5ns. The technical value lies in seamlessly connecting the physical layer signal with the protocol layer specification, making the OTP storage data directly accessible to the vehicle control system bus architecture.

[0160] This embodiment precisely drives the tri-state gate through the verification state identification signal, and only activates the output channel in the data consistent state, thereby eliminating the risk of error data polluting the system bus. Through the multi-stage driving enhancement architecture, the physical layer of the second signal data is optimized, the signal integrity is strengthened, and the load driving capability is improved, thereby ensuring the reliability of data transmission in a high-capacity bus environment. Through the frame header synchronization, check byte, and timestamp tag triple protection mechanism of the protocol packaging engine, plug-and-play system integration and high-reliability data interaction are supported.

[0161] Referring to Figures 2-5 As shown in FIG. 1, in one embodiment, when the operation mode is the error handling trigger mode, the following steps are further included:

[0162] When the check status identification signal is determined to be the data abnormal state (10 code), a reset pulse generation circuit is triggered to perform a width modulation operation. The circuit adopts a voltage controlled oscillator and a duty cycle controller architecture: the oscillator frequency is dynamically adjusted according to the power supply voltage, and the duty cycle controller sets a fixed 20% duty cycle. The modulation process stabilizes the pulse characteristics through a feedback loop, and temperature drift compensation maintains the consistency of the output. The generated reset control pulse (RSTN) presents a 200ns low-level active pulse, the falling edge delay is controlled within 5ns, and the rising edge is configured with a slow slope to eliminate electromagnetic interference. The pulse width tolerance is ±10%, the voltage swing covers the full power supply range of 0V to 1.8V, and the driving capability meets the demand of multiple module parallel load. The pulse parameters strictly match the system reset timing requirements, eliminating the risk of cascading reset conflicts.

[0163] The low-level active edge of the reset control pulse directly drives the address pointer zeroing circuit. The circuit includes an asynchronous reset logic gate and a counter array: the falling edge of the reset pulse triggers the RS latch to output a zero enable signal, which is directly connected to the asynchronous reset port of the address counter. All storage units of the counter are forced to zero within 10ns, and the output is a full 0 binary coded address. The zeroing process runs independently of the system clock, and the response delay is less than the timing constraint boundary. The reset addressing state is verified by the state detection circuit: when the address bus presents a stable full 0 level, a high-level active state flag is output. The state flag signal is transmitted to the reset pulse modulation module to form a closed-loop verification link. The address pointer reset mechanism ensures that the storage array access position returns to the initial state.

[0164] The low-level state of the reset control pulse activates the charge discharge control circuit. The circuit generates a discharge enable signal to drive the NMOS discharge tube array inside the static random access memory: the enable signal turns on the NM5 tube, forcing the second node to ground; the first node voltage is pulled up to the power supply rail by synchronously activating the inverter chain. The charge discharge process resets the node voltage within 50ns, and the discharge current peak is limited within 5mA. The completion status is detected by a voltage comparator. The signal marks the storage unit charge zero state, which is fed back to the reset control module through metal layer wiring. The discharge operation eliminates the interference of residual charge on the restart process.

[0165] The reset addressing state and the residual data clearing signal are input into the reset state machine in parallel to verify each other. When the reset addressing state flag presents a high level (all zeros on the address bus) and the residual data clearing signal maintains a valid high level, the state machine outputs a reset confirmation instruction. The instruction drives the reset control pulse generation module to perform the state reset operation: first, turn off the voltage controlled oscillator power supply, second, clear the internal registers of the duty cycle controller, and finally switch the output stage to a high impedance state. The reset process releases the residual energy of the energy storage element through the charge discharge circuit, and the reset completion flag jumps to a high level within 20 ns. The reset signal generation state represents that the pulse generation circuit has returned to the initial standby state, and the static current has decreased to the microampere level, providing a pure initialization environment for the restart process. The state transition process integrates an interlocking mechanism to ensure that the signal generation module is not reset before the address and memory reset is completed, avoiding timing conflict risks.

[0166] The high level valid flag of the reset signal generation state triggers the verification control signal to reinitialize the process. The initialization sequence is controlled by the state machine: first, load the default high level state of the verification control signal (READ CHECK), second, reset the timing divider phase to the reference position, and finally release the clock gate enable synchronously. The restart verification signal is output through a push-pull driver, with a rise time delay control within 5 ns and a voltage swing strictly limited to 0V-1.8V. The signal characteristics are verified by the calibration circuit: frequency tolerance ±100ppm, duty cycle deviation ≤2%, and phase jitter controlled within 50ps peak-to-peak. The restart verification signal output end is configured with an overshoot suppression network to eliminate high-frequency harmonic interference and ensure signal edge monotonicity. This signal serves as the core timing reference for system restart and directly drives the subsequent double-read verification process activation.

[0167] The rising edge of the restart verification signal triggers the double-read verification full-process restart. The process controller executes a four-stage start-up sequence:

[0168] 1. The address pointer generation module is reset. 2. The static random access memory input path is enabled. 3. The periodic read signal generator is activated synchronously. 4. The verification decision state machine returns to the initial standby state.

[0169] The restart process is tracked in real time by the monitoring circuit: the address counter step action as the addressing recovery flag, the static random access memory latch node voltage as the storage ready flag, and the first rising edge of the periodic read signal (READ) as the timing reference flag. When all monitoring indicators reach a steady state, a high level valid restart process information is output. This information flag indicates that the system has returned to the initial state and can execute the "power supply voltage based power-on reset signal generation" start-up process again. The restart response delay is compressed within 100ns, and the power consumption peak is limited to 120% of the normal working mode.

[0170] The embodiment generates accurate timing reset control pulses through a reset pulse width modulation mechanism, realizes fast response to error state, and thus improves the hardware level recovery speed. Through parallel operation of address pointer asynchronous zero clearing and memory node charge discharge, the core module state is reset, and the risk of interference of residual data on the restart process is eliminated. Through the double verification mechanism of reset state and clearing signal, the integrity and timing coordination of the reset operation are ensured, and the logic conflict caused by cascading reset is avoided.

[0171] Referring to Figure 6 The application provides a dual-read verification device for OTP, which is applied to the dual-read verification method for OTP.

[0172] The power-on reset and address generation module is used for generating a power-on reset signal based on a power supply voltage, responding to a signal, obtaining a periodic reading signal and a verification control signal;

[0173] The reading module is used for performing OTP one-time reading on the OTP read-write system according to the first period of the periodic reading signal and the verification control signal, and storing the data into a static random access memory to obtain reference data;

[0174] The comparison module is used for performing OTP two-time reading according to the second period of the periodic reading signal in combination with the verification control signal, and comparing the data with the reference data to obtain a verification result;

[0175] The processing module is used for performing closed-loop detection on the verification result to obtain an OTP verification result.

[0176] The application provides a double-reading check device of OTP, which establishes reference data in the first reading stage through the time sequence cooperation mechanism of periodic reading signals and check control signals, and realizes instantaneous latching through static random access memory, combines the real-time comparison structure of secondary reading, effectively avoids the data misreading risk caused by power transient fluctuation, and significantly improves the integrity guarantee capability of key storage information. The input / output physical path of the static random access memory is innovatively reused, the reference data establishment and the check read-back function are integrated in the same hardware unit, the storage resource consumption of the traditional triple modular redundancy is eliminated while realizing the double-channel check function, and a resource-efficient reliability solution is provided for cost-sensitive equipment. Relying on the synchronous time sequence control system constructed by the periodic reading signals, the data sampling point is accurately triggered in the secondary reading window, the establishment time conflict problem of asynchronous clock is completely avoided, and the time sequence consistency of the storage unit and the check logic is guaranteed. When the check result is abnormal, the closed-loop detection mechanism automatically triggers the address pointer reset and the memory state refresh, realizes self-contained error recovery through the reset of the signal generation state, and completes the millisecond error correction response at the hardware level. This double-cycle check architecture strengthens the time sequence robustness while compressing the physical resource occupation, can meet the strict requirements of the zero-tolerance scene in the functional safety standard, and provides a storage access paradigm with economy and safety.

[0177] It should be noted that, for the convenience and brevity of description, the specific working processes of the above-described system and each module can be referred to the corresponding processes in the foregoing method embodiments, and will not be described here.

[0178] The above only describes the preferred embodiments of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation based on the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.

Claims

1. A double reading check method of OTP, characterized in that, The method comprises the following steps: generating a power-on reset signal based on a power supply voltage, performing a signal response, obtaining a periodic reading signal and a verification control signal; performing OTP one-time reading on an OTP read-write system according to a first period of the periodic reading signal and the verification control signal, and storing the data into a static random access memory to obtain reference data; performing OTP two-time reading according to a second period of the periodic reading signal in combination with the verification control signal, and comparing with the reference data to obtain a verification result; performing closed-loop detection on the verification result to obtain an OTP verification result; when the verification result is abnormal, the closed-loop detection mechanism automatically triggers address pointer reset and memory state refresh, realizes self-contained error recovery through signal generation state reset, and completes millisecond-level error correction response at the hardware level.

2. The method of claim 1, wherein, The method of generating a power-on reset signal based on a power supply voltage and performing a signal response to obtain a periodic reading signal and a verification control signal comprises the following steps: performing voltage detection and threshold comparison on the power supply voltage to generate a power-on reset signal; obtaining a periodic reading signal generated by the OTP read-write system based on the power-on reset signal; performing OTP control activation based on the power-on reset signal to obtain an OTP read-write control enable signal; performing state machine conversion on the OTP read-write control enable signal according to the periodic reading signal to obtain a verification control signal.

3. The method of claim 1, wherein, The method of performing OTP one-time reading on an OTP read-write system according to a first period of the periodic reading signal and the verification control signal, and storing the data into a static random access memory to obtain reference data comprises the following steps: performing high-level interval detection on the first period to obtain a one-time operation window signal; performing level state reading on the verification control signal according to the one-time operation window signal to obtain a first level state; performing address pointer incremental triggering on the OTP read-write system according to the first level state to obtain a first reading address; performing storage array decoding on the OTP read-write system according to the first reading address to obtain a target storage unit row; performing bit selection conduction reading on the target storage unit row to output first signal data; inputting the first signal data into the static random access memory for latch processing to obtain the reference data.

4. The method of claim 3, wherein, The method of inputting the first signal data into the static random access memory for latch processing to obtain the reference data comprises the following steps: generating a bit selection control signal from a switch control signal of the verification control signal; performing differential conversion on the first signal data to obtain a same-phase data signal and an inverse-phase data signal; performing first input path gate drive on the same-phase data signal according to the bit selection control signal to obtain a first node voltage; performing second input path gate drive on the inverse-phase data signal according to the bit selection control signal to obtain a second node voltage; performing cross-coupled inverter latching on the first node voltage and the second node voltage to obtain a stable node voltage pair; performing output buffering on the stable node voltage pair to obtain reference data.

5. The method of claim 1, wherein, The second period according to the periodic read signal is combined with the check control signal for OTP secondary reading, and is compared with the reference data to obtain a check result, comprising: A high level interval identification is performed on the second period to obtain a secondary operation window signal; A state switching detection is performed on the check control signal according to the secondary operation window signal to obtain a low level state signal; An output channel multiplexing control is performed on the static random access memory according to the low level state signal, and a back-reading channel is activated to extract the reference data; An address pointer increment trigger is performed on the OTP read-write system according to the secondary operation window signal to obtain a second read address; A target cell reading is performed on the OTP read-write system according to the second read address to obtain second signal data; A real-time exclusive OR comparison is performed on the second signal data and the reference data to obtain the check result.

6. The method of claim 5, wherein, The real-time exclusive OR comparison on the second signal data and the reference data to obtain the check result, comprising: A signal buffering is performed on the reference data to obtain an enhanced driving reference signal; A level conversion is performed on the second signal data to obtain a full-swing data signal; An exclusive OR logic gate operation is performed on the enhanced driving reference signal and the full-swing data signal to obtain original check data; An edge trigger verification is performed on the original check data according to the periodic read signal to obtain the check result.

7. The method of claim 5, wherein, The closed loop detection on the check result to obtain an OTP verification result, comprising: A state analysis is performed on the check result to obtain a check state identification signal; A decision branch identification is performed on the check state identification signal to obtain an operation mode; When the operation mode is a data output mode: A tristate gate activation is performed on the OTP read-write system according to the check state identification signal to obtain a data output channel; A driving capability enhancement is performed on the second signal data through the data output channel to obtain bus compatible data; A protocol packaging output is performed on the bus compatible data to obtain the OTP verification result.

8. The method of claim 7, wherein, Further comprising, when the operation mode is an error processing trigger mode: A reset pulse width modulation is performed on the check state identification signal to obtain a reset control pulse; An address pointer asynchronous zero clearing is performed according to the reset control pulse to obtain a reset addressing state; A node charge discharge is performed on the static random access memory according to the reset control pulse to obtain a residual data clearing signal; A signal generation state reset is performed on the reset control pulse according to the reset addressing state and the residual data clearing signal to obtain a reset signal generation state; A check control signal reinitialization is performed according to the reset signal generation state to obtain a restart check signal; A double read check process restart is performed according to the restart check signal to obtain restart process information.

9. A double reading check device for OTP, characterized in that, The OTP double read check method is applied to any one of the above claims 1-8, comprising: The power-on reset and address generation module is used for generating a power-on reset signal based on a power supply voltage, responding to a signal, obtaining a periodic reading signal and a check control signal; The reading module is used for performing OTP one-time reading on the OTP read-write system according to the first period of the periodic reading signal and the check control signal, storing the data into a static random access memory, and obtaining reference data; The comparison module is used for performing OTP two-time reading according to the second period of the periodic reading signal and in combination with the check control signal, comparing with the reference data, and obtaining a check result; The processing module is used for performing closed-loop detection on the check result, and obtaining an OTP inspection result; When the check result is abnormal, the closed-loop detection mechanism automatically triggers address pointer reset and memory state refresh, realizes self-contained error recovery through signal generation state reset, and completes millisecond-level error correction response at the hardware level.

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