Compiler infrastructure based on multi-order intermediate representation and implementation method thereof

Abstract

The invention relates to a compiler design and code optimization technology, in particular to a compiler infrastructure based on multi-order intermediate representation and an implementation method of the compiler infrastructure. A traditional compiler adopts single intermediate representation, so that the coupling degree of the optimization process is high; the method is closely related to high-level / low-level languages, so that the compiler is poor in universality. In order to solve the problems, the invention provides the compiler infrastructure based on the multi-level intermediate representation and the implementation method of the compiler infrastructure, through modular design and hierarchical processing, the relevance of high-level / low-level languages is stripped, and the multi-level intermediate representation is designed, so that the problem that the compiler infrastructure cannot be used in the process of converting the high-level languages into the low-level languages is solved; the processing complexity of the control flow and the data flow is high, the universality is poor, and the subsequent maintenance difficulty is high. The method is suitable for real-time compiling, heterogeneous hardware adaptation and multi-language mixed programming and static optimization scenes, and the development and maintenance cost of the compiler can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to compiler design and code optimization technology, and in particular to a compiler infrastructure based on Multi-Stage Intermediate Representation (MSIR) and an implementation method thereof. Background Art

[0002] A compiler is a tool that converts high-level languages ​​into machine-readable low-level languages. Compiler infrastructure is shared across many different compilers and consists of multiple basic components. It is independent of the implementation of a specific programming language, stripping away the specificities of high-level and low-level languages ​​and enabling easy portability to any compiler implementation. Specifically, compiler infrastructure includes: front-end automaton-based grammatical / syntactic / semantic analysis, including automaton construction logic; mid-end syntax tree conversion to intermediate representation, conversion between different intermediate representation forms, and intermediate representation optimization.

[0003] Traditional compiler infrastructure has only one level of intermediate representation (IR) between high-level languages ​​and low-level languages. IR is a representation of the functionality of the compiled program within the compiler, between the high-level language being compiled and the low-level language instructions of the target platform. Traditional compilers use a single IR, which leads to a high degree of coupling in the optimization process and difficulty adapting to fine-grained optimizations at different abstraction levels. The close correlation with high-level and low-level languages ​​results in poor compiler versatility, and a lot of time and manpower are required to rebuild new and corresponding compiler infrastructure for different high-level and low-level languages. For example, although LLVM's IR supports multi-stage optimization, its single-layer structure cannot effectively separate high-level language features from underlying hardware details, resulting in inefficient cross-language porting and dynamic optimization. In addition, existing technologies lack reverse conversion capabilities, making optimization errors difficult to trace and locate, increasing debugging and maintenance costs.

[0004] A compiler infrastructure based on multi-level intermediate representation and its implementation method, through modular design and layered processing, minimizes the learning curve for users of the compiler infrastructure. This solves the problems of high complexity in control flow and data flow processing, poor versatility, and difficulty in subsequent maintenance when the compiler infrastructure converts high-level languages ​​into low-level languages. Summary of the Invention

[0005] The present invention provides a compiler infrastructure based on multi-level intermediate representation and its implementation method, which supports unified access to different high-level language front-ends (such as C / C++, Java, Python, Rust) and hardware platform back-ends (such as x86, ARM). By stripping away the correlation between high-level and low-level languages, a multi-level intermediate representation (MSIR) is designed, and the compilation process is decomposed into a high-level intermediate representation (HIR) layer, a middle-level intermediate representation (MIR) layer, and a low-level intermediate representation (LIR) layer, a total of three layers of progressive IR. Combined with reversible conversion rules and a cross-level optimization coordination mechanism, high-level languages ​​are gradually converted into low-level languages, realizing a more convenient, intuitive and simple maintenance process for the entire structure and the data it carries.

[0006] The present invention provides a compiler infrastructure based on multi-level intermediate representation and its implementation method, the technical solution of which includes:

[0007] 1. Front-end processing.

[0008] Based on the source code input by the user (such as C / C++, Java, Python, Rust, or any other high-level language), the source code is parsed, language-specific features in the source code are stripped away (such as syntactic sugar and language-specific structures), and a high-level intermediate representation (HIR) is generated that is independent of the high-level language.

[0009] 2. Design of Multi-Order Intermediate Representation (MSIR)

[0010] MSIR is generally decomposed into three layers of progressive IR: the high-level intermediate representation (HIR), the middle-level intermediate representation (MIR), and the low-level intermediate representation (LIR). HIR is usually in the form of graph IR, while MIR and LIR are usually in the form of instruction IR.

[0011] 1) High-level intermediate representation (HIR) layer.

[0012] Based on the HIR generated by the front-end, the HIR layer of the compiler infrastructure has the following functions:

[0013] (1) Preserve high-level semantics (such as loop structures and function calls).

[0014] (2) Support inter-procedural optimization: function inlining, loop unrolling, dependency analysis, and alias analysis.

[0015] In the actual implementation process, the HIR layer can be further subdivided into more levels of hierarchical HIR according to the granularity of the functional division of specific modules.

[0016] 2) According to the conversion rules from the HIR layer to the MIR layer, code conversion is performed on the MIR layer.

[0017] Based on the output of the HIR layer, the MIR of the compiler infrastructure has the following functions:

[0018] (1) Introduce optimizations for basic operations (such as arithmetic simplification and strength reduction).

[0019] (2) Apply instruction-level optimization: constant folding and dead code elimination.

[0020] (3) Apply some inter-procedural optimizations: such as replication propagation, loop invariant extraction, and common subexpression elimination.

[0021] (4) Conversion between non-static single assignment and static single assignment.

[0022] In the actual implementation process, the MIR layer can be further subdivided into more levels of progressive MIR according to the granularity of the functional division of specific modules.

[0023] 3) Perform code conversion at the LIR layer according to the conversion rules from the MIR layer to the LIR layer.

[0024] Based on the output of the MIR layer, the LIR of the compiler infrastructure has the following functions:

[0025] (1) Allocate physical registers / memory locations.

[0026] (2) On the basis of shielding the instruction set characteristics of the underlying target hardware (such as x86, ARM), complete the generalization and standardization of the low-level language form.

[0027] (3) Optimization: instruction scheduling, pipeline filling, branch prediction optimization, and peephole optimization.

[0028] Provides corresponding functions for operations and optimizations related to the hardware platform (such as allocating physical registers / memory locations), but does not perform related specific work.

[0029] At the LIR layer, all processing unrelated to the low-level language is completed, and an intermediate representation is generated that can fully express the semantics of the low-level language but is unrelated to the specific low-level language, providing optimized, generalized, and standardized input for the final low-level language generation.

[0030] In the actual implementation process, the LIR layer can be further subdivided into more levels of progressive LIR according to the granularity of the functional division of specific modules.

[0031] 3. Based on the conversion results of the LIR layer, the generation of low-level language is completed in the low-level language generator.

[0032] Responsible for completing physical register allocation and instruction generation based on LIR and specific hardware instruction set, generating optimized low-level language, and outputting low-level language code.

[0033] 4. Reversible conversion rules.

[0034] By preserving metadata (such as parameter mapping tables and code snapshots before syntactic sugar expansion) and bidirectional converters, a bidirectional and lossless conversion process between different levels of IR (such as HIR→MIR→LIR) is achieved, supporting optimized backtracking and dynamic adjustment.

[0035] 5. Cross-level optimization and coordination mechanism

[0036] Cross-stage optimization is triggered through metadata channels, that is, by passing information through shared data structures.

[0037] The present invention provides a compiler infrastructure based on multi-level intermediate representation and its implementation method, which supports unified access to different high-level language front-ends (such as C / C++, Java, Python, Rust) and hardware platform back-ends (such as x86, ARM). By stripping away the correlation between high-level and low-level languages, designing a multi-level progressive intermediate representation, and combining reversible conversion rules and cross-level optimization coordination mechanisms, high-level languages ​​are gradually converted into low-level languages, achieving a more convenient, intuitive and simple maintenance process for the entire structure and the data it carries.

[0038] Experiments show that this method reduces the number of IR instructions by an average of 12% on the LLVM test set, improves data flow analysis speed by approximately 23%, and significantly reduces JIT compilation latency. By implementing "optimized rollback" through reverse conversion, it improves debugging efficiency and shortens error location time by over 40%. This method is suitable for real-time compilation, heterogeneous hardware adaptation, and multi-language mixed programming and static optimization scenarios, significantly reducing compiler development and maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 : An architectural block diagram of a compiler infrastructure based on multi-order intermediate representation and its implementation method.

[0040] Figure 2 :Schematic diagram of the compilation process of loop accumulation code based on multi-order intermediate representation compiler infrastructure and its implementation method.

[0041] Figure 3 : Schematic diagram of the compilation process of function call code based on multi-order intermediate representation compiler infrastructure and its implementation method. DETAILED DESCRIPTION

[0042] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0043] The features of various aspects of the embodiments of the present invention will be described in detail below. In the detailed description below, many specific details are provided to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can also be implemented without these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is not limited to any specific settings and methods provided below, but rather covers all product structures, any improvements, replacements, etc. of the methods covered without departing from the spirit of the present invention. In the various drawings and the following description, well-known structures and technologies are not shown to avoid unnecessary ambiguity in the present invention.

[0044] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other, and the embodiments can refer to and quote each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] The present invention provides a compiler infrastructure based on multi-level intermediate representation and its implementation method, which supports unified access to different high-level language front-ends (such as C / C++, Java, Python, Rust) and hardware platform back-ends (such as x86, ARM). By stripping away the correlation between high-level and low-level languages, designing a multi-level progressive intermediate representation, and combining reversible conversion rules and cross-level optimization coordination mechanisms, high-level languages ​​are gradually converted into low-level languages, achieving a more convenient, intuitive and simple maintenance process for the entire structure and the data it carries.

[0046] Experiments show that this method reduces the number of IR instructions by an average of 12% on the LLVM test set, improves data flow analysis speed by approximately 23%, and significantly reduces JIT compilation latency. By implementing "optimized rollback" through reverse conversion, it improves debugging efficiency and shortens error location time by over 40%. This method is suitable for real-time compilation, heterogeneous hardware adaptation, and multi-language mixed programming and static optimization scenarios, significantly reducing compiler development and maintenance costs.

[0047] The present invention provides a compiler infrastructure based on multi-order intermediate representation and an implementation method thereof, the method comprising the following steps:

[0048] Step 1: User enters source code

[0049] The source code entered by the user can be in any high-level language such as C / C++, Java, Python, Rust, etc.

[0050] Step 2: Perform front-end preprocessing based on the source code input by the user.

[0051] Parse the source code input by the user, strip off the high-level language features in the source code (such as syntactic sugar and language-specific structures), and generate a language-independent high-level intermediate representation (HIR).

[0052] Step 3: Perform HIR layer code conversion based on HIR.

[0053] Based on the HIR generated by the front-end, the HIR layer of the compiler infrastructure has the following functions:

[0054] (1) Preserve high-level semantics (such as loop structures and function calls).

[0055] (2) Support inter-procedural analysis and optimization: function inlining, loop unrolling, dependency analysis, and alias analysis.

[0056] In the actual implementation process, the HIR layer can be further subdivided into more levels of hierarchical HIR according to the granularity of the functional division of specific modules.

[0057] Step 4: Based on the output of the HIR layer, implement the conversion rules to the middle-order intermediate representation (MIR) of the compiler infrastructure.

[0058] The conversion rules from the HIR layer to the MIR layer are as follows:

[0059] (1) Convert high-order operations in HIR into basic operations (e.g., matrix multiplication into simple numerical operations).

[0060] (2) Reverse mapping information is retained to support reverse conversion.

[0061] That is, it is also possible to convert from MIR to HIR.

[0062] Step 5: According to the conversion rules from the HIR layer to the MIR layer, perform code conversion at the MIR layer.

[0063] Based on the output of the HIR layer, the MIR of the compiler infrastructure has the following functions:

[0064] (1) Introduce optimizations for basic operations (such as arithmetic simplification and strength reduction).

[0065] (2) Apply instruction-level optimization: constant folding and dead code elimination.

[0066] (3) Apply some inter-procedural optimizations: such as step propagation, loop invariant extraction, and common subexpression elimination.

[0067] (4) Conversion between non-static single assignment and static single assignment.

[0068] In the actual implementation process, the MIR layer can be further subdivided into more levels of progressive MIR according to the granularity of the functional division of specific modules.

[0069] Step 6: Based on the output of the MIR layer, implement the conversion rules to the low-level intermediate representation (LIR) of the compiler infrastructure. The conversion rules from the MIR layer to the LIR layer are as follows:

[0070] (1) Convert the symbolic form of the operation into instruction form.

[0071] (2) Preserve debugging information and optimize traceability data.

[0072] Step 7: Perform code conversion at the LIR layer according to the conversion rules from the MIR layer to the LIR layer.

[0073] Based on the output of the MIR layer, the LIR of the compiler infrastructure has the following functions:

[0074] (1) Allocate physical registers / memory locations.

[0075] (2) On the basis of shielding the instruction set characteristics of the underlying target hardware (such as x86, ARM), complete the generalization and standardization of the low-level language form.

[0076] (3) Optimization: instruction scheduling, pipeline filling, branch prediction optimization, and peephole optimization.

[0077] Provides corresponding functions for operations and optimizations related to the hardware platform (such as allocating physical registers / memory locations), but does not perform related specific work.

[0078] At the LIR layer, all processing unrelated to the low-level language is completed, and an intermediate representation is generated that can fully express the semantics of the low-level language but is unrelated to the specific low-level language, providing optimized, generalized, and standardized input for the final low-level language generation.

[0079] In the actual implementation process, the LIR layer can be further subdivided into more levels of progressive LIR according to the specific module division. Step 8: Based on the conversion results of the LIR layer, the low-level language is generated in the low-level language generator.

[0080] Responsible for adapting LIR to the specific hardware instruction set, completing physical register allocation and instruction generation, generating optimized low-level language, and outputting low-level language code.

[0081] Example 1

[0082] Figure 2 It is a schematic diagram of the compilation process of a cyclic accumulation code based on a compiler infrastructure and an implementation method thereof according to an embodiment of the present invention.

[0083] like Figure 2 As shown, the method includes the following steps:

[0084] Step 201. User inputs source code

[0085] User enters Python source code:

[0086]

[0087] Step 202: Front-end processing generates HIR

[0088] Based on the Python source code input by the user, the front-end processing is completed: syntactic sugar is stripped (such as `range` is converted into loop control logic), language-related features are stripped, and language-independent HIR is generated.

[0089] Generate HIR representation as follows:

[0090]

[0091] Loop boundaries (`1 to 100`) and variable scope information are recorded through metadata preservation.

[0092] Step 203: HIR layer code conversion

[0093] HIR layer code conversion completes the following functions:

[0094] (1) Preserve high-order semantics: explicitly preserve the `loop` structure and variable dependencies.

[0095] (2) Interprocedural optimization: Apply loop dependency analysis and mark loop expandability.

[0096] Step 204. Conversion rules from HIR to MIR

[0097] The conversion from HIR to MIR completes the mid-level optimization, and its rules are defined as:

[0098] (1) Convert `loop` to a `while` structure and decompose high-order operations into basic operations.

[0099] (2) Reverse mapping preservation: Establish a mapping table between `HIR-loop` and `MIR-while`.

[0100] The generated MIR is represented as follows:

[0101]

[0102] Step 205. MIR layer code conversion

[0103] MIR layer code conversion completes the following functions:

[0104] (1) Basic operation optimization: Apply constant folding (`i<=100` is always true, and the loop is expanded).

[0105] (2) Instruction-level optimization: dead code elimination (removing redundant conditional judgments).

[0106] (3) Cross-level collaboration: The number of instructions after loop expansion is fed back to the LIR layer through a shared data structure.

[0107] Step 206. Conversion rules from MIR to LIR

[0108] In this embodiment, the conversion rule from MIR to LIR is defined as:

[0109] (1) Allocate symbolic variables as physical registers to mask hardware characteristics.

[0110] (2) Debug information retention: record the mapping relationship between variables and registers (such as `sum→%r1`, `i→%r2`).

[0111] The generated LIR representation, or general low-level representation, is as follows:

[0112]

[0113]

[0114] Step 207. LIR layer code conversion

[0115] LIR layer code conversion performs the following functions:

[0116] (1) Physical register allocation: Optimize register usage based on the number of instructions fed back by MIR.

[0117] (2) Low-level optimization: peephole optimization (`INC % r2` instead of `ADD % r2,1`).

[0118] (3) Cross-stage coordination: When the `%r2` register is detected to be over-pressured, the reverse conversion is triggered to adjust the loop unrolling strategy.

[0119] For example, in this step, a register allocation error (such as `%r2` conflict) is found, and the steps for implementing the reversible conversion are as follows:

[0120] First, locate the `while` loop of the MIR layer in step 104 through the reverse mapping table.

[0121] Next, reverse conversion is performed to the MIR layer, the loop unrolling strategy is adjusted (eg, changed to partial unrolling), and step 105 is executed.

[0122] Again, step 106 is executed again to generate an optimized LIR code.

[0123] Finally, step 107 is executed again.

[0124] Step 208. Generate target code

[0125] In this example, we take the generation of x86 assembly target code as an example. The following operations need to be completed:

[0126] (1) Hardware adaptation: converting LIR into a specific instruction set.

[0127] (2) Output code:

[0128] ```assembly

[0129] mov eax,0;sum

[0130] mov ecx,1;i

[0131] LOOP:

[0132] cmp ecx,100

[0133] jg EXIT

[0134] add eax,ecx

[0135] inc ecx

[0136] jmp LOOP

[0137] EXIT:

[0138] ```

[0139] All steps have been completed, thus completing the compilation process for Python language loop accumulation based on a compiler infrastructure and implementation method for multi-level intermediate representation. This embodiment first strips away the language characteristics of the Python language front end and the x86 hardware platform back end; then designs MSIR, and combines reversible conversion rules that implement feedback and backtracking through metadata channels with a cross-level optimization coordination mechanism to gradually convert high-level languages ​​into low-level languages. This improves the optimization flexibility of the compiler infrastructure and enables a more convenient, intuitive, and simple maintenance process for the entire structure and its hosted data.

[0140] Example 2

[0141] Figure 3 The present invention is a schematic diagram of a compilation process of a function call code of a compiler infrastructure based on a multi-order intermediate representation and an implementation method thereof according to an embodiment of the present invention.

[0142] like Figure 3 As shown, the method includes the following steps:

[0143] Step 301. User inputs source code

[0144] The user enters the following C language code:

[0145]

[0146] Step 302: Front-end processing generates HIR

[0147] This step completes the parsing of function call syntax and stripping away language-related features.

[0148] The converted HIR is represented as follows:

[0149]

[0150] Optionally, metadata can be preserved in this step: `add` is marked as a small function and recommended for inline optimization. Step 303. Code conversion at the HIR layer

[0151] This step completes the following functions:

[0152] (1) Preserve high-order semantics: explicitly preserve function call relationships.

[0153] (2) Interprocedural analysis: Identify the calling frequency and parameter constness of the `add` function.

[0154] Step 304. Conversion rules from HIR to MIR

[0155] This step completes the following functions:

[0156] (1) Rule definition: Convert function calls to inline code and retain the parameter mapping table.

[0157] (2) Reverse mapping preservation: records code snapshots before and after inlining.

[0158] The converted MIR is represented as follows:

[0159]

[0160]

[0161] Step 305. MIR layer code conversion

[0162] This step completes the following functions:

[0163] (1) Basic operation optimization, which is constant folding (`3+5=8`) in this embodiment.

[0164] (2) Interprocedural optimization: dead code elimination (removing unused intermediate variables `x`).

[0165] (3) Cross-level collaboration: Feedback the optimized code complexity to the LIR layer.

[0166] Step 306. Conversion rules from MIR to LIR

[0167] The conversion rule from MIR to LIR is defined as: converting symbolic operations into instruction form and allocating registers.

[0168] In this step, debug information is retained to record the source of the constant (`8` is folded from `3+5`).

[0169] The converted LIR is represented as follows:

[0170]

[0171] Step 307: LIR layer code conversion

[0172] This step completes the following functions:

[0173] (1) Physical register allocation: Directly return constants without register operations.

[0174] (2) Low-level optimization: removing redundant instructions (such as intermediate load operations).

[0175] (3) Cross-level collaboration: Feedback optimization results to the MIR layer to trigger further simplification.

[0176] For example, in this step, it is detected that the frequently used variables are not allocated to the fast registers. The steps for implementing the cross-level coordination example are as follows:

[0177] First, the shared data structure is fed back to the MIR layer and step 204 is executed.

[0178] Next, the MIR layer adjusts the variable activity analysis strategy and executes step 205 .

[0179] Again, the LIR is regenerated, register allocation is optimized, and step 206 is executed again.

[0180] Finally, execute step 207.

[0181] Step 308. Generate low-level language code (ARM assembly)

[0182] This step completes the following functions:

[0183] (1) Hardware adaptation: converting LIR into ARM instruction set.

[0184] (2) Output code:

[0185] ```assembly

[0186] MOV r0,#8

[0187] BX

[0188] ```

[0189] All steps have been completed, thus completing the compilation process of C language function calls using a compiler infrastructure and implementation method based on multi-order intermediate representation. This embodiment first strips away the language characteristics of the C language front-end and the ARM hardware platform back-end. The MSIR design is strictly layered, ensuring that each layer focuses on specific optimizations, reducing the complexity of the compiler infrastructure. Through metadata sharing and reverse conversion, global optimization adjustments are achieved, increasing its dynamic adaptability. The modular design also improves the efficiency of error location and repair, significantly enhancing maintainability.

[0190] In summary, the present invention proposes a compiler infrastructure based on multi-level intermediate representation and its implementation method, which belongs to the field of compiler design and code optimization technology. The method includes: supporting unified access of different high-level language front-ends (such as C / C++, Java, Python, Rust) and hardware platform back-ends (such as x86, ARM), designing a multi-level intermediate representation (MSIR), decomposing the compilation process into a high-level intermediate representation (HIR) layer, a middle-level intermediate representation (MIR) layer, and a low-level intermediate representation (LIR) layer, a total of three layers of progressive IR, combining reversible conversion rules and cross-level optimization coordination mechanisms, gradually converting high-level languages ​​into low-level languages, and realizing a more convenient, intuitive and simple maintenance process for the entire structure and its carried data. Therefore, it not only improves the reusability of the code, but also has good ecological openness.

[0191] Experiments show that this method reduces the number of IR instructions by an average of 12% on the LLVM test set, improves data flow analysis speed by approximately 23%, and significantly reduces JIT compilation latency. By implementing "optimized rollback" through reverse conversion, it improves debugging efficiency and shortens error location time by over 40%. This method is suitable for real-time compilation, heterogeneous hardware adaptation, and multi-language mixed programming and static optimization scenarios, significantly reducing compiler development and maintenance costs.

[0192] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should all be covered by the scope of protection of the present invention.

Claims

1. A compiler infrastructure based on multi-order intermediate representation and its implementation method, characterized in that: It supports unified access to different high-level language front-ends (such as C / C++, Java, Python, and Rust) and hardware platform back-ends (such as x86 and ARM). By stripping away the correlation between high-level and low-level languages, it designs a multi-level intermediate representation (MSIR) and decomposes the compilation process into three layers: the high-level intermediate representation (HIR), the middle-level intermediate representation (MIR), and the low-level intermediate representation (LIR). This progressive IR combines reversible conversion rules and cross-level optimization coordination mechanisms to gradually convert high-level languages ​​into low-level languages.

2. The method according to claim 1, wherein: The support for unified access to different high-level language front-ends (such as C / C++, Java, Python, and Rust) eliminates the dependencies between high-level languages. During front-end processing, the source code input by the user (such as C / C++, Java, Python, Rust, or any other high-level language) is parsed and language-specific features (such as syntactic sugar and language-specific structures) are stripped from the source code to ensure that source codes in different languages ​​can be converted into standard HIR representation.

3. The method according to claim 1, wherein: The multi-level intermediate representation MSIR includes three levels of progressive intermediate representation layers, a high-level intermediate representation HIR layer, a medium-level intermediate representation MIR layer, and a low-level intermediate representation LIR layer, each level having a different abstraction level and optimization goal; Multi-level intermediate representation technology, that is, starting from a high-level intermediate representation, through step-by-step optimization and transformation, gradually transitioning to a lower-level intermediate representation. As a result, the higher-level intermediate representation is closer to the high-level language and closer to the characteristics of the high-level language; the lower-level intermediate representation is closer to the characteristics of the low-level language. The HIR layer focuses on semantic preservation and global optimization; the MIR layer completes the connection between mid-level optimization and SSA management; and the LIR is responsible for the generation of the final low-level code that is hardware-independent.

4. The method according to claim 3, wherein: The HIR layer focuses on semantic preservation and global optimization; The HIR layer retains high-level semantics, such as loop structures and function calls; and supports inter-procedural optimizations, such as function inlining, loop unrolling, dependency analysis, and alias analysis.

5. The method according to claim 3, wherein: The MIR layer completes the connection between mid-order optimization and static single assignment (SSA) management; The MIR layer introduces optimizations for basic operations (such as arithmetic simplification and strength reduction); application instruction-level optimizations (such as constant folding and dead code elimination); Apply some interprocedural optimizations (such as copy propagation, loop invariant extraction, and common subexpression elimination); convert between non-SSA and SSA.

6. The method according to claim 3, wherein: The LIR layer is responsible for generating the final low-level code that is hardware-independent.

7. The LIR layer completes the allocation of physical registers / memory locations; based on masking the instruction set characteristics of the underlying target hardware (such as x86, ARM), it completes the generalization and standardization of the low-level language form; and performs low-level optimizations (instruction scheduling, pipeline filling, branch prediction optimization, peephole optimization) to provide optimized generalized input for the final low-level language generation.

8. The method according to claim 3, wherein: The layers of the three-level progressive intermediate representation can be further subdivided into more levels of progressive IR; In the actual implementation process, the HIR layer, MIR layer and LIR layer can be divided into more levels of hierarchical HIR, MIR and LIR respectively according to the granularity of the functional division of specific modules, so as to ensure that each layer / level of IR only focuses on specific optimizations, thereby reducing the complexity of the compiler infrastructure.

9. The method according to claim 1, wherein: The reversible transformation rules (RTR) are designed to ensure that the transformation between different order IRs (e.g., HIR → MIR → LIR) is bidirectional and lossless, allowing the structure of the higher-order IR to be recovered from the lower-order IR. Reversible transformation rules strip away language features during forward transformation (e.g., HIR→MIR expands syntax sugar); during reverse transformation, they restore the original structure (e.g., MIR→HIR restores loop parameterization markers); Among them, the reversible conversion rule is implemented through the following technologies: Metadata preservation: save the structural information of the original IR during conversion (such as parameter mapping table, code snapshot before syntax sugar expansion); Bidirectional converter: implements forward (e.g. HIR→MIR) and reverse (e.g. MIR→HIR) conversion functions to ensure the reversibility of the conversion process; Reversible transformation rules are used in MSIR debugging and backtracing. When errors are found in low-level IR, the higher-level IR can be restored to locate the problem. Therefore, reversible transformation rules have good optimization flexibility and support strategies for readjusting the higher-level IR after cross-level optimization (such as loop transformation).

10. The method according to claim 1, wherein: The cross-level optimization collaborative mechanism is to transmit optimization-related information between different-level IRs to drive collaborative optimization strategies; The cross-level optimization coordination mechanism includes: Feedback mechanism: When the low-level IR detects a constraint condition (such as insufficient registers) in the high-level IR, it triggers the optimization rework of the high-level IR; Tagging mechanism: High-level IR passes semantic tags (such as loop patterns) to low-level IR to drive instruction generation strategy; The cross-level optimization collaboration mechanism passes information through metadata channels, that is, through shared data structures; The goal of applying the cross-level optimization coordination mechanism is to maximize the optimization effect by utilizing information from different levels of IR, and to optimize the global compiler infrastructure; dynamically adjust the optimization strategy according to the actual operating environment (such as target machine resources) to improve dynamic resource adaptation.

11. The method according to claim 1, wherein: The unified access of different hardware platform backends (such as x86 and ARM) strips away the dependency of low-level languages; At the LIR layer, it provides corresponding functions for operations and optimizations related to the hardware platform (such as allocating physical registers / memory locations), but does not perform related specific work; it completes all processing unrelated to the low-level language, and generates an intermediate representation that can fully express the semantics of the low-level language but is unrelated to the specific low-level language, providing optimized, generalized, and standardized input for the final low-level language generation.

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