Microinstruction operation method and processor

Abstract

The embodiment of the invention provides a microinstruction operation method and a processor. The method comprises the steps that the length of a to-be-inserted microinstruction sequence is determined; determining a target cache group according to the cache length of each cache group in the microinstruction cache; wherein the cache length of the target cache group is greater than or equal to the length of the microinstruction sequence; under the condition that the idle cache line exists in the target cache group, inserting the microinstruction sequence into the idle cache line; and under the condition that the idle cache line does not exist in the target cache group, determining a target cache line from the target cache group according to a target algorithm, and replacing the storage content in the target cache line with the microinstruction sequence. The cache length corresponding to each cache group in the microinstruction cache is set to be different, and the proper cache group is selected according to the sequence length of the microinstruction sequence, so that the waste of storage space is avoided, and the utilization rate of the microinstruction cache is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a microinstruction operation method and a processor. Background Art

[0002] High-performance microprocessors utilize superscalar technology and feature multiple execution pipelines, fetching, decoding, and executing multiple instructions from the instruction stream each cycle. Each instruction is broken down into multiple microinstructions for execution, and the microinstruction cache stores the decoded microinstructions. When the processor performs a value fetch operation, it first queries the microinstruction cache. If the query is in the microinstruction cache, the microinstruction is retrieved directly from the cache. If the relevant microinstruction is not stored in the cache, the instruction cache is used to fetch the instruction.

[0003] Microinstruction caches are widely used in modern processors, but the capacity of microinstruction caches is usually smaller than that of instruction caches. When faced with heavy loads, the miss rate of microinstruction caches is high. In addition, microinstruction caches will produce holes when storing microinstructions, resulting in a large amount of storage space not being effectively utilized. Summary of the Invention

[0004] The embodiments of the present application provide a microinstruction operation method and a processor, which can improve the utilization rate of the microinstruction cache.

[0005] In a first aspect, an embodiment of the present application discloses a microinstruction operation method, the method comprising:

[0006] Determining the length of a microinstruction sequence to be inserted; the microinstruction sequence includes at least one microinstruction;

[0007] Determining a target cache group according to the cache length of each cache group in the microinstruction cache; wherein the cache length of the target cache group is greater than or equal to the length of the microinstruction sequence;

[0008] In a case where there is a free cache line in the target cache group, inserting the microinstruction sequence into the free cache line;

[0009] In the case that there is no free cache line in the target cache group, a target cache line is determined from the target cache group according to a target algorithm, and the storage content in the target cache line is replaced with the microinstruction sequence.

[0010] In a second aspect, an embodiment of the present application discloses a processor, comprising:

[0011] Decoder, which decodes instructions into microinstructions;

[0012] a multi-way set-associative microinstruction cache wherein at least two cache ways have microinstruction cache lines of different lengths;

[0013] A microinstruction cache filler is configured to form a microinstruction sequence from the decoded microinstructions according to a termination condition; and to fill the microinstruction sequence into a cache way with a minimum available length in the microinstruction cache according to the length of the microinstruction sequence.

[0014] The embodiments of the present application include the following advantages:

[0015] The microinstruction operation method provided by the present application can determine the length of the microinstruction sequence to be inserted; determine the target cache group based on the cache length of each cache group in the microinstruction cache; wherein the cache length of the target cache group is greater than or equal to the length of the microinstruction sequence; if there is a free cache line in the target cache group, insert the microinstruction sequence into the free cache line; if there is no free cache line in the target cache group, determine the target cache line from the target cache group according to the target algorithm, and replace the storage content in the target cache line with the microinstruction sequence. By setting the cache length corresponding to each cache group in the microinstruction cache to be different, the appropriate cache group is selected according to the sequence length of the microinstruction sequence, thereby avoiding waste of storage space and improving the utilization rate of the microinstruction cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 It is a flow chart of the steps of an embodiment of a microinstruction operation method of the present invention;

[0018] Figure 2 It is a schematic structural diagram of a cache line of the present invention;

[0019] Figure 3 It is a schematic diagram of the structure of another cache line of the present invention. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] Method Example

[0022] Reference Figure 1, shows a flowchart of a microinstruction operation method embodiment of the present invention, the method may specifically include the following steps:

[0023] Step 101: Determine the length of the microinstruction sequence to be inserted;

[0024] Step 102: Determine a target cache group based on the cache lengths of the respective cache groups in the microinstruction cache; the cache length of the target cache group is greater than or equal to the length of the microinstruction sequence;

[0025] Step 103: If there is a free cache line in the target cache group, insert the microinstruction sequence into the free cache line;

[0026] Step 104 : If there is no free cache line in the target cache group, determine a target cache line from the target cache group according to a target algorithm, and replace the storage content in the target cache line with the microinstruction sequence.

[0027] The microinstruction operation method provided in this application can be used to insert microinstructions into corresponding locations in the microinstruction cache. A microinstruction is the smallest unit of operation executed by a processor and corresponds to the hardware operations in the processor. For example, register data transfer, arithmetic and logical operations, and control signal generation. The microinstruction cache refers to the storage unit within the processor used to store microinstructions, which is used to accelerate the reading and execution of microinstructions.

[0028] Among them, machine instructions are decoded to obtain microinstructions. A machine instruction can usually be divided into at least one microinstruction, and a microinstruction sequence can correspond to multiple machine instructions. For example, a machine instruction is "ADD R1, R2"; it can be divided into microinstruction 1: read the value of R1 from the register file to ALU input port A; microinstruction 2: read the value of R2 from the register file to ALU input port B; microinstruction 3: control the ALU to perform addition operations; microinstruction 4: write the ALU result to the target register. In addition, a machine instruction cache line corresponds to multiple microinstruction cache lines, and the content stored in each microinstruction cache line corresponds to a subset of a machine instruction cache line.

[0029] It's important to note that the microinstruction cache typically uses a set-associative storage organization. Specifically, the microinstruction cache is divided into multiple groups, each containing at least one way, and each way corresponding to a microinstruction cache line. A microinstruction cache line is the smallest unit of data storage in the cache. A "way" represents the number of parallel storage locations within a set-associative cache. A set contains multiple ways, each of which can store a cache line. For example, in a 4-way set-associative cache, each group has 4 ways.

[0030] In an embodiment of the present application, the cache lengths corresponding to the cache lines in the microinstruction cache are different. In the present application, a cache group refers to at least one way forming a cache group, and the cache lengths of the cache lines corresponding to each way are the same. Exemplarily, an 8-way group-associated microinstruction cache refers to a situation where each group in the microinstruction cache contains 8 ways. Furthermore, 1-way and 2-way can form a cache group, 3-way and 4-way form a cache group, and 5-way, 6-way, 7-way, and 8-way form a cache group. Among them, the cache lengths corresponding to the various cache groups are different, that is, the cache lengths of the cache lines corresponding to the ways in each group are different. It is understandable that when the cache lengths of the cache lines are different, the number of microinstructions that the cache lines can store is also different. The microinstruction cache lines can store tags, metadata, immediate fields, and microinstruction fields. The tags are used to identify the addresses corresponding to the cache lines, and the metadata are used to identify the status information of the cache lines. As Figure 2 The diagram below shows the structure of a microinstruction cache line, which can store up to 4 microinstructions and 2 immediate values. Figure 3 The figure shows a schematic diagram of the structure of another microinstruction cache line, which can store up to 2 microinstructions and 1 immediate value.

[0031] Among them, the cache length refers to the number of microinstructions that can be stored in the cache line, and the length of the microinstruction sequence refers to the number of microinstructions contained in the microinstruction sequence. Therefore, the two can be directly compared. After determining the sequence length of the microinstruction sequence, the sequence length of the microinstruction sequence is matched with the cache length corresponding to each cache group in turn, and the cache group with a cache length greater than or equal to the sequence length of the microinstruction sequence is determined as the candidate cache group. A target cache group can be randomly determined from at least one candidate cache group; or a target cache group can be determined from at least one candidate cache group according to a selection strategy, for example, the number of free cache lines in the target cache group is obtained, and the cache group with a large number of free cache lines is preferentially selected as the target cache group. There is no need to replace the content already stored in the cache, avoiding the need to obtain from the instruction cache when accessing data later, thereby improving the efficiency of obtaining instructions.

[0032] It should be noted that a free cache line refers to a cache line that does not store any valid content. The state of a cache line can be indicated by setting the corresponding valid bit for the microinstruction cache line. A microinstruction cache line is the smallest management unit of the microinstruction cache and is typically managed as a whole line. When a microinstruction cache line is marked as free, it means that the microinstruction cache line has not been allocated to store any data or instructions. If the valid bit corresponding to a microinstruction cache line is "invalid," the contents of the entire cache line are considered invalid, meaning the cache line is free. If the valid bit corresponding to a microinstruction cache line is "valid," the contents of the entire cache line are considered valid, meaning the cache line is not free. After data or instructions are written to the cache line, the valid bit of the cache line switches to "valid." For example, a microinstruction cache line contains at least one microinstruction slot. If data or instructions occupy some of the microinstruction slots in the cache line, the valid bit of the cache line is switched to "valid," even if the remaining microinstruction slots are unused.

[0033] Wherein, when there is only one free cache line in the target cache group, the microinstruction sequence is directly inserted into the only free cache line; when there is at least one free cache line in the target cache group, since the cache length corresponding to each cache line in the target cache group is the same, the microinstruction sequence is inserted into any free cache line. When there is no free cache line in the target cache group, that is, each cache line in the target cache group is written with data or microinstructions, the target cache line can be determined from the cache group for replacement or overwriting based on at least one of the write order of the microinstruction sequence corresponding to each cache line, the access status of the microinstruction sequence, and the occupancy status of the microinstruction sequence in the cache line. For example, according to the first-in-first-out principle, the cache line in which the microinstruction sequence is written earliest is determined as the target cache line.

[0034] In an embodiment of the present application, the length of a microinstruction sequence to be inserted is determined; based on the cache lengths of the respective cache groups in the microinstruction cache, a target cache group having a cache length greater than or equal to the sequence length of the microinstruction sequence is determined; if there is a free cache line in the target cache group, the microinstruction sequence is inserted into the free cache line; if there is no free cache line in the target cache group, a target cache line is determined from the target cache group according to a target algorithm, and the stored content in the target cache line is replaced with the microinstruction sequence. Since the cache lengths corresponding to each cache group in the microinstruction cache are diverse, an appropriate cache group can be selected based on the sequence length of the microinstruction sequence, thereby avoiding waste of storage space and improving the utilization rate of the microinstruction cache.

[0035] Optionally, the method further includes:

[0036] Step S11, determining the maximum cache length of a cache line in the microinstruction cache according to the issue width of the processor;

[0037] Step S12: determining the sequence length of the microinstruction sequences in each program running in the processor, grouping the microinstruction sequences according to the sequence length, and determining the proportion of the microinstruction sequences contained in each microinstruction sequence group in all the microinstruction sequences;

[0038] Step S13: determining the cache group configuration information according to the maximum cache length, the sequence lengths and proportions corresponding to the microinstruction sequence groups;

[0039] Step S14: configuring a cache group in the microinstruction cache according to the cache group configuration information.

[0040] The issue width refers to the total number of microinstructions issued by the processor in one clock cycle. Therefore, a microinstruction sequence can contain at most the total number of microinstructions in the microinstruction cache, and the maximum cache width of a cache line does not exceed the issue width. Determining the maximum cache length of a cache line in the microinstruction cache based on the issue width can prevent cache lines from being too long. This can prevent microinstruction sequences from being long enough to occupy the entire cache line, which would otherwise cause holes in the cache line and waste storage space.

[0041] Cache group configuration information is used to uniquely identify cache groups within the microinstruction cache and indicate how storage resources are allocated within the microinstruction cache to form cache groups. It should be noted that the configuration of cache groups within the microinstruction cache in this application requires statistical analysis of a large number of programs, summarizing the sequence lengths and proportion patterns of microinstruction sequences to determine how to divide cache groups within the microinstruction cache. For example, after statistical analysis of a large number of programs, it is determined that microinstruction sequences containing two or three microinstructions have a relatively low proportion, followed by microinstruction sequences containing four, five, and six microinstructions, and the highest proportion is microinstruction sequences containing seven and eight microinstructions. The cache length corresponding to each cache group should be greater than or equal to the sequence length of the microinstruction sequence. Therefore, the microinstruction cache can be divided into three corresponding intervals: a cache group that can store a maximum of three microinstructions, a cache group that can store a maximum of six microinstructions, and a cache group that can store a maximum of eight microinstructions. Furthermore, the number of cache lines and the proportion of microinstruction sequences of each length type within the three cache groups remain consistent. For example, the number of cache lines contained in the cache group that can store up to 3 microinstructions has the lowest proportion in the microinstruction cache, the number of cache lines contained in the cache group that can store up to 3 microinstructions has the second highest proportion in the microinstruction cache, and the number of cache lines contained in the cache group that can store up to 8 microinstructions has the highest proportion in the microinstruction cache.

[0042] In an embodiment of the present application, the maximum cache length of the cache line in the microinstruction cache is determined according to the launch width of the processor; the sequence length of the microinstruction sequence in each program running in the processor is determined, and the microinstruction sequences are grouped according to the sequence length, and the proportion of the microinstruction sequences contained in each microinstruction sequence group in all microinstruction sequences is determined; the cache group configuration information is determined according to the maximum cache length, the sequence length and proportion corresponding to each microinstruction sequence group; and the cache group is configured in the microinstruction cache according to the cache group configuration information. By statistically analyzing the microinstruction sequences in a large number of programs and determining how to allocate storage resources in the microinstruction cache according to the number and proportion of microinstruction sequences, at least one cache group with different cache lengths is formed, and different options are provided when inserting the microinstruction sequence, so that the microinstruction sequence can be inserted into the appropriate cache group, thereby improving the utilization of storage resources.

[0043] Optionally, determining the cache group configuration information according to the maximum cache length, the sequence length, and the proportion of microinstruction sequences corresponding to the sequence length includes:

[0044] Step S21: determining a cache length corresponding to a cache group corresponding to the microinstruction sequence group according to the sequence length of the microinstruction sequence group; the cache length is less than or equal to the maximum cache line length;

[0045] Step S22 : determining the number of cache lines in each cache group according to the proportion corresponding to the microinstruction sequence group and the total number of cache lines in the microinstruction cache.

[0046] It should be noted that the microinstruction sequences are grouped according to the sequence length of the microinstructions, and the sequence length of each microinstruction sequence group is different. One microinstruction sequence group corresponds to one cache group, and the number of microinstructions in the microinstruction sequence group is determined as the cache length of the cache group. In the case that the sequence length of a microinstruction sequence group in at least one microinstruction sequence group is equal to the maximum cache line length, the sequence length of each microinstruction sequence group is directly determined as the cache length corresponding to each cache group. For example, the maximum cache line length is 8, and the sequence lengths corresponding to each microinstruction sequence group are 3, 5, 7, and 8 respectively. Therefore, the cache length corresponding to each cache group is also 3, 5, 7, and 8. In the case that the sequence length of a microinstruction sequence group in at least one microinstruction sequence group is not equal to the maximum cache line length, the cache length corresponding to each cache group is determined based on the sequence length of each microinstruction sequence group and the maximum cache line length. For example, the maximum cache line length is 8, and the sequence lengths corresponding to each microinstruction sequence group are 2, 4, 5, and 7 respectively. Therefore, the cache lengths corresponding to each cache group can be set to 2, 4, 5, and 7, or the cache lengths corresponding to each cache group can be set to 2, 4, 5, 7, and 8.

[0047] After determining the cache length of the cache group and the number of cache lines of the cache group, storage resources are allocated to the cache group in the microinstruction cache according to the cache length and the number of cache lines.

[0048] A multiplication operation is performed between the proportion of the microinstruction sequence group and the total number of cache lines in the microinstruction cache, and the number of cache lines in each cache group is determined based on the multiplication result. For example, if the multiplication result between the proportion of the microinstruction sequence group and the total number of cache lines is an integer, the multiplication result is directly determined as the cache length of the cache group corresponding to the microinstruction sequence group. If the multiplication result between the proportion of the microinstruction sequence group and the total number of cache lines is not an integer, the multiplication result is adjusted to an integer, and the proportion of the number of cache lines of each cache group in the microinstruction cache is ensured to be consistent or close to the proportion of each corresponding microinstruction sequence group. For example, the multiplication results can be rounded up or down. If the sum of the rounded-up multiplication results is greater than the total number of cache lines in the microinstruction cache, the number of cache lines of the cache group corresponding to the microinstruction sequence with the lower proportion is reduced. If the sum of the rounded-down multiplication results is less than the total number of cache lines in the microinstruction cache, the number of cache lines of the cache group corresponding to the microinstruction sequence with the higher proportion is increased. Alternatively, the multiplication results corresponding to the microinstruction sequence groups with a high proportion can be rounded down, and the multiplication results corresponding to the microinstruction sequence groups with a low proportion can be rounded up, as long as the final proportion of the number of cache lines of each cache group in the microinstruction cache is basically consistent with the proportion of the corresponding microinstruction sequence groups.

[0049] For example, the total number of cache lines in the microinstruction cache is 10, there is a microinstruction sequence group A with a sequence length of 7, and a microinstruction sequence group B with a sequence length of 5, group A accounts for 60% of all microinstruction sequences, and group B accounts for 40% of all microinstruction sequences. Therefore, the number of cache lines of the cache group corresponding to group A is 6, and the number of cache lines of the cache group corresponding to group B is 4. The total number of cache lines in the microinstruction cache is 7, there is a microinstruction sequence group A with a sequence length of 7, and a microinstruction sequence group B with a sequence length of 5, group A accounts for 70% of all microinstruction sequences, and group B accounts for 30% of all microinstruction sequences. The calculated multiplication results are 4.9 and 2.1 respectively. The results of each multiplication operation are rounded up to 5 and 3, and the total is 8, which exceeds the total number of cache lines. The number of rows of group B with a low proportion is reduced, that is, 3 is reduced to 2. The total number of cache lines in the microinstruction cache is 11. There are microinstruction sequence group A with a sequence length of 7, microinstruction sequence group B with a sequence length of 4, and microinstruction sequence group C with a sequence length of 2. Group A accounts for 50% of the total microinstruction sequence, group B accounts for 30%, and group C accounts for 20%. The multiplication results are 5.5, 3.3, and 2.2, respectively. The multiplication result corresponding to group A, which has a higher proportion, is rounded down to 5, while the multiplication results corresponding to groups B and C, which have lower proportions, are rounded up to 4 and 3.

[0050] In an embodiment of the present application, the cache length corresponding to the cache group corresponding to the microinstruction sequence group is determined based on the sequence length of the microinstruction sequence group; wherein the cache length corresponding to each cache group is less than or equal to the maximum cache line length; and the number of cache lines in each cache group is determined based on the proportion corresponding to the microinstruction sequence group and the total number of cache lines in the microinstruction cache. Specifically, the sequence length of the microinstruction sequence group can be determined as the cache length corresponding to each cache group, and the number of cache lines in the cache group can be determined based on the proportion corresponding to each microinstruction sequence group, ensuring that the proportion of the number of cache lines of each cache group in the microinstruction cache is basically consistent with the proportion of the corresponding microinstruction sequence group, thereby improving the utilization rate of the storage space in the microinstruction cache.

[0051] Optionally, determining the target cache group according to the cache lengths of the respective cache groups in the microinstruction cache includes:

[0052] Step S31: Determine the priority of each cache group according to the cache length corresponding to each cache group; the smaller the cache length corresponding to the cache group, the higher the priority corresponding to the cache group;

[0053] Step S32: Determine a target cache group according to the priorities corresponding to the respective cache groups; the target cache group is the cache group with the highest priority.

[0054] It should be noted that, by comparing the microinstruction sequence length with the cache length corresponding to each cache group, at least one candidate cache group whose cache length is greater than or equal to the sequence length can be determined. Since the cache length corresponding to each cache group is different, the priority corresponding to at least one candidate cache group can be determined according to the cache length from short to long. The shorter the cache length corresponding to the cache length, the higher the priority corresponding to the candidate cache group. The priority setting rule is to ensure that the microinstruction sequence is inserted into the cache group whose cache length is closest to the sequence length, to avoid the formation of more holes after the insertion of the cache line, resulting in a waste of storage resources.

[0055] For example, the length of the microinstruction sequence to be inserted is 4, and there are 4 cache groups in the microinstruction cache, namely cache group a with a cache length of 2, cache group b with a cache length of 4, cache group c with a cache length of 6, and cache group d with a cache length of 8. After matching the microinstruction sequence length with each cache group, cache groups b, c, and d are determined as candidate cache groups. According to the cache length corresponding to the candidate cache groups, the priority order of cache groups b, c, and d is determined as follows: cache group b has the highest priority, cache group c has the second highest priority, and cache group d has the lowest priority. Therefore, the microinstruction sequence is preferentially inserted into cache group b.

[0056] In the embodiment of the present application, the priorities of the cache groups are determined according to the cache lengths corresponding to the cache groups, from short to long. The smaller the cache length of the cache group, the higher the priority of the cache group. The cache group with the highest priority is determined as the target cache group. This ensures that the microinstruction sequence is inserted into the cache group with the cache length closest to the sequence length, avoiding the formation of more holes in the cache line after insertion, which leads to waste of storage resources, and improving the utilization of the microinstruction cache.

[0057] Optionally, when there is no free cache line in the target cache group, determining the target cache line from the target cache group according to a target algorithm includes:

[0058] Step S41: When there is no free cache line in the target cache group, sort the cache lines in the target cache group according to the access frequency corresponding to the storage content of each cache line in the target cache group to obtain a sorting result;

[0059] Step S42: Determine a target cache line from the target cache group according to the sorting result.

[0060] Specifically, when a new microinstruction sequence needs to be written to the target cache group, if all cache lines in the target cache group are occupied, a cache line needs to be selected from the target cache group for replacement. All cache lines in the target cache group are sorted according to the access frequency of the content stored in each cache line. From the sorting results, the cache line with the lowest access frequency is selected as the replacement target, that is, microinstruction sequences with low usage frequency are eliminated first. By eliminating microinstruction sequences in cache lines with low frequency access in the microinstruction cache, microinstruction sequences with high frequency access are retained in the microinstruction cache, thereby improving the cache hit rate.

[0061] It should be noted that the access frequency can be determined by counting the total number of accesses to each cache line since the microinstruction sequence was loaded, or counting the number of accesses to each cache line within a preset time period, such as the past 100 clock cycles.

[0062] For example, the target cache group contains three occupied cache lines. Cache line 1 stores microinstruction sequence 1, which has been accessed twice; cache line 2 stores microinstruction sequence 2, which has been accessed five times; and cache line 3 stores microinstruction sequence 3, which has been accessed one time. Sorting the cache line by access count from lowest to highest yields cache line 3, cache line 1, and cache line 2. The cache line with the fewest access counts is selected, meaning cache line 3 is determined as the target cache line.

[0063] Optionally, in an embodiment of the present application, cache lines may be sorted based on the time interval between the most recently accessed microinstruction sequence and the time node where a new microinstruction sequence is required to be inserted, with the cache line with the longest time interval between the time node where the new microinstruction sequence is required to be inserted being preferentially selected as the target cache line. In other words, cache lines that have not been accessed for the longest time are preferentially eliminated.

[0064] In an embodiment of the present application, if there are no free cache lines in the target cache group, the cache lines in the target cache group are sorted from low to high according to the access frequency corresponding to the storage content of each cache line in the target cache group; based on the sorting result, the cache line with the lowest access frequency in the target cache group is determined as the target cache line. By replacing the storage content in the target cache line with the lowest access frequency, the frequently accessed microinstruction sequence is retained in the microinstruction cache, thereby improving the cache hit rate.

[0065] Optionally, before determining the length of the microinstruction sequence to be inserted, the method further includes:

[0066] Step S51: Decode the instruction to be decoded to obtain at least one microinstruction;

[0067] Step S52: Accumulate the at least one microinstruction, and when a termination condition is met, stop accumulating to generate a microinstruction sequence.

[0068] The termination condition includes at least one of the following: the number of microinstructions reaches a preset threshold, and the microinstruction is a jump instruction.

[0069] Specifically, the machine instructions to be executed (such as ADD instructions, MOV instructions) are disassembled into lower-level microinstructions, and each machine instruction may correspond to one or more microinstructions. The decoded microinstructions are temporarily stored in order to form a microinstruction sequence. When the number of microinstructions reaches a preset threshold (for example, a maximum of 4 microinstructions are accumulated), or a jump microinstruction (such as JMP, CALL, etc.) is encountered, the accumulation of the current sequence needs to be terminated in advance because the jump will change the execution process. By dynamically generating a microinstruction sequence, the pipeline efficiency is optimized and the pauses caused by dependencies between instructions are reduced. Among them, the sequence length is limited to prevent resource overflow (such as cache capacity or scheduling restrictions). When encountering a JMP, CALL or branch instruction, the execution path of subsequent instructions may change, and the current sequence needs to be ended.

[0070] For example, the termination condition is that each microinstruction sequence contains at most three microinstructions. The instruction sequence to be decoded includes instruction 1: "MOV EAX, [MEM1]"; instruction 2: "ADD EAX, EBX"; instruction 3: "SUB ECX, 1"; and instruction 4: "JNZLOOP". Instruction 1 is decoded into two microinstructions: "LOAD [MEM1] → TEMP" and "STORE TEMP → EAX". The current microinstruction sequence length is 2. Instruction 2 is decoded into three microinstructions: "LOAD EAX → TEMP1", "LOAD EBX → TEMP2", and "EXECUTE ADD TEMP1, TEMP2 → TEMP3". The current microinstruction sequence length is 2 + 3 = 5 (exceeding the threshold of 3). Because the length exceeds the threshold, the first three microinstructions are submitted to form a sequence, and the remaining two are placed in a new sequence.

[0071] For example, the termination condition is encountering a jump microinstruction. The instruction sequence to be decoded is: Instruction 1: "MOV EAX, 5", Instruction 2: "CMP EAX, 0", Instruction 3: "JE EXIT", and Instruction 4: "ADD EBX, EAX". Instruction 1 is decoded into one microinstruction: "STORE 5 → EAX", with a sequence length of 1. Instruction 2 is decoded into two microinstructions: "LOAD EAX → TEMP" and "COMPARETEMP, 0 → FLAGS", with a sequence length of 1 + 2 = 3. Instruction 3 is decoded into a jump microinstruction: "JUMP-IF-EQUAL FLAGS → EXIT". Because a jump instruction is encountered, the current microinstruction sequence is immediately committed, and the subsequent instruction ADD EBX, EAX must be processed in a new microinstruction sequence.

[0072] It should be noted that the termination condition may also be that the number of microinstructions reaches a preset threshold or a jump microinstruction is encountered. If either of these conditions is met, the microinstruction sequence can be submitted.

[0073] In an embodiment of the present application, the instruction to be decoded is decoded to obtain at least one microinstruction; the at least one microinstruction is accumulated, and when the number of microinstructions reaches a preset threshold or a jump microinstruction is encountered, the accumulation is stopped to generate a microinstruction sequence. By limiting the length of the microinstruction sequence, resource contention caused by a single sequence being too long is avoided, the parallelism of the pipeline is improved, and out-of-order execution optimization is achieved by splitting long sequences. The instruction execution path after the jump microinstruction may change, and the current pipeline needs to be cleared and re-fetched. Early termination of the sequence can reduce the performance loss caused by branch prediction errors.

[0074] In summary, the microinstruction operation method provided in the embodiment of the present application can determine the maximum cache length of the cache line in the microinstruction cache according to the issue width of the processor, determine the sequence length of the microinstruction sequence in each program running in the processor and group the microinstruction sequence according to the sequence length, and determine the proportion of the microinstruction sequence contained in each microinstruction sequence group in all microinstruction sequences. According to the sequence length and proportion of the microinstruction sequence, the number of cache groups in the microinstruction cache and the different cache lengths corresponding to the cache groups are determined. When it is necessary to insert a microinstruction sequence into the microinstruction cache, the sequence length of the microinstruction sequence and the cache length corresponding to each cache group are matched, and the cache group with a cache length greater than or equal to the sequence length is determined as the candidate cache group. Randomly or preferentially select a cache group with a short cache length from the candidate cache group as the target cache group. When there is an idle cache line in the target cache group, arbitrarily select a cache line to insert the microinstruction sequence; when there is no idle cache line in the target cache group, select the cache line with the lowest access frequency or the longest unaccessed cache line as the target cache line, and replace the microinstruction sequence with the target cache line. By setting cache groups with different cache lengths in the microinstruction cache, a cache group with a suitable length can be selected when inserting a microinstruction sequence, thereby improving the utilization of the microinstruction cache.

[0075] An embodiment of the present application provides a processor, comprising:

[0076] Decoder, used to decode instructions into microinstructions;

[0077] a multi-way set-associative microinstruction cache, wherein at least two cache sets have microinstruction cache lines of different lengths;

[0078] A microinstruction cache filler is used to form a microinstruction sequence from the decoded microinstructions according to a termination condition; and fill the microinstruction sequence into a target cache group with a minimum available length cache line in the microinstruction cache according to the length of the microinstruction sequence.

[0079] Optionally, the microinstruction cache filler selects a target cache line from a target cache group having a cache line with a minimum available length when replacing a cache line.

[0080] Optionally, selecting a target cache line from a target cache group having a cache line with a minimum available length includes:

[0081] When replacing cache lines, the microinstruction cache filler sorts the cache lines in the target cache group according to the access frequency to obtain a sorting result;

[0082] According to the sorting result, a target cache line is determined from the target cache group.

[0083] Optionally, the termination condition includes at least one of the following: the number of microinstructions obtained by decoding reaches a preset threshold, and the microinstruction is a jump microinstruction.

[0084] In an embodiment of the present application, a processor provided by the embodiment of the present application includes a multi-way group-connected microinstruction cache, wherein at least two cache groups have microinstruction cache lines of different lengths. Instructions are decoded into microinstructions; the decoded microinstructions are formed into a microinstruction sequence, and the microinstruction sequence is inserted into the cache group with the smallest available length, thereby improving the utilization of the microinstruction cache.

[0085] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor. When the program or instruction is executed by the processor, the various steps of the above-mentioned microinstruction operation method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0086] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned microinstruction operation method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0087] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A microinstruction operation method, characterized in that: The method comprises: Determining the length of a microinstruction sequence to be inserted; the microinstruction sequence includes at least one microinstruction; Determining a target cache group according to the cache length of each cache group in the microinstruction cache; wherein the cache length of the target cache group is greater than or equal to the length of the microinstruction sequence; In a case where there is a free cache line in the target cache group, inserting the microinstruction sequence into the free cache line; In the case that there is no free cache line in the target cache group, a target cache line is determined from the target cache group according to a target algorithm, and the storage content in the target cache line is replaced with the microinstruction sequence.

2. The method according to claim 1, characterized in that The method further comprises: Determining a maximum cache length of a cache line in the microinstruction cache according to an issue width of the processor; Determining the sequence length of the microinstruction sequences in each program running in the processor, grouping the microinstruction sequences according to the sequence length, and determining the proportion of the microinstruction sequences contained in each microinstruction sequence group in all the microinstruction sequences; Determining the cache group configuration information according to the maximum cache length, the sequence lengths and proportions corresponding to the microinstruction sequence groups; A cache group is configured in the microinstruction cache according to the cache group configuration information.

3. The method according to claim 2, characterized in that The configuration information includes a cache length and a number of cache lines of the cache group; determining the cache group configuration information based on the maximum cache length, the sequence length, and a proportion of microinstruction sequences corresponding to the sequence length includes: Determining a cache length corresponding to a cache group corresponding to the microinstruction sequence group according to a sequence length of the microinstruction sequence group; the cache length is less than or equal to the maximum cache line length; The number of cache lines in each cache group is determined according to the proportion corresponding to the microinstruction sequence group and the total number of cache lines in the microinstruction cache.

4. The method according to claim 1, wherein The step of determining the target cache group according to the cache lengths of the respective cache groups in the microinstruction cache comprises: Determine the priorities of the cache groups according to the cache lengths corresponding to the cache groups; the smaller the cache lengths corresponding to the cache groups, the higher the priorities corresponding to the cache groups; A target cache group is determined according to the priorities corresponding to the respective cache groups; the target cache group is the cache group with the highest priority.

5. The method according to claim 1, wherein The step of determining a target cache line from the target cache group according to a target algorithm when there is no free cache line in the target cache group includes: In the case that there is no free cache line in the target cache group, sorting the cache lines in the target cache group according to the access frequency corresponding to the storage content of each cache line in the target cache group to obtain a sorting result; According to the sorting result, a target cache line is determined from the target cache group.

6. The method according to claim 1, characterized in that Before determining the length of the microinstruction sequence to be inserted, the method further includes: Decoding the instruction to be decoded to obtain at least one microinstruction; Accumulating the at least one microinstruction, and stopping the accumulation when a termination condition is met, to generate a microinstruction sequence; The termination condition includes at least one of the following: the number of accumulated microinstructions reaches a preset threshold, and the microinstruction is a jump microinstruction.

7. A processor comprising: Decoder, used to decode instructions into microinstructions; a multi-way set-associative microinstruction cache, wherein at least two cache sets have microinstruction cache lines of different lengths; A microinstruction cache filler is used to form a microinstruction sequence from the decoded microinstructions according to a termination condition; and fill the microinstruction sequence into a target cache group with a minimum available length cache line in the microinstruction cache according to the length of the microinstruction sequence.

8. The processor according to claim 7, wherein: The microinstruction cache filler selects a target cache line from a target cache group having a cache line with a minimum available length during cache line replacement.

9. The processor according to claim 8, wherein: The selecting a target cache line in a target cache group having a cache line with a minimum available length comprises: When replacing cache lines, the microinstruction cache filler sorts the cache lines in the target cache group according to access frequency to obtain a sorting result; According to the sorting result, a target cache line is determined from the target cache group.

10. The processor according to claim 7, wherein: The termination condition includes at least one of the following: the number of microinstructions obtained by decoding reaches a preset threshold, and the microinstruction is a jump microinstruction.

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