Instruction processing method and device and related equipment

Abstract

The embodiment of the invention provides an instruction processing method and device and related equipment, and the method comprises the steps that in a low-speed mode, a to-be-executed instruction is obtained, and the to-be-executed instruction is an instruction corresponding to an exception of triggering an instruction execution mode to be switched from a high-speed mode to the low-speed mode; the instruction to be executed is decoded based on the first bit width, operation information and an address to be accessed corresponding to the instruction to be executed are determined, and the address to be accessed is used for accessing target data with the first bit width; splitting the to-be-accessed address into a plurality of sub-access addresses based on a second bit width, performing access and storage of sub-target data based on the sub-access addresses, and judging whether an access and storage exception is an error suppression exception when the access and storage exception exists; and after the sub-target data corresponding to all the sub-access addresses are accessed and stored, executing corresponding processing on target data formed by the accessed and stored sub-target data according to the operation information. According to the scheme, the instruction processing flow is simplified, and the instruction overhead is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an instruction processing method, apparatus, and related equipment. Background Art

[0002] During the execution of instructions, the processor uses an error suppression mechanism to handle memory access exceptions caused by memory access. However, the instruction processing flow under this error suppression mechanism is relatively complex and has a large instruction overhead.

[0003] Therefore, how to provide a technical solution to reduce instruction overhead has become a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0004] Embodiments of the present invention provide an instruction processing method, apparatus, and related devices to reduce instruction overhead.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides an instruction processing method, comprising:

[0007] In the slow mode, obtaining an instruction to be executed, where the instruction to be executed is an instruction corresponding to an exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode;

[0008] Decoding the instruction to be executed based on the first bit width to determine corresponding operation information and an address to be accessed; the address to be accessed is used to access target data having the first bit width, where the first bit width is the data bit width corresponding to executing the instruction to be executed in a fast mode;

[0009] Splitting the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determining whether the memory access exception is an error-suppressed exception;

[0010] After the sub-target data corresponding to all sub-access addresses are accessed, corresponding processing is performed on the target data formed by the accessed sub-target data according to the operation information.

[0011] Optionally, the slow mode is triggered based on a resynchronization failure, and when the resynchronization failure occurs, the slow mode flag is configured to be valid at the same time;

[0012] After decoding the instruction to be executed based on the first bit width and before splitting the address to be accessed into multiple sub-access addresses based on the second bit width, the method further includes:

[0013] Determining whether the slow mode flag is valid;

[0014] If yes, executing the step of splitting the to-be-accessed address into multiple sub-access addresses based on the second bit width; if no, entering the scheduling process of the fast mode;

[0015] After the first instruction in the slow mode is decoded, the slow mode flag is configured to be invalid.

[0016] Optionally, the step of obtaining the instruction to be executed is performed based on an instruction fetch unit, and the instruction fetch unit is used to execute an instruction fetch process in a fast mode;

[0017] The step of decoding the instruction to be executed based on the first bit width is performed by a decoding unit, and the decoding unit is used to perform a decoding process in a fast mode;

[0018] The step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information is performed based on an operation unit, and the operation unit is used to execute the operation process in the fast mode.

[0019] Optionally, splitting the to-be-accessed address into multiple sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error-suppressed exception when a memory access exception occurs include:

[0020] Determine a target sub-access address based on the second bit width and the target start address; the target sub-access address is used to indicate the currently determined sub-access address; wherein the target start address is the start address of the target sub-access address; when the operation is first executed, the target start address is the start address of the target access address; when the operation is not first executed, the target start address is the next address of the end address of the target sub-access address of the previous memory access process;

[0021] Based on the target sub-access address, accessing sub-target data corresponding to the target sub-access address; wherein the accessed sub-target data is used to store in a data buffer;

[0022] When a memory access exception exists, determining whether the memory access exception is an error suppression exception; the error suppression is used to indicate an exception that can be ignored;

[0023] If so, determining whether the current sub-target data is the end data of the target data; the end data is used to indicate the target data including the end address corresponding to the address to be accessed;

[0024] If so, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if not, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

[0025] Optionally, determining whether the memory access exception is an error-suppressed exception includes:

[0026] Calculating target error suppression information at a second bit width based on the error suppression information at the first bit width;

[0027] Based on the target error suppression information corresponding to the target sub-access address, it is determined whether the memory access exception is an error-suppressed exception.

[0028] Optionally, the determination of whether the current sub-target data is the end data of the target data is specifically to determine whether the target sub-access address contains the end address of the address to be accessed; if so, the current sub-target data is the end data of the target data; if not, the current sub-target data is not the end data of the target data.

[0029] Optionally, the bit width of the data buffer is the second bit width, and there are multiple data buffers; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is sequentially stored in each data buffer based on a preset order; the preset order corresponds to the data position of the sub-target data in the target data;

[0030] The performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information includes: splicing the target data based on the data order of the sub-target data; and performing corresponding processing based on the target data.

[0031] Optionally, the bit width of the data buffer is a first bit width; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is sequentially stored in different data bits of the data buffer based on a preset order, and the preset order corresponds to the data bit order of the sub-target data in the target data;

[0032] The performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information is specifically, performing corresponding processing based on the target data stored in the data buffer.

[0033] Optionally, the step of decoding the instruction to be executed based on the first bit width and determining the corresponding operation information and the address to be accessed further includes: storing the decoded operation information into a transmission queue, and configuring the operation information stored in the transmission queue to be in a dormant state;

[0034] In the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, operation information corresponding to the access is obtained after the transmit queue is awakened to perform access to the corresponding target sub-access address.

[0035] Optionally, the steps of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error-suppressed exception when a memory access exception occurs are performed based on the scheduling unit and the memory access unit;

[0036] The scheduling unit is configured with a slow mode state machine, the slow mode state machine is configured with an address storage unit, and the address storage unit is used to store the target starting address; the slow mode state machine is triggered to start based on a slow mode flag.

[0037] Optionally, the slow mode state machine is configured with the following states:

[0038] A waiting initialization state is used to indicate that the current slow mode state machine is in a state of waiting for initialization completion, wherein the initialization is to obtain operation information of the to-be-executed instruction from the transmit queue and configure the address information in the address storage unit as the starting address of the target access address;

[0039] A waiting wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the waiting wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information;

[0040] The address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein the address generation port is used to enable the address generator to generate a target sub-access address;

[0041] Among them, a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

[0042] In a second aspect, an embodiment of the present invention provides an instruction processing device, including:

[0043] An instruction acquisition module is used to acquire, in the slow mode, an instruction to be executed, where the instruction to be executed is an instruction corresponding to an exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode;

[0044] a decoding module, configured to decode the instruction to be executed based on a first bit width, and determine corresponding operation information and an address to be accessed; the address to be accessed is used to access target data having a first bit width, where the first bit width is a data bit width corresponding to executing the instruction to be executed in a fast mode;

[0045] a memory access scheduling module, configured to split the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, perform memory access of sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determine whether the memory access exception is an error-suppressed exception;

[0046] The processing module is used for performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information after the sub-target data corresponding to all the sub-access addresses are accessed.

[0047] Optionally, the instruction acquisition module is an instruction fetch unit, and the instruction fetch unit is used to execute an instruction fetch process in a fast mode;

[0048] The decoding module is a decoding unit, and the decoding unit is used to perform a decoding process in a fast mode;

[0049] The processing module is an operation unit, and the operation unit is used to execute the operation process in the fast mode.

[0050] Optionally, the scheduling memory access module includes a scheduling unit and a memory access unit; wherein, the scheduling unit is configured with a slow mode state machine; the slow mode state machine is configured with an address storage unit, and the address storage unit is used to store the target starting address, the target starting address is the starting address of the target sub-access address, and the target sub-access address is used to indicate the sub-access address currently being executed; the slow mode state machine is triggered to start based on the slow mode mark.

[0051] Optionally, the slow mode state machine is configured with the following states:

[0052] A waiting initialization state is used to indicate that the current slow mode state machine is in a state of waiting for initialization completion, wherein the initialization is to obtain operation information of the to-be-executed instruction from the transmit queue and configure the address information in the address storage unit as the starting address of the target access address;

[0053] A waiting wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the waiting wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information;

[0054] The address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein the address generation port is used to enable the address generator to generate a target sub-access address;

[0055] Among them, a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

[0056] In a third aspect, an embodiment of the present invention provides a processor comprising the instruction processing device as described in the second aspect.

[0057] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising the processor as described in the third aspect.

[0058] An embodiment of the present invention provides an instruction processing method, apparatus and related equipment, the instruction processing method comprising: in slow mode, obtaining an instruction to be executed, the instruction to be executed being an instruction corresponding to an exception that triggers the instruction execution mode to switch from fast mode to slow mode; decoding the instruction to be executed based on the first bit width, determining the corresponding operation information and address to be accessed, the address to be accessed being used to access target data having the first bit width; the first bit width being the data bit width corresponding to the execution exception instruction in fast mode; splitting the address to be accessed into multiple sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and, when a memory access exception exists, determining whether the memory access exception is an error-suppressed exception; after the sub-target data corresponding to all sub-access addresses are accessed, performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information.

[0059] It can be seen that in the embodiment of the present invention, in the slow mode, the instruction is still decoded based on the data bit width corresponding to the instruction to be executed in the fast mode, that is, the first bit width. Only in the memory access process, the address to be accessed for accessing the target data with the first bit width is split into multiple sub-access addresses to achieve small-grained memory access of sub-target data and corresponding error suppression judgment. That is, by reusing the instruction processing flow of the fast mode, the processing flow of the slow mode using the ucode method is avoided, the instruction processing flow is simplified, and the instruction overhead is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0061] Figure 1 This is an example diagram of an optional mode switch;

[0062] Figure 2 An optional flow chart of the instruction processing method provided in an embodiment of the present application;

[0063] Figure 3 An optional flowchart of step S120 provided in an embodiment of the present application;

[0064] Figure 4 Another optional flowchart of step S120 provided in an embodiment of the present application;

[0065] Figure 5 An optional block diagram of an instruction processing device provided by an embodiment of the present invention;

[0066] Figure 6 Another optional example diagram of the instruction processing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] As described in the background technology section, the instruction execution process of existing processors occupies a large amount of hardware resources, which affects the performance and scalability of the processor.

[0068] refer to Figure 1 An example diagram of an optional mode switching is shown. To improve the performance of the processor in executing instructions, for some complex instructions, such as instructions that support error suppression, the execution process includes two instruction processing modes: Fast mode and Slow mode. In Fast mode, instructions are executed based on a larger bit width, and the data to be processed corresponding to the instruction is processed based on the granularity defined by the bit width (the data to be processed corresponding to the bit width can be called the first data block, such as Figure 1 The solid line data block in the figure) has a faster data processing speed. When an exception occurs during the execution of a certain instruction, the system will enter the Slow mode. In this mode, the instruction with the exception (also called the exception instruction) is executed based on a smaller bit width (the data to be processed corresponding to this bit width can be called the second data block, such as Figure 1 The dotted data blocks in the figure, where the first data block is an integer multiple of the second data block, are used to identify the data with exceptions one by one at a smaller granularity. The system then determines whether the data to be processed with the exceptions has been suppressed based on the error suppression information. If so, the exception is ignored. If not, the exception handling process, such as an interrupt or instruction jump, is executed. The system can then switch from Slow mode to Fast mode, and continue executing subsequent instructions in Fast mode.

[0069] In an optional implementation, the Slow mode is executed based on a specific ucode (program sequence). The ucode can obtain instruction information corresponding to the exception instruction, and based on the corresponding instruction information, decode the exception instruction into multiple uops (micro-operations) with element (item, corresponding to the second data block) as an independent processing unit, and further perform scheduling, memory access and writing to a specific register (such as the ft register) in units of element, as well as error suppression judgment. After determining that there is no need to execute the exception handling process, the ucode is jumped out, switched to Fast mode, and subsequent processing is performed based on the data written in the specific register.

[0070] The inventors believe that executing the slow mode process in ucode requires configuring a corresponding ucode interface and implementing instruction splitting, scheduling, and memory access in ucode. This requires providing a complete instruction processing flow in ucode, which complicates the instruction processing flow under existing error suppression mechanisms and results in excessive instruction overhead. In particular, in one optional implementation, different ucodes may need to be configured for different types of instructions, further complicating mode switching and instruction processing and increasing the corresponding instruction overhead.

[0071] In view of this, an embodiment of the present invention provides an instruction processing method, apparatus and related equipment, the instruction processing method comprising: in slow mode, obtaining an instruction to be executed, the instruction to be executed being an instruction corresponding to an exception that triggers the instruction execution mode to switch from fast mode to slow mode; decoding the instruction to be executed based on the first bit width, determining the corresponding operation information and address to be accessed, the address to be accessed being used to access target data with the first bit width; the first bit width being the data bit width corresponding to the execution exception instruction in fast mode; splitting the address to be accessed into multiple sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and, when there is a memory access exception, determining whether the memory access exception is an error-suppressed exception; after the sub-target data corresponding to all sub-access addresses are accessed, performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information.

[0072] It can be seen that in the embodiment of the present invention, in the slow mode, the instruction is still decoded based on the data bit width corresponding to the instruction to be executed in the fast mode, that is, the first bit width. Only in the memory access process, the address to be accessed for accessing the target data with the first bit width is split into multiple sub-access addresses to achieve small-grained memory access of sub-target data and corresponding error suppression judgment. That is, by reusing the instruction processing flow of the fast mode, the processing flow of the slow mode using the ucode method is avoided, the instruction processing flow is simplified, and the instruction overhead is reduced.

[0073] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0074] Figure 2 This is an optional flow chart of the instruction processing method provided by an embodiment of the present invention. Figure 2 , the instruction processing method provided by the embodiment of the present invention includes the following steps.

[0075] Step S100: in the slow mode, obtaining a to-be-executed instruction, wherein the to-be-executed instruction is an instruction corresponding to an exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode;

[0076] When an exception occurs in fast mode, the instruction processing mode can be triggered to switch from fast mode to slow mode. The exception can be an exception generated in the access process of the data to be processed, such as an exception encountered in the access of avx512Kmask-type instructions, such as memory access out-of-bounds, data access permission mismatch, ECC check failure, etc., or other types of exceptions. Among them, the instruction corresponding to the exception that triggers the switch from fast mode to slow mode, that is, the instruction processed by the instruction processing flow corresponding to the exception, is used as the instruction to be executed.

[0077] This step can be performed based on the instruction fetch unit, that is, the instruction to be executed is obtained by using the instruction fetch unit. It is understood that when an exception occurs, the slow mode can re-fetch the instruction, thereby obtaining the last instruction that was not fully executed, that is, the instruction processed by the corresponding instruction processing flow when the exception occurred in the fast mode, and the re-fetched instruction is used as the instruction to be executed.

[0078] The acquisition of instructions to be executed based on the instruction fetch unit can be achieved by reusing the software and hardware in the fast mode, that is, the instruction fetch unit is used to execute the instruction fetch process in the fast mode without configuring a program sequence (ucode) for acquiring the corresponding instruction information and the corresponding hardware resources, thereby reducing the software and hardware overhead of the instructions.

[0079] In an optional implementation, when an exception occurs in fast mode, it cannot be determined whether it is a true fault (that is, an error that is not suppressed under the error suppression mechanism). At this time, a Resync Fault will be generated. The resync fault is used to indicate the re-fetch of instructions from the current PC (Program Counter), thereby indicating the instruction fetch process in slow mode.

[0080] In a specific example, the slow mode in the embodiment of the present invention can perform instruction fetching and decoding based on the instruction fetching and decoding process in the fast mode, and using a resynchronization fault to trigger the slow mode can appropriately adapt to the processing flow of the slow mode.

[0081] Furthermore, in the example of multiplexing the instruction fetch and decode process in fast mode for instruction fetch and decoding, in order to distinguish the mode in which the processing process is located so as to select the corresponding subsequent steps, the present application is also configured with a slow mode (also called MultiAgen) flag. In a specific example, the resynchronization fault is also used to trigger the configuration of the slow mode flag, that is, when the resynchronization fault occurs, the slow mode flag (for example, it can be called the MultiAgen flag) is configured to be valid at the same time, so that the first instruction after the resynchronization fault enters the slow mode scheduling process after instruction fetch and decoding under the instruction of the slow mode flag.

[0082] It is understandable that in fast mode, after instruction fetching and decoding, the scheduling process of fast mode can be further entered based on the indication of the slow mode flag.

[0083] It should be noted that, in a further optional example, the slow mode flag can also be configured to be invalid after the first instruction in slow mode is decoded (for example, the slow mode flag can be cleared) to avoid affecting subsequent instructions and other instructions running in parallel.

[0084] Step S110: Decoding the instruction to be executed based on the first bit width to determine the corresponding operation information and the address to be accessed;

[0085] The address to be accessed is used to access target data having a first bit width, where the first bit width is the data bit width corresponding to executing the instruction to be executed in the fast mode. In other words, the decoding stage in this step is still based on the decoding method in the fast mode, so there is no need to decode it into multiple small-granularity operation information, thereby reducing instruction overhead. The decoding is generally used to indicate that the instruction to be executed is decoded into a micro-operation (uop), and accordingly, the operation information is used to indicate instruction information of the micro-operation.

[0086] This step decodes the instruction to be executed based on the first bit width, and can be performed based on a decoding unit, wherein the decoding unit is used to execute the decoding process in the fast mode, that is, this step can reuse the decoding unit used to execute the decoding process in the fast mode. Furthermore, this step can also store the operation information corresponding to the decoding into the emission queue (issueQ), so as to execute the subsequent process based on the operation information of the emission queue. It is understandable that the operation information stored in the emission queue can be configured as a sleep state (sleep), that is, the operation information stored in the emission queue is configured as a sleep state to wake up in the subsequent process. In addition, the operation information may include identification information for indicating entry into slow mode.

[0087] It can be understood that the acquisition of instructions to be executed based on the decoding unit can be achieved by reusing the software and hardware in fast mode, without configuring the program sequence (ucode) for decoding the instructions to be executed and the corresponding hardware resources, thereby reducing the software and hardware overhead of the instructions.

[0088] Step S120: splitting the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and determining whether a memory access exception is an error-suppressed exception when the memory access exception occurs.

[0089] The address to be accessed is split based on the second bit width. For example, starting from the starting address of the address to be accessed, it can be split into sub-access addresses with a capacity of the second bit width, so that memory access is performed based on the split sub-access addresses. In the process of accessing the sub-target data based on the sub-access addresses, the memory access of the corresponding sub-access addresses can be performed in sequence based on the order of the sub-access addresses. The obtained sub-target data can be stored in a data buffer, that is, the obtained sub-target data is stored in a data buffer. The data buffer can be set in the memory access unit.

[0090] In the specific implementation, Figure 3 This is an optional flowchart of step S120 provided in an embodiment of the present application. Step S120 can implement memory access for each sub-target data by cyclically executing the following sub-memory access process. Specifically, the sub-memory access process includes:

[0091] Step S121: determining a target sub-access address based on the second bit width and the target start address;

[0092] The target start address is the start address of the target sub-access address, and the target start address may be the start address of the target access address, or the next address of the end address of the target sub-access address of the previous memory access process, that is, the sum of the target start address of the target sub-access address of the previous memory access process and the second bit width. It is understandable that when step S121 is executed for the first time, the target start address may be the start address of the target access address, and when step S121 is not executed for the first time, the target start address may be the sum of the target start address of the target sub-access address of the previous memory access process and the second bit width.

[0093] The target sub-access address is used to indicate the currently determined sub-access address, that is, one of the multiple sub-access addresses after the access address is split. Based on the target sub-access address, the sub-target data is accessed.

[0094] Among them, the step of determining the target sub-access address can be performed based on a scheduling unit, and the scheduling unit can configure an address storage unit (Payload), and the address storage unit can be used to store the target starting address, so as to calculate the target sub-access address based on the target starting address.

[0095] Step S122: Based on the target sub-access address, access the sub-target data corresponding to the target sub-access address;

[0096] After the target sub-access address is determined, a memory access to the target sub-access address may be performed to obtain sub-target data corresponding to the target sub-access address, thereby determining whether there is an abnormality in the corresponding memory access process.

[0097] In a specific implementation, the operation information corresponding to step S122 can be obtained after the transmit queue is awakened to perform access to the corresponding target sub-access address.

[0098] It is understood that if there is no memory access exception in the memory access process, the corresponding memory access operation is performed normally, and step S124 is executed. In a specific implementation, this step can further store the accessed sub-target data in a data buffer. The data buffer is a preset storage device for storing sub-target data, so that the corresponding target data is determined based on the respective target data stored in the data buffer.

[0099] The bit width of the data buffer can be the first bit width or the second bit width; if the data buffer is the second bit width, there can be multiple data buffers. In this step, each sub-target data can be stored in each data buffer in sequence based on a preset order, so that in subsequent steps, the target data can be spliced ​​together based on the data bits of the sub-target data; if the data buffer is the first bit width, each sub-target data can be stored in different data bits of the data buffer in sequence based on a preset order, and the preset order corresponds to the data bits of the sub-target data in the target data, so that the target data can be determined directly based on the data stored in the data buffer, without having to obtain the target data based on the splicing of the sub-target data.

[0100] It can be understood that if there is a memory access exception in the memory access process, corresponding exception information will be generated to indicate the exception type, context information, etc. of the memory access exception. Accordingly, when there is a memory access exception, step S123 is executed to determine whether the memory access exception is error suppressed.

[0101] Step S123: Determine whether the memory access exception is an error-suppressed exception;

[0102] In the error suppression mechanism, the error suppression is used to indicate an exception that can be ignored. In a specific example, the error suppression mechanism can be configured with error suppression information, which can be stored in a K register, for example. In a specific implementation, the error suppression information can include the type of memory access exception and whether the sub-target data where the exception occurs is a suppressed target. If so, the exception is ignored and step S124 is continued. If not, the exception handling process is executed.

[0103] In a specific implementation, the error suppression information under the first bit width is recorded based on the first bit width. Accordingly, in this step, the target error suppression information under the second bit width can be first calculated based on the error suppression information under the first bit width. Then, based on the target error suppression information corresponding to the target sub-access address, it is determined whether the memory access exception is an error-suppressed exception.

[0104] In an optional example, the calculation of the target error suppression information (ie, calculating the target error suppression information at the second bit width based on the error suppression information at the first bit width) can be performed during the initialization process or in this step.

[0105] Step S124: determining whether the current sub-target data is the end data of the target data;

[0106] It is understood that the sub-target data are accessed sequentially from the start address to the end address, and the end data is used to indicate the target data containing the end address corresponding to the address to be accessed. Accordingly, this step can specifically include determining whether the target sub-access address contains the end address of the address to be accessed; if so, the current sub-target data is the end data of the target data; if not, the current sub-target data is the end data of the non-target data.

[0107] Whether the sub-memory access process in this step should be looped is determined by determining whether the current sub-target data is the last data of the target data. If the current sub-target data is the last data of the target data, step S130 is executed; if the current sub-target data is the last data of the non-target data, step S121 is executed to start a new loop of the sub-memory access process.

[0108] In a further optional implementation, reference Figure 4 Another optional flowchart of step S120 provided in an embodiment of the present application is shown. Step S120 can also be executed based on a scheduling unit and a memory access unit. In a specific implementation, the scheduling unit can be configured with a slow mode state machine, wherein the address storage unit can be configured in the slow mode state machine so that the slow mode state machine sends an address to the memory access unit based on the second bit width, thereby, based on the control of the slow mode state machine, the memory access unit is used to realize memory access control of each sub-target data.

[0109] In a specific implementation, the slow mode state machine may be triggered to start based on a slow mode flag.

[0110] The slow mode state machine may be configured with the following states:

[0111] Idle state (IDLE): used to indicate that the current slow mode state machine is not used by any thread. The idle state can enter the waiting initialization state based on the trigger information used to trigger initialization.

[0112] Waiting for Initialization (WAIT_SQ): This indicates that the slow mode state machine is in a state where initialization is complete. Initialization involves obtaining operation information about pending instructions from the transmit queue and configuring the address information in the address storage unit as the starting address of the target access address, so that the target sub-access address corresponds to the starting address of the target access address for accessing the first sub-target data (first elemnt) of the target data. After initialization is complete, the state machine enters the Waiting for Wake-up state.

[0113] Waiting wake-up state (WAIT_LS): used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the memory access unit enters the waiting wake-up state after obtaining the target sub-access address and the corresponding operation information, and enters the address preemption state when the memory access unit starts a new round of the sub-memory access process; when the memory access unit determines that the current sub-target data is the end data of the target data, it enters the idle state.

[0114] Address preemption state (JAM): used to indicate that the current slow mode state machine is in the state of preparing to preempt the address generation port (AgPort). In the sub-memory access loop process, it is necessary to generate a target sub-access address based on the address generator (AGU, Address generate unit), and by preempting the address generation port, the address generator generates a target sub-access address (Agen, Address Generation, which is the effective memory access address calculated by the memory access instruction such as the load / store instruction) based on the current target starting address. It can be understood that while generating the target sub-access address, the next target starting address can also be determined, so as to further determine the corresponding target sub-access address in the next sub-memory access loop process. When the address generation port is successfully preempted, it enters the waiting wake-up state.

[0115] It can be understood that a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

[0116] In a specific sub-memory access cycle, the decoded operation information can be stored in a transmit queue and enter a dormant state. Simultaneously, the slow mode state machine is initialized based on the slow mode flag, causing the slow mode state machine to enter a wait-for-initialization state. In an optional example, the target error suppression information can be calculated during the initialization phase.

[0117] After the initialization process is completed, the system can enter the waiting state to wake up the operation information corresponding to the instruction to be executed in the transmit queue. After the operation information corresponding to the instruction to be executed in the transmit queue is awakened, the system can enter the address preemption state until the generated target sub-access address is determined. In this state, after the operation information (uop) corresponding to the first sub-target data (firstelement) is selected (pick) from the transmit queue (issueQ), the address information of the target sub-access address will be stored in the address storage unit (Payload) in the slow mode state machine (MultiAgenEngine). After successfully preempting the address generation port, the system enters the waiting state to wake up.

[0118] Step S130: performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information;

[0119] After the sub-target data corresponding to all sub-access addresses are accessed, subsequent processing can be performed based on the accessed data to complete the task corresponding to the instruction to be processed.

[0120] In a specific implementation, if the bit width of the data buffer is the second bit width, there are multiple data buffers, and each sub-target data is stored in each data buffer in sequence based on a preset order. Accordingly, in this step, the target data can be spliced ​​based on the data bits of the sub-target data; then, corresponding processing is performed based on the target data.

[0121] In another implementation, if the bit width of the data buffer is the first bit width, each sub-target data is stored in different data bits of the data buffer in sequence based on a preset order. Accordingly, the data stored in the data buffer is the spliced ​​target data. Accordingly, this step can perform corresponding processing based on the target data stored in the data buffer.

[0122] The corresponding processing is determined based on the instruction information of the instruction to be executed. The instruction to be executed may be stored in a preset memory, or added to the data in the preset memory and then stored in the preset memory, etc. The present invention does not make specific limitations here.

[0123] It can be understood that, based on the fact that the target data has been completely accessed, the corresponding instruction processing in this step can be executed based on the operation unit, wherein the operation unit is used to execute the operation process in the fast mode, that is, this step can reuse the operation unit used to execute the operation process in the fast mode.

[0124] It can be seen that the acquisition of instructions to be executed based on the operation unit can be achieved by reusing the software and hardware in the fast mode, without the need to configure the program sequence (ucode) for operating the instructions to be executed and the corresponding hardware resources, thereby reducing the software and hardware overhead of the instructions.

[0125] In the optional implementation, in the implementation where the slow mode flag is present, continue to refer to Figure 4 , after step S110 and before step S120, further comprising:

[0126] Step S115: Determine whether the slow mode flag is valid;

[0127] If so, the step of splitting the to-be-accessed address into a plurality of sub-access addresses based on the second bit width is performed; if not, the scheduling process of the fast mode is entered.

[0128] The following describes the instruction processing device provided in an embodiment of the present invention. The instruction processing device described below can be considered as the functional module required to implement the instruction processing method provided in an embodiment of the present invention. This functional module can be a software module or a hardware module (such as a hardware logic unit or a hardware logic circuit module). The content of the instruction processing device described below can be referenced in conjunction with the content of the method described above.

[0129] In an optional implementation, Figure 5 An optional block diagram of an instruction processing device provided by an embodiment of the present invention is shown. Figure 5 As shown, the instruction processing device may include:

[0130] The instruction acquisition module 200 is used to acquire, in the slow mode, instructions to be executed, where the instructions to be executed are instructions corresponding to the exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode;

[0131] A decoding module 210 is configured to decode the instruction to be executed based on the first bit width to determine corresponding operation information and an address to be accessed; the address to be accessed is used to access target data having the first bit width, where the first bit width is the data bit width corresponding to executing the instruction to be executed in the fast mode;

[0132] a memory access scheduling module 220 configured to split the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, perform memory access of sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determine whether the memory access exception is an error-suppressed exception;

[0133] The processing module 230 is configured to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information after the sub-target data corresponding to all sub-access addresses are accessed.

[0134] In an optional implementation, the instruction acquisition module 200 is an instruction fetch unit, and the instruction fetch unit is used to execute the instruction fetch process in the fast mode;

[0135] The decoding module 210 is a decoding unit, which is used to perform a decoding process in a fast mode;

[0136] The processing module 230 is a computing unit configured to execute a computing process in a fast mode.

[0137] For further optional implementation, refer to Figure 6Another optional example diagram of an instruction processing device is shown, in which the scheduling memory access module (not shown in the figure) includes a scheduling unit and a memory access unit; wherein the scheduling unit is configured with a slow mode state machine; the slow mode state machine is configured with an address storage unit, and the address storage unit is used to store a target starting address, the target starting address is the starting address of a target sub-access address, and the target sub-access address is used to indicate a sub-access address currently being executed; the slow mode state machine is triggered to start based on a slow mode flag.

[0138] In a specific implementation, the scheduling unit may further include a transmission queue, an error suppression calculation unit, a multiplexer, and an address generation port.

[0139] Among them, the decoding module can store the operation information corresponding to the decoding into the transmission queue, and configure the operation information stored in the transmission queue to a dormant state; and, when the memory access unit accesses the sub-target data corresponding to the target sub-access address based on the target sub-access address, the operation information corresponding to the memory access is obtained after the transmission queue is woken up to execute the access of the corresponding target sub-access address.

[0140] The error suppression calculation unit is used to calculate the target error suppression information under the second bit width based on the error suppression information under the first bit width, so that subsequent steps can determine whether the memory access exception is an error suppression exception based on the target error suppression information corresponding to the target sub-access address.

[0141] The multiplexer is used to select address information from the issue queue and the address storage unit, and the address generation port is used to enable the address generator to generate a target sub-access address based on the selected address information.

[0142] The slow mode state machine is configured with the following states:

[0143] A waiting initialization state is used to indicate that the current slow mode state machine is in a state of waiting for initialization completion, wherein the initialization is to obtain operation information of the to-be-executed instruction from the transmit queue and configure the address information in the address storage unit as the starting address of the target access address;

[0144] A waiting wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the waiting wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information;

[0145] The address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein the address generation port is used to enable the address generator to generate a target sub-access address;

[0146] Among them, a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

[0147] Optionally, the slow mode is triggered based on a resynchronization failure, and when the resynchronization failure occurs, the slow mode flag is configured to be valid at the same time;

[0148] The instruction processing device further includes a flag bit determination module, the flag bit determination module being configured to determine whether the slow mode flag bit is valid; if so, executing the step of splitting the to-be-accessed address into a plurality of sub-access addresses based on the second bit width; if not, entering the fast mode scheduling process;

[0149] Wherein, after the first instruction in the slow mode is decoded, the slow mode flag is configured to be invalid.

[0150] Optionally, the scheduling memory access module is configured to split the address to be accessed into multiple sub-access addresses based on the second bit width, and perform memory access of sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determine whether the memory access exception is an error-suppressed exception, including:

[0151] Determine a target sub-access address based on the second bit width and the target start address; the target sub-access address is used to indicate the currently determined sub-access address; wherein the target start address is the start address of the target sub-access address; when the operation is first executed, the target start address is the start address of the target access address; when the operation is not first executed, the target start address is the next address of the end address of the target sub-access address of the previous memory access process;

[0152] Based on the target sub-access address, accessing sub-target data corresponding to the target sub-access address; wherein the accessed sub-target data is used to store in a data buffer;

[0153] When a memory access exception exists, determining whether the memory access exception is an error suppression exception; the error suppression is used to indicate an exception that can be ignored;

[0154] If so, determining whether the current sub-target data is the end data of the target data; the end data is used to indicate the target data including the end address corresponding to the address to be accessed;

[0155] If so, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if not, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

[0156] Optionally, the scheduling memory access module is configured to determine whether the memory access exception is an error-suppressed exception, including:

[0157] Calculating target error suppression information at a second bit width based on the error suppression information at the first bit width;

[0158] Based on the target error suppression information corresponding to the target sub-access address, it is determined whether the memory access exception is an error-suppressed exception.

[0159] Optionally, the scheduling memory access module is used to determine whether the current sub-target data is the end data of the target data, specifically, to determine whether the target sub-access address contains the end address of the address to be accessed; if so, the current sub-target data is the end data of the target data, if not, the current sub-target data is not the end data of the target data.

[0160] Optionally, the bit width of the data buffer is the second bit width, and there are multiple data buffers; the scheduling memory access module is used to, in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, store each sub-target data in each data buffer in sequence based on a preset order; the preset order corresponds to the data position of the sub-target data in the target data;

[0161] The processing module is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information, including: splicing the target data based on the data order of the sub-target data; and performing corresponding processing based on the target data.

[0162] Optionally, the bit width of the data buffer is a first bit width; the scheduling memory access module is configured to, in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, store each sub-target data in a different data bit of the data buffer in sequence based on a preset order, wherein the preset order corresponds to the data position of the sub-target data in the target data;

[0163] The processing module is used to perform corresponding processing on the target data formed by the accessed sub-target data according to the operation information, specifically, to perform corresponding processing based on the target data stored in the data buffer.

[0164] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0165] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for processing an instruction, characterized in that: include: In the slow mode, obtaining an instruction to be executed, where the instruction to be executed is an instruction corresponding to an exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode; Decoding the instruction to be executed based on the first bit width to determine corresponding operation information and an address to be accessed; the address to be accessed is used to access target data having the first bit width, where the first bit width is the data bit width corresponding to executing the instruction to be executed in a fast mode; Splitting the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determining whether the memory access exception is an error-suppressed exception; After the sub-target data corresponding to all sub-access addresses are accessed, corresponding processing is performed on the target data formed by the accessed sub-target data according to the operation information.

2. The instruction processing method according to claim 1, wherein: The slow mode is triggered based on a resynchronization failure, and when the resynchronization failure occurs, the slow mode flag is configured to be valid; After decoding the instruction to be executed based on the first bit width and before splitting the address to be accessed into multiple sub-access addresses based on the second bit width, the method further includes: Determining whether the slow mode flag is valid; If yes, executing the step of splitting the to-be-accessed address into multiple sub-access addresses based on the second bit width; if no, entering the scheduling process of the fast mode; After the first instruction in the slow mode is decoded, the slow mode flag is configured to be invalid.

3. The instruction processing method according to claim 1, wherein: The step of obtaining the instruction to be executed is performed based on an instruction fetch unit, and the instruction fetch unit is used to execute the instruction fetch process in the fast mode; The step of decoding the instruction to be executed based on the first bit width is performed by a decoding unit, and the decoding unit is used to perform a decoding process in a fast mode; The step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information is performed based on an operation unit, and the operation unit is used to execute the operation process in the fast mode.

4. The instruction processing method according to claim 1, wherein: The step of splitting the address to be accessed into a plurality of sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error-suppressed exception when a memory access exception occurs include: Determine a target sub-access address based on the second bit width and the target start address; the target sub-access address is used to indicate the currently determined sub-access address; wherein the target start address is the start address of the target sub-access address; when the operation is first executed, the target start address is the start address of the target access address; when the operation is not first executed, the target start address is the next address of the end address of the target sub-access address of the previous memory access process; Based on the target sub-access address, accessing sub-target data corresponding to the target sub-access address; wherein the accessed sub-target data is used to store in a data buffer; When a memory access exception exists, determining whether the memory access exception is an error suppression exception; the error suppression is used to indicate an exception that can be ignored; If so, determining whether the current sub-target data is the end data of the target data; the end data is used to indicate the target data including the end address corresponding to the address to be accessed; If so, execute the step of performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information; if not, execute the step of determining the target sub-access address based on the second bit width and the target starting address.

5. The instruction processing method according to claim 4, wherein: The determining whether the memory access exception is an error-suppressed exception includes: Calculating target error suppression information at a second bit width based on the error suppression information at the first bit width; Based on the target error suppression information corresponding to the target sub-access address, it is determined whether the memory access exception is an error-suppressed exception.

6. The instruction processing method according to claim 4, wherein: The determination of whether the current sub-target data is the end data of the target data is specifically to determine whether the target sub-access address contains the end address of the address to be accessed; if so, the current sub-target data is the end data of the target data; if not, the current sub-target data is not the end data of the target data.

7. The instruction processing method according to claim 4, wherein: The bit width of the data buffer is the second bit width, and there are a plurality of data buffers; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is sequentially stored in each data buffer based on a preset order; the preset order corresponds to the data position of the sub-target data in the target data; The performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information includes: splicing the target data based on the data order of the sub-target data; Based on the target data, corresponding processing is performed.

8. The instruction processing method according to claim 4, wherein: The bit width of the data buffer is the first bit width; in the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, each sub-target data is sequentially stored in different data bits of the data buffer based on a preset order, and the preset order corresponds to the data position of the sub-target data in the target data; The performing corresponding processing on the target data formed from the accessed sub-target data according to the operation information is specifically, performing corresponding processing based on the target data stored in the data buffer.

9. The instruction processing method according to claim 4, wherein: The step of decoding the instruction to be executed based on the first bit width and determining the corresponding operation information and the address to be accessed further includes: storing the decoded operation information into a transmission queue, and configuring the operation information stored in the transmission queue to a dormant state; In the step of accessing the sub-target data corresponding to the target sub-access address based on the target sub-access address, operation information corresponding to the access is obtained after the transmit queue is awakened to perform access to the corresponding target sub-access address.

10. The instruction processing method according to claim 1, wherein: The steps of splitting the address to be accessed into multiple sub-access addresses based on the second bit width, accessing sub-target data based on the sub-access addresses, and determining whether the memory access exception is an error-suppressed exception when a memory access exception occurs are performed based on the scheduling unit and the memory access unit; The scheduling unit is configured with a slow mode state machine, the slow mode state machine is configured with an address storage unit, and the address storage unit is used to store the target starting address; the slow mode state machine is triggered to start based on a slow mode flag.

11. The instruction processing method according to claim 10, wherein: The slow mode state machine is configured with the following states: A waiting initialization state is used to indicate that the current slow mode state machine is in a state of waiting for initialization completion, wherein the initialization is to obtain operation information of the to-be-executed instruction from the transmit queue and configure the address information in the address storage unit as the starting address of the target access address; A waiting wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the waiting wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information; The address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein the address generation port is used to enable the address generator to generate a target sub-access address; Among them, a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

12. An instruction processing device, characterized in that: include: An instruction acquisition module is used to acquire, in the slow mode, an instruction to be executed, where the instruction to be executed is an instruction corresponding to an exception that triggers the switching of the instruction execution mode from the fast mode to the slow mode; a decoding module, configured to decode the instruction to be executed based on a first bit width, and determine corresponding operation information and an address to be accessed; the address to be accessed is used to access target data having a first bit width, where the first bit width is a data bit width corresponding to executing the instruction to be executed in a fast mode; a memory access scheduling module, configured to split the to-be-accessed address into a plurality of sub-access addresses based on the second bit width, perform memory access of sub-target data based on the sub-access addresses, and, when a memory access exception occurs, determine whether the memory access exception is an error-suppressed exception; The processing module is used for performing corresponding processing on the target data formed by the accessed sub-target data according to the operation information after the sub-target data corresponding to all the sub-access addresses are accessed.

13. The instruction processing device according to claim 12, wherein: The instruction acquisition module is an instruction fetch unit, and the instruction fetch unit is used to execute the instruction fetch process in the fast mode; The decoding module is a decoding unit, and the decoding unit is used to perform a decoding process in a fast mode; The processing module is an operation unit, and the operation unit is used to execute the operation process in the fast mode.

14. The instruction processing device according to claim 12, wherein: The scheduling memory access module includes a scheduling unit and a memory access unit; wherein, the scheduling unit is configured with a slow mode state machine; the slow mode state machine is configured with an address storage unit, and the address storage unit is used to store a target starting address, the target starting address is the starting address of the target sub-access address, and the target sub-access address is used to indicate the sub-access address currently being executed; the slow mode state machine is triggered to start based on a slow mode flag.

15. The instruction processing device according to claim 14, wherein: The slow mode state machine is configured with the following states: A waiting initialization state is used to indicate that the current slow mode state machine is in a state of waiting for initialization completion, wherein the initialization is to obtain operation information of the to-be-executed instruction from the transmit queue and configure the address information in the address storage unit as the starting address of the target access address; A waiting wake-up state is used to indicate that the current slow mode state machine is in a state of waiting for the operation information of the instruction to be executed to be awakened, wherein, in multiple sub-memory access cycle processes, the waiting wake-up state is entered after the memory access unit obtains the target sub-access address and the corresponding operation information; The address preemption state is used to indicate that the current slow mode state machine is in a state of preparing to preempt the address generation port; wherein the address generation port is used to enable the address generator to generate a target sub-access address; Among them, a sub-memory access cycle process is used to execute memory access of a target sub-access address. After entering the sub-memory access cycle process, the slow mode state machine executes multiple sub-memory access cycle processes based on the switching of the waiting wake-up state and the address preemption state.

16. A processor, characterized in that: The apparatus comprises an instruction processing device as claimed in any one of claims 12 to 15.

17. An electronic device, characterized in that: comprising the processor of claim 16.

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