Self-recovery method and device of multi-core decoding system, storage medium and program product

Abstract

The invention relates to a self-recovery method and device of a multi-core decoding system, a storage medium and a program product. The method comprises the following steps: in response to a condition that a first decoding instance running on a first decoding core meets a preset migration condition, determining a second decoding core from decoding cores in a schedulable state in a plurality of decoding cores; wherein the preset migration condition at least comprises decoding abnormity of the first decoding instance or decoding abnormity of the first decoding core; creating a second decoding instance on a second decoding core according to the decoding task related parameters of the first decoding instance; copying a code stream corresponding to the first decoding instance to a second memory space corresponding to a second decoding instance from a first memory space corresponding to the first decoding instance; and running the second decoding instance through the second decoding core, returning the decoded data stream to the decoding request source, and binding the second decoding instance to the decoding request source. According to the invention, self-recovery can be realized in a multi-core decoding system through a software scheme.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a self-recovery method for a multi-core decoding system, a self-recovery device for a multi-core decoding system, a non-volatile computer-readable storage medium, and a computer program product. Background Art

[0002] With the rapid development of multimedia technology, video decoding systems play a vital role in various applications, particularly in real-time video playback, video conferencing, and streaming services. Multi-core decoding systems, due to their efficient parallel processing capabilities, are becoming a mainstream solution. However, existing multi-core decoding systems often exhibit poor resilience when faced with decoder failures, severely impacting the user experience. Summary of the Invention

[0003] In view of this, the present disclosure provides a self-recovery technical solution for a multi-core decoding system.

[0004] According to one aspect of the present disclosure, a self-recovery method for a multi-core decoding system is provided, wherein the multi-core decoding system includes a plurality of decoding cores, the plurality of decoding cores including a first decoding core, and the method includes:

[0005] In response to a first decoding instance running on the first decoding core meeting a preset migration condition, determining a second decoding core from decoding cores in a schedulable state among the plurality of decoding cores; wherein the preset migration condition at least includes a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core;

[0006] Creating a second decoding instance on the second decoding core according to decoding task-related parameters of the first decoding instance;

[0007] Copying the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance;

[0008] The second decoding instance is run through the second decoding core, a decoded data stream is returned to a decoding request source, and the second decoding instance is bound to the decoding request source.

[0009] In one possible implementation, the method further includes at least the following:

[0010] In response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core, determining that a decoding exception occurs in the first decoding instance;

[0011] In response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core, determining that a decoding exception occurs in the first decoding core;

[0012] In response to detecting that a timeout occurs in the response of the first decoding core to the decoding command, it is determined that a decoding exception occurs in the first decoding core.

[0013] In a possible implementation, when a decoding exception occurs in the first decoding instance, the preset migration condition further includes:

[0014] The decoding exception of the first decoding instance occurs in the intra-frame coding frame decoding stage.

[0015] In a possible implementation, the method further includes:

[0016] In response to an exception occurring in decoding a non-intra-coded frame in the first decoding instance, a decoding result of a previous frame of the non-intra-coded frame is used as the decoding result of the non-intra-coded frame.

[0017] In a possible implementation, the method further includes:

[0018] In response to a decoding exception occurring in the first decoding core, setting the first decoding core to an unschedulable state;

[0019] Resetting the first decoding core;

[0020] The reset first decoding core is reset to a schedulable state.

[0021] In one possible implementation, the multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver. The decoding device includes a storage subsystem and the multiple decoding cores. The method is applied to the decoding device driver.

[0022] In a possible implementation, the decoding task related parameters include at least part of the following: video encoding format, resolution, frame rate, and code stream memory address.

[0023] In a possible implementation, determining the second decoding core from the decoding cores in the plurality of decoding cores that are in a schedulable state includes:

[0024] According to a preset load balancing strategy, a second decoding core is determined from the decoding cores in the plurality of decoding cores that are in a schedulable state.

[0025] According to another aspect of the present disclosure, a self-recovery device for a multi-core decoding system is provided, wherein the multi-core decoding system includes a plurality of decoding cores, the plurality of decoding cores including a first decoding core, and the device includes:

[0026] a first determining module configured to determine, in response to a first decoding instance running on the first decoding core satisfying a preset migration condition, a second decoding core from the plurality of decoding cores that are in a schedulable state; wherein the preset migration condition includes at least a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core;

[0027] a creation module, configured to create a second decoding instance on the second decoding core according to decoding task-related parameters of the first decoding instance;

[0028] a copy module, configured to copy the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance;

[0029] The return and binding module is used to run the second decoding instance through the second decoding core, return the decoded data stream to the decoding request source, and bind the second decoding instance to the decoding request source.

[0030] In a possible implementation, the apparatus further includes at least the following:

[0031] a second determining module, configured to determine that a decoding exception occurs in the first decoding instance in response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core;

[0032] a third determining module, configured to determine that a decoding exception occurs in the first decoding core in response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core;

[0033] The fourth determining module is configured to determine that a decoding exception occurs in the first decoding core in response to detecting that the first decoding core times out in responding to the decoding command.

[0034] In a possible implementation, when a decoding exception occurs in the first decoding instance, the preset migration condition further includes:

[0035] The decoding exception of the first decoding instance occurs in the intra-frame coding frame decoding stage.

[0036] In a possible implementation, the apparatus further includes:

[0037] The fifth determining module is configured to, in response to an exception occurring in decoding a non-intra-coded frame in the first decoding instance, use a decoding result of a previous frame of the non-intra-coded frame as the decoding result of the non-intra-coded frame.

[0038] In a possible implementation, the apparatus further includes:

[0039] a first setting module, configured to set the first decoding core to an unschedulable state in response to a decoding exception occurring in the first decoding core;

[0040] A reset module, configured to reset the first decoding core;

[0041] The second setting module is configured to reset the first decoding core to a schedulable state after being reset.

[0042] In one possible implementation, the multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver. The decoding device includes a storage subsystem and the multiple decoding cores. The method is applied to the decoding device driver.

[0043] In a possible implementation, the decoding task related parameters include at least part of the following: video encoding format, resolution, frame rate, and code stream memory address.

[0044] In a possible implementation, the first determining module is configured to:

[0045] According to a preset load balancing strategy, a second decoding core is determined from the decoding cores in the plurality of decoding cores that are in a schedulable state.

[0046] According to another aspect of the present disclosure, a self-recovery device for a multi-core decoding system is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0047] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0048] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program implements the steps of the above method when executed by a processor.

[0049] In an embodiment of the present disclosure, in response to a first decoding instance running on the first decoding core satisfying a preset migration condition, a second decoding core is determined from the decoding cores in the multiple decoding cores that are in a schedulable state, wherein the preset migration condition at least includes a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core, and according to decoding task-related parameters of the first decoding instance, a second decoding instance is created on the second decoding core, and the code stream corresponding to the first decoding instance is copied from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance, and the second decoding instance is run through the second decoding core, the decoded data stream is returned to the decoding request source, and the second decoding instance is bound to the decoding request source. In this way, efficient self-recovery can be achieved in a multi-core decoding system through a software solution without adding or modifying hardware, and the decoding interruption problem caused by decoder failure in the related art can be solved, thereby improving the robustness of the decoding system and user experience.

[0050] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0052] Figure 1 A flowchart of a self-recovery method for a multi-core decoding system provided by an embodiment of the present disclosure is shown.

[0053] Figure 2 A schematic diagram of a multi-core decoding system provided by an embodiment of the present disclosure is shown.

[0054] Figure 3 A block diagram of a self-recovery device for a multi-core decoding system provided by an embodiment of the present disclosure is shown.

[0055] Figure 4 FIG. 1 is a block diagram showing a self-recovery device 1900 of a multi-core decoding system according to an exemplary embodiment. DETAILED DESCRIPTION

[0056] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0057] As used herein, the terms "comprises," "comprising," "having," or variations thereof are open ended and include one or more stated features, integers, elements, steps, parts, or functions, but do not preclude the presence or addition of one or more other features, integers, elements, steps, parts, functions, or groups thereof.

[0058] When an element is referred to as being "connected," "coupled," "responsive" or variations thereof to another element, it can be directly connected, coupled or responsive to the other element or intervening elements may be present.

[0059] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another element / operation. Therefore, without departing from the teachings of the present invention, the first element / operation in some embodiments may be referred to as the second element / operation in other embodiments.

[0060] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0061] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0062] Currently, hardware decoding technology is often unable to self-recover from decoding anomalies. For example, if the decoder itself malfunctions (such as a hardware anomaly or a timeout), related technologies typically require powering the device back on or shutting down the user-mode application and reloading the bitstream to restore decoding functionality. This recovery method is not only cumbersome but can also interrupt the decoding process, severely impacting the user experience.

[0063] While some solutions attempt to improve decoding system stability through software-level error detection or redundant design, these approaches often fail to fundamentally address the self-recovery issues faced by multi-core decoding systems in the event of a decoding core failure. For example, some solutions can only handle specific types of bitstream errors and cannot cope with hardware failures in the decoding core. Other solutions rely on additional hardware resources or complex restart processes, increasing system complexity and cost.

[0064] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a self-recovery method for a multi-core decoding system. In response to a first decoding instance running on a first decoding core satisfying a preset migration condition, a second decoding core is determined from the decoding cores in the multiple decoding cores that are in a schedulable state, wherein the preset migration condition at least includes a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core. According to the decoding task-related parameters of the first decoding instance, a second decoding instance is created on the second decoding core, and the code stream corresponding to the first decoding instance is copied from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance. The second decoding instance is run through the second decoding core, the decoded data stream is returned to the decoding request source, and the second decoding instance is bound to the decoding request source. In this way, efficient self-recovery can be achieved in the multi-core decoding system through a software solution without adding or modifying hardware, and the decoding interruption problem caused by decoder failure in the related art can be solved, thereby improving the robustness and user experience of the decoding system.

[0065] The self-recovery method of the multi-core decoding system provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0066] Figure 1 A flow chart showing a self-recovery method for a multi-core decoding system provided by an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the self-recovery method for the multi-core decoding system may be a self-recovery device of the multi-core decoding system. For example, the self-recovery method for the multi-core decoding system may be executed by a terminal device or a server or other electronic device. Among them, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the self-recovery method for the multi-core decoding system may be implemented by a processor calling computer-readable instructions stored in a memory. In an embodiment of the present disclosure, the multi-core decoding system includes a plurality of decoding cores, and the plurality of decoding cores includes a first decoding core. As Figure 1 As shown, the self-recovery method of the multi-core decoding system includes steps S11 to S14.

[0067] In step S11, in response to the first decoding instance running on the first decoding core meeting a preset migration condition, a second decoding core is determined from the decoding cores in the multiple decoding cores that are in a schedulable state; wherein the preset migration condition includes at least a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core.

[0068] In step S12, a second decoding instance is created on the second decoding core according to the decoding task-related parameters of the first decoding instance.

[0069] In step S13, the code stream corresponding to the first decoding instance is copied from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance.

[0070] In step S14 , the second decoding instance is run by the second decoding core, the decoded data stream is returned to the decoding request source, and the second decoding instance is bound to the decoding request source.

[0071] In the disclosed embodiment, the multi-core decoding system is a hardware architecture based on multiple independent decoding cores, which can be used to efficiently and in parallel process decoding tasks of video, audio or other multimedia data.

[0072] In one possible implementation, the multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver. The decoding device includes a storage subsystem and the multiple decoding cores. The method is applied to the decoding device driver.

[0073] Figure 2 FIG. 1 is a schematic diagram of a multi-core decoding system provided by an embodiment of the present disclosure. Figure 2 As shown, a multi-core decoding system may include a host system, a bus, and a decoding device. The decoding device may include n decoding cores and a storage subsystem, where n is an integer greater than 1. The host system may install a decoding device driver.

[0074] The host system is the main control unit of the entire multi-core decoding system. It is responsible for the management of decoding device drivers, the issuance of decoding tasks, and self-recovery when decoding task anomalies are detected.

[0075] The bus is the communication path between the host system and the decoding device for transmitting data, addresses, and control signals. The bus can be a Peripheral Component Interconnect Express (PCIE) bus, an Accelerated Graphics Port (AGP) bus, or other similar bus types. When the bus detects the insertion of a decoding device, it notifies the host system to load the decoding device driver.

[0076] The decoding device driver is a driver used by the host system to manage the decoding device. It can be used to allocate, initialize, start, manage, and assign decoding tasks to the decoding core firmware memory, as well as initialize, allocate, release, and organize the storage subsystem.

[0077] The decoding device contains multiple independent decoding cores, each capable of operating in parallel without interfering with one another. The storage subsystem receives and stores bitstream data transmitted by the host system. A bitstream represents the data stream to be decoded. When the host system activates a decoding core and issues a decoding task, the core accesses the bitstream data in the storage subsystem via the decoding device's internal bus and performs decoding. After decoding is complete, the output data is stored back in the storage subsystem.

[0078] In this implementation, the execution subject of the self-recovery method of the multi-core decoding system can be a decoding device driver. By executing the self-recovery method of the multi-core decoding system through the decoding device driver, it is possible to achieve efficient self-recovery using a software solution without adding or modifying hardware. When an exception occurs in the decoding core or decoding instance, the decoding device driver can quickly respond and trigger the migration of the decoding task, and migrate the abnormal decoding instance to the normally working decoding core for continued execution, thereby avoiding the interruption of the decoding task due to a decoding core failure or a decoding instance failure, and significantly improving the robustness and reliability of the multi-core decoding system. At the same time, this method can also effectively reduce the user waiting time caused by decoding anomalies, avoid the tedious operations and long interruptions brought about by traditional recovery methods (such as restarting the device or closing the user-mode program to reload the code stream), greatly optimize the user experience, and ensure the efficient and stable operation of the decoding system. It is particularly suitable for application scenarios with high requirements for decoding continuity, such as real-time video playback, video conferencing, and streaming media services.

[0079] In other possible implementations, the executor of the self-recovery method of the multi-core decoding system may also be one or more decoding cores in the decoding device itself. For example, the decoding core may be designed to have self-detection and recovery capabilities, and when it detects that a decoding anomaly occurs in itself, it actively triggers the migration and recovery process of the decoding instance without relying on the decoding device driver of the host system to intervene. Alternatively, the executor of the self-recovery method of the multi-core decoding system may also be a special monitoring module or self-recovery management module in the host system, which is independent of the decoding device driver and is specifically responsible for monitoring the operating status of the decoding system, and when a decoding anomaly is detected, it performs the migration and recovery operations of the decoding instance according to preset strategies and processes.

[0080] In the following, the self-recovery method of the multi-core decoding system is described by taking the decoding device driver as an example.

[0081] In the embodiment of the present disclosure, the decoding request source may be any entity that initiates a decoding request to the host system, for example, a user-mode application, a system service, or a hardware module.

[0082] User-mode applications can be video players, multimedia processing tools (such as ffmpeg, GStreamer), video conferencing software, etc. User-mode applications can submit decoding tasks to the host system through standard APIs (such as VA-API, VDPAU, DXVA) or system calls.

[0083] System services can be background transcoding engines, operating system kernel modules, virtualized decoding services within containers or virtual machines, etc. System services can be automatically triggered or scheduled by the system without direct user interaction.

[0084] Hardware modules can include sensor data processors, DMA (Direct Memory Access) controllers or coprocessors, network accelerator cards, and more. Hardware modules can trigger the decoding process through interrupts, bus signals, or memory sharing mechanisms. For example, a camera's ISP (Internet Service Provider) module can trigger real-time video decoding, while an FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) can directly initiate decoding requests via the bus.

[0085] In an embodiment of the present disclosure, after the multi-core decoding system is powered on and started, the decoding device driver can perform initialization operations on the decoding device. This process can include configuring the hardware resources in the decoding device (such as the storage subsystem), as well as performing initialization operations such as firmware loading, memory allocation, and parameter setting on each decoding core. Through these steps, the decoding device driver can ensure that each decoding core is in a normal working state and mark it as a schedulable state, that is, these decoding cores are ready to receive and process decoding tasks and can respond to task allocation requests from the host system at any time, thereby laying the foundation for subsequent parallel decoding task allocation and processing.

[0086] When a decoding request from any decoding request source arrives at the host system, the decoding device driver can select a decoding core (such as the first decoding core) to process the decoding request based on the preset load balancing strategy and the load conditions of each decoding core in a schedulable state. Among them, the preset load balancing strategy can refer to a predefined rule or algorithm for reasonably distributing decoding tasks among multiple decoding cores to optimize the overall performance and resource utilization of the multi-core decoding system. For example, if the current load of a decoding core is low, while the load of other decoding cores is high, then the load balancing strategy can choose to create a new decoding instance on the decoding core with the lower load to avoid excessive load on certain decoding cores, while ensuring that the decoding tasks of the entire multi-core decoding system can be efficiently processed in parallel. In this way, the stability and decoding efficiency of the multi-core decoding system can be effectively improved, especially when the task needs to be reallocated due to decoding anomalies, the decoding process can be quickly restored to improve the user experience.

[0087] After determining the first decoding core, the decoding device driver can create a decoding instance (referred to as the first decoding instance) on the first decoding core. The first decoding instance can be understood as a logical processing unit that encapsulates all information and operations related to the current decoding task.

[0088] The decoding process needs to process a large amount of code stream data (such as video or audio encoding data), which needs to be stored in the memory so that the first decoding core can read and process it. Therefore, the decoding device driver can allocate a dedicated memory space (recorded as the first memory space) for the first decoding instance to store the code stream data required for decoding and the intermediate results generated during the decoding process. Among them, the process of allocating memory space may involve the application, allocation and management of system memory. The decoding device driver can dynamically allocate sufficient memory space according to decoding task-related parameters (such as video resolution, bit rate, etc.) to ensure the smooth progress of the decoding process. The allocated first memory space can be mapped to the address space of the first decoding core, so that the first decoding core can directly access these memory areas.

[0089] The decoding device driver can pass decoding task-related parameters to the first decoding instance. The decoding task-related parameters can represent various parameters and configuration information related to the current decoding task. The first decoding instance can record the decoding task-related parameters so that they can be used at any time during the decoding process. The decoding task-related parameters can not only be used for the current decoding task, but also for recovery operations in the event of decoding anomalies. For example, when it is necessary to migrate the decoding instance from the first decoding core to the second decoding core, the recorded decoding task-related parameters can be used to recreate the decoding instance on the new decoding core, thereby ensuring the continuity of the decoding task.

[0090] In a possible implementation, the decoding task related parameters include at least part of the following: video encoding format, resolution, frame rate, and code stream memory address.

[0091] As an example of this implementation, decoding task-related parameters may include the video encoding format. For example, the video encoding format may be H.264, H.265, AV1, etc., which are not limited here. The decoding core may select an appropriate decoding algorithm based on the video encoding format.

[0092] As an example of this implementation, decoding task-related parameters may include resolution. For example, the resolution may be 1080p, 4K, etc., which are not limited here. The decoding core may configure the decoding buffer and processing power based on the resolution.

[0093] As an example of this implementation, the decoding task-related parameters may include a frame rate, such as 30 fps, 60 fps, etc. The decoding core may control the decoding speed according to the frame rate.

[0094] As an example of this implementation, decoding task-related parameters may include a bitstream memory address. The bitstream memory address may indicate the storage location of the bitstream in memory. The decoding core may read the bitstream data based on the bitstream memory address.

[0095] Of course, the decoding task related parameters may also include other parameters, such as audio sampling rate, encoding parameters, etc.

[0096] In the disclosed embodiment, the first decoding core can begin executing a decoding task based on the decoding task-related parameters of the first decoding instance. The first decoding core can read code stream data from the first memory space and convert it into a decoded data stream using a decoding algorithm. The decoded data stream can represent the output result of the decoding task, such as decoded video frame data or audio sample data. The decoded data stream can be directly used for display or playback.

[0097] After the first decoding core decodes and obtains the decoded data stream, the decoded data stream can be returned to the decoding request source. In one possible implementation, after the first decoding core completes decoding, the decoded data stream can be stored in the first memory space and a notification can be sent to the decoding device driver. The decoding device driver can send a notification to the decoding request source and provide the storage location (such as a memory address) of the decoded data stream. The decoding request source can read the decoded data stream from the first memory space based on the information in the notification. If the decoding request source is a user-mode application, the decoding request source can pass the decoded video frame to the display module for rendering, or pass the decoded audio sample to the audio playback module for playback.

[0098] In one possible implementation, the method also includes at least part of the following: in response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core, determining that a decoding exception has occurred in the first decoding instance; in response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core, determining that a decoding exception has occurred in the first decoding core; in response to detecting that the first decoding core's response to the decoding command has timed out, determining that a decoding exception has occurred in the first decoding core.

[0099] As an example of this implementation, the decoding device driver may determine that a decoding exception occurs in the first decoding instance in response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core.

[0100] In this example, the decoding core has error detection and reporting capabilities. When the first decoding instance encounters an error during decoding, the first decoding core can generate an error interrupt signal and report it to the decoding device driver. The decoding device driver can monitor the status of the decoding core and receive interrupt signals from the decoding core. When the decoding device driver receives the error interrupt signal reported by the first decoding core, it can analyze the error interrupt signal and determine that a decoding anomaly has occurred in the first decoding instance.

[0101] As an example of this implementation, the decoding device driver may determine that a decoding exception occurs in the first decoding core in response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core.

[0102] In this example, the decoding core has error detection and reporting capabilities. During operation, the decoding core may encounter hardware-level errors (e.g., hardware failures, register errors, bus errors, etc.). These errors may affect the normal operation of the entire decoding core, not just a specific decoding instance. After receiving the error interrupt signal reported by the first decoding core, the decoding device driver can parse the error interrupt signal to determine if the first decoding core itself has experienced an abnormality.

[0103] As an example of this implementation, the decoding device driver may determine that a decoding exception occurs in the first decoding core in response to detecting that the first decoding core times out in responding to a decoding command.

[0104] In this example, the decoding device driver has a timeout detection function. After sending a decoding command to the decoding core, the decoding device driver can set a timeout mechanism. If the decoding core does not respond to the decoding command within the specified time, it can be considered that the decoding core's response to the decoding command has timed out. The decoding device driver can use the timeout detection mechanism to determine whether the decoding core is functioning properly. If a response timeout is detected, the decoding device driver can determine that a decoding anomaly has occurred in the decoding core.

[0105] This implementation introduces multiple anomaly detection mechanisms, including error interrupt signals for decoding instances, error interrupt signals for decoding cores, and detection of response timeouts for decoding commands. This enables comprehensive and timely identification of anomalies during the decoding process. This significantly improves the robustness of the multi-core decoding system, enabling it to quickly respond to anomalies in decoding instances or decoding cores, preventing single-point failures from causing the entire decoding task to fail, thereby ensuring the stable operation of the multi-core decoding system.

[0106] In an embodiment of the present disclosure, the first decoding instance running on the first decoding core may be migrated in response to the first decoding instance meeting a preset migration condition, wherein the preset migration condition at least includes a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core.

[0107] In one possible implementation, in response to a decoding exception occurring in the first decoding core, a self-recovery process corresponding to the first decoding core can be started. In this implementation, when a decoding exception occurs in the first decoding core, it can be determined that each decoding instance (including the first decoding instance) running on the first decoding core meets the preset migration conditions, and each decoding instance running on the first decoding core can be migrated to other decoding cores. For example, the first decoding instance can be migrated to the second decoding core. In this implementation, since a decoding exception occurs in the entire first decoding core, the second decoding core is not the same decoding core as the first decoding core.

[0108] In another possible implementation, in response to a decoding exception occurring in the first decoding instance, a self-recovery process corresponding to the first decoding instance can be initiated. In this implementation, if a decoding exception occurs in the first decoding instance, it can be determined that the first decoding instance meets preset migration conditions, and the first decoding instance can be migrated. In this implementation, since the decoding exception occurs only in the first decoding instance, and not in the entire first decoding core, the second decoding core can be the same decoding core as the first decoding core, or different decoding cores.

[0109] In a possible implementation, when a decoding exception occurs in the first decoding instance, the preset migration condition further includes: the decoding exception of the first decoding instance occurs in an intra-frame coding frame decoding stage.

[0110] In this implementation, when a decoding exception occurs in the first decoding instance, the decoding device driver can further determine whether the current decoding exception of the first decoding instance occurs in the intra-frame coded frame (I frame) decoding stage or the non-intra-frame coded frame decoding stage, that is, it can further determine whether the current decoding error of the first decoding instance is the I frame.

[0111] If the decoding anomaly of the first decoding instance occurs during the decoding of an intra-frame (i.e., the first decoding instance is currently decoding an I-frame with an error), the migration operation of the first decoding instance can be immediately triggered. Since the I-frame is an independent and complete frame, decoding can be restarted directly from this frame after migration, ensuring image continuity and avoiding cumulative errors.

[0112] If the decoding exception of the first decoding instance occurs during the decoding of a non-intra-coded frame (i.e., the first decoding instance currently experiencing a decoding error is a non-I frame), the first decoding instance can be temporarily not migrated. If a decoding command for an intra-coded frame is subsequently received, the first decoding instance can be migrated and the decoding process can be resynchronized based on the I frame.

[0113] This implementation distinguishes between I-frame and non-I-frame anomalies and only migrates when there are keyframe errors, reducing unnecessary switching overhead. This approach also avoids frequent migrations due to non-keyframe errors, improving the overall utilization of the multi-core decoding system.

[0114] In a possible implementation, the method further includes: in response to an exception occurring in the first decoding instance when decoding a non-intra-coded frame, using a decoding result of a previous frame of the non-intra-coded frame as the decoding result of the non-intra-coded frame.

[0115] In this implementation, if an exception occurs when the first decoding instance decodes a non-intra-coded frame, it can use a preceding frame padding method to use the decoding result of the previous frame of the non-intra-coded frame as the decoding result of the non-intra-coded frame, and can notify the decoding request source that the current frame decoding is complete. If the code stream subsequently received by the first decoding instance is a non-intra-coded frame, the decoding request source can continue to be notified in this way. This implementation can also solve the problem of errors in the code stream of non-intra-coded frames themselves, and can actively skip the problem frame, so that the decoding process is not interrupted.

[0116] In an embodiment of the present disclosure, the decoding device driver may determine a second decoding core from decoding cores in a schedulable state in response to a first decoding instance satisfying a preset migration condition.

[0117] In one possible implementation, determining the second decoding core from the decoding cores in the multiple decoding cores that are in a schedulable state includes: determining the second decoding core from the decoding cores in the multiple decoding cores that are in a schedulable state according to a preset load balancing strategy.

[0118] In this implementation, the decoding device driver can, in response to the first decoding instance meeting the preset migration conditions, select a suitable decoding core from the schedulable decoding cores according to a preset load balancing policy as the second decoding core. This selection process, based on the load balancing policy, ensures the overall performance and resource utilization of the multi-core decoding system.

[0119] After determining the second decoding core, the decoding device driver can create a new decoding instance, namely the second decoding instance, on the second decoding core based on the decoding task-related parameters of the first decoding instance (such as video encoding format, resolution, frame rate, code stream memory address, etc.). The decoding task-related parameters are the core information of the decoding task and ensure that the second decoding instance can decode according to the same configuration as the first decoding instance. In addition, the decoding device driver can allocate a new memory space (second memory space) for the second decoding instance to store the code stream data required for decoding and the intermediate results generated during the decoding process. By allocating the second memory space to the second decoding instance, the second decoding instance can run independently of the first decoding instance, avoiding data conflicts or errors.

[0120] The decoding device driver can copy the code stream data corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space. In this way, the second decoding instance can use the same code stream data as the first decoding instance for decoding, ensuring the continuity of the decoding task. The decoding device driver can notify the second decoding core to start decoding according to the decoding task-related parameters. The second decoding instance can record the decoding task-related parameters for easy use during the decoding process, enabling the second decoding core to correctly decode the code stream data. After the second decoding core completes decoding, it generates a decoded data stream (such as a decoded video frame or audio sample).

[0121] The decoding device driver can return the decoded data stream to the decoding request source (such as a user-mode application or system service) for further processing (such as display or playback). At the same time, the decoding device driver binds the second decoding instance to the decoding request source so that subsequent decoding commands can be directly sent to the second decoding instance on the second decoding core. This binding mechanism ensures the continuity and stability of the decoding task. Even if an exception occurs in the first decoding instance, the decoding task can be seamlessly transferred to the second decoding instance for continued execution.

[0122] In a possible implementation, the method further includes: in response to a decoding exception occurring in the first decoding core, setting the first decoding core to an unschedulable state; resetting the first decoding core; and resetting the reset first decoding core to a schedulable state.

[0123] In this implementation, when a decoding anomaly is detected in the first decoding core, the decoding device driver can set the first decoding core to an unschedulable state to prevent it from receiving new decoding tasks, thereby preventing further errors or instability. The decoding device driver can remove the first decoding core from the load system to ensure that no new decoding tasks are assigned to it until it returns to normal operation. This operation improves the stability and reliability of the multi-core decoding system and prevents the abnormal decoding core from negatively impacting the decoding task processing of the entire system.

[0124] The decoding device driver can reset the first decoding core. This reset operation clears abnormal conditions in the first decoding core and restores it to its initial normal operating state. For example, the decoding device driver can send a reset signal or execute a reset instruction to the first decoding core. The reset operation can include clearing the decoding core's internal state, register contents, memory mapping, and other information to restore it to its initial state. The reset operation can clear internal errors or faults that may have caused abnormalities, allowing the first decoding core to resume normal operation.

[0125] After the reset operation is complete, if the first decoding core returns to normal, the first decoding core can be reintegrated into the load system so that it can continue to participate in processing decoding tasks. Specifically, the decoding device driver can re-register the first decoding core into the load system and mark it as schedulable, allowing the first decoding core to once again receive new decoding tasks.

[0126] By adopting this implementation, the decoding device driver can effectively handle abnormal decoding cores. This approach not only quickly isolates the fault, preventing the faulty decoding core from affecting the entire system, but also restores its functionality after the fault is resolved, fully utilizing system resources and ensuring efficient and stable operation of the multi-core decoding system.

[0127] The self-recovery method for a multi-core decoding system provided by the embodiments of the present disclosure can be applied to technical fields such as decoding systems and self-recovery mechanisms, and is not limited here.

[0128] The following describes a self-recovery method for a multi-core decoding system provided by an embodiment of the present disclosure using a specific application scenario. In this application scenario, the multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver, and the decoding device includes a storage subsystem and multiple decoding cores.

[0129] After the multi-core decoding system is powered on, the decoding device driver can complete the initialization of the decoding device to enable each decoding core to enter a schedulable state.

[0130] When a decoding request from any decoding request source arrives at the host system, the decoding device driver can select a first decoding core from each decoding core in a schedulable state based on a preset load balancing strategy and the load conditions of each decoding core in a schedulable state, create a first decoding instance on the first decoding core, and allocate a first memory space for the first decoding instance. The decoding device driver can pass decoding task-related parameters to the first decoding instance, and the first decoding instance can record the decoding task-related parameters. The first decoding core can start executing the decoding task based on the decoding task-related parameters of the first decoding instance. The first decoding core can read the code stream data from the first memory space, convert it into a decoded data stream through a decoding algorithm, and return the decoded data stream to the decoding request source.

[0131] The decoding device driver may determine that a decoding exception has occurred in the first decoding instance in response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core. The decoding device driver may determine that a decoding exception has occurred in the first decoding core in response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core. The decoding device driver may determine that a decoding exception has occurred in the first decoding core in response to detecting that a response of the first decoding core to a decoding command has timed out.

[0132] In response to a first decoding instance satisfying a first preset migration condition or a second preset migration condition, the decoding device driver may determine a second decoding core from the schedulable decoding cores. The first preset migration condition may be a decoding exception occurring in the first decoding core. The second preset migration condition may be a decoding exception occurring in the first decoding instance, where the decoding exception occurred during the I-frame decoding phase. After determining the second decoding core, the decoding device driver may create a second decoding instance on the second decoding core based on the decoding task parameters of the first decoding instance. Furthermore, the decoding device driver may allocate a second memory space for the second decoding instance. The decoding device driver may copy the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space and notify the second decoding core to perform decoding according to the decoding task parameters. The second decoding instance may record the decoding task parameters for easy use during the decoding process. After the second decoding core decodes the decoded data stream, the decoding device driver may return the decoded data stream to the decoding request source and bind the second decoding instance to the decoding request source so that subsequent decoding commands can be issued to the second decoding instance on the second decoding core.

[0133] When a decoding exception occurs in the first decoding core, the decoding device driver may set the first decoding core to an unschedulable state, reset the first decoding core, and set the reset first decoding core to a schedulable state again.

[0134] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0135] In addition, the present disclosure also provides a self-recovery device, a non-volatile computer-readable storage medium, and a computer program product for a multi-core decoding system. The above can be used to implement any self-recovery method of a multi-core decoding system provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0136] Figure 3 FIG. 1 is a block diagram of a self-recovery device for a multi-core decoding system provided by an embodiment of the present disclosure. The multi-core decoding system includes a plurality of decoding cores, wherein the plurality of decoding cores includes a first decoding core, such as Figure 3 As shown, the self-recovery device of the multi-core decoding system includes:

[0137] A first determining module 31 is configured to determine a second decoding core from among the plurality of decoding cores that are in a schedulable state in response to a first decoding instance running on the first decoding core satisfying a preset migration condition, wherein the preset migration condition includes at least a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core;

[0138] a creation module 32, configured to create a second decoding instance on the second decoding core according to decoding task-related parameters of the first decoding instance;

[0139] a copy module 33, configured to copy the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance;

[0140] The return and binding module 34 is configured to run the second decoding instance through the second decoding core, return the decoded data stream to the decoding request source, and bind the second decoding instance to the decoding request source.

[0141] In a possible implementation, the apparatus further includes at least the following:

[0142] a second determining module, configured to determine that a decoding exception occurs in the first decoding instance in response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core;

[0143] a third determining module, configured to determine that a decoding exception occurs in the first decoding core in response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core;

[0144] The fourth determining module is configured to determine that a decoding exception occurs in the first decoding core in response to detecting that the first decoding core times out in responding to the decoding command.

[0145] In a possible implementation, when a decoding exception occurs in the first decoding instance, the preset migration condition further includes:

[0146] The decoding exception of the first decoding instance occurs in the intra-frame coding frame decoding stage.

[0147] In a possible implementation, the apparatus further includes:

[0148] The fifth determining module is configured to, in response to an exception occurring in decoding a non-intra-coded frame in the first decoding instance, use a decoding result of a previous frame of the non-intra-coded frame as the decoding result of the non-intra-coded frame.

[0149] In a possible implementation, the apparatus further includes:

[0150] a first setting module, configured to set the first decoding core to an unschedulable state in response to a decoding exception occurring in the first decoding core;

[0151] A reset module, configured to reset the first decoding core;

[0152] The second setting module is configured to reset the first decoding core to a schedulable state after being reset.

[0153] In one possible implementation, the multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver. The decoding device includes a storage subsystem and the multiple decoding cores. The method is applied to the decoding device driver.

[0154] In a possible implementation, the decoding task related parameters include at least part of the following: video encoding format, resolution, frame rate, and code stream memory address.

[0155] In a possible implementation, the first determining module 31 is configured to:

[0156] According to a preset load balancing strategy, a second decoding core is determined from the decoding cores in the plurality of decoding cores that are in a schedulable state.

[0157] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0158] An embodiment of the present disclosure further provides a self-recovery device for a multi-core decoding system, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0159] An embodiment of the present disclosure further provides a non-volatile computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0160] An embodiment of the present disclosure further provides a computer program product, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program implements the steps of the above method when executed by a processor.

[0161] Figure 4 1 is a block diagram of a self-recovery device 1900 for a multi-core decoding system according to an exemplary embodiment. For example, the device 1900 can be provided as a server or a terminal device. Figure 4 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0162] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , MacOS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0163] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the apparatus 1900 to perform the above-described method.

[0164] A computer-readable storage medium can be a tangible device that can hold and store programs / instructions used by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0165] The computer programs (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0166] The computer program (or computer program instructions) for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, by utilizing state information of computer-readable program instructions to personalize and customize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0167] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0168] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0169] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0170] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0171] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0172] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0173] If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained the individual's separate consent before processing the sensitive personal information, and at the same time meet the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0174] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A self-recovery method for a multi-core decoding system, characterized in that: The multi-core decoding system includes a plurality of decoding cores, the plurality of decoding cores including a first decoding core, and the method includes: In response to a first decoding instance running on the first decoding core meeting a preset migration condition, determining a second decoding core from decoding cores in a schedulable state among the plurality of decoding cores; wherein the preset migration condition at least includes a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core; Creating a second decoding instance on the second decoding core according to decoding task-related parameters of the first decoding instance; Copying the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance; The second decoding instance is run through the second decoding core, a decoded data stream is returned to a decoding request source, and the second decoding instance is bound to the decoding request source.

2. The method according to claim 1, characterized in that The method further comprises at least part of: In response to receiving an error interrupt signal corresponding to the first decoding instance reported by the first decoding core, determining that a decoding exception occurs in the first decoding instance; In response to receiving an error interrupt signal corresponding to the first decoding core reported by the first decoding core, determining that a decoding exception occurs in the first decoding core; In response to detecting that a timeout occurs in the response of the first decoding core to the decoding command, it is determined that a decoding exception occurs in the first decoding core.

3. The method according to claim 1, characterized in that In the event that a decoding exception occurs in the first decoding instance, the preset migration condition further includes: The decoding exception of the first decoding instance occurs in the intra-frame coding frame decoding stage.

4. The method according to claim 3, characterized in that The method further comprises: In response to an exception occurring in decoding a non-intra-coded frame in the first decoding instance, a decoding result of a previous frame of the non-intra-coded frame is used as the decoding result of the non-intra-coded frame.

5. The method according to claim 1, wherein The method further comprises: In response to a decoding exception occurring in the first decoding core, setting the first decoding core to an unschedulable state; Resetting the first decoding core; The reset first decoding core is reset to a schedulable state.

6. The method according to claim 1, wherein The multi-core decoding system includes a host system, a bus, and a decoding device. The host system includes a decoding device driver. The decoding device includes a storage subsystem and the multiple decoding cores. The method is applied to the decoding device driver.

7. The method according to claim 1, characterized in that The decoding task related parameters include at least part of the following: video encoding format, resolution, frame rate, and code stream memory address.

8. The method according to claim 1, characterized in that The step of determining a second decoding core from the decoding cores in the schedulable state among the plurality of decoding cores includes: According to a preset load balancing strategy, a second decoding core is determined from the decoding cores in the plurality of decoding cores that are in a schedulable state.

9. A self-recovery device for a multi-core decoding system, characterized in that: The multi-core decoding system includes a plurality of decoding cores, the plurality of decoding cores including a first decoding core, and the apparatus includes: a first determining module configured to determine, in response to a first decoding instance running on the first decoding core satisfying a preset migration condition, a second decoding core from the plurality of decoding cores that are in a schedulable state; wherein the preset migration condition includes at least a decoding exception occurring in the first decoding instance or a decoding exception occurring in the first decoding core; a creation module, configured to create a second decoding instance on the second decoding core according to decoding task-related parameters of the first decoding instance; a copy module, configured to copy the code stream corresponding to the first decoding instance from the first memory space corresponding to the first decoding instance to the second memory space corresponding to the second decoding instance; The return and binding module is used to run the second decoding instance through the second decoding core, return the decoded data stream to the decoding request source, and bind the second decoding instance to the decoding request source.

10. A self-recovery device for a multi-core decoding system, comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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