Detection method and device of logic protection module, program product and electronic equipment

Abstract

The invention discloses a logic protection module detection method and device, a program product and electronic equipment. The method comprises the following steps: determining a first test process based on the model and the component version of a to-be-tested module, and determining a second test process based on the logic version of the to-be-tested module; the method comprises the following steps: performing function test on X channels of a to-be-tested module according to a first test process through a first circuit to obtain a first test result, and performing logic test and pulse width test on the to-be-tested module according to a second test process through a second circuit to obtain a second test result, and determining a detection result of the to-be-tested module based on the first test result and the second test result. The technical problem that when the logic protection module is detected based on the prior art, a logic operation part in the logic protection module needs to be skipped, and an output channel of the logic protection module is directly controlled, so that the detection accuracy is low is solved.

Description

Technical Field

[0001] The present application relates to the field of distributed technology, and in particular to a detection method, device, program product, and electronic device for a logic protection module. Background Art

[0002] With the development of distributed technology, DCS (distributed control systems) systems have been widely used in the fields of automation control in electric power, petroleum, chemical industry, steel, papermaking, cement, desulfurization, dust removal and water treatment. The DCS system is a multi-level computer system composed of process control level and process monitoring level with a communication network as the link. It integrates computer (Computer), communication (Communication), display (CRT) and control (Control) technologies. Its basic concept is decentralized control, centralized operation, hierarchical management, flexible configuration and convenient configuration.

[0003] On the other hand, the inspection technology of DCS systems has developed accordingly. DCS systems often have dozens of cabinets, or even hundreds or even thousands of cabinets. In order to check the quality of DCS system cards, traditional inspection instruments can allow users to quickly detect the operating status of cards on site and detect potential fault hazards of LP (Logic Protection) modules in the DCS system.

[0004] However, traditional spot inspection instruments only test the general functions of LP modules and can only check the basic on / off functions of the LP module's input channels (Digital Input, abbreviated as DI) and output channels (Digital Output, abbreviated as DO). Due to the different internal operating logic of different LP modules, traditional spot inspection instruments often issue debugging instructions from the controller during testing, skipping the logic content in the LP module and directly operating the final output DO point for testing. This approach cannot detect the quality of the LP module's internal logic or the logic action time, resulting in technical problems such as low accuracy in LP module testing.

[0005] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0006] The present application provides a detection method, device, program product and electronic device for a logic protection module, so as to at least solve the technical problem of low detection accuracy caused by the need to skip the logical operation part inside the logic protection module and directly control the output channel of the logic protection module when detecting the logic protection module based on the existing technology.

[0007] According to one aspect of the present application, a detection method for a logic protection module is provided, comprising: determining a first test process based on the model and component version of the module to be tested, and determining a second test process based on the logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system; performing a functional test on X channels of the module to be tested according to the first test process by a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit, and a generator, the generator being configured to generate different types of test pulse signals, X being a positive integer, and the X channels including at least one of the following: an input channel, an output channel, and an event sequence recording channel; performing a logic test and a pulse width test on the module to be tested according to the second test process by a second circuit to obtain a second test result, wherein the second circuit is configured to simulate the circuit logic of the module to be tested; and determining a detection result of the module to be tested based on the first test result and the second test result.

[0008] Optionally, the step of determining the second test process based on the logic version of the module to be tested includes: determining the logic configuration file of the module to be tested based on the logic version of the module to be tested; determining first information and second information based on the logic configuration file, wherein the first information is used to characterize the combinational logic of the module to be tested, and the second information is used to characterize the timing logic of the module to be tested; determining the second test process based on the first information and the second information.

[0009] Optionally, the step of performing functional testing on X channels of the module to be tested according to the first test process through the first circuit to obtain a first test result includes: disconnecting the input channel through the first circuit, and taking the collected voltage and the number of communication points connected to the input channel as the first sub-result; closing the input channel through the first circuit, and taking the collected current and the number of communication points connected to the input channel as the second sub-result; switching the module to be tested to a preset mode through the first circuit, setting the output channel to a low-level state, and taking the collected voltage as the third sub-result; switching the module to be tested to a preset mode through the first circuit, setting the output channel to a high-level state, connecting a test resistor, and taking the collected voltage and current as the fourth sub-result; and determining the first test result based on the first sub-result, the second sub-result, the third sub-result, and the fourth sub-result.

[0010] Optionally, the step of performing a functional test on X channels of the module to be tested according to the first test process through the first circuit to obtain a first test result includes: executing a preset operation on the L event sequence recording channels of the module to be tested through the first signal generated by the first circuit, and taking the action response time and system clock of each event sequence recording channel collected as the fifth sub-result, wherein L is a positive integer, the first signal is used to determine the action interval duration between adjacent event sequence recording channels, and the preset operation is an open operation or a closed operation; executing a preset operation on the L event sequence recording channels of the module to be tested through the second signal generated by the first circuit, and taking the action response time and system clock of each event sequence recording channel collected as the sixth sub-result, wherein the action interval duration corresponding to the second signal is less than the action interval duration corresponding to the first signal; and determining the first test result based on the fifth sub-result and the sixth sub-result.

[0011] Optionally, the step of performing a logic test and a pulse width test on the module to be tested according to the second test process through the second circuit to obtain a second test result includes: generating M groups of test data through the second circuit, wherein M is a positive integer, and the M groups of test data are used to cover different combinational logic input scenarios of the module to be tested; inputting each group of test data into the module to be tested for logic operation to obtain third data, wherein the third data is the result of the combinational logic operation performed by the module to be tested based on each group of test data; inputting the third data into the target trigger to obtain fourth data, wherein the target trigger is used to perform a reset operation, and the fourth data is the output result of the target trigger; inputting the fourth data into the output delay module to obtain fifth data, wherein the output delay module is used to remove noise data in the input data of the module to be tested; and determining the second test result based on the fifth data.

[0012] Optionally, the step of determining the second test result based on the fifth data includes: controlling the pulse generator in the module to be tested to generate a target signal based on the fifth data, wherein the target signal is a signal generated by the module to be tested based on a set of test data; determining sixth data based on the target signal through a second circuit, wherein the sixth data includes at least the hardware response time, logic processing time, output delay time and actual pulse width of the target signal during the process of the module to be tested performing a logic action; and determining the second test result based on the target signal and the sixth data.

[0013] Optionally, the step of determining the second test result based on the target signal and the sixth data includes: taking the moment when the test data corresponding to the target signal is input into the module to be tested as the first moment; taking the moment when the target signal is generated as the second moment; taking the interval between the first moment and the second moment as the test duration; and determining the second test result based on the test duration and the sixth data.

[0014] According to another aspect of the present application, a detection device for a logic protection module is also provided, including: a first determination unit, configured to determine a first test process based on the model and component version of the module to be tested, and to determine a second test process based on the logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system; a first test unit, configured to perform a functional test on X channels of the module to be tested according to the first test process through a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit, and a generator, the generator being configured to generate different types of test pulse signals, X being a positive integer, and the X channels including at least one of the following: an input channel, an output channel, and an event sequence recording channel; a second test unit, configured to perform a logic test and a pulse width test on the module to be tested according to the second test process through a second circuit to obtain a second test result, wherein the second circuit is configured to simulate the circuit logic of the module to be tested; and a second determination unit, configured to determine the detection result of the module to be tested based on the first test result and the second test result.

[0015] According to another aspect of the present application, a computer program product is provided, in which a computer program is stored. When the computer program is running, the computer program product is controlled to execute any one of the above-mentioned detection methods for the logic protection module.

[0016] According to another aspect of the present application, an electronic device is also provided, wherein the electronic device includes one or more processors and a memory, the memory being used to store one or more programs, wherein when the one or more programs are executed by one or more processors, the one or more processors implement any of the above-mentioned detection methods for the logic protection module.

[0017] In the present application, a first test process is first determined based on the model and component version of the module to be tested, and a second test process is determined based on the logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system. Afterwards, the present application performs a functional test on X channels of the module to be tested according to the first test process through a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit and a generator, the generator is used to generate different types of test pulse signals, X is a positive integer, and the X channels include at least one of the following: an input channel, an output channel and an event sequence recording channel, and the present application performs a logic test and a pulse width test on the module to be tested according to the second test process through a second circuit to obtain a second test result, wherein the second circuit is used to simulate the circuit logic of the module to be tested. Finally, the present application determines the detection result of the module to be tested based on the first test result and the second test result.

[0018] From the above content, it can be seen that this application determines the first test process and the second test process by analyzing the model, component version and logic version of the logic protection module (i.e., the module to be tested). Subsequently, this application executes the test content corresponding to the first test process through the first circuit, and executes the test content corresponding to the second test process through the second circuit, thereby achieving the purpose of comprehensively testing the conventional functions and logic protection functions of the logic protection module through the first circuit and the second circuit.

[0019] It can be seen that compared with the prior art, the present application can not only perform conventional functional tests on the logic protection module through the first circuit, but also perform logic tests and pulse width tests on the logic protection module through the second circuit, thereby filling the gap in the test of the logical operation part inside the logic protection module in the prior art, thereby achieving the technical effect of improving the test accuracy of the logic protection module, and further solving the technical problem of low detection accuracy caused by the need to skip the logical operation part inside the logic protection module and directly control the output channel of the logic protection module when testing the logic protection module based on the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 This is a frame diagram of an optional LP spot checker;

[0022] Figure 2 is a framework diagram of an optional detection system for a logic protection module according to an embodiment of the present application;

[0023] Figure 3 is a flow chart of an optional detection method of a logic protection module according to an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of an optional detection device for a logic protection module according to an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] It should also be noted that the relevant information (including but not limited to information used for display and analysis) and data (including but not limited to the model, component version, and logic version data of the module to be tested) involved in this application are all information and data authorized by the user or fully authorized by all parties. For example, an interface is set up between this system and the relevant user or organization. Before obtaining relevant information, it is necessary to send an acquisition request to the aforementioned user or organization through the interface, and obtain the relevant information after receiving the consent information fed back by the aforementioned user or organization.

[0029] In addition, the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant information and data involved in this application comply with the relevant laws, regulations and standards of the relevant regions, and necessary confidentiality measures have been taken, and do not violate public order and good morals. In addition, this application provides corresponding operation entrances for users to choose to agree to authorization or refuse authorization. If the user chooses to refuse authorization, he / she will enter the corresponding expert decision-making process.

[0030] The LP modules involved in this application are introduced as follows:

[0031] The main input signal of the LP module is the switch dry contact DI signal. DI usually has 24 channels, 32 channels, 48 ​​channels, etc. Then, the LP inspection instrument uses the internally set logic (updated in advance or online according to user needs, so the logic of each user is different) to drive specific switch outputs (usually relay outputs) according to different input combinations, including but not limited to AND, OR, NOT, three-choose-two, four-choose-two, delay, RS trigger (Reset-Set, set-reset), and other different logic combinations. DO has 6 independent channels. For example, the three-choose-two logic is as follows: select two from three among DI0, DI1, and DI2, and then perform AND logic with DI3, and then drive DO0 output. The LP module is an important module in the DCS system, mainly responsible for processing fast cutting and tripping signals.

[0032] In an optional embodiment, Figure 1 This is a frame diagram of an optional LP spot checker, such as Figure 1 As shown, the LP inspection instrument includes a communication module, a control module, a switch on-off control module, a sequence generator, a switch on-off detection module and multiple loop support multi-block modules, wherein the multiple loop support multi-block modules are used to enhance the parallel testing capability and flexibility of the inspection instrument.

[0033] However, these LP testers typically only test the general functions of the LP module, and can only check the basic on / off functions of the LP module's input and output channels. Because different LP modules have different internal operating logic, traditional testers often issue debugging instructions from the controller during testing, skipping the logic content in the LP module and directly operating the final output DO point. This approach cannot detect the quality of the LP module's internal logic or the timing of logical operation.

[0034] Therefore, testing the LP module using the LP spot inspection instrument in the prior art may have the following hidden dangers:

[0035] 1) Logic error: An on-site LP module does not have only one logic element; there may be multiple logic elements installed mixed up.

[0036] 2) Slow action time of logic elements: As the device ages, the action response time of the LP module may become slower and fail to meet business needs.

[0037] 3) SOE (Sequence of Event) event recording error: The LP module has SOE function, including multiple SOE channels. The LP module may have the problem of confusing multiple event sequence records.

[0038] According to an embodiment of the present application, an embodiment of a detection method for a logic protection module is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0039] The present application provides a detection system for a logic protection module (hereinafter referred to as the detection system) for executing the detection method for the logic protection module in the present application. Figure 2 is a framework diagram of a detection system for an optional logic protection module according to an embodiment of the present application, such as Figure 2 As shown, the detection system includes a computer and a spot inspection instrument.

[0040] Optionally, the computer is used to run the host computer software to perform spot inspection operations, that is, it is responsible for starting and stopping the spot inspection instrument, judging the correctness of the test data, and generating the spot inspection test report.

[0041] Optionally, the inspection instrument includes: a communication circuit, a conventional detection circuit (ie, a first circuit) and a logic test circuit (ie, a second circuit).

[0042] Optionally, the communication circuit is used to communicate data with the computer and the module to be tested, and can read information such as the model, component version, and logic version of the module to be tested.

[0043] Optionally, the conventional detection circuit includes: a voltage sampling circuit, a current sampling circuit, an ADC (Analog Digital Converter) circuit, a channel switching circuit and an SOE generator.

[0044] Optionally, a voltage sampling circuit is used to check the query voltage of the DI and the drive voltage of the DO in the LP module; a current sampling circuit is used to detect the minimum current of the DI and the drive current of the DO in the LP module; an ADC circuit is used for digital-to-analog signal conversion; a channel switching circuit is used to switch the channel to be tested; and an SOE generator is used to generate a sequence of sequential events and adjust the time intervals between sequentially occurring events, including a time sequence with a time interval of 0.5ms and a time sequence with a time interval of 1.5ms. Through different sequential event sequences, combined with a high-frequency jitter generator, the SOE filtering time can be detected.

[0045] Optionally, the ADC circuit is preferably set to ADS8320, which can collect voltage signals from 0 to 2.5V.

[0046] Optionally, the channel switching circuit is preferably set to MUX508.

[0047] Optional logic test circuit: This circuit simulates the logic of the module under test, tests the corresponding switching channels based on the logic, and records the actuation time to ensure the normal operation of the field protection function. The logic test circuit tests the module logic in detail to avoid faults and hidden dangers such as module logic errors and incorrect actuation time.

[0048] Optionally, the inspection instrument further includes a control module and multiple loops supporting multiple modules, wherein the control module adopts FPGA (Field-Programmable Gate Array) and MCU (Microcontroller Unit) structures.

[0049] Optionally, the FPGA preferably uses the Lattice LCMXO2-2000HC, which is responsible for logic detection and action time measurement; the MCU preferably uses the M0516LDN, which can drive the ADC circuit sampling.

[0050] Optionally, multiple loops support multiple modules for supporting simultaneous testing of multiple LP modules, with up to eight LP modules being tested simultaneously.

[0051] In an optional embodiment, Figure 3 is a flow chart of an optional detection method of a logic protection module according to an embodiment of the present application, such as Figure 3 As shown, the method includes the following steps:

[0052] Step S301 : determining a first test process based on the model and component version of the module to be tested, and determining a second test process based on the logic version of the module to be tested.

[0053] In step S301 , the module to be tested is a logic protection module in a distributed control system.

[0054] Optionally, the above-mentioned first test process is executed through a first circuit, which at least includes a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit (i.e., an ADC circuit), a channel switching circuit, and a generator (i.e., an SOE generator).

[0055] Optionally, the second test process is executed by a second circuit, and the second circuit is used to simulate the circuit logic of the module to be tested.

[0056] Optionally, the detection system analyzes the model, component version and logic version of the module to be tested, thereby generating a first test process based on the model and component version of the module to be tested, and generating a second test process based on the logic version of the module to be tested, providing a test data basis for subsequent routine functional testing and logic testing of the module to be tested.

[0057] Step S302 : performing a functional test on X channels of the module to be tested according to a first test process by using a first circuit to obtain a first test result.

[0058] In step S302, the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit, and a generator, wherein the generator is used to generate different types of test pulse signals, X is a positive integer, and the X channels include at least one of the following: an input channel, an output channel, and an event sequence recording channel.

[0059] Optionally, a voltage sampling circuit is used to check the query voltage of the DI and the drive voltage of the DO in the LP module; a current sampling circuit is used to detect the minimum current of the DI and the drive current of the DO in the LP module; an ADC circuit is used for digital-to-analog signal conversion; a channel switching circuit is used to switch the channel to be tested; and an SOE generator is used to generate a sequence of sequential events and adjust the time intervals between sequentially occurring events, including a time sequence with a time interval of 0.5ms and a time sequence with a time interval of 1.5ms. Through different sequential event sequences, combined with a high-frequency jitter generator, the SOE filtering time can be detected.

[0060] Optionally, the detection system performs functional testing on X channels of the LP module according to a first test process through a first circuit, thereby ensuring that basic input and output functions of the LP module that passes the test operate correctly. The first test process includes at least verification steps of query voltage detection, drive voltage detection, current detection, and SOE time recording functions, thereby ensuring that the LP module that passes the test can meet the most basic on-off function requirements.

[0061] Step S303 : performing a logic test and a pulse width test on the module to be tested according to a second test flow through a second circuit to obtain a second test result.

[0062] In step S303 , the second circuit is used to simulate the circuit logic of the module to be tested.

[0063] Optionally, the detection system performs a logic test and a pulse width test on the module to be tested according to a second test process through a second circuit, that is, verifies the internal logic processing capability of the LP module and the accuracy of the output signal. The logic test step in the second test process can ensure that the internal logic operation of the verified LP module is correct, and the pulse width test step in the second test process can ensure that the delay of the output signal meets the design requirements.

[0064] Step S304: Determine the detection result of the module to be tested based on the first test result and the second test result.

[0065] Optionally, when both the first test result and the second test result are consistent with preset results, it is determined that the module to be tested has passed the detection.

[0066] Optionally, through the above test steps, the detection system can comprehensively evaluate the performance of the LP module, not only checking its basic on-off functions, but also deeply verifying the logic processing capabilities and output signal accuracy of the LP module, thereby ensuring the reliability and safety of key protection functions in the DCS system.

[0067] From the above content, it can be seen that this application determines the first test process and the second test process by analyzing the model, component version and logic version of the logic protection module (i.e., the module to be tested). Subsequently, this application executes the test content corresponding to the first test process through the first circuit, and executes the test content corresponding to the second test process through the second circuit, thereby achieving the purpose of comprehensively testing the conventional functions and logic protection functions of the logic protection module through the first circuit and the second circuit.

[0068] It can be seen that compared with the prior art, the present application can not only perform conventional functional tests on the logic protection module through the first circuit, but also perform logic tests and pulse width tests on the logic protection module through the second circuit, thereby filling the gap in the test of the logical operation part inside the logic protection module in the prior art, thereby achieving the technical effect of improving the test accuracy of the logic protection module, and further solving the technical problem of low detection accuracy caused by the need to skip the logical operation part inside the logic protection module and directly control the output channel of the logic protection module when testing the logic protection module based on the prior art.

[0069] In an optional embodiment, the detection system first determines the logic configuration file of the module to be tested based on the logic version of the module to be tested. Then, the detection system determines the first information and the second information based on the logic configuration file, wherein the first information is used to characterize the combinational logic of the module to be tested and the second information is used to characterize the timing logic of the module to be tested. Then, the detection system determines the second test process based on the first information and the second information.

[0070] Optionally, the logic version refers to an internal logic identification number of the LP module. Since each LP module is configured with different logic according to user requirements, a specific logic configuration file can be identified and matched based on the identification number.

[0071] Optionally, the detection system first reads the internal logic identification number of the LP module through a computer and finds the logic configuration file corresponding to the internal logic identification number. The configuration file has been placed in the computer software when the detection system leaves the factory. At the same time, the user can also update the logic configuration file of the new type of LP module and store it in the computer, read the logic configuration file through the computer, and then send the configuration file to the corresponding inspection instrument and burn the FPGA on the inspection instrument.

[0072] Optionally, the logic configuration file contains various logic rules preset by the LP module, including but not limited to logical combinations such as AND, OR, NOT, three-choose-two, four-choose-two, and delay, as well as trigger settings. The logic configuration file is a blueprint of the module's logical behavior and is used to guide the detection system to perform logic testing.

[0073] Optionally, after reading the logic configuration file through a computer, the internal logic of the LP is decomposed based on the logic configuration file to obtain combinational logic (i.e., first information) and sequential logic (second information). The combinational logic represents that the logic output depends only on the input at that moment and is independent of the previous state, including "AND", "OR" and "NOT" logic, etc.; the sequential logic is not only related to the input at that moment, but also to the previous historical input, including D flip-flops, RS flip-flops and delay logic, etc. The logic of the LP module is generally the combinational logic of the input signal followed by a flip-flop (for reset and self-locking), and then the output is delayed by the delay logic, and a "1" signal output of several hundred milliseconds to several seconds is generated by the pulse generation module. The FPGA tests the logic of the target module according to the new logic.

[0074] Optionally, the detection system helps the inspection instrument build a test scenario by parsing the first information and the second information representing specific logic rules from the logic configuration file, simulating the expected output of the LP module under different input states, especially those complex logics involving time delays and historical states, thereby ensuring that the inspection instrument can fully cover the logic function test of the LP module based on the second test process.

[0075] In an optional embodiment, the detection system first disconnects the input channel through the first circuit, and takes the collected voltage and the number of communication points connected to the input channel as the first sub-result. Afterwards, the detection system closes the input channel through the first circuit, and takes the collected current and the number of communication points connected to the input channel as the second sub-result. Then, the detection system switches the module to be tested to a preset mode through the first circuit, sets the output channel to a low level state, and takes the collected voltage as the third sub-result.

[0076] Next, the detection system switches the module to be tested to a preset mode through the first circuit, sets the output channel to a high level state, connects the test resistor, and uses the collected voltage and current as the fourth sub-result. Finally, the detection system determines the first test result based on the first sub-result, the second sub-result, the third sub-result, and the fourth sub-result.

[0077] For example, during the execution of the first test flow for the first circuit, the steps involved in the conventional functional test are as follows:

[0078] 1) Check DI general functions:

[0079] 1.1) Disconnect the DI channel and check the query voltage on the channel. The DI query voltage is generally 24V or 48V. By reading the LP module type, its query voltage can be known. Through voltage sampling, it should be no less than 22V or 45V. Otherwise, the module is judged to be faulty. At this time, it is also necessary to determine whether the DI communication point corresponding to the LP module (that is, the number of communication points connected to the input channel) is 0.

[0080] 1.2) Close the DI channel and detect the current on the test path. It should usually be between 3.5mA and 4mA. If it exceeds this range, it should be judged as a module failure. At this time, the DI communication point of the LP module should also be judged to be 1.

[0081] 2) Check DO general functions:

[0082] 2.1) Set the LP module to debug mode, breaking away from the original logic. That is, directly operate the DO on and off of the LP module through the computer. The DO channel is a wet node. When "0", there is no voltage output, and when "1", there is a 24V voltage output.

[0083] 2.2) Set the DO channel of the LP module to "0" and detect the voltage on the channel. It should be less than 0.1V, otherwise the module is judged to be faulty.

[0084] 2.3) Set the DO channel of the LP module to "1" and test the voltage on the channel. It should be greater than 22V, otherwise the module is faulty. After connecting the test resistor and current detection module, the theoretical current should be 100mA, and the actual current of the test channel should be between 90 and 110mA. Otherwise, the module is faulty.

[0085] Optionally, by disconnecting the DI channel and detecting the query voltage, the inspection instrument can determine whether the query voltage of the LP module is within the normal range, and whether the communication point of the DI channel in the disconnected state correctly reflects the disconnected state, which is used to detect the basic functional status of the DI channel of the LP module.

[0086] Optionally, when the DI channel is in a closed state, the current intensity passing through the channel and whether the DI channel communication point correctly reflects the closed state are detected to verify the working condition of the DI channel of the LP module when there is a signal input.

[0087] Optionally, by placing the LP module in debug mode, setting its DO channel to a low level, and detecting whether the voltage on the channel is lower than a threshold, confirm whether the DO channel of the LP module behaves normally in the low-level state to avoid potential problems such as short circuits or power leakage.

[0088] Optionally, when the DO channel is set to a high level, connect a test resistor and detect the voltage and current to verify the driving capability and stability of the DO channel in the high-level state, ensuring that the LP module can correctly drive external loads such as relays.

[0089] In summary, the detection system comprehensively analyzes the four sub-results to form the first test result on the basic functions of the LP module's DI and DO channels. That is, by comparing the test data with the expected standard values, it determines whether the LP module's input and output channels are functioning properly. This includes querying the rationality of the voltage and drive voltage, whether the current size meets the specification, and whether the DO channel's performance is stable in high and low voltage states, thereby determining the health of the LP module at the general functional level.

[0090] In an optional embodiment, the detection system first performs a preset operation on the L event sequence recording channels of the module to be tested through the first signal generated by the first circuit, and takes the collected action response time and system clock of each event sequence recording channel as the fifth sub-result, wherein L is a positive integer, the first signal is used to determine the action interval duration between adjacent event sequence recording channels, and the preset operation is an open operation or a closed operation. Afterwards, the detection system performs a preset operation on the L event sequence recording channels of the module to be tested through the second signal generated by the first circuit, and takes the collected action response time and system clock of each event sequence recording channel as the sixth sub-result, wherein the action interval duration corresponding to the second signal is less than the action interval duration corresponding to the first signal. Finally, the detection system determines the first test result based on the fifth sub-result and the sixth sub-result.

[0091] Optionally, the preset operation is to send an open or close command to the SOE channel to simulate the signal input change in actual operation.

[0092] Optionally, the action interval duration refers to the time difference between actions (ie, recording state changes) between adjacent SOE channels under the control of the first signal, and is used to verify the accuracy of the SOE function.

[0093] For example, during the second test process of the second circuit, the logic test steps involved are as follows:

[0094] 1.1) Generate a channel sequence, starting with channel 1. After closing channel 1, close channel 2 after a 0.5ms interval, and so on, to complete the closure of all channels. Determine the difference between the SOE data and the system clock based on the communication return data. The difference between the SOE data channels should be within 1.2ms. Then, open the SOE channel in a 1.5ms sequence. Determine the difference between the SOE data and the system clock based on the communication return data. The difference between the SOE data channels should be within 1.2ms. Otherwise, it is judged as a module failure.

[0095] 1.2) Generate a 10ms high-frequency jitter interference pulse to check whether the SOE module is working correctly. If there is a false alarm, it is judged to be a module failure.

[0096] Optionally, under the control of the first signal, when the SOE channel receives an open or close operation, the detection system can accurately record and report the time of the state change. By comparing the difference between the actual action response time of each SOE channel and the system clock, the detection system can evaluate whether the SOE function of the LP module meets the expected time accuracy requirements.

[0097] Optionally, the detection system can test whether the SOE function can correctly distinguish and record the sequence of events under high-speed state changes by using a second signal to simulate faster signal changes, which helps to discover possible capture delays or omissions.

[0098] In an optional embodiment, the detection system first generates M groups of test data through the second circuit, where M is a positive integer, and the M groups of test data are used to cover different combinational logic input scenarios of the module to be tested. Afterwards, the detection system inputs each group of test data into the module to be tested for logical operation to obtain third data, wherein the third data is the result of the combinational logic operation performed by the module to be tested based on each group of test data. Then, the detection system inputs the third data into the target trigger to obtain fourth data, wherein the target trigger is used to perform a reset operation, and the fourth data is the output result of the target trigger. In addition, the detection system inputs the fourth data into the output delay module to obtain fifth data, wherein the output delay module is used to remove noise data in the input data of the module to be tested. Finally, the detection system determines the second test result based on the fifth data.

[0099] For example, the detection system first analyzes the combinational logic part and tests it according to different input conditions based on its logical content. The test needs to be in place. For example, the "AND" and "OR" logic of two channel data needs to test "0" + "0"; "0" + "1"; "1" + "0"; "1" + "1" and other situations; if the "AND" and "OR" logic of multiple channel data, the values ​​of other channels are locked to all "0" and "1" and tested in the same way, "0" + all "0"; "0" + all "1"; "1" + all "0"; "1" + all "1" and other situations; if three-choose-two, A+B; B+C; A+C are tested respectively. After that, all required combination information is tested to ensure logical correctness.

[0100] Then, the result of the combinational logic operation is input into a D flip-flop or an RS flip-flop. The flip-flop is mainly used for reset. When the reset signal exists, the input logic is invalid and the output is always 0; when the reset signal does not exist, the output is equal to the input.

[0101] Afterwards, the output data of the trigger is input to the output delay module. After the combinational logic result changes, the output delay module performs a delay. If the combinational logic recovers during the delay process, no output data will be generated.

[0102] Optionally, the detection system generates M groups of test data simulating all combinational logic inputs that may be encountered in actual operation based on the second test process through the second circuit, thereby ensuring that the inspection instrument can comprehensively detect the logic processing function of the LP module, wherein each group of test data simulates a specific logic input scenario, thereby being able to verify the response of the LP module under different logic combinations.

[0103] Optionally, the detection system inputs M groups of test data into the LP module one by one, allowing the module to perform its internal combinational logic operations to obtain third data, that is, the actual output of the module under different logic input scenarios. This step directly tests the logic processing function of the LP module and verifies whether it can correctly generate output signals according to preset logic rules.

[0104] Optionally, the testing system verifies the module's ability to perform a reset operation based on the result of a logic operation by passing third data to a target flip-flop. The target flip-flop should ensure that, when the reset signal is present, the LP module's output returns to a safe state, regardless of the result of the logic operation. This step verifies the LP module's safety and the integrity of its logic processing.

[0105] Optionally, the detection system further verifies the stability and accuracy of the LP module output signal by inputting the fourth data into the output delay module. The function of the output delay module is not limited to delay. More importantly, it provides a mechanism to ensure that the output signal eliminates possible transient noise effects after the necessary delay and achieves the expected stable output state.

[0106] In summary, the above test steps can fully detect the core logic processing and safety control functions of the LP module, ensuring that it can accurately and promptly respond to various logic inputs, perform necessary reset operations, and provide stable output signals in actual applications to ensure the normal operation and safety of the DCS system.

[0107] In an optional embodiment, the detection system first controls the pulse generator in the module to be tested to generate a target signal based on fifth data, wherein the target signal is a signal generated by the module to be tested based on a set of test data. Afterwards, the detection system determines sixth data based on the target signal through a second circuit, wherein the sixth data includes at least the hardware response time, logic processing time, output delay time and actual pulse width of the target signal during the process of the module to be tested executing the logic action. Finally, the detection system determines the second test result based on the target signal and the sixth data.

[0108] For example, a pulse generator generally generates a pulse for a set time after the logic output is "1" (generally only for "1" and not for "0"). It remains "1" during this set time and is locked to "0" after the time is up. Even if the input logic has not changed at this time, the lock is released after the input changes, and the pulse will be reactivated if the input changes subsequently.

[0109] Optionally, the pulse generator is a functional unit inside the LP module, which is used to generate a pulse signal with a certain width according to the result of the logic operation, and is usually activated when the result of the logic operation meets a certain condition.

[0110] Optionally, the detection system controls the pulse generator in the LP module to generate a target signal according to the indication of the fifth data. This process is intended to test whether the LP module can correctly generate a pulse signal of a predetermined width under the guidance of the logical operation result, and whether the timing of generating the pulse signal is in line with expectations.

[0111] Alternatively, the hardware response time refers to the time required for the LP module to receive an input signal and for the internal circuit to respond, reflecting the physical processing speed of the module.

[0112] Optionally, the logic processing time refers to the time required for the LP module to process input signals and perform logic operations, including the processing of combinational logic and sequential logic.

[0113] Optionally, the output delay time refers to the time that the output delay module delays the logic operation result before the pulse is generated, which is used to eliminate noise and stabilize the output.

[0114] Optionally, the actual pulse width of the target signal, ie, the duration of the pulse in the target signal, is compared with the preset pulse width of the LP module to evaluate the accuracy of the pulse generator.

[0115] Optionally, the detection system monitors and records the target signal generation process using the second circuit based on the second test process, including key indicators such as hardware response time, logic operation time, output delay time, and pulse width. The sixth data contains all necessary information for evaluating the integrity of the LP module's logical operations. This data can be used to check whether the LP module's total response time meets the required response time when processing logical operations, as well as whether the pulse signal quality meets the required requirements.

[0116] Optionally, the aforementioned test steps are intended to thoroughly examine the dynamic performance of the LP module, particularly its ability to process logical actions and generate pulse signals. Through precise measurement and analysis, the inspection instrument can determine whether the LP module can quickly and accurately generate pulse signals of a preset width while ensuring logical correctness, thereby meeting the stringent industrial requirements for response speed and signal quality.

[0117] In an optional embodiment, the detection system first uses the moment when the test data corresponding to the target signal is input into the module to be tested as the first moment. Thereafter, the detection system uses the moment when the target signal is generated as the second moment. Then, the detection system uses the interval between the first moment and the second moment as the test duration. Finally, the detection system determines the second test result based on the test duration and the sixth data.

[0118] For example, based on the above information, applying the required combinational logic to the DI input generates intermediate result 1. Then, based on the state of the RS flip-flop, intermediate result 2 is further generated. Delays and pulses are used to generate intermediate result 3. The final result is the output DO signal. By measuring the time between the final DO signal and the input DI signal, the correctness of the entire processing process can be determined. For example, if the logic is ANDed with DI0 and DI1, a high-level "1" is generated after a 500ms delay through the RS flip-flop, and the "1" pulse lasts for 300ms. The test process involves applying 0+0, 0+1, 1+0, and 1+1 to DI0 and DI1, respectively, and using the FPGA to record the time it takes from the input signal change to the output signal change. The theoretical time should be 500ms + 30ms (hardware response time). If the delay time deviates by more than 20ms from this value, the module is considered faulty. In the above use case, 0+0 should remain at "0" after 550ms, with no "1" generated. However, 1+1 should output "1" within 530-550ms. Then use FPGA to record the high-level pulse time, which should be within the theoretical time of 300ms±10ms, otherwise it is considered that the module is faulty.

[0119] Optionally, the detection system also needs to check the correctness of the reset logic. The LP module channel has a reset channel. When reset, the output is open and input changes of other channels are invalid.

[0120] Optionally, the test procedure described above combines the test duration (i.e., the time difference between the first and second moments) with the various time parameters in the sixth data, allowing the inspection instrument to determine the performance of the LP module when executing the logic processing action. The second test result will comprehensively reflect the LP module's logic processing speed, pulse generation accuracy, and overall process stability. Specifically, the inspection instrument compares the test duration with a preset time threshold, as well as the various indicators in the sixth data with standard values, to determine whether the LP module meets performance requirements and whether there are any issues such as logic processing delays, inaccurate pulse widths, or unstable output.

[0121] From the above content, it can be seen that this application determines the first test process and the second test process by analyzing the model, component version and logic version of the logic protection module (i.e., the module to be tested). Subsequently, this application executes the test content corresponding to the first test process through the first circuit, and executes the test content corresponding to the second test process through the second circuit, thereby achieving the purpose of comprehensively testing the conventional functions and logic protection functions of the logic protection module through the first circuit and the second circuit.

[0122] It can be seen that compared with the prior art, the present application can not only perform conventional functional tests on the logic protection module through the first circuit, but also perform logic tests and pulse width tests on the logic protection module through the second circuit, thereby filling the gap in the test of the logical operation part inside the logic protection module in the prior art, thereby achieving the technical effect of improving the test accuracy of the logic protection module, and further solving the technical problem of low detection accuracy caused by the need to skip the logical operation part inside the logic protection module and directly control the output channel of the logic protection module when testing the logic protection module based on the prior art.

[0123] According to another aspect of the embodiment of the present application, a detection device for a logic protection module is provided. Figure 4 is a schematic diagram of an optional detection device for a logic protection module according to an embodiment of the present application, such as Figure 4 As shown, the detection device of the logic protection module includes: a first determination unit 401 , a first testing unit 402 , a second testing unit 403 and a second determination unit 404 .

[0124] Optionally, a first determination unit 401 is used to determine a first test process based on the model and component version of the module to be tested, and to determine a second test process based on the logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system; a first test unit 402 is used to perform a functional test on X channels of the module to be tested according to the first test process through a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit and a generator, the generator is used to generate different types of test pulse signals, X is a positive integer, and the X channels include at least one of the following: an input channel, an output channel and an event sequence recording channel; a second test unit 403 is used to perform a logic test and a pulse width test on the module to be tested according to the second test process through a second circuit to obtain a second test result, wherein the second circuit is used to simulate the circuit logic of the module to be tested; a second determination unit 404 is used to determine the detection result of the module to be tested based on the first test result and the second test result.

[0125] In an optional embodiment, the first determining unit includes: a first determining subunit, a second determining subunit, and a third determining subunit.

[0126] Optionally, the first determination subunit is used to determine the logic configuration file of the module to be tested based on the logic version of the module to be tested; the second determination subunit is used to determine the first information and the second information based on the logic configuration file, wherein the first information is used to characterize the combinational logic of the module to be tested and the second information is used to characterize the timing logic of the module to be tested; the third determination subunit is used to determine the second test process based on the first information and the second information.

[0127] In an optional embodiment, the first test unit includes: a fourth determining subunit, a fifth determining subunit, a sixth determining subunit, a seventh determining subunit, and an eighth determining subunit.

[0128] Optionally, the fourth determination subunit is used to disconnect the input channel through the first circuit, and use the collected voltage and the number of communication points connected to the input channel as the first sub-result; the fifth determination subunit is used to close the input channel through the first circuit, and use the collected current and the number of communication points connected to the input channel as the second sub-result; the sixth determination subunit is used to switch the module to be tested to the preset mode through the first circuit, set the output channel to a low level state, and use the collected voltage as the third sub-result; the seventh determination subunit is used to switch the module to be tested to the preset mode through the first circuit, set the output channel to a high level state, connect the test resistor, and use the collected voltage and current as the fourth sub-result; the eighth determination subunit is used to determine the first test result based on the first sub-result, the second sub-result, the third sub-result and the fourth sub-result.

[0129] In an optional embodiment, the first testing unit further includes: a ninth determining subunit, a tenth determining subunit, and an eleventh determining subunit.

[0130] Optionally, the ninth determination subunit is used to perform a preset operation on the L event sequence recording channels of the module to be tested through the first signal generated by the first circuit, and to use the collected action response time and system clock of each event sequence recording channel as the fifth sub-result, wherein L is a positive integer, and the first signal is used to determine the action interval duration between adjacent event sequence recording channels, and the preset operation is an open operation or a closed operation; the tenth determination subunit is used to perform a preset operation on the L event sequence recording channels of the module to be tested through the second signal generated by the first circuit, and to use the collected action response time and system clock of each event sequence recording channel as the sixth sub-result, wherein the action interval duration corresponding to the second signal is less than the action interval duration corresponding to the first signal; the eleventh determination subunit is used to determine the first test result based on the fifth sub-result and the sixth sub-result.

[0131] In an optional embodiment, the second test unit includes: a test data generating subunit, a first input subunit, a second input subunit, a third input subunit and a twelfth determining subunit.

[0132] Optionally, a test data generation subunit is used to generate M groups of test data through a second circuit, wherein M is a positive integer, and the M groups of test data are used to cover different combinational logic input scenarios of the module to be tested; a first input subunit is used to input each group of test data into the module to be tested for logical operation to obtain third data, wherein the third data is the result of the combinational logic operation performed by the module to be tested based on each group of test data; a second input subunit is used to input the third data into a target trigger to obtain fourth data, wherein the target trigger is used to perform a reset operation, and the fourth data is the output result of the target trigger; a third input subunit is used to input the fourth data into an output delay module to obtain fifth data, wherein the output delay module is used to remove noise data in the input data of the module to be tested; a twelfth determination subunit is used to determine the second test result based on the fifth data.

[0133] In an optional embodiment, the twelfth determining subunit includes: a first signal generating module, a first determining module, and a second determining module.

[0134] Optionally, the first signal generating module is used to control the pulse generator in the module to be tested to generate a target signal based on fifth data, wherein the target signal is a signal generated by the module to be tested based on a set of test data; the first determining module is used to determine sixth data based on the target signal through the second circuit, wherein the sixth data includes at least the hardware response time, logic processing time, output delay time and actual pulse width of the target signal during the process of the module to be tested executing the logic action; the second determining module is used to determine the second test result based on the target signal and the sixth data.

[0135] In an optional embodiment, the second determination module includes: a first input submodule, a first determination submodule, a second determination submodule, and a third determination submodule.

[0136] Optionally, the first input submodule is used to take the moment when the test data corresponding to the target signal is input into the module to be tested as the first moment; the first determination submodule is used to take the moment when the target signal is generated as the second moment; the second determination submodule is used to take the interval between the first moment and the second moment as the test duration; and the third determination submodule is used to determine the second test result based on the test duration and the sixth data.

[0137] From the above content, it can be seen that this application determines the first test process and the second test process by analyzing the model, component version and logic version of the logic protection module (i.e., the module to be tested). Subsequently, this application executes the test content corresponding to the first test process through the first circuit, and executes the test content corresponding to the second test process through the second circuit, thereby achieving the purpose of comprehensively testing the conventional functions and logic protection functions of the logic protection module through the first circuit and the second circuit.

[0138] It can be seen that compared with the prior art, the present application can not only perform conventional functional tests on the logic protection module through the first circuit, but also perform logic tests and pulse width tests on the logic protection module through the second circuit, thereby filling the gap in the test of the logical operation part inside the logic protection module in the prior art, thereby achieving the technical effect of improving the test accuracy of the logic protection module, and further solving the technical problem of low detection accuracy caused by the need to skip the logical operation part inside the logic protection module and directly control the output channel of the logic protection module when testing the logic protection module based on the prior art.

[0139] According to another aspect of an embodiment of the present application, a computer program product is further provided. The computer program product includes a stored computer program, wherein when the computer program is running, the computer program product is controlled to execute any one of the above-mentioned logic protection module detection methods.

[0140] According to another aspect of an embodiment of the present application, an electronic device is also provided, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute any of the above-mentioned logic protection module detection methods by executing the executable instructions.

[0141] Optionally, Figure 5 is a schematic diagram of an optional electronic device according to an embodiment of the present application, such as Figure 5 As shown, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program stored in the memory and runnable on the processor. When the processor executes the program, the detection method of the logic protection module of any one of the above items is implemented.

[0142] The above-mentioned embodiments or examples disclosed in this application are not exhaustive, but are only illustrations of some embodiments or examples, and are not intended to be specific limitations on the scope of protection disclosed in this application. In the absence of contradiction, each step in a certain embodiment or example in this application can be implemented as an independent example, and the steps can be arbitrarily combined. For example, the solution after removing some steps in a certain embodiment or example can also be implemented as an independent example, and the order of the steps in a certain embodiment or example can be arbitrarily exchanged. In addition, the optional methods or optional examples in a certain embodiment or example can be arbitrarily combined; in addition, the various embodiments or examples can be arbitrarily combined. For example, some or all of the steps in different embodiments or examples can be arbitrarily combined, and a certain embodiment or example can be arbitrarily combined with the optional methods or optional examples of other embodiments or examples.

[0143] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0144] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1A step that specifies a function in one or more boxes.

[0147] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-permanent storage in a computer-readable medium, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0148] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0149] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0150] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A method for detecting a logic protection module, characterized in that: include: Determining a first test process based on the model and component version of a module to be tested, and determining a second test process based on the logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system; Performing a functional test on X channels of the module to be tested according to the first test process using a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit, and a generator, the generator being configured to generate different types of test pulse signals, X being a positive integer, and the X channels including at least one of the following: an input channel, an output channel, and an event sequence recording channel; performing a logic test and a pulse width test on the module to be tested according to the second test process by a second circuit to obtain a second test result, wherein the second circuit is used to simulate the circuit logic of the module to be tested; A detection result of the module to be tested is determined based on the first test result and the second test result.

2. The detection method of the logic protection module according to claim 1, characterized in that: Determining a second test process based on the logic version of the module to be tested includes: Determining a logic configuration file of the module to be tested based on a logic version of the module to be tested; Determining first information and second information based on the logic configuration file, wherein the first information is used to characterize the combinational logic of the module to be tested, and the second information is used to characterize the sequential logic of the module to be tested; The second test procedure is determined based on the first information and the second information.

3. The detection method of the logic protection module according to claim 1, characterized in that: Performing a functional test on the X channels of the module to be tested according to the first test process by the first circuit to obtain a first test result includes: disconnecting the input channel through the first circuit, and taking the collected voltage and the number of communication points connected to the input channel as a first sub-result; closing the input channel through the first circuit, and taking the collected current and the number of communication points connected to the input channel as a second sub-result; Switching the module to be tested to a preset mode through the first circuit, setting the output channel to a low level state, and using the collected voltage as a third sub-result; Switching the module to be tested to the preset mode through the first circuit, setting the output channel to a high level state, connecting a test resistor, and using the collected voltage and current as a fourth sub-result; The first test result is determined based on the first sub-result, the second sub-result, the third sub-result, and the fourth sub-result.

4. The detection method of the logic protection module according to claim 1, characterized in that: Performing a functional test on the X channels of the module to be tested according to the first test process by the first circuit to obtain a first test result includes: performing a preset operation on L event sequence recording channels of the module to be tested using a first signal generated by the first circuit, and using the collected action response time and system clock of each event sequence recording channel as a fifth sub-result, wherein L is a positive integer, the first signal is used to determine the action interval duration between adjacent event sequence recording channels, and the preset operation is an opening operation or a closing operation; performing the preset operation on the L event sequence recording channels of the module to be tested using the second signal generated by the first circuit, and using the collected action response time and system clock of each event sequence recording channel as a sixth sub-result, wherein the action interval duration corresponding to the second signal is less than the action interval duration corresponding to the first signal; The first test result is determined based on the fifth sub-result and the sixth sub-result.

5. The detection method of the logic protection module according to claim 1, characterized in that: Performing a logic test and a pulse width test on the module to be tested according to the second test process by a second circuit to obtain a second test result includes: Generate M groups of test data by the second circuit, where M is a positive integer, and the M groups of test data are used to cover different combinational logic input scenarios of the module to be tested; Inputting each set of test data into the module to be tested to perform a logic operation to obtain third data, wherein the third data is a result of the combinational logic operation performed by the module to be tested based on each set of test data; Inputting the third data into a target trigger to obtain fourth data, wherein the target trigger is used to perform a reset operation, and the fourth data is an output result of the target trigger; Inputting the fourth data into an output delay module to obtain fifth data, wherein the output delay module is used to remove noise data from the input data of the module to be tested; The second test result is determined based on the fifth data.

6. The detection method of the logic protection module according to claim 5, characterized in that: Determining the second test result based on the fifth data includes: controlling a pulse generator in the module to be tested to generate a target signal based on the fifth data, wherein the target signal is a signal generated by the module to be tested based on a set of test data; determining sixth data based on the target signal by the second circuit, wherein the sixth data includes at least a hardware response time, a logic processing time, an output delay time, and an actual pulse width of the target signal during the process of the module to be tested performing a logic action; The second test result is determined according to the target signal and the sixth data.

7. The detection method of the logic protection module according to claim 6, characterized in that: Determining the second test result according to the target signal and the sixth data includes: The moment when the test data corresponding to the target signal is input into the module to be tested is taken as the first moment; Taking the generation moment of the target signal as the second moment; The interval between the first moment and the second moment is used as the test duration; The second test result is determined based on the test duration and the sixth data.

8. A detection device for a logic protection module, characterized in that: include: A first determining unit is configured to determine a first test process based on a model and a component version of a module to be tested, and to determine a second test process based on a logic version of the module to be tested, wherein the module to be tested is a logic protection module in a distributed control system; a first testing unit, configured to perform a functional test on X channels of the module to be tested according to the first test process using a first circuit to obtain a first test result, wherein the first circuit includes at least a voltage sampling circuit, a current sampling circuit, an analog-to-digital conversion circuit, a channel switching circuit, and a generator, the generator being configured to generate different types of test pulse signals, X being a positive integer, and the X channels including at least one of the following: an input channel, an output channel, and an event sequence recording channel; a second testing unit, configured to perform a logic test and a pulse width test on the module to be tested according to the second testing process through a second circuit to obtain a second test result, wherein the second circuit is configured to simulate the circuit logic of the module to be tested; The second determining unit is configured to determine a detection result of the module to be tested based on the first test result and the second test result.

9. A computer program product, characterized in that The computer program product comprises a computer program, wherein when the computer program is run, the computer program product is controlled to execute the method for detecting a logic protection module according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The device comprises one or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the detection method of the logic protection module according to any one of claims 1 to 7.

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