AXI4Lite bus use optimization method and device and medium

Abstract

The invention discloses an AXI4Lite bus use optimization method, an AXI4Lite bus use optimization device and a medium. The method comprises the following steps: respectively acquiring signals sent by a write-in address channel and a write-in data channel in real time to obtain a data address write-in effective joint signal, writing the data address write-in effective joint signal and generating a write operation completion signal; when it is determined that the write operation completion signal is in an effective state, the write-in signals are processed through a write-in automatic response method, and automatic response of each channel signal is completed in combination with write-in anti-crash judgment logic; when it is determined that a reading operation completion signal is in an effective state, the reading signals are processed through a reading automatic response method, and automatic response of each channel signal is completed in combination with reading anti-crash judgment logic, so that writing of the AXI4Lite bus and use optimization of a reading channel are completed. The problems that the number of signal ports is large, use is complex and the difficulty is large are solved, the signal ports are simplified, and the use complexity and difficulty are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of communication protocol data processing, and in particular to an AXI4_Lite bus usage optimization method, device, and medium. Background Art

[0002] In the AXI bus, AXI4_Lite is a lightweight address-mapped single-transfer bus that can communicate on the device side or the server side. It occupies very few logic units and has the characteristics of low latency and low power consumption. It is suitable for simple, low-throughput memory-mapped communications, such as logic control and status registration.

[0003] In the process of realizing the present invention, the inventors found that the existing technology has the following defects: Currently, the communication of AXI4_Lite complies with the AXI4 specification, and each channel has an independent handshake mechanism. Therefore, the user needs to control more signal ports, which is more complicated and difficult to use, and the port usage flexibility is poor. Summary of the Invention

[0004] The present invention provides an AXI4_Lite bus usage optimization method, device and medium, so as to effectively simplify signal ports and reduce usage complexity and difficulty.

[0005] According to one aspect of the present invention, there is provided an AXI4_Lite bus usage optimization method, which includes: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel;

[0006] respectively obtaining the real-time signals emitted by the write address channel and the write data channel, and if the signals are valid signals, obtaining a data address write valid combined signal through a preset valid signal combination method, and writing the data address write valid combined signal if the data address write valid combined signal meets the validity condition, and generating a write operation completion signal;

[0007] When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel are processed respectively through a preset write automatic response method, and combined with the preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus;

[0008] Obtain and generate a read operation completion signal based on a read address valid signal in a read address channel;

[0009] When it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively through a preset read automatic response method, and combined with the preset read anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the read channel of the AXI4_Lite bus.

[0010] According to another aspect of the present invention, there is provided an AXI4_Lite bus usage optimization device, which includes: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel;

[0011] A write operation completion signal generation module is used to obtain the real-time signals emitted by the write address channel and the write data channel respectively. If the signals are valid signals, a data address write valid combined signal is obtained through a preset valid signal combination method. If the data address write valid combined signal meets the validity condition, the data address write valid combined signal is written and the write operation completion signal is generated.

[0012] A write channel usage optimization module is configured to process the readiness signals in the write address channel and the write data channel, and the feedback handshake valid signal in the write response channel respectively through a preset write automatic response method when determining that the write operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with a preset write anti-crash judgment logic to optimize the use of the write channel of the AXI4_Lite bus;

[0013] A read operation completion signal generating module is used to obtain and generate a read operation completion signal according to a read address valid signal in a read address channel;

[0014] The read channel usage optimization module is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a preset read automatic response method when determining that the read operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with the preset read anti-crash judgment logic to complete the usage optimization of the read channel of the AXI4_Lite bus.

[0015] According to another aspect of the present invention, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the AXI4_Lite bus usage optimization method according to any embodiment of the present invention is implemented.

[0016] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the AXI4_Lite bus usage optimization method described in any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present invention is to respectively obtain the signals emitted in real time by the write address channel and the write data channel. If the signals are valid signals, a data address write valid joint signal is obtained by a pre-set valid signal combination method. When the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written and a write operation completion signal is generated. When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel, are processed by a pre-set write automatic response method, and combined with a pre-set write anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the write channel of the AXI4_Lite bus. The read address valid signal in the read address channel is obtained and generated according to the read operation completion signal. When it is determined that the read operation completion signal is in a valid state, the read address ready signal in the read address channel and the read data valid signal in the read data channel are processed by a pre-set read automatic response method, and combined with a pre-set read anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the read channel of the AXI4_Lite bus. The problem of too many signal ports, complicated use and high difficulty is solved, the signal ports are simplified, the complexity and difficulty of use are reduced, and the flexibility of port use is improved.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a flowchart of an AXI4_Lite bus usage optimization method provided according to the first embodiment of the present invention;

[0021] Figure 22 is a schematic diagram of the structure of an AXI4_Lite bus usage optimization device provided according to a second embodiment of the present invention;

[0022] Figure 3 It is a structural diagram of an electronic device provided according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "target", "current", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] Example 1

[0026] Figure 1 A flowchart of an AXI4_Lite bus usage optimization method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of optimizing the usage of an AXI4_Lite bus. The method can be performed by an AXI4_Lite bus usage optimization device, which can be implemented in the form of hardware and / or software.

[0027] Among them, the AXI4_Lite bus includes a write address channel, a write data channel, a write response channel, a read address channel and a read data channel.

[0028] Correspondingly, such as Figure 1 As shown, the method includes:

[0029] S110. Obtain the signals emitted in real time by the write address channel and the write data channel respectively. If the signals are valid signals, obtain a data address write valid joint signal through a preset valid signal combination method. When the data address write valid joint signal meets the validity condition, write the data address write valid joint signal and generate a write operation completion signal.

[0030] Optionally, the write address channel includes a write address ready signal and a write address valid signal; the write data channel includes a write data ready signal and a write data valid signal; the write response channel includes a feedback handshake ready signal and a feedback handshake valid signal; the read address channel includes a read address ready signal and a read address valid signal; the read data channel includes a read data ready signal and a read data valid signal.

[0031] In this embodiment, each channel in the AXI4_Lite bus includes different signals.

[0032] In addition, the write address channel also includes a write address channel address interface signal; the write data channel also includes a write data channel data interface signal; the read address channel also includes a read address channel address interface signal; the read data channel also includes a read data channel data interface signal and a read address channel response interface signal.

[0033] Optionally, the valid signal includes a write address valid signal and a write data valid signal; the signals emitted in real time by the write address channel and the write data channel are respectively obtained, and if the signal is a valid signal, a data address write valid joint signal is obtained through a preset valid signal combination method, and when the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written, and a write operation completion signal is generated, including: obtaining the signals emitted in real time by the write address channel and the write data channel respectively, and if the signal is a write address valid signal or a write data valid signal, the write address valid signal and the write data valid signal are combined and merged through a preset valid signal combination method to obtain a data address write valid joint signal; when the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written, and the data address write valid joint signal is delayed to generate a write operation completion signal.

[0034] Exemplarily, it is assumed that the write address valid signal is axi_awvalid; the write data valid signal is axi_wvalid; the data address write valid combined signal is wreq; and the write data channel data interface signal is axi_wdata.

[0035] Specifically, obtain the real-time signals emitted by the write address channel and the write data channel respectively. If the signals are axi_awvalid and axi_wvalid, it is necessary to combine axi_awvalid and axi_wvalid through the effective signal combination method to obtain wreq.

[0036] Furthermore, it is determined whether wreq is valid. When wreq meets the validity condition, axi_wdata on the data line needs to be written.

[0037] Accordingly, the data address write valid combined signal wreq is delayed to generate a write operation completion signal, which can be set to wack.

[0038] The advantage of this arrangement is that multiple interfaces can be represented by writing valid joint signals through data addresses, which simplifies the acquisition operation of multiple interface signals and simplifies the use steps.

[0039] S120. When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel are processed respectively through a preset write automatic response method, and combined with the preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus.

[0040] In this embodiment, the write address ready signal, the write data ready signal and the feedback handshake valid signal need to be converted into an automatic response signal. In detail, the process of converting the feedback handshake valid signal into the automatic response signal needs to be combined with the specific situation of the feedback handshake ready signal.

[0041] Optionally, when it is determined that the write operation completion signal is in a valid state, the preparation signals in the write address channel and the write data channel are processed respectively through a preset write automatic response method, and combined with a preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus, including: when it is determined that the write operation completion signal is in a valid state, the preset write automatic response method is used to determine whether the write address preparation signal or the write data preparation signal is in a high state; if so, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current automatic response processing operation is ended; if the write address preparation signal or the write data preparation signal is in a high state, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current automatic response processing operation is ended; if the write address preparation signal or the write data preparation signal is in a high state, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current automatic response processing operation is ended The ready signal is not in the high state. If the write operation completion signal is in the high state, the write address ready signal or the write data ready signal is pulled high at the next moment, and the current automatic response processing operation is terminated; if the write address ready signal or the write data ready signal is not in the high state, if the write operation completion signal is not in the high state, the preset write operation allowed cycle threshold is obtained, and combined with the preset write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, the write operation completion signal is pulled high, and the current automatic response processing operation is terminated; the automatic response of the write address channel and the write data channel is completed to complete the use optimization of the write channel of the AXI4_Lite bus.

[0042] In this embodiment, the automatic response processing methods for the write address ready signal and the write data ready signal are the same.

[0043] Continuing with the previous example, let's take the write data ready signal, axi_wready, as an example. First, we need to determine whether wack is valid. If wack is valid, we use the write auto-acknowledge method to determine whether axi_wready is in a high state. If so, axi_wready is pulled low at the next moment, ending the current auto-acknowledge operation.

[0044] Furthermore, if axi_wready is not in the high state, and if wack is in the high state, axi_wready is processed to be in the high state at the next moment, and the current automatic response processing operation is terminated;

[0045] Accordingly, if axi_wready is not in the high state and if wack is not in the high state, the write operation cycle threshold is obtained. Assuming that the write operation cycle threshold is 20 cycles and the current total number of write operation cycles is 21 cycles, combined with the write anti-crash judgment logic, since the current total number of write operation cycles exceeds the write operation cycle threshold, wack is pulled high, ending the current automatic response processing operation; the automatic response of the write address channel and the write data channel is completed, thus optimizing the use of the AXI4_Lite bus write channel. In this way, by comparing the cycle threshold and pulling wack high, the current automatic response operation can be forced to end, avoiding the waste of memory resources.

[0046] Optionally, when it is determined that the write operation completion signal is in a valid state, the feedback handshake valid signal in the write response channel is processed by a preset write automatic response method, and combined with a preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus, including: when it is determined that the write operation completion signal is in a valid state, the preset write automatic response method is used to determine whether the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are both in a pulled-up state; if so, the feedback handshake valid signal is pulled down at the next moment, and the current automatic response processing operation is ended; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are both in a pulled-up state, If the hand-hand ready signal does not meet the requirements of both being in the high state, if the write operation completion signal is in the high state, and the feedback handshake valid signal is pulled high at the next moment, the current automatic response processing operation is terminated; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel do not meet the requirements of both being in the high state, if the write operation completion signal is not in the high state, the preset write operation allowed cycle threshold is obtained, and combined with the preset write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, the write operation completion signal is pulled high and the current automatic response processing operation is terminated; the automatic response of the write response channel is completed to complete the use optimization of the write channel of the AXI4_Lite bus.

[0047] Continuing with the previous example, assume that the feedback handshake valid signal is axi_bvalid; the feedback handshake ready signal is axi_bready.

[0048] Specifically, it is necessary to first determine whether wack is in a valid state. If wack is in a valid state, then by writing the automatic response method, it is determined whether axi_bvalid and axi_bready are both in a high state. If so, axi_bvalid is pulled down at the next moment and the current automatic response processing operation is ended.

[0049] Furthermore, if axi_bvalid and axi_bready are not both in the high state, if wack is in the high state, and axi_bvalid is processed to be in the high state at the next moment, the current automatic response processing operation is terminated.

[0050] Accordingly, if axi_bvalid and axi_bready are not both in the high state, and if wack is not in the high state, the write operation cycle threshold is obtained. Combined with the write anti-crash judgment logic, if the total number of current write operation cycles exceeds the write operation cycle threshold, wack is pulled high, ending the current automatic response processing operation; the automatic response of the write response channel is completed, thus optimizing the use of the AXI4_Lite bus write channel. The write anti-crash judgment logic processing operation here is the same as the ready signal processing method in the write address channel and write data channel, and will not be repeated here.

[0051] S130 , obtaining and generating a read operation completion signal according to a read address valid signal in the read address channel.

[0052] Optionally, acquiring and generating a read operation completion signal based on a read address valid signal in a read address channel includes: acquiring and obtaining a read operation flag signal based on a read address valid signal in a read address channel; and delaying the read operation flag signal to generate the read operation completion signal.

[0053] In this embodiment, assuming that the read address valid signal is axi_arvalid and the read operation flag signal is rreq, wherein the read operation flag signal is equal to the read address valid signal, axi_arvalid needs to be assigned to rreq.

[0054] Furthermore, rreq is delayed to generate a read operation completion signal.

[0055] S140. When it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively through a preset read automatic response method, and combined with a preset read anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the read channel of the AXI4_Lite bus.

[0056] Optionally, when it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively through a preset read automatic response method, and combined with the preset read anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the read channel of the AXI4_Lite bus, including: when it is determined that the read operation completion signal is in a valid state, the preset read automatic response method is used to determine whether the read address preparation signal satisfies the high state, and if so, the read address preparation signal is pulled low at the next moment, and the current automatic response processing operation is ended; if it is determined that the read address preparation signal does not satisfy the high state, then it is determined whether the read operation completion signal is in a high state, and if so, the read address preparation signal is pulled high at the next moment, and the current automatic response processing operation is ended; if the read operation completion signal is not in a high state, the preset read operation allowed cycle threshold is obtained, and combined with the preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation is completed. The signal is pulled high to terminate the current automatic response processing operation; when it is determined that the read operation completion signal is in a valid state, the read address preparation signal and the read data valid signal are respectively judged by a preset read automatic response method to determine whether both the read address preparation signal and the read data valid signal meet the pull-up state. If so, the read data valid signal and the read data channel data interface signal are pulled low at the next moment, and the current automatic response processing operation is terminated; if it is determined that the read address preparation signal or the read data valid signal does not meet the pull-up state, then it is determined whether the read operation completion signal is in a pull-up state. If so, the current data read is sent to the read data channel data interface. When the read address preparation signal is in a valid state, the read data valid signal is pulled low at the next moment, and the current automatic response processing operation is terminated; if the read operation completion signal is not in a pull-up state, a preset read operation allowed cycle threshold is obtained, and combined with a preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is pulled high to terminate the current automatic response processing operation, so as to complete the use optimization of the read channel of the AXI4_Lite bus.

[0057] For example, it is assumed that the read address preparation signal is axi_arready; the read data valid signal is axi_rvalid; and the read operation completion signal is rack.

[0058] For the automatic response processing of axi_arready, it is first necessary to determine whether rack is in a valid state. If rack is in a valid state, the automatic response method is read to determine whether axi_arready satisfies the pull-up state. If so, axi_arready is pulled down at the next moment and the current automatic response processing operation is ended.

[0059] Furthermore, if it is determined that axi_arready does not satisfy the high state, it is determined whether rack is in the high state. If so, axi_arready is subjected to a high state processing operation at the next moment, and the current automatic response processing operation is terminated.

[0060] Accordingly, if the rack is not in the high state, the read operation cycle threshold is obtained. Combined with the read anti-crash judgment logic, if the total number of read operation cycles currently exceeds the read operation cycle threshold, the read operation completion signal is pulled high, terminating the current automatic response processing operation. Specifically, assuming the read operation cycle threshold is 10 and the current total number of read operation cycles is 11, since the current total number of read operation cycles exceeds the read operation cycle threshold, the rack is pulled high, terminating the current automatic response processing operation.

[0061] For the automatic response processing of axi_rvalid, it is first necessary to determine whether rack is in a valid state. If rack is in a valid state, the automatic response method is read to determine whether axi_arready and axi_rvalid are both in a high state. If so, axi_rvalid is pulled low at the next moment, and the data interface signal of the read data channel is also pulled low, and the current automatic response processing operation is ended.

[0062] Furthermore, if it is determined that axi_arready or axi_rvalid is not in the high state, it is determined whether rack is in the high state. If so, the current data read is sent to the data channel data interface axi_rdata. When axi_arready is in the valid state, axi_rvalid is pulled down at the next moment, and the current automatic response processing operation is ended.

[0063] Correspondingly, if the rack is not in the high state, the read operation allowed cycle threshold is obtained. Combined with the read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the rack is pulled high and the current automatic response processing operation is ended to complete the use optimization of the AXI4_Lite bus read channel.

[0064] In this embodiment, for write operations on the AXI4_Lite bus used on the device side, when the wreq signal is valid, it indicates that the server has successfully written data to the write address. For read operations on the AXI4_Lite bus used on the device side, when the rreq signal is valid, the read data is updated, indicating that the server has successfully completed the read operation at the read address.

[0065] The technical solution of the embodiment of the present invention is to respectively obtain the signals emitted in real time by the write address channel and the write data channel. If the signals are valid signals, a data address write valid joint signal is obtained by a pre-set valid signal combination method. When the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written and a write operation completion signal is generated. When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel, are processed by a pre-set write automatic response method, and combined with a pre-set write anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the write channel of the AXI4_Lite bus. The read address valid signal in the read address channel is obtained and generated according to the read operation completion signal. When it is determined that the read operation completion signal is in a valid state, the read address ready signal in the read address channel and the read data valid signal in the read data channel are processed by a pre-set read automatic response method, and combined with a pre-set read anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the read channel of the AXI4_Lite bus. The problem of too many signal ports, complicated use and high difficulty is solved, the signal ports are simplified, the complexity and difficulty of use are reduced, and the flexibility of port use is improved.

[0066] Example 2

[0067] Figure 2 This is a schematic diagram of the structure of an AXI4_Lite bus usage optimization device provided in the second embodiment of the present invention. The AXI4_Lite bus usage optimization device provided in this embodiment can be implemented through software and / or hardware, and can be configured in a terminal device or server to implement an AXI4_Lite bus usage optimization method in the embodiment of the present invention. Figure 2 As shown, the device includes: a write operation completion signal generation module, a write channel usage optimization module, a read operation completion signal generation module and a read channel usage optimization module.

[0068] The AXI4_Lite bus includes a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel.

[0069] Wherein, the write operation completion signal generation module is used to obtain the real-time signals emitted by the write address channel and the write data channel respectively, and if the signals are valid signals, obtain the data address write valid joint signal through a preset valid signal combination method, and write the data address write valid joint signal if the data address write valid joint signal meets the validity condition, and generate a write operation completion signal;

[0070] A write channel usage optimization module is configured to process the readiness signals in the write address channel and the write data channel, and the feedback handshake valid signal in the write response channel respectively through a preset write automatic response method when determining that the write operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with a preset write anti-crash judgment logic to optimize the use of the write channel of the AXI4_Lite bus;

[0071] A read operation completion signal generating module is used to obtain and generate a read operation completion signal according to a read address valid signal in a read address channel;

[0072] The read channel usage optimization module is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a preset read automatic response method when determining that the read operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with the preset read anti-crash judgment logic to complete the usage optimization of the read channel of the AXI4_Lite bus.

[0073] The technical solution of the embodiment of the present invention is to respectively obtain the signals emitted in real time by the write address channel and the write data channel. If the signals are valid signals, a data address write valid joint signal is obtained by a pre-set valid signal combination method. When the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written and a write operation completion signal is generated. When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel, are processed by a pre-set write automatic response method, and combined with a pre-set write anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the write channel of the AXI4_Lite bus. The read address valid signal in the read address channel is obtained and generated according to the read operation completion signal. When it is determined that the read operation completion signal is in a valid state, the read address ready signal in the read address channel and the read data valid signal in the read data channel are processed by a pre-set read automatic response method, and combined with a pre-set read anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the read channel of the AXI4_Lite bus. The problem of too many signal ports, complicated use and high difficulty is solved, the signal ports are simplified, the complexity and difficulty of use are reduced, and the flexibility of port use is improved.

[0074] Based on the above embodiments, the write address channel includes a write address ready signal and a write address valid signal; the write data channel includes a write data ready signal and a write data valid signal; the write response channel includes a feedback handshake ready signal and a feedback handshake valid signal; the read address channel includes a read address ready signal and a read address valid signal; and the read data channel includes a read data ready signal and a read data valid signal.

[0075] Based on the above embodiments, the valid signal includes a write address valid signal and a write data valid signal.

[0076] Based on the above embodiments, the write operation completion signal generation module can be specifically used to: obtain the signals emitted in real time by the write address channel and the write data channel respectively; if the signal is a write address valid signal or a write data valid signal, the write address valid signal and the write data valid signal are combined and merged by a pre-set valid signal combination method to obtain a data address write valid joint signal; when the data address write valid joint signal meets the validity condition, the data address write valid joint signal is written, and the data address write valid joint signal is delayed to generate a write operation completion signal.

[0077] Based on the above embodiments, the write channel usage optimization module can be specifically configured to: upon determining that the write operation completion signal is in a valid state, determine whether the write address preparation signal or the write data preparation signal is in a high state using a preset write automatic response method; if so, pull the write address preparation signal or the write data preparation signal to a low state at the next moment and terminate the current automatic response processing operation; if the write address preparation signal or the write data preparation signal is not in a high state, and if the write operation completion signal is in a high state, pull the write address preparation signal or the write data preparation signal to a high state at the next moment and terminate the current automatic response processing operation; if the write address preparation signal or the write data preparation signal is not in a high state, and if the write operation completion signal is not in a high state, obtain a preset write operation allowed cycle threshold, and combine with a preset write anti-crash judgment logic; if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, pull the write operation completion signal to a high state and terminate the current automatic response processing operation; complete the automatic response of the write address channel and the write data channel to complete the usage optimization of the write channel of the AXI4_Lite bus.

[0078] Based on the above embodiments, the write channel usage optimization module may further be specifically configured to: upon determining that the write operation completion signal is in a valid state, determine, using a preset write automatic response method, whether the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are both in a high state; if so, pull the feedback handshake valid signal to a low state at the next moment and terminate the current automatic response processing operation; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both in a high state, if the write operation completion signal is in a high state, pull the feedback handshake valid signal to a high state at the next moment and terminate the current automatic response processing operation; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both in a high state, if the write operation completion signal is not in a high state, obtain a preset write operation allowed cycle threshold, combine with a preset write anti-crash judgment logic, and if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, pull the write operation completion signal to a high state and terminate the current automatic response processing operation; complete the automatic response of the write response channel to complete the usage optimization of the write channel of the AXI4_Lite bus.

[0079] Based on the above embodiments, the read operation completion signal generating module can be specifically used to: obtain and obtain a read operation flag signal based on a read address valid signal in a read address channel; and perform delay processing on the read operation flag signal to generate the read operation completion signal.

[0080] On the basis of the above embodiments, the read channel uses an optimization module, which can be specifically used for: when it is determined that the read operation completion signal is in a valid state, the read address preparation signal is judged to be in a high state by a preset read automatic response method. If so, the read address preparation signal is pulled low at the next moment and the current automatic response processing operation is ended; if it is determined that the read address preparation signal does not meet the high state, the read operation completion signal is judged to be in a high state. If so, the read address preparation signal is pulled high at the next moment and the current automatic response processing operation is ended; if the read operation completion signal is not in a high state, the preset read operation allowed cycle threshold is obtained, and combined with the preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is pulled high and the current automatic response processing operation is ended; when it is determined that the read operation completion signal is in a valid state, the read automatic response method is preset. The response method judges whether the read address preparation signal and the read data valid signal both meet the high state. If so, the read data valid signal and the read data channel data interface signal are pulled down at the next moment, and the current automatic response processing operation is ended; if it is judged that the read address preparation signal or the read data valid signal does not meet the high state, then it is judged whether the read operation completion signal is in the high state. If so, the current data read is sent to the read data channel data interface. When the read address preparation signal is in the valid state, the read data valid signal is pulled down at the next moment, and the current automatic response processing operation is ended; if the read operation completion signal is not in the high state, the preset read operation allowed cycle threshold is obtained, combined with the preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is pulled up, and the current automatic response processing operation is ended to complete the use optimization of the read channel of the AXI4_Lite bus.

[0081] The AXI4_Lite bus usage optimization device provided in the embodiment of the present invention can execute the AXI4_Lite bus usage optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0082] Example 3

[0083] Figure 3A schematic diagram of the structure of an electronic device 10 that can be used to implement the third embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0084] like Figure 3 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0085] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0086] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors for running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the AXI4_Lite bus usage optimization method.

[0087] In some embodiments, the AXI4_Lite bus usage optimization method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the AXI4_Lite bus usage optimization method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the AXI4_Lite bus usage optimization method in any other appropriate manner (for example, by means of firmware).

[0088] The method includes: respectively acquiring signals emitted in real time by a write address channel and a write data channel; if the signals are valid signals, obtaining a data address write valid joint signal by a preset valid signal combination method; and if the data address write valid joint signal satisfies a validity condition, writing the data address write valid joint signal, and generating a write operation completion signal; when it is determined that the write operation completion signal is in a valid state, respectively processing the preparation signals in the write address channel and the write data channel, and the feedback handshake valid signal in the write response channel by a preset write automatic response method, and combining with a preset write anti-crash judgment logic, completing automatic response of the signals of each channel to complete the use optimization of the write channel of the AXI4_Lite bus; acquiring and generating a read operation completion signal based on a read address valid signal in the read address channel; and when it is determined that the read operation completion signal is in a valid state, respectively processing the read address preparation signal in the read address channel and the read data valid signal in the read data channel by a preset read automatic response method, and combining with a preset read anti-crash judgment logic, completing automatic response of the signals of each channel to complete the use optimization of the read channel of the AXI4_Lite bus.

[0089] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0093] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0094] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0095] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0096] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

[0097] Example 4

[0098] The fourth embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable instructions are used to execute an AXI4_Lite bus usage optimization method when executed by a computer processor, the method comprising: respectively obtaining the signals emitted in real time by the write address channel and the write data channel, and if the signals are valid signals, obtaining the data address write valid joint signal through a preset valid signal combination method, and when the data address write valid joint signal meets the validity condition, writing the data address write valid joint signal, and generating a write operation completion signal; when it is determined that the write operation completion signal is in a valid state, respectively writing the write address channel and the write data channel through a preset write automatic response method. The system processes the read address preparation signal and the feedback handshake valid signal in the write response channel, and completes the automatic response of each channel signal in combination with the preset write anti-crash judgment logic to complete the use optimization of the write channel of the AXI4_Lite bus; obtains and generates a read operation completion signal based on the read address valid signal in the read address channel; when it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively by a preset read automatic response method, and completes the automatic response of each channel signal in combination with the preset read anti-crash judgment logic to complete the use optimization of the read channel of the AXI4_Lite bus.

[0099] Of course, the computer-readable storage medium provided in the embodiment of the present invention has computer-executable instructions that are not limited to the method operations described above, and can also execute related operations in the AXI4_Lite bus usage optimization provided in any embodiment of the present invention.

[0100] Through the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented with the help of software and necessary general-purpose hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0101] It is worth noting that in the above-mentioned embodiment of the optimized use of the AXI4_Lite bus, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present invention.

[0102] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for optimizing the use of an AXI4_Lite bus, characterized in that: The AXI4_Lite bus includes: write address channel, write data channel, write response channel, read address channel and read data channel; respectively obtaining the real-time signals emitted by the write address channel and the write data channel, and if the signals are valid signals, obtaining a data address write valid combined signal through a preset valid signal combination method, and writing the data address write valid combined signal if the data address write valid combined signal meets the validity condition, and generating a write operation completion signal; When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel are processed respectively through a preset write automatic response method, and combined with the preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus; Obtain and generate a read operation completion signal based on a read address valid signal in a read address channel; When it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively through a preset read automatic response method, and combined with the preset read anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the read channel of the AXI4_Lite bus.

2. The method according to claim 1, characterized in that The write address channel includes a write address preparation signal and a write address valid signal; the write data channel includes a write data preparation signal and a write data valid signal; the write response channel includes a feedback handshake preparation signal and a feedback handshake valid signal; The read address channel includes a read address preparation signal and a read address valid signal; The read data channel includes a read data ready signal and a read data valid signal.

3. The method according to claim 2, characterized in that The valid signal includes a write address valid signal and a write data valid signal; The method comprises: respectively acquiring the signals emitted in real time by the write address channel and the write data channel, obtaining a data address write valid combined signal by a preset valid signal combination method if the signals are valid signals, and writing the data address write valid combined signal if the data address write valid combined signal meets the validity condition, and generating a write operation completion signal, including: respectively acquiring signals emitted in real time by a write address channel and a write data channel, and if the signals are write address valid signals or write data valid signals, combining the write address valid signals and the write data valid signals by a preset valid signal combination method to obtain a data address write valid combined signal; When the data address write valid combined signal meets the validity condition, the data address write valid combined signal is written, and the data address write valid combined signal is delayed to generate a write operation completion signal.

4. The method according to claim 3, characterized in that When it is determined that the write operation completion signal is in a valid state, the ready signals in the write address channel and the write data channel are processed respectively through a preset write automatic response method, and combined with the preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus, including: When it is determined that the write operation completion signal is in a valid state, a predetermined write automatic response method is used to determine whether the write address preparation signal or the write data preparation signal is in a high state; if so, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current automatic response processing operation is terminated; If the write address ready signal or the write data ready signal is not in the high state, if the write operation completion signal is in the high state, the write address ready signal or the write data ready signal is pulled high at the next moment, and the current automatic response processing operation is terminated; If the write address preparation signal or the write data preparation signal is not in the high state, and if the write operation completion signal is not in the high state, then the preset write operation allowable cycle threshold is obtained, and combined with the preset write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowable cycle threshold, then the write operation completion signal is pulled high to end the current automatic response processing operation; Automatic responses of the write address channel and the write data channel are completed to optimize the use of the write channel of the AXI4_Lite bus.

5. The method according to claim 3, characterized in that When it is determined that the write operation completion signal is in a valid state, the feedback handshake valid signal in the write response channel is processed by a preset write automatic response method, and combined with the preset write anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the write channel of the AXI4_Lite bus, including: When it is determined that the write operation completion signal is in a valid state, a predetermined write automatic response method is used to determine whether the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are both in a high state. If so, the feedback handshake valid signal is pulled low at the next moment, and the current automatic response processing operation is terminated; If the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both in the high state, if the write operation completion signal is in the high state, and the feedback handshake valid signal is pulled high at the next moment, the current automatic response processing operation is terminated; If the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both in the high state, and if the write operation completion signal is not in the high state, then the preset write operation allowed cycle threshold is obtained, and combined with the preset write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, then the write operation completion signal is pulled high to end the current automatic response processing operation; The automatic response of the write response channel is completed to optimize the use of the write channel of the AXI4_Lite bus.

6. The method according to claim 2, characterized in that The step of obtaining and generating a read operation completion signal according to a read address valid signal in a read address channel includes: Obtaining and obtaining a read operation flag signal according to a read address valid signal in a read address channel; Delay processing is performed on the read operation flag signal to generate the read operation completion signal.

7. The method according to claim 6, characterized in that When it is determined that the read operation completion signal is in a valid state, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed respectively by a preset read automatic response method, and combined with the preset read anti-crash judgment logic, the automatic response of each channel signal is completed to complete the use optimization of the read channel of the AXI4_Lite bus, including: After determining that the read operation completion signal is in a valid state, a preset read automatic response method is used to determine whether the read address preparation signal satisfies the pull-up state. If so, a pull-down state processing operation is performed on the read address preparation signal at the next moment, and the current automatic response processing operation is terminated; if it is determined that the read address preparation signal does not satisfy the pull-up state, it is determined whether the read operation completion signal is in a pull-up state. If so, a pull-up state processing operation is performed on the read address preparation signal at the next moment, and the current automatic response processing operation is terminated; if the read operation completion signal is not in a pull-up state, a preset read operation allowed cycle threshold is obtained, and combined with a preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is pulled high, and the current automatic response processing operation is terminated; When it is determined that the read operation completion signal is in a valid state, a preset read automatic response method is used to determine whether the read address preparation signal and the read data valid signal both meet the high state. If so, the read data valid signal and the read data channel data interface signal are pulled low at the next moment, and the current automatic response processing operation is terminated; if it is determined that the read address preparation signal or the read data valid signal does not meet the high state, it is determined whether the read operation completion signal is in a high state. If so, the current data read is sent to the read data channel data interface. When the read address preparation signal is in a valid state, the read data valid signal is pulled low at the next moment, and the current automatic response processing operation is terminated; if the read operation completion signal is not in a high state, a preset read operation allowed cycle threshold is obtained, and combined with the preset read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is pulled high, and the current automatic response processing operation is terminated to complete the use optimization of the read channel of the AXI4_Lite bus.

8. An AXI4_Lite bus usage optimization device, characterized in that: The AXI4_Lite bus includes: write address channel, write data channel, write response channel, read address channel and read data channel; A write operation completion signal generation module is used to obtain the real-time signals emitted by the write address channel and the write data channel respectively. If the signals are valid signals, a data address write valid combined signal is obtained through a preset valid signal combination method. If the data address write valid combined signal meets the validity condition, the data address write valid combined signal is written and the write operation completion signal is generated. A write channel usage optimization module is configured to process the readiness signals in the write address channel and the write data channel, and the feedback handshake valid signal in the write response channel respectively through a preset write automatic response method when determining that the write operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with a preset write anti-crash judgment logic to optimize the use of the write channel of the AXI4_Lite bus; A read operation completion signal generating module is used to obtain and generate a read operation completion signal according to a read address valid signal in a read address channel; The read channel usage optimization module is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a preset read automatic response method when determining that the read operation completion signal is in a valid state, and complete the automatic response of each channel signal in combination with the preset read anti-crash judgment logic to complete the usage optimization of the read channel of the AXI4_Lite bus.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, an AXI4_Lite bus usage optimization method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement an AXI4_Lite bus usage optimization method according to any one of claims 1 to 7 when executed.

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